61 lines
1.8 KiB
Diff
61 lines
1.8 KiB
Diff
From accab6de53267aaa0aa105a2555b3ec68223c466 Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Thu, 12 Jan 2017 16:34:57 +0100
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Subject: [PATCH 001/351] clk: sunxi-ng: Set maximum P and M factors to 1 for
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H3 pll-cpux clock
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When using M factor greater than 1 system is experiencing
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occasional lockups. P factor should only be used for clock
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speeds below 288MHz. We don't use such speeds in the mainline
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kernel.
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This change was verified to fix lockups with PLL stress
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tester available at https://xff.cz/git/arisc-firmware/.
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Note that M factor must not be used outside the kernel either,
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so for example u-boot needs a similar patch.
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Signed-off-by: Ondrej Jirman <megous@megous.com>
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---
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drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 24 +++++++++++++++---------
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1 file changed, 15 insertions(+), 9 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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index 6b636362379e..ca55c2ae999d 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -23,15 +23,21 @@
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#include "ccu-sun8i-h3.h"
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-static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
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- "osc24M", 0x000,
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- 8, 5, /* N */
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- 4, 2, /* K */
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- 0, 2, /* M */
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- 16, 2, /* P */
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- BIT(31), /* gate */
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- BIT(28), /* lock */
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- CLK_SET_RATE_UNGATE);
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+static struct ccu_nkmp pll_cpux_clk = {
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+ .enable = BIT(31),
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+ .lock = BIT(28),
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+ .n = _SUNXI_CCU_MULT(8, 5),
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+ .k = _SUNXI_CCU_MULT(4, 2),
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+ .m = _SUNXI_CCU_DIV_MAX(0, 2, 1),
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+ .p = _SUNXI_CCU_DIV_MAX(16, 2, 1),
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+ .common = {
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+ .reg = 0x000,
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+ .hw.init = CLK_HW_INIT("pll-cpux",
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+ "osc24M",
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+ &ccu_nkmp_ops,
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+ CLK_SET_RATE_UNGATE),
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+ },
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+};
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/*
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* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
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--
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2.34.0
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