389 lines
13 KiB
Diff
389 lines
13 KiB
Diff
From 01a8876b2c8350798aaddb3be15fe389c5027ff7 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 25 Aug 2019 05:35:08 -0500
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Subject: [PATCH 165/351] irqchip/sun6i-r: Use a stacked irqchip driver
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The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the
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original sun4i interrupt controller than the sun7i/sun9i NMI controller.
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It is used for two distinct purposes:
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1) To control the trigger, latch, and mask for the NMI input pin
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2) To provide the interrupt input for the ARISC coprocessor
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As this interrupt controller is not documented, information about it
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comes from vendor-provided ARISC firmware and from experimentation.
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Like the original sun4i interrupt controller, it has:
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- A VECTOR_REG at 0x00 (configurable via the BASE_ADDR_REG at 0x04)
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- A NMI_CTRL_REG, PENDING_REG, and ENABLE_REG as used by both the
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sun4i and sunxi-nmi drivers
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- A MASK_REG at 0x50
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- A RESP_REG at 0x60
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Differences from the sun4i interrupt controller appear to be:
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- It is only known to have one register of each kind (max 32 inputs)
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- There is no FIQ-related logic
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- There is no interrupt priority logic
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In order to fulfill its two purposes, this hardware block combines two
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types of IRQs. First, the NMI pin is routed to the "IRQ 0" input on this
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chip, with a trigger type controlled by the NMI_CTRL_REG. The "IRQ 0
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pending" output from this chip, if enabled, is then routed to a SPI IRQ
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input on the GIC, as IRQ_TYPE_LEVEL_HIGH. In other words, bit 0 of
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ENABLE_REG *does* affect the NMI IRQ seen at the GIC.
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The NMI is then followed by a contiguous block of (at least) 15 IRQ
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inputs that are connected in parallel to both R_INTC and the GIC. Or
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in other words, the other bits of ENABLE_REG *do not* affect the IRQs
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seen at the GIC.
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Finally, the global "IRQ pending" output from R_INTC, after being masked
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by MASK_REG and RESP_REG, is connected to the "external interrupt" input
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of the ARISC CPU (an OR1200). This path is not relevant to Linux.
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Because of the 1:1 correspondence between R_INTC and GIC inputs, this is
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a perfect scenario for using a stacked irqchip driver. We want to hook
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into enabling/disabling IRQs to add more features to the GIC
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(specifically to allow masking the NMI and setting its trigger type),
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but we don't need to actually handle the IRQ in this driver.
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And since R_INTC is in the always-on power domain, and its output is
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connected directly in to the power management coprocessor, a stacked
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irqchip driver provides a simple way to add wakeup support to this set
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of IRQs. That is a future patch; for now, just the NMI is moved over.
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This driver keeps the same DT binding as the existing driver. The
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"interrupt" property of the R_INTC node is used to determine 1) the
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offset between GIC and R_INTC hwirq numbers and 2) the type of trigger
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between the R_INTC "IRQ 0 pending" output and the GIC NMI input.
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This commit mostly reverts commit 173bda53b340 ("irqchip/sunxi-nmi:
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Support sun6i-a31-r-intc compatible").
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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arch/arm/mach-sunxi/Kconfig | 2 +
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arch/arm64/Kconfig.platforms | 2 +
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drivers/irqchip/Makefile | 1 +
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drivers/irqchip/irq-sun6i-r.c | 216 ++++++++++++++++++++++++++++++++
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drivers/irqchip/irq-sunxi-nmi.c | 26 +---
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5 files changed, 224 insertions(+), 23 deletions(-)
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create mode 100644 drivers/irqchip/irq-sun6i-r.c
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diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
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index eeadb1a4dcfe..e5c2fce281cd 100644
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--- a/arch/arm/mach-sunxi/Kconfig
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+++ b/arch/arm/mach-sunxi/Kconfig
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@@ -6,6 +6,8 @@ menuconfig ARCH_SUNXI
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select CLKSRC_MMIO
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select GENERIC_IRQ_CHIP
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select GPIOLIB
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+ select IRQ_DOMAIN_HIERARCHY
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+ select IRQ_FASTEOI_HIERARCHY_HANDLERS
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select PINCTRL
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select PM_OPP
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select SUN4I_TIMER
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diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
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index 5c4ac1c9f4e0..9f9f8479b1b9 100644
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--- a/arch/arm64/Kconfig.platforms
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+++ b/arch/arm64/Kconfig.platforms
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@@ -17,6 +17,8 @@ config ARCH_SUNXI
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bool "Allwinner sunxi 64-bit SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select GENERIC_IRQ_CHIP
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+ select IRQ_DOMAIN_HIERARCHY
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+ select IRQ_FASTEOI_HIERARCHY_HANDLERS
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select PINCTRL
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select RESET_CONTROLLER
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help
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diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
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index 94c2885882ee..aec0a92f909e 100644
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--- a/drivers/irqchip/Makefile
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+++ b/drivers/irqchip/Makefile
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@@ -24,6 +24,7 @@ obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
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obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
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obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
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+obj-$(CONFIG_ARCH_SUNXI) += irq-sun6i-r.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
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obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
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obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
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diff --git a/drivers/irqchip/irq-sun6i-r.c b/drivers/irqchip/irq-sun6i-r.c
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new file mode 100644
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index 000000000000..f8bfa5515f20
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--- /dev/null
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+++ b/drivers/irqchip/irq-sun6i-r.c
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@@ -0,0 +1,216 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+//
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+// Allwinner A31 and newer SoCs R_INTC driver
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+//
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+
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+#include <linux/irq.h>
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+#include <linux/irqchip.h>
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+#include <linux/irqdomain.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+#include <linux/of_irq.h>
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+
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+
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+#define NMI_HWIRQ 0
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+#define NMI_HWIRQ_BIT BIT(NMI_HWIRQ)
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+
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+#define SUN6I_R_INTC_NR_IRQS 16
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+
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+#define SUN6I_R_INTC_NMI_CTRL 0x0c
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+#define SUN6I_R_INTC_PENDING 0x10
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+#define SUN6I_R_INTC_ENABLE 0x40
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+
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+static void __iomem *base;
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+static irq_hw_number_t parent_offset;
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+static u32 parent_type;
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+
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+static struct irq_chip sun6i_r_intc_edge;
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+static struct irq_chip sun6i_r_intc_level;
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+
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+static void sun6i_r_intc_nmi_ack(void)
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+{
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+ /*
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+ * The NMI IRQ channel has a latch, separate from its trigger.
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+ * This latch must be cleared to clear the output to the GIC.
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+ */
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+ writel_relaxed(NMI_HWIRQ_BIT, base + SUN6I_R_INTC_PENDING);
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+}
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+
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+static void sun6i_r_intc_irq_ack(struct irq_data *data)
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+{
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+ if (data->hwirq == NMI_HWIRQ)
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+ sun6i_r_intc_nmi_ack();
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+}
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+
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+static void sun6i_r_intc_irq_eoi(struct irq_data *data)
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+{
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+ if (data->hwirq == NMI_HWIRQ)
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+ sun6i_r_intc_nmi_ack();
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+
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+ irq_chip_eoi_parent(data);
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+}
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+
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+static int sun6i_r_intc_irq_set_type(struct irq_data *data, unsigned int type)
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+{
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+ /*
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+ * Only the NMI IRQ is routed through this interrupt controller on its
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+ * way to the GIC. Other IRQs are routed to the GIC in parallel and
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+ * must have a trigger type appropriate for the GIC.
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+ *
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+ * The "External NMI" input to the GIC actually comes from bit 0 of
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+ * this device's PENDING register. So the IRQ type of the NMI, as seen
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+ * by the GIC, does not depend on the IRQ type of the NMI pin itself.
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+ */
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+ if (data->hwirq == NMI_HWIRQ) {
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+ u32 nmi_src_type;
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+
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+ switch (type) {
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+ case IRQ_TYPE_LEVEL_LOW:
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+ nmi_src_type = 0;
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+ break;
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+ case IRQ_TYPE_EDGE_FALLING:
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+ nmi_src_type = 1;
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+ break;
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+ case IRQ_TYPE_LEVEL_HIGH:
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+ nmi_src_type = 2;
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+ break;
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+ case IRQ_TYPE_EDGE_RISING:
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+ nmi_src_type = 3;
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+ break;
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+ default:
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+ pr_err("%pOF: invalid trigger type %d for IRQ %d\n",
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+ irq_domain_get_of_node(data->domain), type,
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+ data->irq);
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+ return -EBADR;
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+ }
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+
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+ if (type & IRQ_TYPE_EDGE_BOTH) {
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+ irq_set_chip_handler_name_locked(data,
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+ &sun6i_r_intc_edge,
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+ handle_fasteoi_ack_irq,
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+ NULL);
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+ } else {
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+ irq_set_chip_handler_name_locked(data,
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+ &sun6i_r_intc_level,
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+ handle_fasteoi_irq,
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+ NULL);
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+ }
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+
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+ writel_relaxed(nmi_src_type, base + SUN6I_R_INTC_NMI_CTRL);
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+
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+ /* Send the R_INTC -> GIC trigger type to the GIC driver. */
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+ type = parent_type;
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+ }
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+
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+ return irq_chip_set_type_parent(data, type);
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+}
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+
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+static struct irq_chip sun6i_r_intc_edge = {
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+ .name = "sun6i-r-intc",
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+ .irq_ack = sun6i_r_intc_irq_ack,
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+ .irq_mask = irq_chip_mask_parent,
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+ .irq_unmask = irq_chip_unmask_parent,
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+ .irq_eoi = irq_chip_eoi_parent,
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+ .irq_set_affinity = irq_chip_set_affinity_parent,
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+ .irq_set_type = sun6i_r_intc_irq_set_type,
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+ .irq_get_irqchip_state = irq_chip_get_parent_state,
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+ .irq_set_irqchip_state = irq_chip_set_parent_state,
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+ .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
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+ .flags = IRQCHIP_SET_TYPE_MASKED,
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+};
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+
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+static struct irq_chip sun6i_r_intc_level = {
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+ .name = "sun6i-r-intc",
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+ .irq_mask = irq_chip_mask_parent,
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+ .irq_unmask = irq_chip_unmask_parent,
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+ .irq_eoi = sun6i_r_intc_irq_eoi,
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+ .irq_set_affinity = irq_chip_set_affinity_parent,
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+ .irq_set_type = sun6i_r_intc_irq_set_type,
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+ .irq_get_irqchip_state = irq_chip_get_parent_state,
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+ .irq_set_irqchip_state = irq_chip_set_parent_state,
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+ .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
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+ .flags = IRQCHIP_SET_TYPE_MASKED |
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+ IRQCHIP_EOI_THREADED,
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+};
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+
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+static int sun6i_r_intc_domain_alloc(struct irq_domain *domain,
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+ unsigned int virq,
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+ unsigned int nr_irqs, void *arg)
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+{
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+ struct irq_fwspec *fwspec = arg;
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+ struct irq_fwspec gic_fwspec;
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+ irq_hw_number_t hwirq;
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+ unsigned int type;
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+ int i, ret;
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+
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+ ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
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+ if (ret)
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+ return ret;
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+ if (hwirq + nr_irqs > SUN6I_R_INTC_NR_IRQS)
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+ return -EINVAL;
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+
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+ /* Construct a GIC-compatible fwspec from this fwspec. */
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+ gic_fwspec = (struct irq_fwspec) {
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+ .fwnode = domain->parent->fwnode,
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+ .param_count = 3,
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+ .param = { GIC_SPI, parent_offset + hwirq, type },
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+ };
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+
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+ for (i = 0; i < nr_irqs; ++i)
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+ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
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+ &sun6i_r_intc_level, NULL);
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+
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+ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_fwspec);
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+}
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+
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+static const struct irq_domain_ops sun6i_r_intc_domain_ops = {
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+ .translate = irq_domain_translate_twocell,
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+ .alloc = sun6i_r_intc_domain_alloc,
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+ .free = irq_domain_free_irqs_common,
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+};
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+
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+static int __init sun6i_r_intc_init(struct device_node *node,
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+ struct device_node *parent)
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+{
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+ struct irq_domain *domain, *parent_domain;
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+ struct of_phandle_args parent_irq;
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+ int ret;
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+
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+ /* Extract the R_INTC -> GIC mapping from the OF node. */
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+ ret = of_irq_parse_one(node, 0, &parent_irq);
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+ if (ret)
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+ return ret;
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+ if (parent_irq.args_count != 3 || parent_irq.args[0] != GIC_SPI)
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+ return -EINVAL;
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+ parent_offset = parent_irq.args[1];
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+ parent_type = parent_irq.args[2];
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+
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+ parent_domain = irq_find_host(parent);
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+ if (!parent_domain) {
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+ pr_err("%pOF: Failed to obtain parent domain\n", node);
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+ return -ENXIO;
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+ }
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+
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+ base = of_io_request_and_map(node, 0, NULL);
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+ if (IS_ERR(base)) {
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+ pr_err("%pOF: Failed to map MMIO region\n", node);
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+ return PTR_ERR(base);
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+ }
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+
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+ domain = irq_domain_add_hierarchy(parent_domain, 0,
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+ SUN6I_R_INTC_NR_IRQS, node,
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+ &sun6i_r_intc_domain_ops, NULL);
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+ if (!domain) {
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+ pr_err("%pOF: Failed to allocate domain\n", node);
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+ iounmap(base);
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+ return -ENOMEM;
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+ }
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+
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+ /* Clear and enable the NMI. */
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+ writel_relaxed(NMI_HWIRQ_BIT, base + SUN6I_R_INTC_PENDING);
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+ writel_relaxed(NMI_HWIRQ_BIT, base + SUN6I_R_INTC_ENABLE);
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+
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+ return 0;
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+}
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+IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc", sun6i_r_intc_init);
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diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
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index a412b5d5d0fa..9f2bd0c5d289 100644
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--- a/drivers/irqchip/irq-sunxi-nmi.c
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+++ b/drivers/irqchip/irq-sunxi-nmi.c
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@@ -27,18 +27,12 @@
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#define SUNXI_NMI_IRQ_BIT BIT(0)
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-#define SUN6I_R_INTC_CTRL 0x0c
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-#define SUN6I_R_INTC_PENDING 0x10
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-#define SUN6I_R_INTC_ENABLE 0x40
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-
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/*
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* For deprecated sun6i-a31-sc-nmi compatible.
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- * Registers are offset by 0x0c.
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*/
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-#define SUN6I_R_INTC_NMI_OFFSET 0x0c
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-#define SUN6I_NMI_CTRL (SUN6I_R_INTC_CTRL - SUN6I_R_INTC_NMI_OFFSET)
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-#define SUN6I_NMI_PENDING (SUN6I_R_INTC_PENDING - SUN6I_R_INTC_NMI_OFFSET)
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-#define SUN6I_NMI_ENABLE (SUN6I_R_INTC_ENABLE - SUN6I_R_INTC_NMI_OFFSET)
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+#define SUN6I_NMI_CTRL 0x00
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+#define SUN6I_NMI_PENDING 0x04
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+#define SUN6I_NMI_ENABLE 0x34
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#define SUN7I_NMI_CTRL 0x00
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#define SUN7I_NMI_PENDING 0x04
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@@ -61,12 +55,6 @@ struct sunxi_sc_nmi_reg_offs {
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u32 enable;
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};
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-static const struct sunxi_sc_nmi_reg_offs sun6i_r_intc_reg_offs __initconst = {
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- .ctrl = SUN6I_R_INTC_CTRL,
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- .pend = SUN6I_R_INTC_PENDING,
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- .enable = SUN6I_R_INTC_ENABLE,
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-};
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-
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static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst = {
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.ctrl = SUN6I_NMI_CTRL,
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.pend = SUN6I_NMI_PENDING,
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@@ -232,14 +220,6 @@ static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
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return ret;
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}
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-static int __init sun6i_r_intc_irq_init(struct device_node *node,
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- struct device_node *parent)
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-{
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- return sunxi_sc_nmi_irq_init(node, &sun6i_r_intc_reg_offs);
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-}
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-IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc",
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- sun6i_r_intc_irq_init);
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-
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static int __init sun6i_sc_nmi_irq_init(struct device_node *node,
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struct device_node *parent)
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{
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--
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2.34.0
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