95 lines
3.3 KiB
Diff
95 lines
3.3 KiB
Diff
From 35bc81c5530f28a3907272ca271abeb3ca9b62ce Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Tue, 20 Aug 2019 14:31:38 +0200
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Subject: [PATCH 061/323] net: stmmac: sun8i: Add support for enabling a
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regulator for PHY I/O pins
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Orange Pi 3 has two regulators that power the Realtek RTL8211E. According
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to the phy datasheet, both regulators need to be enabled at the same time.
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Add support for the second optional regulator, "phy-io", to the glue
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driver.
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Signed-off-by: Ondrej Jirman <megous@megous.com>
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---
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.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 25 ++++++++++++++++---
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1 file changed, 22 insertions(+), 3 deletions(-)
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diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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index 5b6d64ada..0182136a4 100644
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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@@ -60,6 +60,7 @@ struct emac_variant {
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* @tx_clk: reference to MAC TX clock
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* @ephy_clk: reference to the optional EPHY clock for the internal PHY
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* @regulator_phy: reference to the optional regulator
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+ * @regulator_phy_io: reference to the optional regulator for PHY I/O pins
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* @rst_ephy: reference to the optional EPHY reset for the internal PHY
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* @variant: reference to the current board variant
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* @regmap: regmap for using the syscon
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@@ -71,6 +72,7 @@ struct sunxi_priv_data {
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struct clk *tx_clk;
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struct clk *ephy_clk;
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struct regulator *regulator_phy;
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+ struct regulator *regulator_phy_io;
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struct reset_control *rst_ephy;
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const struct emac_variant *variant;
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struct regmap_field *regmap_field;
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@@ -549,10 +551,16 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
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struct sunxi_priv_data *gmac = priv;
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int ret;
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+ ret = regulator_enable(gmac->regulator_phy_io);
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+ if (ret) {
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+ dev_err(&pdev->dev, "Fail to enable PHY I/O regulator\n");
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+ return ret;
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+ }
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+
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ret = regulator_enable(gmac->regulator_phy);
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if (ret) {
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dev_err(&pdev->dev, "Fail to enable regulator_phy\n");
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- return ret;
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+ goto err_disable_regulator_phy_io;
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}
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ret = clk_prepare_enable(gmac->tx_clk);
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@@ -572,8 +580,9 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
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err_disable_clk:
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clk_disable_unprepare(gmac->tx_clk);
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err_disable_regulator:
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- if (gmac->regulator)
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- regulator_disable(gmac->regulator);
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+ regulator_disable(gmac->regulator_phy);
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+err_disable_regulator_phy_io:
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+ regulator_disable(gmac->regulator_phy_io);
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return ret;
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}
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@@ -1025,6 +1034,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
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clk_disable_unprepare(gmac->tx_clk);
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regulator_disable(gmac->regulator_phy);
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+ regulator_disable(gmac->regulator_phy_io);
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}
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static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
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@@ -1160,6 +1170,15 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
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return ret;
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}
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+ /* Optional regulator for PHY I/O pins */
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+ gmac->regulator_phy_io = devm_regulator_get(dev, "phy-io");
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+ if (IS_ERR(gmac->regulator_phy_io)) {
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+ ret = PTR_ERR(gmac->regulator_phy_io);
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+ if (ret != -EPROBE_DEFER)
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+ dev_err(dev, "Failed to get PHY I/O regulator (%d)\n", ret);
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+ return ret;
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+ }
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+
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/* The "GMAC clock control" register might be located in the
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* CCU address range (on the R40), or the system control address
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* range (on most other sun8i and later SoCs).
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--
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2.34.0
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