192 lines
5.3 KiB
Diff
192 lines
5.3 KiB
Diff
diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
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index d2e94f6b7..23f8c2048 100644
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--- a/arch/arm/boot/dts/overlay/Makefile
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+++ b/arch/arm/boot/dts/overlay/Makefile
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@@ -60,6 +60,9 @@ dtbo-$(CONFIG_MACH_SUN7I) += \
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dtbo-$(CONFIG_MACH_SUN8I) += \
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sun8i-h3-analog-codec.dtbo \
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sun8i-h3-cir.dtbo \
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+ sun8i-h3-cpu-clock-1.2GHz-1.3v.dtbo \
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+ sun8i-h3-cpu-clock-1.368GHz-1.3v.dtbo \
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+ sun8i-h3-cpu-clock-1.3GHz-1.3v.dtbo \
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sun8i-h3-i2c0.dtbo \
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sun8i-h3-i2c1.dtbo \
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sun8i-h3-i2c2.dtbo \
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diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dts
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new file mode 100644
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index 000000000..b07e694c7
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dts
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@@ -0,0 +1,31 @@
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+// DT overlay for CPU frequency operating points to up to 1.2GHz at a maximum CPU voltage of 1.3v
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+
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ fragment@0 {
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+ target = <&cpu0_opp_table>;
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+
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+ __overlay__ {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ // in order to match the existing DT cooling-maps, update the existing OP table in-place
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+ // with the new voltages
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+
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+ opp-1104000000 {
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+ opp-hz = /bits/ 64 <1104000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+ };
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+ };
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+};
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+
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diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dts
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new file mode 100644
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index 000000000..e3fd7e5c8
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dts
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@@ -0,0 +1,67 @@
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+// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v
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+
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ fragment@0 {
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+ target = <&cpu0_opp_table>;
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+
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+ __overlay__ {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ // in order to match the DT cooling-maps, update the existing OP table in-place
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+ // with the new voltages
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+
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+ opp-1056000000 {
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+ opp-hz = /bits/ 64 <1056000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1104000000 {
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+ opp-hz = /bits/ 64 <1104000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1152000000 {
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+ opp-hz = /bits/ 64 <1152000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1224000000 {
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+ opp-hz = /bits/ 64 <1224000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1248000000 {
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+ opp-hz = /bits/ 64 <1248000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1296000000 {
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+ opp-hz = /bits/ 64 <1296000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1368000000 {
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+ opp-hz = /bits/ 64 <1368000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+ };
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+ };
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+};
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+
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diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dts
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new file mode 100644
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index 000000000..413222831
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dts
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@@ -0,0 +1,61 @@
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+// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v
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+
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ fragment@0 {
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+ target = <&cpu0_opp_table>;
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+
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+ __overlay__ {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ // in order to match the DT cooling-maps, update the existing OP table in-place
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+ // with the new voltages
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+
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+ opp-1056000000 {
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+ opp-hz = /bits/ 64 <1056000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1104000000 {
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+ opp-hz = /bits/ 64 <1104000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1152000000 {
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+ opp-hz = /bits/ 64 <1152000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1224000000 {
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+ opp-hz = /bits/ 64 <1224000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1248000000 {
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+ opp-hz = /bits/ 64 <1248000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1296000000 {
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+ opp-hz = /bits/ 64 <1296000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+ };
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+ };
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+};
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+
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