81 lines
2.6 KiB
Diff
81 lines
2.6 KiB
Diff
From 16fcf04a8075816f34cc1fb69b7c98dfaffe67c7 Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Mon, 10 May 2021 11:01:31 +0100
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Subject: [PATCH 024/101] drv:phy: sun4i-usb: Introduce port2 SIDDQ quirk
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At least the Allwinner H616 SoC requires a weird quirk to make most
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USB PHYs work: Only port2 works out of the box, but all other ports
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need some help from this port2 to work correctly: The CLK_BUS_PHY2 and
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RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in
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the PMU PHY control register needs to be cleared. For this register to
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be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask ....
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Instead of disguising this as some generic feature, do exactly that
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in our PHY init:
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If the quirk bit is set, and we initialise a PHY other than PHY2, ungate
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this one special clock, and clear the SIDDQ bit. We can pull in the
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other required clocks via the DT.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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---
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drivers/phy/allwinner/phy-sun4i-usb.c | 29 +++++++++++++++++++++++++++
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1 file changed, 29 insertions(+)
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diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
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index 39b285e9b..f121da65a 100644
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--- a/drivers/phy/allwinner/phy-sun4i-usb.c
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+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
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@@ -121,6 +121,7 @@ struct sun4i_usb_phy_cfg {
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u8 phyctl_offset;
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bool dedicated_clocks;
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bool phy0_dual_route;
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+ bool needs_phy2_siddq;
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int missing_phys;
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};
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@@ -335,6 +336,27 @@ static int sun4i_usb_phy_init(struct phy *_phy)
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queue_delayed_work(system_wq, &data->detect, 0);
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}
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+ /* Some PHYs on some SoCs need the help of PHY2 to work. */
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+ if (data->cfg->needs_phy2_siddq && phy->index != 2) {
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+ struct sun4i_usb_phy *phy2 = &data->phys[2];
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+
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+ /*
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+ * This extra clock is just needed to access the
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+ * REG_HCI_PHY_CTL PMU register for PHY2.
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+ */
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+ ret = clk_prepare_enable(phy2->clk2);
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+ if (ret)
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+ return ret;
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+
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+ if (phy2->pmu && data->cfg->hci_phy_ctl_clear) {
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+ val = readl(phy2->pmu + REG_HCI_PHY_CTL);
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+ val &= ~data->cfg->hci_phy_ctl_clear;
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+ writel(val, phy2->pmu + REG_HCI_PHY_CTL);
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+ }
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+
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+ clk_disable_unprepare(phy->clk2);
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+ }
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+
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return 0;
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}
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@@ -821,6 +843,13 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
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dev_err(dev, "failed to get clock %s\n", name);
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return PTR_ERR(phy->clk2);
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}
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+ } else {
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+ snprintf(name, sizeof(name), "pmu%d_clk", i);
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+ phy->clk2 = devm_clk_get_optional(dev, name);
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+ if (IS_ERR(phy->clk2)) {
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+ dev_err(dev, "failed to get clock %s\n", name);
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+ return PTR_ERR(phy->clk2);
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+ }
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}
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snprintf(name, sizeof(name), "usb%d_reset", i);
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--
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2.31.1
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