213 lines
6.1 KiB
Diff
213 lines
6.1 KiB
Diff
From 98419a39d1dc276ac395c230ba2e6cf435a624b9 Mon Sep 17 00:00:00 2001
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From: Liang Chen <cl@rock-chips.com>
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Date: Mon, 26 Jul 2021 11:03:55 +0200
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Subject: [PATCH 074/478] arm64: dts: rockchip: add pwm nodes for rk3568
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Add the pwm controller nodes to the core rk3568 dtsi.
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Signed-off-by: Liang Chen <cl@rock-chips.com>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Link: https://lore.kernel.org/r/20210726090355.1548483-2-heiko@sntech.de
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 176 +++++++++++++++++++++++
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1 file changed, 176 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index ec73e8783d42..b721a34ffa8c 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -263,6 +263,50 @@ uart0: serial@fdd50000 {
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status = "disabled";
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};
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+ pwm0: pwm@fdd70000 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfdd70000 0x0 0x10>;
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+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm0m0_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ pwm1: pwm@fdd70010 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfdd70010 0x0 0x10>;
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+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm1m0_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ pwm2: pwm@fdd70020 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfdd70020 0x0 0x10>;
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+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm2m0_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ pwm3: pwm@fdd70030 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfdd70030 0x0 0x10>;
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+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm3_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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pmu: power-management@fdd90000 {
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compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
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reg = <0x0 0xfdd90000 0x0 0x1000>;
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@@ -863,6 +907,138 @@ saradc: saradc@fe720000 {
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status = "disabled";
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};
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+ pwm4: pwm@fe6e0000 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfe6e0000 0x0 0x10>;
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+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm4_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ pwm5: pwm@fe6e0010 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfe6e0010 0x0 0x10>;
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+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm5_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ pwm6: pwm@fe6e0020 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfe6e0020 0x0 0x10>;
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+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm6_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ pwm7: pwm@fe6e0030 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfe6e0030 0x0 0x10>;
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+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm7_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ pwm8: pwm@fe6f0000 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfe6f0000 0x0 0x10>;
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+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm8m0_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ pwm9: pwm@fe6f0010 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfe6f0010 0x0 0x10>;
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+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm9m0_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ pwm10: pwm@fe6f0020 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfe6f0020 0x0 0x10>;
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+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm10m0_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ pwm11: pwm@fe6f0030 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfe6f0030 0x0 0x10>;
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+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm11m0_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ pwm12: pwm@fe700000 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfe700000 0x0 0x10>;
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+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm12m0_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ pwm13: pwm@fe700010 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfe700010 0x0 0x10>;
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+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm13m0_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ pwm14: pwm@fe700020 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfe700020 0x0 0x10>;
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+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm14m0_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ pwm15: pwm@fe700030 {
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+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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+ reg = <0x0 0xfe700030 0x0 0x10>;
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+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
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+ clock-names = "pwm", "pclk";
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+ pinctrl-0 = <&pwm15m0_pins>;
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+ pinctrl-names = "active";
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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pinctrl: pinctrl {
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compatible = "rockchip,rk3568-pinctrl";
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rockchip,grf = <&grf>;
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--
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2.35.3
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