144 lines
3.7 KiB
Diff
144 lines
3.7 KiB
Diff
From 5067f459e5ee22857eeb4f659219db8e28c6263e Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Sat, 10 Jul 2021 11:10:32 -0400
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Subject: [PATCH 023/478] arm64: dts: rockchip: split rk3568 device tree
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In preparation for the rk3566 inclusion, split apart the rk3568 specific
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nodes into a separate device tree.
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This allows us to create the rk3566 device tree without deleting nodes.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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Link: https://lore.kernel.org/r/20210710151034.32857-3-pgwipeout@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 48 ++++++++++++++++++++++++
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 36 ------------------
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2 files changed, 48 insertions(+), 36 deletions(-)
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi
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diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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new file mode 100644
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index 000000000000..da01a59f6f26
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -0,0 +1,48 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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+ */
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+
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+#include "rk356x.dtsi"
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+
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+/ {
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+ compatible = "rockchip,rk3568";
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+
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+ qos_pcie3x1: qos@fe190080 {
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+ compatible = "rockchip,rk3568-qos", "syscon";
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+ reg = <0x0 0xfe190080 0x0 0x20>;
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+ };
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+
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+ qos_pcie3x2: qos@fe190100 {
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+ compatible = "rockchip,rk3568-qos", "syscon";
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+ reg = <0x0 0xfe190100 0x0 0x20>;
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+ };
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+
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+ qos_sata0: qos@fe190200 {
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+ compatible = "rockchip,rk3568-qos", "syscon";
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+ reg = <0x0 0xfe190200 0x0 0x20>;
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+ };
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+};
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+
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+&cpu0_opp_table {
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+ opp-1992000000 {
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+ opp-hz = /bits/ 64 <1992000000>;
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+ opp-microvolt = <1150000 1150000 1150000>;
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+ };
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+};
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+
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+&power {
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+ power-domain@RK3568_PD_PIPE {
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+ reg = <RK3568_PD_PIPE>;
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+ clocks = <&cru PCLK_PIPE>;
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+ pm_qos = <&qos_pcie2x1>,
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+ <&qos_pcie3x1>,
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+ <&qos_pcie3x2>,
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+ <&qos_sata0>,
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+ <&qos_sata1>,
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+ <&qos_sata2>,
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+ <&qos_usb3_0>,
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+ <&qos_usb3_1>;
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+ #power-domain-cells = <0>;
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+ };
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+};
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index 11825909c5db..4bddf8de4f51 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -13,8 +13,6 @@
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#include <dt-bindings/thermal/thermal.h>
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/ {
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- compatible = "rockchip,rk3568";
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-
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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@@ -121,11 +119,6 @@ opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1050000 1050000 1150000>;
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};
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-
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- opp-1992000000 {
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- opp-hz = /bits/ 64 <1992000000>;
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- opp-microvolt = <1150000 1150000 1150000>;
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- };
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};
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firmware {
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@@ -334,20 +327,6 @@ power-domain@RK3568_PD_RKVENC {
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<&qos_rkvenc_wr_m0>;
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#power-domain-cells = <0>;
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};
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-
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- power-domain@RK3568_PD_PIPE {
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- reg = <RK3568_PD_PIPE>;
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- clocks = <&cru PCLK_PIPE>;
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- pm_qos = <&qos_pcie2x1>,
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- <&qos_pcie3x1>,
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- <&qos_pcie3x2>,
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- <&qos_sata0>,
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- <&qos_sata1>,
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- <&qos_sata2>,
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- <&qos_usb3_0>,
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- <&qos_usb3_1>;
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- #power-domain-cells = <0>;
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- };
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};
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};
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@@ -445,21 +424,6 @@ qos_pcie2x1: qos@fe190000 {
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reg = <0x0 0xfe190000 0x0 0x20>;
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};
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- qos_pcie3x1: qos@fe190080 {
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- compatible = "rockchip,rk3568-qos", "syscon";
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- reg = <0x0 0xfe190080 0x0 0x20>;
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- };
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-
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- qos_pcie3x2: qos@fe190100 {
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- compatible = "rockchip,rk3568-qos", "syscon";
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- reg = <0x0 0xfe190100 0x0 0x20>;
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- };
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-
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- qos_sata0: qos@fe190200 {
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- compatible = "rockchip,rk3568-qos", "syscon";
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- reg = <0x0 0xfe190200 0x0 0x20>;
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- };
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-
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qos_sata1: qos@fe190280 {
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compatible = "rockchip,rk3568-qos", "syscon";
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reg = <0x0 0xfe190280 0x0 0x20>;
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--
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2.35.3
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