4965 lines
117 KiB
Diff
4965 lines
117 KiB
Diff
From e24b1918124a6977614e34a8a8224d1ba70eb2f4 Mon Sep 17 00:00:00 2001
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From: The-going <48602507+The-going@users.noreply.github.com>
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Date: Wed, 2 Feb 2022 12:54:05 +0300
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Subject: [PATCH 109/153] arm:dts:overlay Add Overlays for sunxi
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---
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arch/arm/boot/dts/Makefile | 2 +
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arch/arm/boot/dts/overlay/Makefile | 97 +++++
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.../dts/overlay/README.sun4i-a10-overlays | 278 ++++++++++++++
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.../dts/overlay/README.sun5i-a13-overlays | 172 +++++++++
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.../dts/overlay/README.sun7i-a20-overlays | 348 ++++++++++++++++++
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.../boot/dts/overlay/README.sun8i-h3-overlays | 250 +++++++++++++
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.../dts/overlay/sun4i-a10-analog-codec.dts | 13 +
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arch/arm/boot/dts/overlay/sun4i-a10-can.dts | 15 +
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.../boot/dts/overlay/sun4i-a10-fixup.scr-cmd | 124 +++++++
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arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts | 22 ++
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arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts | 22 ++
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arch/arm/boot/dts/overlay/sun4i-a10-nand.dts | 103 ++++++
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.../boot/dts/overlay/sun4i-a10-pps-gpio.dts | 29 ++
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arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts | 15 +
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.../boot/dts/overlay/sun4i-a10-spdif-out.dts | 38 ++
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.../dts/overlay/sun4i-a10-spi-jedec-nor.dts | 57 +++
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.../boot/dts/overlay/sun4i-a10-spi-spidev.dts | 57 +++
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arch/arm/boot/dts/overlay/sun4i-a10-spi0.dts | 23 ++
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arch/arm/boot/dts/overlay/sun4i-a10-spi1.dts | 22 ++
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arch/arm/boot/dts/overlay/sun4i-a10-spi2.dts | 23 ++
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arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts | 37 ++
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arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts | 47 +++
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arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts | 37 ++
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arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts | 32 ++
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arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts | 32 ++
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arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts | 32 ++
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.../boot/dts/overlay/sun4i-a10-w1-gpio.dts | 29 ++
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.../dts/overlay/sun5i-a13-analog-codec.dts | 13 +
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.../boot/dts/overlay/sun5i-a13-fixup.scr-cmd | 48 +++
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arch/arm/boot/dts/overlay/sun5i-a13-i2c1.dts | 22 ++
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arch/arm/boot/dts/overlay/sun5i-a13-i2c2.dts | 22 ++
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arch/arm/boot/dts/overlay/sun5i-a13-nand.dts | 60 +++
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arch/arm/boot/dts/overlay/sun5i-a13-pwm.dts | 15 +
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.../dts/overlay/sun5i-a13-spi-jedec-nor.dts | 57 +++
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.../boot/dts/overlay/sun5i-a13-spi-spidev.dts | 57 +++
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arch/arm/boot/dts/overlay/sun5i-a13-spi0.dts | 38 ++
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arch/arm/boot/dts/overlay/sun5i-a13-spi1.dts | 39 ++
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arch/arm/boot/dts/overlay/sun5i-a13-spi2.dts | 22 ++
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arch/arm/boot/dts/overlay/sun5i-a13-uart0.dts | 32 ++
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arch/arm/boot/dts/overlay/sun5i-a13-uart1.dts | 22 ++
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arch/arm/boot/dts/overlay/sun5i-a13-uart2.dts | 22 ++
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arch/arm/boot/dts/overlay/sun5i-a13-uart3.dts | 22 ++
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.../dts/overlay/sun7i-a20-analog-codec.dts | 13 +
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arch/arm/boot/dts/overlay/sun7i-a20-can.dts | 15 +
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.../boot/dts/overlay/sun7i-a20-fixup.scr-cmd | 143 +++++++
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arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts | 22 ++
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arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts | 22 ++
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arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts | 22 ++
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arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts | 32 ++
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arch/arm/boot/dts/overlay/sun7i-a20-i2s0.dts | 25 ++
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arch/arm/boot/dts/overlay/sun7i-a20-i2s1.dts | 25 ++
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arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts | 18 +
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arch/arm/boot/dts/overlay/sun7i-a20-nand.dts | 103 ++++++
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.../boot/dts/overlay/sun7i-a20-pps-gpio.dts | 29 ++
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arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts | 15 +
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.../boot/dts/overlay/sun7i-a20-spdif-out.dts | 38 ++
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.../dts/overlay/sun7i-a20-spi-add-cs1.dts | 16 +
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.../dts/overlay/sun7i-a20-spi-jedec-nor.dts | 57 +++
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.../boot/dts/overlay/sun7i-a20-spi-spidev.dts | 57 +++
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arch/arm/boot/dts/overlay/sun7i-a20-spi0.dts | 23 ++
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arch/arm/boot/dts/overlay/sun7i-a20-spi1.dts | 22 ++
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arch/arm/boot/dts/overlay/sun7i-a20-spi2.dts | 23 ++
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arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts | 32 ++
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arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts | 42 +++
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arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts | 22 ++
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arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts | 22 ++
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arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts | 22 ++
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arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts | 22 ++
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.../boot/dts/overlay/sun7i-a20-w1-gpio.dts | 29 ++
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.../dts/overlay/sun8i-h3-analog-codec.dts | 17 +
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arch/arm/boot/dts/overlay/sun8i-h3-cir.dts | 15 +
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.../boot/dts/overlay/sun8i-h3-fixup.scr-cmd | 110 ++++++
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arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts | 20 +
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arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts | 20 +
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arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts | 20 +
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.../boot/dts/overlay/sun8i-h3-pps-gpio.dts | 29 ++
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arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts | 39 ++
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.../boot/dts/overlay/sun8i-h3-spdif-out.dts | 38 ++
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.../boot/dts/overlay/sun8i-h3-spi-add-cs1.dts | 41 +++
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.../dts/overlay/sun8i-h3-spi-jedec-nor.dts | 42 +++
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.../boot/dts/overlay/sun8i-h3-spi-spidev.dts | 42 +++
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arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts | 22 ++
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arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts | 22 ++
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arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts | 22 ++
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.../boot/dts/overlay/sun8i-h3-usbhost0.dts | 27 ++
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.../boot/dts/overlay/sun8i-h3-usbhost1.dts | 27 ++
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.../boot/dts/overlay/sun8i-h3-usbhost2.dts | 27 ++
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.../boot/dts/overlay/sun8i-h3-usbhost3.dts | 27 ++
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.../arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts | 29 ++
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arch/arm/boot/dts/overlay/sun8i-r40-i2c2.dts | 20 +
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arch/arm/boot/dts/overlay/sun8i-r40-i2c3.dts | 20 +
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.../dts/overlay/sun8i-r40-spi-spidev0.dts | 27 ++
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.../dts/overlay/sun8i-r40-spi-spidev1.dts | 27 ++
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arch/arm/boot/dts/overlay/sun8i-r40-uart2.dts | 22 ++
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arch/arm/boot/dts/overlay/sun8i-r40-uart4.dts | 22 ++
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arch/arm/boot/dts/overlay/sun8i-r40-uart5.dts | 22 ++
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arch/arm/boot/dts/overlay/sun8i-r40-uart7.dts | 22 ++
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97 files changed, 4176 insertions(+)
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create mode 100644 arch/arm/boot/dts/overlay/Makefile
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create mode 100644 arch/arm/boot/dts/overlay/README.sun4i-a10-overlays
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create mode 100644 arch/arm/boot/dts/overlay/README.sun5i-a13-overlays
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create mode 100644 arch/arm/boot/dts/overlay/README.sun7i-a20-overlays
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create mode 100644 arch/arm/boot/dts/overlay/README.sun8i-h3-overlays
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-can.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-nand.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-spi0.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-spi1.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-spi2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-analog-codec.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-fixup.scr-cmd
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-i2c1.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-i2c2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-nand.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-pwm.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-spi-jedec-nor.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-spi-spidev.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-spi0.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-spi1.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-spi2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-uart0.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-uart1.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-uart2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun5i-a13-uart3.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-can.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-i2s0.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-i2s1.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-nand.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-spi-add-cs1.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-spi0.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-spi1.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-spi2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-cir.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-usbhost1.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-i2c2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-i2c3.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev0.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev1.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-uart2.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-uart4.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-uart5.dts
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create mode 100644 arch/arm/boot/dts/overlay/sun8i-r40-uart7.dts
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diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
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index 32710062a..b0f6a635b 100644
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -1647,3 +1647,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
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aspeed-bmc-vegman-n110.dtb \
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aspeed-bmc-vegman-rx20.dtb \
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aspeed-bmc-vegman-sx20.dtb
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+
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+subdir-y := overlay
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diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
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new file mode 100644
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index 000000000..d2e94f6b7
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlay/Makefile
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@@ -0,0 +1,97 @@
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+# SPDX-License-Identifier: GPL-2.0
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+dtbo-$(CONFIG_MACH_SUN4I) += \
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+ sun4i-a10-analog-codec.dtbo \
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+ sun4i-a10-can.dtbo \
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+ sun4i-a10-i2c1.dtbo \
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+ sun4i-a10-i2c2.dtbo \
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+ sun4i-a10-nand.dtbo \
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+ sun4i-a10-pps-gpio.dtbo \
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+ sun4i-a10-pwm.dtbo \
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+ sun4i-a10-spdif-out.dtbo \
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+ sun4i-a10-spi-jedec-nor.dtbo \
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+ sun4i-a10-spi-spidev.dtbo \
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+ sun4i-a10-uart2.dtbo \
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|
+ sun4i-a10-uart3.dtbo \
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+ sun4i-a10-uart4.dtbo \
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|
+ sun4i-a10-uart5.dtbo \
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+ sun4i-a10-uart6.dtbo \
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+ sun4i-a10-uart7.dtbo \
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+ sun4i-a10-w1-gpio.dtbo
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+
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+dtbo-$(CONFIG_MACH_SUN5I) += \
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+ sun5i-a13-analog-codec.dtbo \
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+ sun5i-a13-i2c1.dtbo \
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+ sun5i-a13-i2c2.dtbo \
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|
+ sun5i-a13-nand.dtbo \
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|
+ sun5i-a13-pwm.dtbo \
|
|
+ sun5i-a13-spi0.dtbo \
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+ sun5i-a13-spi1.dtbo \
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|
+ sun5i-a13-spi2.dtbo \
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|
+ sun5i-a13-spi-jedec-nor.dtbo \
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|
+ sun5i-a13-spi-spidev.dtbo \
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|
+ sun5i-a13-uart0.dtbo \
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+ sun5i-a13-uart1.dtbo \
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+ sun5i-a13-uart2.dtbo \
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+ sun5i-a13-uart3.dtbo
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+
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+dtbo-$(CONFIG_MACH_SUN7I) += \
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|
+ sun7i-a20-analog-codec.dtbo \
|
|
+ sun7i-a20-can.dtbo \
|
|
+ sun7i-a20-i2c1.dtbo \
|
|
+ sun7i-a20-i2c2.dtbo \
|
|
+ sun7i-a20-i2c3.dtbo \
|
|
+ sun7i-a20-i2c4.dtbo \
|
|
+ sun7i-a20-mmc2.dtbo \
|
|
+ sun7i-a20-nand.dtbo \
|
|
+ sun7i-a20-pps-gpio.dtbo \
|
|
+ sun7i-a20-pwm.dtbo \
|
|
+ sun7i-a20-spdif-out.dtbo \
|
|
+ sun7i-a20-spi-add-cs1.dtbo \
|
|
+ sun7i-a20-spi-jedec-nor.dtbo \
|
|
+ sun7i-a20-spi-spidev.dtbo \
|
|
+ sun7i-a20-uart2.dtbo \
|
|
+ sun7i-a20-uart3.dtbo \
|
|
+ sun7i-a20-uart4.dtbo \
|
|
+ sun7i-a20-uart5.dtbo \
|
|
+ sun7i-a20-uart6.dtbo \
|
|
+ sun7i-a20-uart7.dtbo \
|
|
+ sun7i-a20-w1-gpio.dtbo
|
|
+
|
|
+dtbo-$(CONFIG_MACH_SUN8I) += \
|
|
+ sun8i-h3-analog-codec.dtbo \
|
|
+ sun8i-h3-cir.dtbo \
|
|
+ sun8i-h3-i2c0.dtbo \
|
|
+ sun8i-h3-i2c1.dtbo \
|
|
+ sun8i-h3-i2c2.dtbo \
|
|
+ sun8i-h3-pps-gpio.dtbo \
|
|
+ sun8i-h3-pwm.dtbo \
|
|
+ sun8i-h3-spdif-out.dtbo \
|
|
+ sun8i-h3-spi-add-cs1.dtbo \
|
|
+ sun8i-h3-spi-jedec-nor.dtbo \
|
|
+ sun8i-h3-spi-spidev.dtbo \
|
|
+ sun8i-h3-uart1.dtbo \
|
|
+ sun8i-h3-uart2.dtbo \
|
|
+ sun8i-h3-uart3.dtbo \
|
|
+ sun8i-h3-usbhost0.dtbo \
|
|
+ sun8i-h3-usbhost1.dtbo \
|
|
+ sun8i-h3-usbhost2.dtbo \
|
|
+ sun8i-h3-usbhost3.dtbo \
|
|
+ sun8i-h3-w1-gpio.dtbo \
|
|
+ sun8i-r40-i2c2.dtbo \
|
|
+ sun8i-r40-i2c3.dtbo \
|
|
+ sun8i-r40-spi-spidev0.dtbo \
|
|
+ sun8i-r40-spi-spidev1.dtbo \
|
|
+ sun8i-r40-uart2.dtbo \
|
|
+ sun8i-r40-uart4.dtbo \
|
|
+ sun8i-r40-uart5.dtbo \
|
|
+ sun8i-r40-uart7.dtbo
|
|
+
|
|
+scr-$(CONFIG_MACH_SUN4I) += sun4i-a10-fixup.scr
|
|
+scr-$(CONFIG_MACH_SUN5I) += sun5i-a13-fixup.scr
|
|
+scr-$(CONFIG_MACH_SUN7I) += sun7i-a20-fixup.scr
|
|
+scr-$(CONFIG_MACH_SUN8I) += sun8i-h3-fixup.scr
|
|
+
|
|
+dtbotxt-$(CONFIG_MACH_SUN4I) += README.sun4i-a10-overlays
|
|
+dtbotxt-$(CONFIG_MACH_SUN5I) += README.sun5i-a13-overlays
|
|
+dtbotxt-$(CONFIG_MACH_SUN7I) += README.sun7i-a20-overlays
|
|
+dtbotxt-$(CONFIG_MACH_SUN8I) += README.sun8i-h3-overlays
|
|
diff --git a/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays b/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays
|
|
new file mode 100644
|
|
index 000000000..e0795f13d
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays
|
|
@@ -0,0 +1,278 @@
|
|
+This document describes overlays provided in the kernel packages
|
|
+For generic Armbian overlays documentation please see
|
|
+https://docs.armbian.com/User-Guide_Allwinner_overlays/
|
|
+
|
|
+### Platform:
|
|
+
|
|
+sun4i-a10 (Allwinner A10)
|
|
+
|
|
+### Platform details:
|
|
+
|
|
+Supported pin banks: PB, PC, PD, PE, PG, PH, PI
|
|
+
|
|
+SPI controller 0 have 2 exposed hardware CS,
|
|
+other SPI controllers have only one hardware CS
|
|
+Reference: A10 User manual section 17.4.13, A10 datasheet section 5.2
|
|
+
|
|
+I2C bus 0 is used for the AXP209 PMIC
|
|
+
|
|
+### Provided overlays:
|
|
+
|
|
+- analog-codec
|
|
+- can
|
|
+- i2c1
|
|
+- i2c2
|
|
+- nand
|
|
+- pps-gpio
|
|
+- pwm
|
|
+- spdif-out
|
|
+- spi0
|
|
+- spi1
|
|
+- spi2
|
|
+- spi-jedec-nor
|
|
+- spi-spidev
|
|
+- uart1
|
|
+- uart2
|
|
+- uart3
|
|
+- uart4
|
|
+- uart5
|
|
+- uart6
|
|
+- uart7
|
|
+- w1-gpio
|
|
+
|
|
+### Overlay details:
|
|
+
|
|
+### analog-codec
|
|
+
|
|
+Activates SoC analog codec driver that provides Line Out and Mic In
|
|
+functionality
|
|
+
|
|
+## can
|
|
+
|
|
+Activates SoC CAN controller
|
|
+
|
|
+CAN pins (TX, RX): PH20, PH21
|
|
+
|
|
+### i2c1
|
|
+
|
|
+Activates TWI/I2C bus 1
|
|
+
|
|
+I2C1 pins (SCL, SDA): PB18, PB19
|
|
+
|
|
+### i2c2
|
|
+
|
|
+Activates TWI/I2C bus 2
|
|
+
|
|
+I2C2 pins (SCL, SDA): PB20, PB21
|
|
+
|
|
+### nand
|
|
+
|
|
+Activates NAND controller
|
|
+
|
|
+This overlay should not be used until mainline MLC NAND support
|
|
+allows using NAND storage reliably
|
|
+
|
|
+### pps-gpio
|
|
+
|
|
+Activates pulse-per-second GPIO client
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_pps_pin (pin)
|
|
+ Pin PPS source is connected to
|
|
+ Optional
|
|
+ Default: PI15
|
|
+
|
|
+param_pps_falling_edge (bool)
|
|
+ Assert by falling edge
|
|
+ Optional
|
|
+ Default: 0
|
|
+ When set (to 1), assert is indicated by a falling edge
|
|
+ (instead of by a rising edge)
|
|
+
|
|
+### pwm
|
|
+
|
|
+Activates hardware PWM controller
|
|
+
|
|
+PWM pins (PWM0, PWM1): PB2, PI3
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_pwm_pins (string)
|
|
+ PWM pins activated with this overlay
|
|
+ Optional
|
|
+ Default: both
|
|
+ Supported values: 0, 1, both
|
|
+ If set to 0 only PWM0 can be used,
|
|
+ if set to 1 then only PWM1 can be used,
|
|
+ if set to both (default), both PWM0 and PWM1 can be used
|
|
+
|
|
+### spdif-out
|
|
+
|
|
+Activates SPDIF/Toslink audio output
|
|
+
|
|
+SPDIF pin: PB13
|
|
+
|
|
+### spi0
|
|
+
|
|
+Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it
|
|
+
|
|
+SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
|
|
+
|
|
+### spi1
|
|
+
|
|
+Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it
|
|
+
|
|
+SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
|
|
+
|
|
+### spi2
|
|
+
|
|
+Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it
|
|
+
|
|
+SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
|
|
+SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_spi2_bus_pins (char)
|
|
+ SPI bus 2 pinmux variant
|
|
+ Optional
|
|
+ Default: a
|
|
+ Supported values: a, b
|
|
+ Determines what pins SPI bus 2 is exposed on if SPI 2 is used
|
|
+
|
|
+
|
|
+### spi-jedec-nor
|
|
+
|
|
+Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
|
|
+supported by the kernel SPI NOR driver
|
|
+
|
|
+SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
|
|
+SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
|
|
+SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
|
|
+SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_spinor_spi_bus (int)
|
|
+ SPI bus to activate SPI NOR flash support on
|
|
+ Required
|
|
+ Supported values: 0, 1, 2
|
|
+
|
|
+param_spinor_max_freq (int)
|
|
+ Maximum SPI frequency
|
|
+ Optional
|
|
+ Default: 1000000
|
|
+ Range: 3000 - 100000000
|
|
+
|
|
+### spi-spidev
|
|
+
|
|
+Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
|
|
+where X is the bus number and Y is the CS number
|
|
+
|
|
+SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
|
|
+SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
|
|
+SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
|
|
+SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_spidev_spi_bus (int)
|
|
+ SPI bus to activate mcp2515 support on
|
|
+ Required
|
|
+ Supported values: 0, 1, 2
|
|
+
|
|
+param_spidev_max_freq (int)
|
|
+ Maximum SPIdev frequency
|
|
+ Optional
|
|
+ Default: 1000000
|
|
+ Range: 3000 - 100000000
|
|
+
|
|
+### uart2
|
|
+
|
|
+Activates serial port 2 (/dev/ttyS2)
|
|
+
|
|
+UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_uart2_rtscts (bool)
|
|
+ Enable RTS and CTS pins
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Set to 1 to enable CTS and RTS pins
|
|
+
|
|
+### uart3
|
|
+
|
|
+Activates serial port 3 (/dev/ttyS3)
|
|
+
|
|
+UART 3 pins a (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
|
|
+UART 3 pins b (TX, RX, RTS, CTS): PH0, PH1, PH2, PH3
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_uart3_pins (char)
|
|
+ Determines what pins UART 3 is exposed on
|
|
+ Optional
|
|
+ Default: a
|
|
+ Supported values: a, b
|
|
+
|
|
+param_uart3_rtscts (bool)
|
|
+ Enable RTS and CTS pins
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Set to 1 to enable CTS and RTS pins
|
|
+
|
|
+### uart4
|
|
+
|
|
+Activates serial port 4 (/dev/ttyS4)
|
|
+
|
|
+UART 4 pins a (TX, RX): PG10, PG11
|
|
+UART 4 pins b (TX, RX): PH4, PH5
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_uart4_pins (char)
|
|
+ Determines what pins UART 4 is exposed on
|
|
+ Optional
|
|
+ Default: a
|
|
+ Supported values: a, b
|
|
+
|
|
+### uart 5
|
|
+
|
|
+Activates serial port 5 (/dev/ttyS5)
|
|
+
|
|
+UART 5 pins (TX, RX): PH6, PH7
|
|
+
|
|
+### uart 6
|
|
+
|
|
+Activates serial port 6 (/dev/ttyS6)
|
|
+
|
|
+UART 6 pins (TX, RX): PI12, PI13
|
|
+
|
|
+### uart 7
|
|
+
|
|
+Activates serial port 7 (/dev/ttyS7)
|
|
+
|
|
+UART 7 pins (TX, RX): PI20, PI21
|
|
+
|
|
+### w1-gpio
|
|
+
|
|
+Activates 1-Wire GPIO master
|
|
+Requires an external pull-up resistor on the data pin
|
|
+or enabling the internal pull-up
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_w1_pin (pin)
|
|
+ Data pin for 1-Wire master
|
|
+ Optional
|
|
+ Default: PI15
|
|
+
|
|
+param_w1_pin_int_pullup (bool)
|
|
+ Enable internal pull-up for the data pin
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Set to 1 to enable the pull-up
|
|
+ This option should not be used with multiple sensors or long wires -
|
|
+ please use external pull-up resistor instead
|
|
diff --git a/arch/arm/boot/dts/overlay/README.sun5i-a13-overlays b/arch/arm/boot/dts/overlay/README.sun5i-a13-overlays
|
|
new file mode 100644
|
|
index 000000000..9f9653f09
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/README.sun5i-a13-overlays
|
|
@@ -0,0 +1,172 @@
|
|
+This document describes overlays provided in the kernel packages
|
|
+For generic Armbian overlays documentation please see
|
|
+https://docs.armbian.com/User-Guide_Allwinner_overlays/
|
|
+
|
|
+### Platform:
|
|
+
|
|
+sun5i-a13 (Allwinner A13)
|
|
+
|
|
+### Platform details:
|
|
+
|
|
+I2C bus 0 is used for the AXP209 PMIC
|
|
+
|
|
+### Provided overlays:
|
|
+
|
|
+- analog-codec
|
|
+- i2c1
|
|
+- i2c2
|
|
+- nand
|
|
+- pwm
|
|
+- spi0
|
|
+- spi1
|
|
+- spi2
|
|
+- spi-jedec-nor
|
|
+- spi-spidev
|
|
+- uart0
|
|
+- uart1
|
|
+- uart2
|
|
+- uart3
|
|
+
|
|
+### Overlay details:
|
|
+
|
|
+### analog-codec
|
|
+
|
|
+Activates SoC analog codec driver that provides HP Out and Mic In
|
|
+functionality
|
|
+
|
|
+### i2c1
|
|
+
|
|
+Activates TWI/I2C bus 1
|
|
+
|
|
+I2C1 pins (SCL, SDA): PB15, PB16
|
|
+
|
|
+### i2c2
|
|
+
|
|
+Activates TWI/I2C bus 2
|
|
+
|
|
+I2C2 pins (SCL, SDA): PB17, PB18
|
|
+
|
|
+### nand
|
|
+
|
|
+Activates NAND controller
|
|
+
|
|
+This overlay should not be used until mainline MLC NAND support
|
|
+allows using NAND storage reliably
|
|
+
|
|
+### pwm
|
|
+
|
|
+Activates hardware PWM controller
|
|
+
|
|
+PWM pins (PWM0): PB2
|
|
+
|
|
+### spi0
|
|
+
|
|
+Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it
|
|
+
|
|
+SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3
|
|
+
|
|
+### spi1
|
|
+
|
|
+Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it
|
|
+
|
|
+SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9
|
|
+
|
|
+### spi2
|
|
+
|
|
+Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it
|
|
+
|
|
+SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0
|
|
+
|
|
+### spi-jedec-nor
|
|
+
|
|
+Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
|
|
+supported by the kernel SPI NOR driver
|
|
+
|
|
+SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3
|
|
+SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9
|
|
+SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_spinor_spi_bus (int)
|
|
+ SPI bus to activate SPI NOR flash support on
|
|
+ Required
|
|
+ Supported values: 0, 1, 2
|
|
+
|
|
+param_spinor_max_freq (int)
|
|
+ Maximum SPI frequency
|
|
+ Optional
|
|
+ Default: 1000000
|
|
+ Range: 3000 - 100000000
|
|
+
|
|
+### spi-spidev
|
|
+
|
|
+Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
|
|
+where X is the bus number and Y is the CS number
|
|
+
|
|
+SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3
|
|
+SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9
|
|
+SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_spidev_spi_bus (int)
|
|
+ SPI bus to activate mcp2515 support on
|
|
+ Required
|
|
+ Supported values: 0, 1, 2
|
|
+
|
|
+param_spidev_max_freq (int)
|
|
+ Maximum SPIdev frequency
|
|
+ Optional
|
|
+ Default: 1000000
|
|
+ Range: 3000 - 100000000
|
|
+
|
|
+### uart 0
|
|
+
|
|
+Activates serial port 0 (/dev/ttyS0)
|
|
+
|
|
+UART 0 pins (TX, RX): PF2, PF4
|
|
+
|
|
+### uart 1
|
|
+
|
|
+Activates serial port 1 (/dev/ttyS1)
|
|
+
|
|
+UART 1 pins a (TX, RX): PE10, PE11
|
|
+UART 1 pins b (TX, RX): PG3, PG4
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_uart1_pins (char)
|
|
+ UART 1 pinmux variant
|
|
+ Optional
|
|
+ Default: a
|
|
+ Supported values: a, b
|
|
+ Determines what pins UART 1 is exposed on if UART 1 is used
|
|
+
|
|
+### uart2
|
|
+
|
|
+Activates serial port 2 (/dev/ttyS2)
|
|
+
|
|
+UART 2 pins (TX, RX, RTS, CTS): PD2, PD3, PD4, PD5
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_uart2_rtscts (bool)
|
|
+ Enable RTS and CTS pins
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Set to 1 to enable CTS and RTS pins
|
|
+
|
|
+### uart3
|
|
+
|
|
+Activates serial port 3 (/dev/ttyS3)
|
|
+
|
|
+UART 3 pins (TX, RX, RTS, CTS): PG9, PG10, PG12, PG11
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_uart3_rtscts (bool)
|
|
+ Enable RTS and CTS pins
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Set to 1 to enable CTS and RTS pins
|
|
diff --git a/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays
|
|
new file mode 100644
|
|
index 000000000..362f87961
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays
|
|
@@ -0,0 +1,348 @@
|
|
+This document describes overlays provided in the kernel packages
|
|
+For generic Armbian overlays documentation please see
|
|
+https://docs.armbian.com/User-Guide_Allwinner_overlays/
|
|
+
|
|
+### Platform:
|
|
+
|
|
+sun7i-a20 (Allwinner A20)
|
|
+
|
|
+### Platform details:
|
|
+
|
|
+Supported pin banks: PB, PC, PD, PE, PG, PH, PI
|
|
+
|
|
+SPI controller 0 have 2 exposed hardware CS,
|
|
+other SPI controllers have only one hardware CS
|
|
+Reference: A20 Datasheet sections 6.3.5.1, 1.19.2
|
|
+
|
|
+I2C bus 0 is used for the AXP209 PMIC
|
|
+
|
|
+### Provided overlays:
|
|
+
|
|
+- analog-codec
|
|
+- can
|
|
+- i2c1
|
|
+- i2c2
|
|
+- i2c3
|
|
+- i2c4
|
|
+- i2s0
|
|
+- i2s1
|
|
+- mmc2
|
|
+- nand
|
|
+- pps-gpio
|
|
+- pwm
|
|
+- spdif-out
|
|
+- spi0
|
|
+- spi1
|
|
+- spi2
|
|
+- spi-add-cs1
|
|
+- spi-jedec-nor
|
|
+- spi-spidev
|
|
+- uart1
|
|
+- uart2
|
|
+- uart3
|
|
+- uart4
|
|
+- uart5
|
|
+- uart6
|
|
+- uart7
|
|
+- w1-gpio
|
|
+
|
|
+### Overlay details:
|
|
+
|
|
+### analog-codec
|
|
+
|
|
+Activates SoC analog codec driver that provides Line Out and Mic In
|
|
+functionality
|
|
+
|
|
+## can
|
|
+
|
|
+Activates SoC CAN controller
|
|
+
|
|
+CAN pins (TX, RX): PH20, PH21
|
|
+
|
|
+### i2c1
|
|
+
|
|
+Activates TWI/I2C bus 1
|
|
+
|
|
+I2C1 pins (SCL, SDA): PB18, PB19
|
|
+
|
|
+### i2c2
|
|
+
|
|
+Activates TWI/I2C bus 2
|
|
+
|
|
+I2C2 pins (SCL, SDA): PB20, PB21
|
|
+
|
|
+### i2c3
|
|
+
|
|
+Activates TWI/I2C bus 3
|
|
+
|
|
+I2C3 pins (SCL, SDA): PI0, PI1
|
|
+
|
|
+### i2c4
|
|
+
|
|
+Activates TWI/I2C bus 4
|
|
+
|
|
+I2C4 pins (SCL, SDA): PI2, PI3
|
|
+
|
|
+### i2s0
|
|
+
|
|
+Activates SoC I2S controller 0
|
|
+
|
|
+I2S0 pins (MCLK, BCLK, LRCK, DO0, DO1, DO2, DO3, DI): PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12
|
|
+
|
|
+### i2s1
|
|
+
|
|
+Activates SoC I2S controller 1
|
|
+
|
|
+I2S1 pins (MCLK, BCLK, LRCK, DO, DI): PA9, PA14, PA15, PA16, PA17
|
|
+
|
|
+### mmc2
|
|
+
|
|
+Activates SD/MMC controller 2. To be used on boards with second SD slot, eMMC
|
|
+or tSD instead of NAND storage.
|
|
+
|
|
+MMC2 pins: PC6, PC7, PC8, PC9, PC10, PC11
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_mmc2_cd_pin (pin)
|
|
+ SD/MMC 2 card detect pin
|
|
+ Optional
|
|
+ Default: PH0
|
|
+
|
|
+param_mmc2_non_removable (bool)
|
|
+ Option for non-removable storage options on MMC 2 controller (eMMC or tSD)
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Set to 1 to use this option
|
|
+
|
|
+### nand
|
|
+
|
|
+Activates NAND controller
|
|
+
|
|
+This overlay should not be used until mainline MLC NAND support
|
|
+allows using NAND storage reliably
|
|
+
|
|
+### pps-gpio
|
|
+
|
|
+Activates pulse-per-second GPIO client
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_pps_pin (pin)
|
|
+ Pin PPS source is connected to
|
|
+ Optional
|
|
+ Default: PI15
|
|
+
|
|
+param_pps_falling_edge (bool)
|
|
+ Assert by falling edge
|
|
+ Optional
|
|
+ Default: 0
|
|
+ When set (to 1), assert is indicated by a falling edge
|
|
+ (instead of by a rising edge)
|
|
+
|
|
+### pwm
|
|
+
|
|
+Activates hardware PWM controller
|
|
+
|
|
+PWM pins (PWM0, PWM1): PB2, PI3
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_pwm_pins (string)
|
|
+ PWM pins activated with this overlay
|
|
+ Optional
|
|
+ Default: both
|
|
+ Supported values: 0, 1, both
|
|
+ If set to 0 only PWM0 can be used,
|
|
+ if set to 1 then only PWM1 can be used,
|
|
+ if set to both (default), both PWM0 and PWM1 can be used
|
|
+
|
|
+### spdif-out
|
|
+
|
|
+Activates SPDIF/Toslink audio output
|
|
+
|
|
+SPDIF pin: PB13
|
|
+
|
|
+### spi0
|
|
+
|
|
+Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it
|
|
+
|
|
+SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
|
|
+
|
|
+### spi1
|
|
+
|
|
+Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it
|
|
+
|
|
+SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
|
|
+
|
|
+### spi2
|
|
+
|
|
+Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it
|
|
+
|
|
+SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
|
|
+SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_spi2_bus_pins (char)
|
|
+ SPI bus 2 pinmux variant
|
|
+ Optional
|
|
+ Default: a
|
|
+ Supported values: a, b
|
|
+ Determines what pins SPI bus 2 is exposed on if SPI 2 is used
|
|
+
|
|
+### spi-add-cs1
|
|
+
|
|
+Activates SPI chip select 1 on SPI controller 0
|
|
+This overlay is required for using chip select 1 with other SPI overlays
|
|
+
|
|
+SPI 0 CS1 pin: PI14
|
|
+
|
|
+### spi-jedec-nor
|
|
+
|
|
+Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
|
|
+supported by the kernel SPI NOR driver
|
|
+
|
|
+SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
|
|
+SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
|
|
+SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
|
|
+SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_spinor_spi_bus (int)
|
|
+ SPI bus to activate SPI NOR flash support on
|
|
+ Required
|
|
+ Supported values: 0, 1, 2
|
|
+
|
|
+param_spinor_spi_cs (int)
|
|
+ SPI chip select number for SPI NOR connected to SPI bus 0
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Supported values: 0, 1
|
|
+ Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay
|
|
+
|
|
+param_spinor_max_freq (int)
|
|
+ Maximum SPI frequency
|
|
+ Optional
|
|
+ Default: 1000000
|
|
+ Range: 3000 - 100000000
|
|
+
|
|
+### spi-spidev
|
|
+
|
|
+Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
|
|
+where X is the bus number and Y is the CS number
|
|
+
|
|
+SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
|
|
+SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
|
|
+SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
|
|
+SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_spidev_spi_bus (int)
|
|
+ SPI bus to activate mcp2515 support on
|
|
+ Required
|
|
+ Supported values: 0, 1, 2
|
|
+
|
|
+param_spidev_spi_cs (int)
|
|
+ SPI chip select number for SPIdev on SPI bus 0
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Supported values: 0, 1
|
|
+ Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay
|
|
+
|
|
+param_spidev_max_freq (int)
|
|
+ Maximum SPIdev frequency
|
|
+ Optional
|
|
+ Default: 1000000
|
|
+ Range: 3000 - 100000000
|
|
+
|
|
+### uart2
|
|
+
|
|
+Activates serial port 2 (/dev/ttyS2)
|
|
+
|
|
+UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_uart2_rtscts (bool)
|
|
+ Enable RTS and CTS pins
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Set to 1 to enable CTS and RTS pins
|
|
+
|
|
+### uart3
|
|
+
|
|
+Activates serial port 3 (/dev/ttyS3)
|
|
+
|
|
+UART 3 pins a (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
|
|
+UART 3 pins b (TX, RX, RTS, CTS): PH0, PH1, PH2, PH3
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_uart3_pins (char)
|
|
+ Determines what pins UART 3 is exposed on
|
|
+ Optional
|
|
+ Default: a
|
|
+ Supported values: a, b
|
|
+
|
|
+param_uart3_rtscts (bool)
|
|
+ Enable RTS and CTS pins
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Set to 1 to enable CTS and RTS pins
|
|
+
|
|
+### uart4
|
|
+
|
|
+Activates serial port 4 (/dev/ttyS4)
|
|
+
|
|
+UART 4 pins a (TX, RX): PG10, PG11
|
|
+UART 4 pins b (TX, RX): PH4, PH5
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_uart4_pins (char)
|
|
+ Determines what pins UART 4 is exposed on
|
|
+ Optional
|
|
+ Default: a
|
|
+ Supported values: a, b
|
|
+
|
|
+### uart 5
|
|
+
|
|
+Activates serial port 5 (/dev/ttyS5)
|
|
+
|
|
+UART 5 pins (TX, RX): PH6, PH7
|
|
+
|
|
+### uart 6
|
|
+
|
|
+Activates serial port 6 (/dev/ttyS6)
|
|
+
|
|
+UART 6 pins (TX, RX): PI12, PI13
|
|
+
|
|
+### uart 7
|
|
+
|
|
+Activates serial port 7 (/dev/ttyS7)
|
|
+
|
|
+UART 7 pins (TX, RX): PI20, PI21
|
|
+
|
|
+### w1-gpio
|
|
+
|
|
+Activates 1-Wire GPIO master
|
|
+Requires an external pull-up resistor on the data pin
|
|
+or enabling the internal pull-up
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_w1_pin (pin)
|
|
+ Data pin for 1-Wire master
|
|
+ Optional
|
|
+ Default: PI15
|
|
+
|
|
+param_w1_pin_int_pullup (bool)
|
|
+ Enable internal pull-up for the data pin
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Set to 1 to enable the pull-up
|
|
+ This option should not be used with multiple sensors or long wires -
|
|
+ please use external pull-up resistor instead
|
|
diff --git a/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays
|
|
new file mode 100644
|
|
index 000000000..302973491
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays
|
|
@@ -0,0 +1,250 @@
|
|
+This document describes overlays provided in the kernel packages
|
|
+For generic Armbian overlays documentation please see
|
|
+https://docs.armbian.com/User-Guide_Allwinner_overlays/
|
|
+
|
|
+### Platform:
|
|
+
|
|
+sun8i-h3 (Allwinner H3)
|
|
+
|
|
+### Platform details:
|
|
+
|
|
+Supported pin banks: PA, PC, PD, PG
|
|
+
|
|
+Both SPI controllers have only one hardware CS pin exposed,
|
|
+adding fixed software (GPIO) chip selects is possible with a separate overlay
|
|
+
|
|
+### Provided overlays:
|
|
+
|
|
+- analog-codec
|
|
+- cir
|
|
+- i2c0
|
|
+- i2c1
|
|
+- i2c2
|
|
+- pps-gpio
|
|
+- pwm
|
|
+- spdif-out
|
|
+- spi-add-cs1
|
|
+- spi-jedec-nor
|
|
+- spi-spidev
|
|
+- uart1
|
|
+- uart2
|
|
+- uart3
|
|
+- usbhost0
|
|
+- usbhost1
|
|
+- usbhost2
|
|
+- usbhost3
|
|
+- w1-gpio
|
|
+
|
|
+### Overlay details:
|
|
+
|
|
+### analog-codec
|
|
+
|
|
+Activates SoC analog codec driver that provides Line Out and Mic In
|
|
+functionality
|
|
+
|
|
+### cir
|
|
+
|
|
+Activates CIR (Infrared remote) receiver
|
|
+
|
|
+CIR pin: PL11
|
|
+
|
|
+### i2c0
|
|
+
|
|
+Activates TWI/I2C bus 0
|
|
+
|
|
+I2C0 pins (SCL, SDA): PA11, PA12
|
|
+
|
|
+### i2c1
|
|
+
|
|
+Activates TWI/I2C bus 1
|
|
+
|
|
+I2C1 pins (SCL, SDA): PA18, PA19
|
|
+
|
|
+### i2c2
|
|
+
|
|
+Activates TWI/I2C bus 2
|
|
+
|
|
+I2C2 pins (SCL, SDA): PE12, PE13
|
|
+
|
|
+On most board this bus is wired to Camera (CSI) socket
|
|
+
|
|
+### pps-gpio
|
|
+
|
|
+Activates pulse-per-second GPIO client
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_pps_pin (pin)
|
|
+ Pin PPS source is connected to
|
|
+ Optional
|
|
+ Default: PD14
|
|
+
|
|
+param_pps_falling_edge (bool)
|
|
+ Assert by falling edge
|
|
+ Optional
|
|
+ Default: 0
|
|
+ When set (to 1), assert is indicated by a falling edge
|
|
+ (instead of by a rising edge)
|
|
+
|
|
+### pwm
|
|
+
|
|
+Activates hardware PWM controller
|
|
+
|
|
+PWM pin: PA5
|
|
+
|
|
+Pin PA5 is used as UART0 RX by default, so if this overlay is activated,
|
|
+UART0 and kernel console on ttyS0 will be disabled
|
|
+
|
|
+### spdif-out
|
|
+
|
|
+Activates SPDIF/Toslink audio output
|
|
+
|
|
+SPDIF pin: PA17
|
|
+
|
|
+### spi-add-cs1
|
|
+
|
|
+Adds support for using SPI chip select 1 with GPIO for both SPI controllers
|
|
+Respective GPIO will be claimed only if controller is enabled by another
|
|
+overlay
|
|
+This overlay is required for using chip select 1 with other SPI overlays
|
|
+Due to the u-boot limitations CS1 pin can't be customized by a parameter, but
|
|
+it can be changed by using an edited copy of this overlay
|
|
+A total of 4 chip selects can be used with custom overlays (1 HW + 3 GPIO)
|
|
+
|
|
+SPI 0 pins (CS1): PA21
|
|
+SPI 1 pins (CS1): PA10
|
|
+
|
|
+### spi-jedec-nor
|
|
+
|
|
+Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
|
|
+supported by the kernel SPI NOR driver
|
|
+
|
|
+SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
|
|
+SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_spinor_spi_bus (int)
|
|
+ SPI bus to activate SPI NOR flash support on
|
|
+ Required
|
|
+ Supported values: 0, 1
|
|
+
|
|
+param_spinor_spi_cs (int)
|
|
+ SPI chip select number
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Supported values: 0, 1
|
|
+ Using chip select 1 requires using "spi-add-cs1" overlay
|
|
+
|
|
+param_spinor_max_freq (int)
|
|
+ Maximum SPI frequency
|
|
+ Optional
|
|
+ Default: 1000000
|
|
+ Range: 3000 - 100000000
|
|
+
|
|
+### spi-spidev
|
|
+
|
|
+Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
|
|
+where X is the bus number and Y is the CS number
|
|
+
|
|
+SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
|
|
+SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_spidev_spi_bus (int)
|
|
+ SPI bus to activate SPIdev support on
|
|
+ Required
|
|
+ Supported values: 0, 1
|
|
+
|
|
+param_spidev_spi_cs (int)
|
|
+ SPI chip select number
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Supported values: 0, 1
|
|
+ Using chip select 1 requires using "spi-add-cs1" overlay
|
|
+
|
|
+param_spidev_max_freq (int)
|
|
+ Maximum SPIdev frequency
|
|
+ Optional
|
|
+ Default: 1000000
|
|
+ Range: 3000 - 100000000
|
|
+
|
|
+### uart1
|
|
+
|
|
+Activates serial port 1 (/dev/ttyS1)
|
|
+
|
|
+UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_uart1_rtscts (bool)
|
|
+ Enable RTS and CTS pins
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Set to 1 to enable
|
|
+
|
|
+### uart2
|
|
+
|
|
+Activates serial port 2 (/dev/ttyS2)
|
|
+
|
|
+UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_uart2_rtscts (bool)
|
|
+ Enable RTS and CTS pins
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Set to 1 to enable CTS and RTS pins
|
|
+
|
|
+### uart3
|
|
+
|
|
+Activates serial port 3 (/dev/ttyS3)
|
|
+
|
|
+UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_uart3_rtscts (bool)
|
|
+ Enable RTS and CTS pins
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Set to 1 to enable CTS and RTS pins
|
|
+
|
|
+### usbhost0
|
|
+
|
|
+Activates USB host controller 0
|
|
+
|
|
+### usbhost1
|
|
+
|
|
+Activates USB host controller 1
|
|
+
|
|
+### usbhost2
|
|
+
|
|
+Activates USB host controller 2
|
|
+
|
|
+### usbhost3
|
|
+
|
|
+Activates USB host controller 3
|
|
+
|
|
+### w1-gpio
|
|
+
|
|
+Activates 1-Wire GPIO master
|
|
+Requires an external pull-up resistor on the data pin
|
|
+or enabling the internal pull-up
|
|
+
|
|
+Parameters:
|
|
+
|
|
+param_w1_pin (pin)
|
|
+ Data pin for 1-Wire master
|
|
+ Optional
|
|
+ Default: PD14
|
|
+
|
|
+param_w1_pin_int_pullup (bool)
|
|
+ Enable internal pull-up for the data pin
|
|
+ Optional
|
|
+ Default: 0
|
|
+ Set to 1 to enable the pull-up
|
|
+ This option should not be used with multiple devices, parasite power setup
|
|
+ or long wires - please use external pull-up resistor instead
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts b/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts
|
|
new file mode 100644
|
|
index 000000000..9254e22e0
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts
|
|
@@ -0,0 +1,13 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&codec>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-can.dts b/arch/arm/boot/dts/overlay/sun4i-a10-can.dts
|
|
new file mode 100644
|
|
index 000000000..1a9511d19
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-can.dts
|
|
@@ -0,0 +1,15 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&can0>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&can0_ph_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd
|
|
new file mode 100644
|
|
index 000000000..c5614cb95
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd
|
|
@@ -0,0 +1,124 @@
|
|
+# overlays fixup script
|
|
+# implements (or rather substitutes) overlay arguments functionality
|
|
+# using u-boot scripting, environment variables and "fdt" command
|
|
+
|
|
+# setexpr test_var ${tmp_bank} - A
|
|
+# works only for hex numbers (A-F)
|
|
+
|
|
+setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1";
|
|
+setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
|
|
+test "${tmp_bank}" = "B" && setenv tmp_bank 1;
|
|
+test "${tmp_bank}" = "C" && setenv tmp_bank 2;
|
|
+test "${tmp_bank}" = "D" && setenv tmp_bank 3;
|
|
+test "${tmp_bank}" = "E" && setenv tmp_bank 4;
|
|
+test "${tmp_bank}" = "G" && setenv tmp_bank 6;
|
|
+test "${tmp_bank}" = "H" && setenv tmp_bank 7;
|
|
+test "${tmp_bank}" = "I" && setenv tmp_bank 8'
|
|
+
|
|
+if test -n "${param_spinor_spi_bus}"; then
|
|
+ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
|
|
+ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
|
|
+ test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
|
|
+ fdt set /soc/${tmp_spi_path} status "okay"
|
|
+ fdt set /soc/${tmp_spi_path}/spiflash status "okay"
|
|
+ if test -n "${param_spinor_max_freq}"; then
|
|
+ fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
|
|
+ fi
|
|
+ env delete tmp_spi_path
|
|
+fi
|
|
+
|
|
+if test -n "${param_spidev_spi_bus}"; then
|
|
+ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
|
|
+ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
|
|
+ test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
|
|
+ fdt set /soc/${tmp_spi_path} status "okay"
|
|
+ fdt set /soc/${tmp_spi_path}/spidev status "okay"
|
|
+ if test -n "${param_spidev_max_freq}"; then
|
|
+ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
|
|
+ fi
|
|
+ env delete tmp_spi_path
|
|
+fi
|
|
+
|
|
+if test "${param_spi2_bus_pins}" = "b"; then
|
|
+ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/spi2@1 phandle
|
|
+ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/spi2_cs0@1 phandle
|
|
+ fdt set /soc/spi@1c17000 pinctrl-0 "<${tmp_phandle1}>"
|
|
+ fdt set /soc/spi@1c17000 pinctrl-1 "<${tmp_phandle2}>"
|
|
+ env delete tmp_phandle1 tmp_phandle2
|
|
+fi
|
|
+
|
|
+if test -n "${param_pps_pin}"; then
|
|
+ setenv tmp_bank "${param_pps_pin}"
|
|
+ setenv tmp_pin "${param_pps_pin}"
|
|
+ run decompose_pin
|
|
+ fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}"
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
|
|
+ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
|
|
+ env delete tmp_pin tmp_bank tmp_phandle
|
|
+fi
|
|
+
|
|
+if test "${param_pps_falling_edge}" = "1"; then
|
|
+ fdt set /pps@0 assert-falling-edge
|
|
+fi
|
|
+
|
|
+if test "${param_pwm_pins}" = "0"; then
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm0@0
|
|
+ fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>"
|
|
+ env delete tmp_phandle
|
|
+fi
|
|
+
|
|
+if test "${param_pwm_pins}" = "1"; then
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm1@0
|
|
+ fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>"
|
|
+ env delete tmp_phandle
|
|
+fi
|
|
+
|
|
+if test -n "${param_w1_pin}"; then
|
|
+ setenv tmp_bank "${param_w1_pin}"
|
|
+ setenv tmp_pin "${param_w1_pin}"
|
|
+ run decompose_pin
|
|
+ fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}"
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
|
|
+ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
|
|
+ env delete tmp_pin tmp_bank tmp_phandle
|
|
+fi
|
|
+
|
|
+if test "${param_w1_pin_int_pullup}" = "1"; then
|
|
+ fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up
|
|
+fi
|
|
+
|
|
+if test "${param_uart2_rtscts}" = "1"; then
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800/uart2@0 phandle
|
|
+ fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle}>"
|
|
+ env delete tmp_phandle
|
|
+fi
|
|
+
|
|
+if test "${param_uart3_pins}" = "b"; then
|
|
+ if test "${param_uart3_rtscts}" = "1"; then
|
|
+ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3_pins_b phandle
|
|
+ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3_pins_b_rts_cts phandle
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
|
|
+ env delete tmp_phandle1 tmp_phandle2
|
|
+ else
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800/uart3_pins_b phandle
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle}>"
|
|
+ env delete tmp_phandle
|
|
+ fi
|
|
+else
|
|
+ if test "${param_uart3_rtscts}" = "1"; then
|
|
+ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3_pins_a phandle
|
|
+ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3_pins_a_rts_cts phandle
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
|
|
+ env delete tmp_phandle1 tmp_phandle2
|
|
+ fi
|
|
+fi
|
|
+
|
|
+if test "${param_uart4_pins}" = "b"; then
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800/uart4@1 phandle
|
|
+ fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle}>"
|
|
+ env delete tmp_phandle
|
|
+fi
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts b/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts
|
|
new file mode 100644
|
|
index 000000000..4c104bf4a
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c1 = "/soc@1c00000/i2c@1c2b000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c1>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c1_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts b/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts
|
|
new file mode 100644
|
|
index 000000000..1c2c3e9ac
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c2 = "/soc@1c00000/i2c@1c2b400";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c2>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c2_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts b/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts
|
|
new file mode 100644
|
|
index 000000000..f0d4c2f34
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts
|
|
@@ -0,0 +1,103 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ nand_pins_a: nand_pins@0 {
|
|
+ pins = "PC0", "PC1", "PC2",
|
|
+ "PC5", "PC8", "PC9", "PC10",
|
|
+ "PC11", "PC12", "PC13", "PC14",
|
|
+ "PC15", "PC16";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_cs0_pins_a: nand_cs@0 {
|
|
+ pins = "PC4";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_cs1_pins_a: nand_cs@1 {
|
|
+ pins = "PC3";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_cs2_pins_a: nand_cs@2 {
|
|
+ pins = "PC17";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_cs3_pins_a: nand_cs@3 {
|
|
+ pins = "PC18";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_rb0_pins_a: nand_rb@0 {
|
|
+ pins = "PC6";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_rb1_pins_a: nand_rb@1 {
|
|
+ pins = "PC7";
|
|
+ function = "nand0";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&nfc>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>;
|
|
+ status = "okay";
|
|
+
|
|
+ nand@0 {
|
|
+ reg = <0>;
|
|
+ allwinner,rb = <0>;
|
|
+ nand-ecc-mode = "hw";
|
|
+ nand-on-flash-bbt;
|
|
+
|
|
+ partitions {
|
|
+ compatible = "fixed-partitions";
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ partition@0 {
|
|
+ label = "SPL";
|
|
+ reg = <0x0 0x0 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@400000 {
|
|
+ label = "SPL.backup";
|
|
+ reg = <0x0 0x400000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@800000 {
|
|
+ label = "U-Boot";
|
|
+ reg = <0x0 0x800000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@c00000 {
|
|
+ label = "U-Boot.backup";
|
|
+ reg = <0x0 0xc00000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@1000000 {
|
|
+ label = "env";
|
|
+ reg = <0x0 0x1000000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@1400000 {
|
|
+ label = "rootfs";
|
|
+ reg = <0x0 0xa00000 0x01 0xff000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts
|
|
new file mode 100644
|
|
index 000000000..6031fc53e
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts
|
|
@@ -0,0 +1,29 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ pps_pins: pps_pins {
|
|
+ pins = "PI15";
|
|
+ function = "gpio_in";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ pps@0 {
|
|
+ compatible = "pps-gpio";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pps_pins>;
|
|
+ gpios = <&pio 8 15 0>; /* PI15 */
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts b/arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts
|
|
new file mode 100644
|
|
index 000000000..ba885004f
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts
|
|
@@ -0,0 +1,15 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pwm>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts
|
|
new file mode 100644
|
|
index 000000000..234dfc880
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts
|
|
@@ -0,0 +1,38 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&spdif>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spdif_tx_pin>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ sound {
|
|
+ compatible = "simple-audio-card";
|
|
+ simple-audio-card,name = "On-board SPDIF";
|
|
+
|
|
+ simple-audio-card,cpu {
|
|
+ sound-dai = <&spdif>;
|
|
+ };
|
|
+
|
|
+ simple-audio-card,codec {
|
|
+ sound-dai = <&spdif_out>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spdif_out: spdif-out {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "linux,spdif-dit";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts
|
|
new file mode 100644
|
|
index 000000000..ee4ff6f45
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts
|
|
@@ -0,0 +1,57 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc@1c00000/spi@1c05000";
|
|
+ spi1 = "/soc@1c00000/spi@1c06000";
|
|
+ spi2 = "/soc@1c00000/spi@1c17000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@3 {
|
|
+ target = <&spi2>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts
|
|
new file mode 100644
|
|
index 000000000..eac4f1e2d
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts
|
|
@@ -0,0 +1,57 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc@1c00000/spi@1c05000";
|
|
+ spi1 = "/soc@1c00000/spi@1c06000";
|
|
+ spi2 = "/soc@1c00000/spi@1c17000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spidev@0 {
|
|
+ compatible = "armbian,spi-dev";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spidev@0 {
|
|
+ compatible = "armbian,spi-dev";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@3 {
|
|
+ target = <&spi2>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spidev@0 {
|
|
+ compatible = "armbian,spi-dev";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi0.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi0.dts
|
|
new file mode 100644
|
|
index 000000000..cad50d8a2
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi0.dts
|
|
@@ -0,0 +1,23 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc@1c00000/spi@1c05000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default", "default";
|
|
+ pinctrl-0 = <&spi0_pi_pins>;
|
|
+ pinctrl-1 = <&spi0_cs0_pi_pin>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi1.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi1.dts
|
|
new file mode 100644
|
|
index 000000000..8c606d6b0
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi1.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi1 = "/soc@1c00000/spi@1c06000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi2.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi2.dts
|
|
new file mode 100644
|
|
index 000000000..145f28558
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi2.dts
|
|
@@ -0,0 +1,23 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi2 = "/soc@1c00000/spi@1c17000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi2>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default", "default";
|
|
+ pinctrl-0 = <&spi2_pins_a>;
|
|
+ pinctrl-1 = <&spi2_cs0_pins_a>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts
|
|
new file mode 100644
|
|
index 000000000..89bb44d5a
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts
|
|
@@ -0,0 +1,37 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial2 = "/soc@1c00000/serial@1c28800";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ uart2_pins_a: uart2@0 {
|
|
+ pins = "PI16", "PI17", "PI18", "PI19";
|
|
+ function = "uart2";
|
|
+ };
|
|
+
|
|
+ uart2_pins_a_2: uart2@1 {
|
|
+ pins = "PI18", "PI19";
|
|
+ function = "uart2";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&uart2>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart2_pins_a_2>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts
|
|
new file mode 100644
|
|
index 000000000..f599d9208
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts
|
|
@@ -0,0 +1,47 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial3 = "/soc@1c00000/serial@1c28c00";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ uart3_pins_a: uart3@0 {
|
|
+ pins = "PG6", "PG7";
|
|
+ function = "uart3";
|
|
+ };
|
|
+
|
|
+ uart3_pins_a_rts_cts: uart3@1 {
|
|
+ pins = "PG8", "PG9";
|
|
+ function = "uart3";
|
|
+ };
|
|
+
|
|
+ uart3_pins_b: uart3@2 {
|
|
+ pins = "PH0", "PH1";
|
|
+ function = "uart3";
|
|
+ };
|
|
+
|
|
+ uart3_pins_b_rts_cts: uart3@3 {
|
|
+ pins = "PH2", "PH3";
|
|
+ function = "uart3";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&uart3>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart3_pins_a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts
|
|
new file mode 100644
|
|
index 000000000..b5e562a64
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts
|
|
@@ -0,0 +1,37 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial4 = "/soc@1c00000/serial@1c29000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ uart4_pins_a: uart4@0 {
|
|
+ pins = "PG10", "PG11";
|
|
+ function = "uart4";
|
|
+ };
|
|
+
|
|
+ uart4_pins_b: uart4@1 {
|
|
+ pins = "PH4", "PH5";
|
|
+ function = "uart4";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&uart4>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart4_pins_a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts
|
|
new file mode 100644
|
|
index 000000000..12c3f9699
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts
|
|
@@ -0,0 +1,32 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial5 = "/soc@1c00000/serial@1c29400";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ uart5_pins_a: uart5@0 {
|
|
+ pins = "PH6", "PH7";
|
|
+ function = "uart5";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&uart5>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart5_pins_a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts
|
|
new file mode 100644
|
|
index 000000000..6be41d505
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts
|
|
@@ -0,0 +1,32 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial6 = "/soc@1c00000/serial@1c29800";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ uart6_pins_a: uart6@0 {
|
|
+ pins = "PI12", "PI13";
|
|
+ function = "uart6";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&uart6>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart6_pins_a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts
|
|
new file mode 100644
|
|
index 000000000..967f6afbe
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts
|
|
@@ -0,0 +1,32 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial7 = "/soc@1c00000/serial@1c29c00";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ uart7_pins_a: uart7@0 {
|
|
+ pins = "PI20", "PI21";
|
|
+ function = "uart7";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&uart7>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart7_pins_a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts
|
|
new file mode 100644
|
|
index 000000000..41da08c60
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts
|
|
@@ -0,0 +1,29 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ w1_pins: w1_pins {
|
|
+ pins = "PI15";
|
|
+ function = "gpio_in";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ onewire@0 {
|
|
+ compatible = "w1-gpio";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&w1_pins>;
|
|
+ gpios = <&pio 8 15 0>; /* PI15 */
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-analog-codec.dts b/arch/arm/boot/dts/overlay/sun5i-a13-analog-codec.dts
|
|
new file mode 100644
|
|
index 000000000..60e2717fc
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-analog-codec.dts
|
|
@@ -0,0 +1,13 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun4i-a13";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&codec>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun5i-a13-fixup.scr-cmd
|
|
new file mode 100644
|
|
index 000000000..c82590c1a
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-fixup.scr-cmd
|
|
@@ -0,0 +1,48 @@
|
|
+# overlays fixup script
|
|
+# implements (or rather substitutes) overlay arguments functionality
|
|
+# using u-boot scripting, environment variables and "fdt" command
|
|
+
|
|
+if test -n "${param_spinor_spi_bus}"; then
|
|
+ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
|
|
+ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
|
|
+ test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
|
|
+ fdt set /soc/${tmp_spi_path} status "okay"
|
|
+ fdt set /soc/${tmp_spi_path}/spiflash status "okay"
|
|
+ if test -n "${param_spinor_max_freq}"; then
|
|
+ fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
|
|
+ fi
|
|
+ env delete tmp_spi_path
|
|
+fi
|
|
+
|
|
+if test -n "${param_spidev_spi_bus}"; then
|
|
+ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
|
|
+ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
|
|
+ test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
|
|
+ fdt set /soc/${tmp_spi_path} status "okay"
|
|
+ fdt set /soc/${tmp_spi_path}/spidev status "okay"
|
|
+ if test -n "${param_spidev_max_freq}"; then
|
|
+ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
|
|
+ fi
|
|
+ env delete tmp_spi_path
|
|
+fi
|
|
+
|
|
+if test "${param_uart1_pins}" = "b"; then
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c28400/uart1@1 phandle
|
|
+ fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle}>"
|
|
+ env delete tmp_phandle
|
|
+fi
|
|
+
|
|
+if test "${param_uart2_rtscts}" = "1"; then
|
|
+ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2@0 phandle
|
|
+ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-cts-rts@0 phandle
|
|
+ fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>, <${tmp_phandle2}>"
|
|
+ env delete tmp_phandle1 tmp_phandle2
|
|
+fi
|
|
+
|
|
+if test "${param_uart3_rtscts}" = "1"; then
|
|
+ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3@0 phandle
|
|
+ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts@0 phandle
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>, <${tmp_phandle2}>"
|
|
+ env delete tmp_phandle1 tmp_phandle2
|
|
+fi
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-i2c1.dts b/arch/arm/boot/dts/overlay/sun5i-a13-i2c1.dts
|
|
new file mode 100644
|
|
index 000000000..444c32ca0
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-i2c1.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun5i-a13";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c1 = "/soc@1c00000/i2c@1c2b000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c1>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c1_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-i2c2.dts b/arch/arm/boot/dts/overlay/sun5i-a13-i2c2.dts
|
|
new file mode 100644
|
|
index 000000000..7a30681ca
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-i2c2.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun5i-a13";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c2 = "/soc@1c00000/i2c@1c2b400";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c2>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c2_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-nand.dts b/arch/arm/boot/dts/overlay/sun5i-a13-nand.dts
|
|
new file mode 100644
|
|
index 000000000..0c5fc89a1
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-nand.dts
|
|
@@ -0,0 +1,60 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun5i-a13";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&nfc>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&nand_pins>, <&nand_cs0_pin>, <&nand_rb0_pin>;
|
|
+ status = "okay";
|
|
+
|
|
+ nand@0 {
|
|
+ reg = <0>;
|
|
+ allwinner,rb = <0>;
|
|
+ nand-ecc-mode = "hw";
|
|
+ nand-on-flash-bbt;
|
|
+
|
|
+ partitions {
|
|
+ compatible = "fixed-partitions";
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ partition@0 {
|
|
+ label = "SPL";
|
|
+ reg = <0x0 0x0 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@400000 {
|
|
+ label = "SPL.backup";
|
|
+ reg = <0x0 0x400000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@800000 {
|
|
+ label = "U-Boot";
|
|
+ reg = <0x0 0x800000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@c00000 {
|
|
+ label = "U-Boot.backup";
|
|
+ reg = <0x0 0xc00000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@1000000 {
|
|
+ label = "env";
|
|
+ reg = <0x0 0x1000000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@1400000 {
|
|
+ label = "rootfs";
|
|
+ reg = <0x0 0xa00000 0x01 0xff000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-pwm.dts b/arch/arm/boot/dts/overlay/sun5i-a13-pwm.dts
|
|
new file mode 100644
|
|
index 000000000..54f5d5123
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-pwm.dts
|
|
@@ -0,0 +1,15 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun5i-a13";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pwm>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pwm0_pin>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi-jedec-nor.dts
|
|
new file mode 100644
|
|
index 000000000..8cebb0b98
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi-jedec-nor.dts
|
|
@@ -0,0 +1,57 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun5i-a13";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc/spi@1c05000";
|
|
+ spi1 = "/soc/spi@1c06000";
|
|
+ spi2 = "/soc/spi@1c17000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@3 {
|
|
+ target = <&spi2>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi-spidev.dts
|
|
new file mode 100644
|
|
index 000000000..ad0685f8a
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi-spidev.dts
|
|
@@ -0,0 +1,57 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun5i-a10";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc/spi@1c05000";
|
|
+ spi1 = "/soc/spi@1c06000";
|
|
+ spi2 = "/soc/spi@1c17000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spidev@0 {
|
|
+ compatible = "armbian,spi-dev";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spidev@0 {
|
|
+ compatible = "armbian,spi-dev";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@3 {
|
|
+ target = <&spi2>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spidev@0 {
|
|
+ compatible = "armbian,spi-dev";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi0.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi0.dts
|
|
new file mode 100644
|
|
index 000000000..b23a754c0
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi0.dts
|
|
@@ -0,0 +1,38 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun5i-a13";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc/spi@1c05000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ spi0_pins_a: spi0@0 {
|
|
+ pins = "PC0", "PC1", "PC2";
|
|
+ function = "spi0";
|
|
+ };
|
|
+
|
|
+ spi0_cs0_pins_a: spi0-cs0@0 {
|
|
+ pins = "PC3";
|
|
+ function = "spi0";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default", "default";
|
|
+ pinctrl-0 = <&spi0_pins_a>;
|
|
+ pinctrl-1 = <&spi0_cs0_pins_a>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi1.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi1.dts
|
|
new file mode 100644
|
|
index 000000000..cc0af5db3
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi1.dts
|
|
@@ -0,0 +1,39 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun5i-a13";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi1 = "/soc/spi@1c06000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ spi1_pins_a: spi1@0 {
|
|
+ pins = "PG10", "PG11", "PG12";
|
|
+ function = "spi1";
|
|
+ };
|
|
+
|
|
+ spi1_cs0_pins_a: spi1-cs0@0 {
|
|
+ pins = "PG9";
|
|
+ function = "spi1";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi2.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi2.dts
|
|
new file mode 100644
|
|
index 000000000..6cf5c41a9
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi2.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun5i-a13";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi2 = "/soc/spi@1c17000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi2>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-uart0.dts b/arch/arm/boot/dts/overlay/sun5i-a13-uart0.dts
|
|
new file mode 100644
|
|
index 000000000..6edad42bf
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-uart0.dts
|
|
@@ -0,0 +1,32 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun5i-a13";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ uart0 = "/soc@1c00000/serial@1c28000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ uart0_pa_pins: uart0@0 {
|
|
+ pins = "PF2", "PF4";
|
|
+ function = "uart0";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&uart0>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart0_pa_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-uart1.dts b/arch/arm/boot/dts/overlay/sun5i-a13-uart1.dts
|
|
new file mode 100644
|
|
index 000000000..675b701ed
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-uart1.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun5i-a13";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ uart1 = "/soc@1c00000/serial@1c28400";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart1>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart1_pe_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-uart2.dts b/arch/arm/boot/dts/overlay/sun5i-a13-uart2.dts
|
|
new file mode 100644
|
|
index 000000000..b3c4e3d7a
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-uart2.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun5i-a13";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ uart2 = "/soc@1c00000/serial@1c28800";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart2>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart2_pd_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-uart3.dts b/arch/arm/boot/dts/overlay/sun5i-a13-uart3.dts
|
|
new file mode 100644
|
|
index 000000000..15c25d0c5
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun5i-a13-uart3.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun5i-a13";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ uart3 = "/soc@1c00000/serial@1c28c00";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart3>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart3_pg_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts b/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts
|
|
new file mode 100644
|
|
index 000000000..e1a70c510
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts
|
|
@@ -0,0 +1,13 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&codec>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-can.dts b/arch/arm/boot/dts/overlay/sun7i-a20-can.dts
|
|
new file mode 100644
|
|
index 000000000..65aebcd41
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-can.dts
|
|
@@ -0,0 +1,15 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&can0>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&can0_pins_a>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd
|
|
new file mode 100644
|
|
index 000000000..b97042a72
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd
|
|
@@ -0,0 +1,143 @@
|
|
+# overlays fixup script
|
|
+# implements (or rather substitutes) overlay arguments functionality
|
|
+# using u-boot scripting, environment variables and "fdt" command
|
|
+
|
|
+# setexpr test_var ${tmp_bank} - A
|
|
+# works only for hex numbers (A-F)
|
|
+
|
|
+setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1";
|
|
+setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
|
|
+test "${tmp_bank}" = "B" && setenv tmp_bank 1;
|
|
+test "${tmp_bank}" = "C" && setenv tmp_bank 2;
|
|
+test "${tmp_bank}" = "D" && setenv tmp_bank 3;
|
|
+test "${tmp_bank}" = "E" && setenv tmp_bank 4;
|
|
+test "${tmp_bank}" = "G" && setenv tmp_bank 6;
|
|
+test "${tmp_bank}" = "H" && setenv tmp_bank 7;
|
|
+test "${tmp_bank}" = "I" && setenv tmp_bank 8'
|
|
+
|
|
+if test -n "${param_spinor_spi_bus}"; then
|
|
+ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
|
|
+ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
|
|
+ test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
|
|
+ fdt set /soc/${tmp_spi_path} status "okay"
|
|
+ fdt set /soc/${tmp_spi_path}/spiflash status "okay"
|
|
+ if test -n "${param_spinor_max_freq}"; then
|
|
+ fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
|
|
+ fi
|
|
+ if test "${param_spinor_spi_bus}" = "0" && test "${param_spinor_spi_cs}" = "1"; then
|
|
+ fdt set /soc/${tmp_spi_path}/spiflash reg "<1>"
|
|
+ fi
|
|
+ env delete tmp_spi_path
|
|
+fi
|
|
+
|
|
+if test -n "${param_spidev_spi_bus}"; then
|
|
+ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
|
|
+ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
|
|
+ test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
|
|
+ fdt set /soc/${tmp_spi_path} status "okay"
|
|
+ fdt set /soc/${tmp_spi_path}/spidev status "okay"
|
|
+ if test -n "${param_spidev_max_freq}"; then
|
|
+ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
|
|
+ fi
|
|
+ if test "${param_spidev_spi_bus}" = "0" && test "${param_spidev_spi_cs}" = "1"; then
|
|
+ fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
|
|
+ fi
|
|
+ env delete tmp_spi_path
|
|
+fi
|
|
+
|
|
+if test "${param_spi2_bus_pins}" = "b"; then
|
|
+ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/spi2@1 phandle
|
|
+ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/spi2_cs0@1 phandle
|
|
+ fdt set /soc/spi@1c17000 pinctrl-0 "<${tmp_phandle1}>"
|
|
+ fdt set /soc/spi@1c17000 pinctrl-1 "<${tmp_phandle2}>"
|
|
+ env delete tmp_phandle1 tmp_phandle2
|
|
+fi
|
|
+
|
|
+if test -n "${param_pps_pin}"; then
|
|
+ setenv tmp_bank "${param_pps_pin}"
|
|
+ setenv tmp_pin "${param_pps_pin}"
|
|
+ run decompose_pin
|
|
+ fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}"
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
|
|
+ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
|
|
+ env delete tmp_pin tmp_bank tmp_phandle
|
|
+fi
|
|
+
|
|
+if test "${param_pps_falling_edge}" = "1"; then
|
|
+ fdt set /pps@0 assert-falling-edge
|
|
+fi
|
|
+
|
|
+if test "${param_pwm_pins}" = "0"; then
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm0@0
|
|
+ fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>"
|
|
+ env delete tmp_phandle
|
|
+fi
|
|
+
|
|
+if test "${param_pwm_pins}" = "1"; then
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm1@0
|
|
+ fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>"
|
|
+ env delete tmp_phandle
|
|
+fi
|
|
+
|
|
+if test -n "${param_w1_pin}"; then
|
|
+ setenv tmp_bank "${param_w1_pin}"
|
|
+ setenv tmp_pin "${param_w1_pin}"
|
|
+ run decompose_pin
|
|
+ fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}"
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
|
|
+ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
|
|
+ env delete tmp_pin tmp_bank tmp_phandle
|
|
+fi
|
|
+
|
|
+if test -n "${param_mmc2_cd_pin}"; then
|
|
+ setenv tmp_bank "${param_mmc2_cd_pin}"
|
|
+ setenv tmp_pin "${param_mmc2_cd_pin}"
|
|
+ run decompose_pin
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
|
|
+ fdt set /soc/mmc@1c11000 cd-gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 1>"
|
|
+fi
|
|
+
|
|
+if test "${param_mmc2_non_removable}" = "1"; then
|
|
+ fdt rm /soc/mmc@1c11000 cd-gpios
|
|
+ fdt set /soc/mmc@1c11000 non-removable
|
|
+fi
|
|
+
|
|
+if test "${param_w1_pin_int_pullup}" = "1"; then
|
|
+ fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up
|
|
+fi
|
|
+
|
|
+if test "${param_uart2_rtscts}" = "1"; then
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800/uart2-pi-pins phandle
|
|
+ fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle}>"
|
|
+ env delete tmp_phandle
|
|
+fi
|
|
+
|
|
+if test "${param_uart3_pins}" = "b"; then
|
|
+ if test "${param_uart3_rtscts}" = "1"; then
|
|
+ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-ph-pins phandle
|
|
+ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts-ph-pins phandle
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
|
|
+ env delete tmp_phandle1 tmp_phandle2
|
|
+ else
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800/uart3-ph-pins phandle
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle}>"
|
|
+ env delete tmp_phandle
|
|
+ fi
|
|
+else
|
|
+ if test "${param_uart3_rtscts}" = "1"; then
|
|
+ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-pg-pins phandle
|
|
+ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts-pg-pins phandle
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
|
|
+ env delete tmp_phandle1 tmp_phandle2
|
|
+ fi
|
|
+fi
|
|
+
|
|
+if test "${param_uart4_pins}" = "b"; then
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800/uart4-pg-pins phandle
|
|
+ fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle}>"
|
|
+ env delete tmp_phandle
|
|
+fi
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts
|
|
new file mode 100644
|
|
index 000000000..c5f6e9732
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c1 = "/soc@1c00000/i2c@1c2b000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c1>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c1_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts
|
|
new file mode 100644
|
|
index 000000000..fa93d1ed9
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c2 = "/soc@1c00000/i2c@1c2b400";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c2>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c2_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts
|
|
new file mode 100644
|
|
index 000000000..945795c33
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c3 = "/soc@1c00000/i2c@1c2b800";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c3>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c3_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts
|
|
new file mode 100644
|
|
index 000000000..4fcf08c24
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts
|
|
@@ -0,0 +1,32 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c4 = "/soc@1c00000/i2c@1c2c000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ i2c4_pins_a: i2c4@0 {
|
|
+ pins = "PI2", "PI3";
|
|
+ function = "i2c4";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&i2c4>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c4_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2s0.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2s0.dts
|
|
new file mode 100644
|
|
index 000000000..1a19a2417
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2s0.dts
|
|
@@ -0,0 +1,25 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ i2s0_pins: i2s0 {
|
|
+ pins = "PB5", "PB6", "PB7", "PB8", "PB9", "PB10", "PB11", "PB12";
|
|
+ function = "i2s0";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2s0>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2s0_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2s1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2s1.dts
|
|
new file mode 100644
|
|
index 000000000..e6f0a22b7
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2s1.dts
|
|
@@ -0,0 +1,25 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ i2s1_pins: i2s1 {
|
|
+ pins = "PA9", "PA14", "PA15", "PA16", "PA17";
|
|
+ function = "i2s1";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2s1>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2s1_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts
|
|
new file mode 100644
|
|
index 000000000..ede92f243
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts
|
|
@@ -0,0 +1,18 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&mmc2>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&mmc2_pins>;
|
|
+ vmmc-supply = <®_vcc3v3>;
|
|
+ bus-width = <4>;
|
|
+ cd-gpios = <&pio 7 0 1>; /* PH0, active low */
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts b/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts
|
|
new file mode 100644
|
|
index 000000000..ffa49cc69
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts
|
|
@@ -0,0 +1,103 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ nand_pins_a: nand_pins@0 {
|
|
+ pins = "PC0", "PC1", "PC2",
|
|
+ "PC5", "PC8", "PC9", "PC10",
|
|
+ "PC11", "PC12", "PC13", "PC14",
|
|
+ "PC15", "PC16";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_cs0_pins_a: nand_cs@0 {
|
|
+ pins = "PC4";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_cs1_pins_a: nand_cs@1 {
|
|
+ pins = "PC3";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_cs2_pins_a: nand_cs@2 {
|
|
+ pins = "PC17";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_cs3_pins_a: nand_cs@3 {
|
|
+ pins = "PC18";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_rb0_pins_a: nand_rb@0 {
|
|
+ pins = "PC6";
|
|
+ function = "nand0";
|
|
+ };
|
|
+
|
|
+ nand_rb1_pins_a: nand_rb@1 {
|
|
+ pins = "PC7";
|
|
+ function = "nand0";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&nfc>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>;
|
|
+ status = "okay";
|
|
+
|
|
+ nand@0 {
|
|
+ reg = <0>;
|
|
+ allwinner,rb = <0>;
|
|
+ nand-ecc-mode = "hw";
|
|
+ nand-on-flash-bbt;
|
|
+
|
|
+ partitions {
|
|
+ compatible = "fixed-partitions";
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ partition@0 {
|
|
+ label = "SPL";
|
|
+ reg = <0x0 0x0 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@400000 {
|
|
+ label = "SPL.backup";
|
|
+ reg = <0x0 0x400000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@800000 {
|
|
+ label = "U-Boot";
|
|
+ reg = <0x0 0x800000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@c00000 {
|
|
+ label = "U-Boot.backup";
|
|
+ reg = <0x0 0xc00000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@1000000 {
|
|
+ label = "env";
|
|
+ reg = <0x0 0x1000000 0x0 0x400000>;
|
|
+ };
|
|
+
|
|
+ partition@1400000 {
|
|
+ label = "rootfs";
|
|
+ reg = <0x0 0xa00000 0x01 0xff000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts
|
|
new file mode 100644
|
|
index 000000000..fe3e2bd96
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts
|
|
@@ -0,0 +1,29 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ pps_pins: pps_pins {
|
|
+ pins = "PI15";
|
|
+ function = "gpio_in";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ pps@0 {
|
|
+ compatible = "pps-gpio";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pps_pins>;
|
|
+ gpios = <&pio 8 15 0>; /* PI15 */
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts b/arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts
|
|
new file mode 100644
|
|
index 000000000..b0cfe4dea
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts
|
|
@@ -0,0 +1,15 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pwm>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts
|
|
new file mode 100644
|
|
index 000000000..11a09396b
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts
|
|
@@ -0,0 +1,38 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&spdif>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spdif_tx_pin>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ sound {
|
|
+ compatible = "simple-audio-card";
|
|
+ simple-audio-card,name = "On-board SPDIF";
|
|
+
|
|
+ simple-audio-card,cpu {
|
|
+ sound-dai = <&spdif>;
|
|
+ };
|
|
+
|
|
+ simple-audio-card,codec {
|
|
+ sound-dai = <&spdif_out>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spdif_out: spdif-out {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "linux,spdif-dit";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-add-cs1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-add-cs1.dts
|
|
new file mode 100644
|
|
index 000000000..c0a4ba2b3
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-add-cs1.dts
|
|
@@ -0,0 +1,16 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default", "default", "default";
|
|
+ pinctrl-0 = <&spi0_pi_pins>;
|
|
+ pinctrl-1 = <&spi0_cs0_pi_pin>;
|
|
+ pinctrl-2 = <&spi0_cs1_pi_pin>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts
|
|
new file mode 100644
|
|
index 000000000..b91097eca
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts
|
|
@@ -0,0 +1,57 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc@1c00000/spi@1c05000";
|
|
+ spi1 = "/soc@1c00000/spi@1c06000";
|
|
+ spi2 = "/soc@1c00000/spi@1c17000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@3 {
|
|
+ target = <&spi2>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts
|
|
new file mode 100644
|
|
index 000000000..341fe3229
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts
|
|
@@ -0,0 +1,57 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc@1c00000/spi@1c05000";
|
|
+ spi1 = "/soc@1c00000/spi@1c06000";
|
|
+ spi2 = "/soc@1c00000/spi@1c17000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spidev@0 {
|
|
+ compatible = "armbian,spi-dev";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spidev@0 {
|
|
+ compatible = "armbian,spi-dev";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@3 {
|
|
+ target = <&spi2>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spidev@0 {
|
|
+ compatible = "armbian,spi-dev";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi0.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi0.dts
|
|
new file mode 100644
|
|
index 000000000..cad50d8a2
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi0.dts
|
|
@@ -0,0 +1,23 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc@1c00000/spi@1c05000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default", "default";
|
|
+ pinctrl-0 = <&spi0_pi_pins>;
|
|
+ pinctrl-1 = <&spi0_cs0_pi_pin>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi1.dts
|
|
new file mode 100644
|
|
index 000000000..f0218eb9f
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi1.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi1 = "/soc@1c00000/spi@1c06000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi1_pi_pins>, <&spi1_cs0_pi_pin>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi2.dts
|
|
new file mode 100644
|
|
index 000000000..effba42b4
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi2.dts
|
|
@@ -0,0 +1,23 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi2 = "/soc@1c00000/spi@1c17000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi2>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default", "default";
|
|
+ pinctrl-0 = <&spi2_pb_pins>;
|
|
+ pinctrl-1 = <&spi2_pb_cs0_pin>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts
|
|
new file mode 100644
|
|
index 000000000..79d1dca7a
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts
|
|
@@ -0,0 +1,32 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial2 = "/soc@1c00000/serial@1c28800";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ uart2_pins_a_2: uart2@1 {
|
|
+ pins = "PI18", "PI19";
|
|
+ function = "uart2";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&uart2>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart2_pins_a_2>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts
|
|
new file mode 100644
|
|
index 000000000..703acbcf3
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts
|
|
@@ -0,0 +1,42 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial3 = "/soc@1c00000/serial@1c28c00";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ uart3_pins_a_2: uart3@2 {
|
|
+ pins = "PG6", "PG7";
|
|
+ function = "uart3";
|
|
+ };
|
|
+
|
|
+ uart3_pins_a_rts_cts: uart3@1 {
|
|
+ pins = "PG8", "PG9";
|
|
+ function = "uart3";
|
|
+ };
|
|
+
|
|
+ uart3_pins_b_rts_cts: uart3@3 {
|
|
+ pins = "PH2", "PH3";
|
|
+ function = "uart3";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&uart3>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart3_pins_a_2>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts
|
|
new file mode 100644
|
|
index 000000000..19180341a
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial4 = "/soc@1c00000/serial@1c29000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart4>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart4_pg_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts
|
|
new file mode 100644
|
|
index 000000000..a1369eee2
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial5 = "/soc@1c00000/serial@1c29400";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart5>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart5_pi_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts
|
|
new file mode 100644
|
|
index 000000000..fb9efe2a9
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial6 = "/soc@1c00000/serial@1c29800";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart6>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart6_pi_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts
|
|
new file mode 100644
|
|
index 000000000..bbdca3ec6
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial7 = "/soc@1c00000/serial@1c29c00";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart7>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart7_pi_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts
|
|
new file mode 100644
|
|
index 000000000..7d77606a1
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts
|
|
@@ -0,0 +1,29 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun7i-a20";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ w1_pins: w1_pins {
|
|
+ pins = "PI15";
|
|
+ function = "gpio_in";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ onewire@0 {
|
|
+ compatible = "w1-gpio";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&w1_pins>;
|
|
+ gpios = <&pio 8 15 0>; /* PI15 */
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts b/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts
|
|
new file mode 100644
|
|
index 000000000..36dbc31ae
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts
|
|
@@ -0,0 +1,17 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&codec>;
|
|
+ __overlay__ {
|
|
+ allwinner,audio-routing =
|
|
+ "Line Out", "LINEOUT",
|
|
+ "MIC1", "Mic",
|
|
+ "Mic", "MBIAS";
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts
|
|
new file mode 100644
|
|
index 000000000..bf4a0eafa
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts
|
|
@@ -0,0 +1,15 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&ir>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&r_ir_rx_pin>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd
|
|
new file mode 100644
|
|
index 000000000..604fe8bb7
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd
|
|
@@ -0,0 +1,110 @@
|
|
+# overlays fixup script
|
|
+# implements (or rather substitutes) overlay arguments functionality
|
|
+# using u-boot scripting, environment variables and "fdt" command
|
|
+
|
|
+# setexpr test_var ${tmp_bank} - A
|
|
+# works only for hex numbers (A-F)
|
|
+
|
|
+setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1";
|
|
+setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
|
|
+test "${tmp_bank}" = "A" && setenv tmp_bank 0;
|
|
+test "${tmp_bank}" = "C" && setenv tmp_bank 2;
|
|
+test "${tmp_bank}" = "D" && setenv tmp_bank 3;
|
|
+test "${tmp_bank}" = "G" && setenv tmp_bank 6'
|
|
+
|
|
+if test -n "${param_spinor_spi_bus}"; then
|
|
+ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000"
|
|
+ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000"
|
|
+ fdt set /soc/${tmp_spi_path} status "okay"
|
|
+ fdt set /soc/${tmp_spi_path}/spiflash status "okay"
|
|
+ if test -n "${param_spinor_max_freq}"; then
|
|
+ fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
|
|
+ fi
|
|
+ if test "${param_spinor_spi_cs}" = "1"; then
|
|
+ fdt set /soc/${tmp_spi_path}/spiflash reg "<1>"
|
|
+ fi
|
|
+ env delete tmp_spi_path
|
|
+fi
|
|
+
|
|
+if test -n "${param_spidev_spi_bus}"; then
|
|
+ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000"
|
|
+ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000"
|
|
+ fdt set /soc/${tmp_spi_path} status "okay"
|
|
+ fdt set /soc/${tmp_spi_path}/spidev status "okay"
|
|
+ if test -n "${param_spidev_max_freq}"; then
|
|
+ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
|
|
+ fi
|
|
+ if test "${param_spidev_spi_cs}" = "1"; then
|
|
+ fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
|
|
+ fi
|
|
+ env delete tmp_spi_path
|
|
+fi
|
|
+
|
|
+if test -n "${param_pps_pin}"; then
|
|
+ setenv tmp_bank "${param_pps_pin}"
|
|
+ setenv tmp_pin "${param_pps_pin}"
|
|
+ run decompose_pin
|
|
+ fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}"
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
|
|
+ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
|
|
+ env delete tmp_pin tmp_bank tmp_phandle
|
|
+fi
|
|
+
|
|
+if test "${param_pps_falling_edge}" = "1"; then
|
|
+ fdt set /pps@0 assert-falling-edge
|
|
+fi
|
|
+
|
|
+for f in ${overlays}; do
|
|
+ if test "${f}" = "pwm"; then
|
|
+ setenv bootargs_new ""
|
|
+ for arg in ${bootargs}; do
|
|
+ if test "${arg}" = "console=ttyS0,115200"; then
|
|
+ echo "Warning: Disabling ttyS0 console due to enabled PWM overlay"
|
|
+ else
|
|
+ setenv bootargs_new "${bootargs_new} ${arg}"
|
|
+ fi
|
|
+ done
|
|
+ setenv bootargs "${bootargs_new}"
|
|
+ fi
|
|
+done
|
|
+
|
|
+if test -n "${param_w1_pin}"; then
|
|
+ setenv tmp_bank "${param_w1_pin}"
|
|
+ setenv tmp_pin "${param_w1_pin}"
|
|
+ run decompose_pin
|
|
+ fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}"
|
|
+ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
|
|
+ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
|
|
+ env delete tmp_pin tmp_bank tmp_phandle
|
|
+fi
|
|
+
|
|
+if test "${param_w1_pin_int_pullup}" = "1"; then
|
|
+ fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up
|
|
+fi
|
|
+
|
|
+if test "${param_uart1_rtscts}" = "1"; then
|
|
+ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1-pins phandle
|
|
+ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1-rts-cts-pins phandle
|
|
+ fdt set /soc/serial@1c28400 pinctrl-names "default" "default"
|
|
+ fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>"
|
|
+ fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>"
|
|
+ env delete tmp_phandle1 tmp_phandle2
|
|
+fi
|
|
+
|
|
+if test "${param_uart2_rtscts}" = "1"; then
|
|
+ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2-pins phandle
|
|
+ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-rts-cts-pins phandle
|
|
+ fdt set /soc/serial@1c28800 pinctrl-names "default" "default"
|
|
+ fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>"
|
|
+ fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>"
|
|
+ env delete tmp_phandle1 tmp_phandle2
|
|
+fi
|
|
+
|
|
+if test "${param_uart3_rtscts}" = "1"; then
|
|
+ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-pins phandle
|
|
+ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-rts-cts-pins phandle
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
|
|
+ fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
|
|
+ env delete tmp_phandle1 tmp_phandle2
|
|
+fi
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts
|
|
new file mode 100644
|
|
index 000000000..a36ac8667
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts
|
|
@@ -0,0 +1,20 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c0 = "/soc/i2c@1c2ac00";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c0>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts
|
|
new file mode 100644
|
|
index 000000000..258c86de0
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts
|
|
@@ -0,0 +1,20 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c1 = "/soc/i2c@1c2b000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c1>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts
|
|
new file mode 100644
|
|
index 000000000..a1e328498
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts
|
|
@@ -0,0 +1,20 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c2 = "/soc/i2c@1c2b400";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c2>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts
|
|
new file mode 100644
|
|
index 000000000..16a737b02
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts
|
|
@@ -0,0 +1,29 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ pps_pins: pps_pins {
|
|
+ pins = "PD14";
|
|
+ function = "gpio_in";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ pps@0 {
|
|
+ compatible = "pps-gpio";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pps_pins>;
|
|
+ gpios = <&pio 3 14 0>; /* PD14 */
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts b/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts
|
|
new file mode 100644
|
|
index 000000000..ed3b8e606
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts
|
|
@@ -0,0 +1,39 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/chosen";
|
|
+ __overlay__ {
|
|
+ /delete-property/ stdout-path;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart0>;
|
|
+ __overlay__ {
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ pwm0_pin: pwm0 {
|
|
+ pins = "PA5";
|
|
+ function = "pwm0";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@3 {
|
|
+ target = <&pwm>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pwm0_pin>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts
|
|
new file mode 100644
|
|
index 000000000..35b2d5677
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts
|
|
@@ -0,0 +1,38 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&spdif>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spdif_tx_pin>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ sound {
|
|
+ compatible = "simple-audio-card";
|
|
+ simple-audio-card,name = "On-board SPDIF";
|
|
+
|
|
+ simple-audio-card,cpu {
|
|
+ sound-dai = <&spdif>;
|
|
+ };
|
|
+
|
|
+ simple-audio-card,codec {
|
|
+ sound-dai = <&spdif_out>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spdif_out: spdif-out {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "linux,spdif-dit";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts
|
|
new file mode 100644
|
|
index 000000000..bd8e25617
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts
|
|
@@ -0,0 +1,41 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ spi0_cs1: spi0_cs1 {
|
|
+ pins = "PA21";
|
|
+ function = "gpio_out";
|
|
+ output-high;
|
|
+ };
|
|
+
|
|
+ spi1_cs1: spi1_cs1 {
|
|
+ pins = "PA10";
|
|
+ function = "gpio_out";
|
|
+ output-high;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default", "default";
|
|
+ pinctrl-1 = <&spi0_cs1>;
|
|
+ cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default", "default";
|
|
+ pinctrl-1 = <&spi1_cs1>;
|
|
+ cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts
|
|
new file mode 100644
|
|
index 000000000..95fa5f2ca
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts
|
|
@@ -0,0 +1,42 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc/spi@1c68000";
|
|
+ spi1 = "/soc/spi@1c69000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spiflash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts
|
|
new file mode 100644
|
|
index 000000000..c79beb95e
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts
|
|
@@ -0,0 +1,42 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc/spi@1c68000";
|
|
+ spi1 = "/soc/spi@1c69000";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spidev@0 {
|
|
+ compatible = "armbian,spi-dev";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&spi1>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ spidev@0 {
|
|
+ compatible = "armbian,spi-dev";
|
|
+ status = "disabled";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts
|
|
new file mode 100644
|
|
index 000000000..3c10d4db4
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial1 = "/soc/serial@1c28400";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart1>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart1_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts
|
|
new file mode 100644
|
|
index 000000000..f16e61862
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial2 = "/soc/serial@1c28800";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart2>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart2_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts
|
|
new file mode 100644
|
|
index 000000000..b1aef575e
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial3 = "/soc/serial@1c28c00";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&uart3>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart3_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts
|
|
new file mode 100644
|
|
index 000000000..6bd8aedbe
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts
|
|
@@ -0,0 +1,27 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&ehci0>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&ohci0>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&usbphy>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost1.dts
|
|
new file mode 100644
|
|
index 000000000..4c7222b10
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost1.dts
|
|
@@ -0,0 +1,27 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&ehci1>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&ohci1>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&usbphy>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts
|
|
new file mode 100644
|
|
index 000000000..2b83ec933
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts
|
|
@@ -0,0 +1,27 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&ehci2>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&ohci2>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&usbphy>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts
|
|
new file mode 100644
|
|
index 000000000..e2f28ab1a
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts
|
|
@@ -0,0 +1,27 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&ehci3>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&ohci3>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&usbphy>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts
|
|
new file mode 100644
|
|
index 000000000..f4ccb7fba
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts
|
|
@@ -0,0 +1,29 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&pio>;
|
|
+ __overlay__ {
|
|
+ w1_pins: w1_pins {
|
|
+ pins = "PD14";
|
|
+ function = "gpio_in";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target-path = "/";
|
|
+ __overlay__ {
|
|
+ onewire@0 {
|
|
+ compatible = "w1-gpio";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&w1_pins>;
|
|
+ gpios = <&pio 3 14 0>; /* PD14 */
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-i2c2.dts b/arch/arm/boot/dts/overlay/sun8i-r40-i2c2.dts
|
|
new file mode 100644
|
|
index 000000000..a1e328498
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-r40-i2c2.dts
|
|
@@ -0,0 +1,20 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c2 = "/soc/i2c@1c2b400";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c2>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-i2c3.dts b/arch/arm/boot/dts/overlay/sun8i-r40-i2c3.dts
|
|
new file mode 100644
|
|
index 000000000..949a98234
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-r40-i2c3.dts
|
|
@@ -0,0 +1,20 @@
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-h3";
|
|
+
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ i2c3 = "/soc/i2c@1c2b800";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&i2c3>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev0.dts b/arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev0.dts
|
|
new file mode 100644
|
|
index 000000000..fae9c3f75
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev0.dts
|
|
@@ -0,0 +1,27 @@
|
|
+/dts-v1/;
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-r40";
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi0 = "/soc/spi@1c05000";
|
|
+ };
|
|
+ };
|
|
+ fragment@1 {
|
|
+ target = <0xffffffff>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <0x00000001>;
|
|
+ #size-cells = <0x00000000>;
|
|
+ status = "okay";
|
|
+ spidev@0 {
|
|
+ compatible = "armbian,spi-dev";
|
|
+ status = "okay";
|
|
+ reg = <0x00000000>;
|
|
+ spi-max-frequency = <0x000f4240>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ __fixups__ {
|
|
+ spi0 = "/fragment@1:target:0";
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev1.dts b/arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev1.dts
|
|
new file mode 100644
|
|
index 000000000..cb98ddf6b
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-r40-spi-spidev1.dts
|
|
@@ -0,0 +1,27 @@
|
|
+/dts-v1/;
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-r40";
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ spi1 = "/soc/spi@1c06000";
|
|
+ };
|
|
+ };
|
|
+ fragment@1 {
|
|
+ target = <0xffffffff>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <0x00000001>;
|
|
+ #size-cells = <0x00000000>;
|
|
+ status = "okay";
|
|
+ spidev@0 {
|
|
+ compatible = "armbian,spi-dev";
|
|
+ status = "okay";
|
|
+ reg = <0x00000000>;
|
|
+ spi-max-frequency = <0x000f4240>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ __fixups__ {
|
|
+ spi1 = "/fragment@1:target:0";
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-uart2.dts b/arch/arm/boot/dts/overlay/sun8i-r40-uart2.dts
|
|
new file mode 100644
|
|
index 000000000..2030d6777
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-r40-uart2.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-r40";
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial2 = "/soc/serial@1c28800";
|
|
+ };
|
|
+ };
|
|
+ fragment@1 {
|
|
+ target = <0xffffffff>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <0xffffffff>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ __fixups__ {
|
|
+ uart2 = "/fragment@1:target:0";
|
|
+ uart2_pi_pins = "/fragment@1/__overlay__:pinctrl-0:0";
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-uart4.dts b/arch/arm/boot/dts/overlay/sun8i-r40-uart4.dts
|
|
new file mode 100644
|
|
index 000000000..0d7f934f6
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-r40-uart4.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-r40";
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial4 = "/soc/serial@1c29000";
|
|
+ };
|
|
+ };
|
|
+ fragment@1 {
|
|
+ target = <0xffffffff>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <0xffffffff>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ __fixups__ {
|
|
+ uart4 = "/fragment@1:target:0";
|
|
+ uart4_ph_pins = "/fragment@1/__overlay__:pinctrl-0:0";
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-uart5.dts b/arch/arm/boot/dts/overlay/sun8i-r40-uart5.dts
|
|
new file mode 100644
|
|
index 000000000..e695535af
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-r40-uart5.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-r40";
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial5 = "/soc/serial@1c29400";
|
|
+ };
|
|
+ };
|
|
+ fragment@1 {
|
|
+ target = <0xffffffff>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <0xffffffff>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ __fixups__ {
|
|
+ uart5 = "/fragment@1:target:0";
|
|
+ uart5_ph_pins = "/fragment@1/__overlay__:pinctrl-0:0";
|
|
+ };
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/overlay/sun8i-r40-uart7.dts b/arch/arm/boot/dts/overlay/sun8i-r40-uart7.dts
|
|
new file mode 100644
|
|
index 000000000..e57259833
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/overlay/sun8i-r40-uart7.dts
|
|
@@ -0,0 +1,22 @@
|
|
+/dts-v1/;
|
|
+/ {
|
|
+ compatible = "allwinner,sun8i-r40";
|
|
+ fragment@0 {
|
|
+ target-path = "/aliases";
|
|
+ __overlay__ {
|
|
+ serial7 = "/soc/serial@1c29c00";
|
|
+ };
|
|
+ };
|
|
+ fragment@1 {
|
|
+ target = <0xffffffff>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <0xffffffff>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+ __fixups__ {
|
|
+ uart7 = "/fragment@1:target:0";
|
|
+ uart7_pi_pins = "/fragment@1/__overlay__:pinctrl-0:0";
|
|
+ };
|
|
+};
|
|
--
|
|
2.35.3
|
|
|