80 lines
2.8 KiB
Diff
80 lines
2.8 KiB
Diff
From 9eb08837ea313181edc163501db67e4f3cb62cff Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megi@xff.cz>
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Date: Mon, 28 Nov 2022 10:12:50 +0100
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Subject: [PATCH 322/469] drm: rockchip: dw-mipi-dsi: Fix hsclk calculation for
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non-burst video modes
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For panels that don't use video burst mode, hsclock should match the
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pixel clock * bpp / lane exactly. This fixes display image corruption
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on Pinephone Pro, which doesn't use video burst mode to drive the panel.
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To simplify the addition of exact fout calculation for non-burst modes,
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the code is re-organized in order to not redo the same calculation
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multiple times, and to use identical algorithm for per-lane bitrate
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for internal and external dphy use cases.
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Signed-off-by: Ondrej Jirman <megi@xff.cz>
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---
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.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 28 ++++++++-----------
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1 file changed, 12 insertions(+), 16 deletions(-)
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diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
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index 917e79951aac..47890245f85f 100644
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--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
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+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
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@@ -542,8 +542,6 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
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{
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struct dw_mipi_dsi_rockchip *dsi = priv_data;
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int bpp;
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- unsigned long mpclk, tmp;
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- unsigned int target_mbps = 1000;
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unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
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unsigned long best_freq = 0;
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unsigned long fvco_min, fvco_max, fin, fout;
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@@ -561,30 +559,28 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
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return bpp;
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}
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- mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
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- if (mpclk) {
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- /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
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- tmp = mpclk * (bpp / lanes) * 10 / 8;
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- if (tmp < max_mbps)
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- target_mbps = tmp;
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- else
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- DRM_DEV_ERROR(dsi->dev,
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- "DPHY clock frequency is out of range\n");
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+ fout = mode->clock * bpp / lanes;
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+ if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
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+ fout = fout * 12 / 10;
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+ fout *= MSEC_PER_SEC;
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+
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+ if (fout > max_mbps * USEC_PER_SEC) {
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+ DRM_DEV_ERROR(dsi->dev,
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+ "DPHY clock frequency is out of range\n");
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+ return -EINVAL;
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}
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- /* for external phy only a the mipi_dphy_config is necessary */
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+ /* for external phy only the mipi_dphy_config is necessary */
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if (dsi->phy) {
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- phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8,
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- bpp, lanes,
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+ phy_mipi_dphy_get_default_config_for_hsclk(fout, lanes,
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&dsi->phy_opts.mipi_dphy);
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- dsi->lane_mbps = target_mbps;
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+ dsi->lane_mbps = DIV_ROUND_UP(fout, USEC_PER_SEC);
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*lane_mbps = dsi->lane_mbps;
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return 0;
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}
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fin = clk_get_rate(dsi->pllref_clk);
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- fout = target_mbps * USEC_PER_SEC;
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/* constraint: 5Mhz <= Fref / N <= 40MHz */
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min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
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--
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2.34.1
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