69 lines
1.7 KiB
Diff
69 lines
1.7 KiB
Diff
From 04fe537c6a4f0f839f6077246da7425410506819 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Wed, 19 Apr 2023 20:49:46 +0200
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Subject: [PATCH 432/469] dt-bindings: PCI: dwc: rockchip: Update for RK3588
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The PCIe 2.0 controllers on RK3588 need one additional clock,
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one additional reset line and one for ranges entry.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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---
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.../bindings/pci/rockchip-dw-pcie.yaml | 16 +++++++++++++---
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1 file changed, 13 insertions(+), 3 deletions(-)
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diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
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index bf81d306cc80..7897af0ec297 100644
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--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
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+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
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@@ -41,20 +41,24 @@ properties:
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- const: config
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clocks:
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+ minItems: 5
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items:
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- description: AHB clock for PCIe master
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- description: AHB clock for PCIe slave
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- description: AHB clock for PCIe dbi
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- description: APB clock for PCIe
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- description: Auxiliary clock for PCIe
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+ - description: PIPE clock
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clock-names:
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+ minItems: 5
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items:
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- const: aclk_mst
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- const: aclk_slv
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- const: aclk_dbi
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- const: pclk
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- const: aux
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+ - const: pipe
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interrupts:
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maxItems: 5
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@@ -97,13 +101,19 @@ properties:
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maxItems: 1
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ranges:
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- maxItems: 2
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+ minItems: 2
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+ maxItems: 3
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resets:
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- maxItems: 1
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+ minItems: 1
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+ maxItems: 2
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reset-names:
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- const: pipe
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+ oneOf:
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+ - const: pipe
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+ - items:
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+ - const: pwr
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+ - const: pipe
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vpcie3v3-supply: true
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--
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2.34.1
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