424 lines
14 KiB
Diff
424 lines
14 KiB
Diff
From 9d7f24dccedb91015a556ca7759c4be9acb95581 Mon Sep 17 00:00:00 2001
|
|
From: Ondrej Jirman <megi@xff.cz>
|
|
Date: Sat, 10 Jun 2023 18:28:40 +0200
|
|
Subject: [PATCH 448/464] arm64: dts: rockchip: add PCIE3 controller and phy
|
|
for RK3588
|
|
|
|
RK3588 has one PCIE3 x4 lanes, with one dedicated PCIE phy.
|
|
|
|
This introduces the following needed nodes:
|
|
|
|
- pcie30_phy_grf node
|
|
With the existing rk3588-pcie3-phy-grf compatible string.
|
|
|
|
- pcie3x4 and pcie3x2 nodes
|
|
The main nodes for the pcie controller.
|
|
They share the same phy, thus only one of them can be enabled.
|
|
|
|
- pcie30phy node
|
|
It's the dedicated PCIE phy.
|
|
|
|
The differences between upstream and downstream dts are:
|
|
|
|
- The interrupt cells
|
|
Upstream has two ppi partitions, thus requires #interrupt-cells = <4>
|
|
to specify which partition is preferred.
|
|
|
|
- The configuration space
|
|
The downstream goes with an invalid range window, and modifies
|
|
DesignWare driver to use that invalid range as configure space.
|
|
|
|
Change the cursed method to use the proper "config" reg.
|
|
|
|
- Reg names
|
|
The downstream always has unnecessary "pcie-" prefix, while upstream
|
|
DesignWare driver never checks such prefix.
|
|
|
|
Signed-off-by: Qu Wenruo <wqu@suse.com>
|
|
Signed-off-by: Ondrej Jirman <megi@xff.cz>
|
|
---
|
|
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 130 ++++++++++++++++++++--
|
|
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 ++++++-------
|
|
2 files changed, 160 insertions(+), 50 deletions(-)
|
|
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
|
|
index a0ab543c4c54..5f4877e1d2d4 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
|
|
@@ -35,6 +35,11 @@ usbdrd_dwc3_1: usb@fc400000 {
|
|
};
|
|
};
|
|
|
|
+ pcie30_phy_grf: syscon@fd5b8000 {
|
|
+ compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
|
|
+ reg = <0x0 0xfd5b8000 0x0 0x10000>;
|
|
+ };
|
|
+
|
|
pipe_phy1_grf: syscon@fd5c0000 {
|
|
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
|
reg = <0x0 0xfd5c0000 0x0 0x100>;
|
|
@@ -139,6 +144,108 @@ i2s10_8ch: i2s@fde00000 {
|
|
status = "disabled";
|
|
};
|
|
|
|
+ pcie3x4: pcie@fe150000 {
|
|
+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ bus-range = <0x00 0x0f>;
|
|
+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
|
|
+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
|
|
+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
|
|
+ clock-names = "aclk_mst", "aclk_slv",
|
|
+ "aclk_dbi", "pclk",
|
|
+ "aux", "pipe";
|
|
+ device_type = "pci";
|
|
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
|
|
+ <0 0 0 2 &pcie3x4_intc 1>,
|
|
+ <0 0 0 3 &pcie3x4_intc 2>,
|
|
+ <0 0 0 4 &pcie3x4_intc 3>;
|
|
+ linux,pci-domain = <0>;
|
|
+ max-link-speed = <3>;
|
|
+ msi-map = <0x0000 &its1 0x0000 0x1000>;
|
|
+ num-lanes = <4>;
|
|
+ phys = <&pcie30phy>;
|
|
+ phy-names = "pcie-phy";
|
|
+ power-domains = <&power RK3588_PD_PCIE>;
|
|
+ ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
|
|
+ <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
|
|
+ <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
|
|
+ reg = <0xa 0x40000000 0x0 0x00400000>,
|
|
+ <0x0 0xfe150000 0x0 0x00010000>,
|
|
+ <0x0 0xf0000000 0x0 0x00100000>;
|
|
+ reg-names = "dbi", "apb", "config";
|
|
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
|
|
+ reset-names = "pwr", "pipe";
|
|
+ status = "disabled";
|
|
+
|
|
+ pcie3x4_intc: legacy-interrupt-controller {
|
|
+ interrupt-controller;
|
|
+ #address-cells = <0>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-parent = <&gic>;
|
|
+ interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pcie3x2: pcie@fe160000 {
|
|
+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ bus-range = <0x10 0x1f>;
|
|
+ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
|
|
+ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
|
|
+ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
|
|
+ clock-names = "aclk_mst", "aclk_slv",
|
|
+ "aclk_dbi", "pclk",
|
|
+ "aux", "pipe";
|
|
+ device_type = "pci";
|
|
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
+ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
|
|
+ <0 0 0 2 &pcie3x2_intc 1>,
|
|
+ <0 0 0 3 &pcie3x2_intc 2>,
|
|
+ <0 0 0 4 &pcie3x2_intc 3>;
|
|
+ linux,pci-domain = <1>;
|
|
+ max-link-speed = <3>;
|
|
+ msi-map = <0x1000 &its1 0x1000 0x1000>;
|
|
+ num-lanes = <2>;
|
|
+ phys = <&pcie30phy>;
|
|
+ phy-names = "pcie-phy";
|
|
+ power-domains = <&power RK3588_PD_PCIE>;
|
|
+ ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
|
|
+ <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
|
|
+ <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
|
|
+ reg = <0xa 0x40400000 0x0 0x00400000>,
|
|
+ <0x0 0xfe160000 0x0 0x00010000>,
|
|
+ <0x0 0xf1000000 0x0 0x00100000>;
|
|
+ reg-names = "dbi", "apb", "config";
|
|
+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
|
|
+ reset-names = "pwr", "pipe";
|
|
+ status = "disabled";
|
|
+
|
|
+ pcie3x2_intc: legacy-interrupt-controller {
|
|
+ interrupt-controller;
|
|
+ #address-cells = <0>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-parent = <&gic>;
|
|
+ interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
pcie2x1l0: pcie@fe170000 {
|
|
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
|
#address-cells = <3>;
|
|
@@ -164,9 +271,6 @@ pcie2x1l0: pcie@fe170000 {
|
|
<0 0 0 3 &pcie2x1l0_intc 2>,
|
|
<0 0 0 4 &pcie2x1l0_intc 3>;
|
|
linux,pci-domain = <2>;
|
|
- num-ib-windows = <8>;
|
|
- num-ob-windows = <8>;
|
|
- num-viewport = <4>;
|
|
max-link-speed = <2>;
|
|
msi-map = <0x2000 &its0 0x2000 0x1000>;
|
|
num-lanes = <1>;
|
|
@@ -175,7 +279,7 @@ pcie2x1l0: pcie@fe170000 {
|
|
power-domains = <&power RK3588_PD_PCIE>;
|
|
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
|
|
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
|
|
- <0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
|
|
+ <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
|
|
reg = <0xa 0x40800000 0x0 0x00400000>,
|
|
<0x0 0xfe170000 0x0 0x00010000>,
|
|
<0x0 0xf2000000 0x0 0x00100000>;
|
|
@@ -191,7 +295,6 @@ pcie2x1l0_intc: legacy-interrupt-controller {
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
|
|
};
|
|
-
|
|
};
|
|
|
|
gmac0: ethernet@fe1b0000 {
|
|
@@ -246,11 +349,11 @@ gmac0_mtl_tx_setup: tx-queues-config {
|
|
sata1: sata@fe220000 {
|
|
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
|
reg = <0 0xfe220000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
|
|
<&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
|
|
<&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
|
|
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
|
- interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
ports-implemented = <0x1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
@@ -300,16 +403,29 @@ usbdp_phy1_u3: usb3-port {
|
|
combphy1_ps: phy@fee10000 {
|
|
compatible = "rockchip,rk3588-naneng-combphy";
|
|
reg = <0x0 0xfee10000 0x0 0x100>;
|
|
- #phy-cells = <1>;
|
|
clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
|
|
<&cru PCLK_PHP_ROOT>;
|
|
clock-names = "ref", "apb", "pipe";
|
|
assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
|
|
assigned-clock-rates = <100000000>;
|
|
+ #phy-cells = <1>;
|
|
resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
|
|
reset-names = "phy", "apb";
|
|
rockchip,pipe-grf = <&php_grf>;
|
|
rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
|
|
status = "disabled";
|
|
};
|
|
+
|
|
+ pcie30phy: phy@fee80000 {
|
|
+ compatible = "rockchip,rk3588-pcie3-phy";
|
|
+ reg = <0x0 0xfee80000 0x0 0x20000>;
|
|
+ #phy-cells = <0>;
|
|
+ clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
|
|
+ clock-names = "pclk";
|
|
+ resets = <&cru SRST_PCIE30_PHY>;
|
|
+ reset-names = "phy";
|
|
+ rockchip,pipe-grf = <&php_grf>;
|
|
+ rockchip,phy-grf = <&pcie30_phy_grf>;
|
|
+ status = "disabled";
|
|
+ };
|
|
};
|
|
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
|
index e19f7716b601..b272af6a40d0 100644
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
|
@@ -8,9 +8,9 @@
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/power/rk3588-power.h>
|
|
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
|
|
-#include <dt-bindings/thermal/thermal.h>
|
|
#include <dt-bindings/phy/phy.h>
|
|
#include <dt-bindings/ata/ahci.h>
|
|
+#include <dt-bindings/thermal/thermal.h>
|
|
|
|
/ {
|
|
compatible = "rockchip,rk3588";
|
|
@@ -949,6 +949,36 @@ sys_grf: syscon@fd58c000 {
|
|
reg = <0x0 0xfd58c000 0x0 0x1000>;
|
|
};
|
|
|
|
+ bigcore0_grf: syscon@fd590000 {
|
|
+ compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
|
|
+ reg = <0x0 0xfd590000 0x0 0x100>;
|
|
+ };
|
|
+
|
|
+ bigcore1_grf: syscon@fd592000 {
|
|
+ compatible = "rockchip,rk3588-bigcore1-grf", "syscon";
|
|
+ reg = <0x0 0xfd592000 0x0 0x100>;
|
|
+ };
|
|
+
|
|
+ php_grf: syscon@fd5b0000 {
|
|
+ compatible = "rockchip,rk3588-php-grf", "syscon";
|
|
+ reg = <0x0 0xfd5b0000 0x0 0x1000>;
|
|
+ };
|
|
+
|
|
+ pipe_phy0_grf: syscon@fd5bc000 {
|
|
+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
|
+ reg = <0x0 0xfd5bc000 0x0 0x100>;
|
|
+ };
|
|
+
|
|
+ pipe_phy2_grf: syscon@fd5c4000 {
|
|
+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
|
+ reg = <0x0 0xfd5c4000 0x0 0x100>;
|
|
+ };
|
|
+
|
|
+ usbdpphy0_grf: syscon@fd5c8000 {
|
|
+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
|
+ reg = <0x0 0xfd5c8000 0x0 0x4000>;
|
|
+ };
|
|
+
|
|
usb2phy0_grf: syscon@fd5d0000 {
|
|
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
|
|
"simple-mfd";
|
|
@@ -1036,36 +1066,6 @@ u2phy3_host: host-port {
|
|
};
|
|
};
|
|
|
|
- bigcore0_grf: syscon@fd590000 {
|
|
- compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
|
|
- reg = <0x0 0xfd590000 0x0 0x100>;
|
|
- };
|
|
-
|
|
- bigcore1_grf: syscon@fd592000 {
|
|
- compatible = "rockchip,rk3588-bigcore1-grf", "syscon";
|
|
- reg = <0x0 0xfd592000 0x0 0x100>;
|
|
- };
|
|
-
|
|
- php_grf: syscon@fd5b0000 {
|
|
- compatible = "rockchip,rk3588-php-grf", "syscon";
|
|
- reg = <0x0 0xfd5b0000 0x0 0x1000>;
|
|
- };
|
|
-
|
|
- pipe_phy0_grf: syscon@fd5bc000 {
|
|
- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
|
- reg = <0x0 0xfd5bc000 0x0 0x100>;
|
|
- };
|
|
-
|
|
- pipe_phy2_grf: syscon@fd5c4000 {
|
|
- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
|
- reg = <0x0 0xfd5c4000 0x0 0x100>;
|
|
- };
|
|
-
|
|
- usbdpphy0_grf: syscon@fd5c8000 {
|
|
- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
|
- reg = <0x0 0xfd5c8000 0x0 0x4000>;
|
|
- };
|
|
-
|
|
ioc: syscon@fd5f0000 {
|
|
compatible = "rockchip,rk3588-ioc", "syscon";
|
|
reg = <0x0 0xfd5f0000 0x0 0x10000>;
|
|
@@ -1805,9 +1805,6 @@ pcie2x1l1: pcie@fe180000 {
|
|
<0 0 0 3 &pcie2x1l1_intc 2>,
|
|
<0 0 0 4 &pcie2x1l1_intc 3>;
|
|
linux,pci-domain = <3>;
|
|
- num-ib-windows = <8>;
|
|
- num-ob-windows = <8>;
|
|
- num-viewport = <4>;
|
|
max-link-speed = <2>;
|
|
msi-map = <0x3000 &its0 0x3000 0x1000>;
|
|
num-lanes = <1>;
|
|
@@ -1816,7 +1813,7 @@ pcie2x1l1: pcie@fe180000 {
|
|
power-domains = <&power RK3588_PD_PCIE>;
|
|
ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
|
|
<0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
|
|
- <0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
|
|
+ <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
|
|
reg = <0xa 0x40c00000 0x0 0x00400000>,
|
|
<0x0 0xfe180000 0x0 0x00010000>,
|
|
<0x0 0xf3000000 0x0 0x00100000>;
|
|
@@ -1859,9 +1856,6 @@ pcie2x1l2: pcie@fe190000 {
|
|
<0 0 0 3 &pcie2x1l2_intc 2>,
|
|
<0 0 0 4 &pcie2x1l2_intc 3>;
|
|
linux,pci-domain = <4>;
|
|
- num-ib-windows = <8>;
|
|
- num-ob-windows = <8>;
|
|
- num-viewport = <4>;
|
|
max-link-speed = <2>;
|
|
msi-map = <0x4000 &its0 0x4000 0x1000>;
|
|
num-lanes = <1>;
|
|
@@ -1870,7 +1864,7 @@ pcie2x1l2: pcie@fe190000 {
|
|
power-domains = <&power RK3588_PD_PCIE>;
|
|
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
|
|
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
|
|
- <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
|
|
+ <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
|
|
reg = <0xa 0x41000000 0x0 0x00400000>,
|
|
<0x0 0xfe190000 0x0 0x00010000>,
|
|
<0x0 0xf4000000 0x0 0x00100000>;
|
|
@@ -1940,11 +1934,11 @@ gmac1_mtl_tx_setup: tx-queues-config {
|
|
sata0: sata@fe210000 {
|
|
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
|
reg = <0 0xfe210000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
|
|
<&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
|
|
<&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
|
|
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
|
- interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
ports-implemented = <0x1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
@@ -1963,11 +1957,11 @@ sata-port@0 {
|
|
sata2: sata@fe230000 {
|
|
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
|
reg = <0 0xfe230000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
|
|
<&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
|
|
<&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
|
|
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
|
- interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
ports-implemented = <0x1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
@@ -2801,12 +2795,12 @@ usbdp_phy0_u3: usb3-port {
|
|
combphy0_ps: phy@fee00000 {
|
|
compatible = "rockchip,rk3588-naneng-combphy";
|
|
reg = <0x0 0xfee00000 0x0 0x100>;
|
|
- #phy-cells = <1>;
|
|
clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
|
|
<&cru PCLK_PHP_ROOT>;
|
|
clock-names = "ref", "apb", "pipe";
|
|
assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
|
|
assigned-clock-rates = <100000000>;
|
|
+ #phy-cells = <1>;
|
|
resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
|
|
reset-names = "phy", "apb";
|
|
rockchip,pipe-grf = <&php_grf>;
|
|
@@ -2817,12 +2811,12 @@ combphy0_ps: phy@fee00000 {
|
|
combphy2_psu: phy@fee20000 {
|
|
compatible = "rockchip,rk3588-naneng-combphy";
|
|
reg = <0x0 0xfee20000 0x0 0x100>;
|
|
- #phy-cells = <1>;
|
|
clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
|
|
<&cru PCLK_PHP_ROOT>;
|
|
clock-names = "ref", "apb", "pipe";
|
|
assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
|
|
assigned-clock-rates = <100000000>;
|
|
+ #phy-cells = <1>;
|
|
resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
|
|
reset-names = "phy", "apb";
|
|
rockchip,pipe-grf = <&php_grf>;
|
|
--
|
|
2.34.1
|
|
|