193 lines
5.6 KiB
Diff
193 lines
5.6 KiB
Diff
From 9f41c90afbcc7434aa1779992225ce492bfcd2a1 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Tue, 25 Apr 2023 17:38:57 +0200
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Subject: [PATCH 441/464] dt-bindings: phy: add rockchip usbdp combo phy
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document
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Add device tree binding document for Rockchip USBDP Combo PHY
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with Samsung IP block.
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Co-developed-by: Frank Wang <frank.wang@rock-chips.com>
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Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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---
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.../bindings/phy/phy-rockchip-usbdp.yaml | 166 ++++++++++++++++++
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1 file changed, 166 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
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diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
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new file mode 100644
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index 000000000000..dcca84d57e99
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
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@@ -0,0 +1,166 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Rockchip USBDP Combo PHY with Samsung IP block
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+
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+maintainers:
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+ - Frank Wang <frank.wang@rock-chips.com>
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+ - Zhang Yubing <yubing.zhang@rock-chips.com>
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+
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+properties:
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+ compatible:
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+ enum:
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+ - rockchip,rk3588-usbdp-phy
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ maxItems: 4
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+
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+ clock-names:
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+ items:
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+ - const: refclk
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+ - const: immortal
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+ - const: pclk
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+ - const: utmi
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+
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+ resets:
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+ maxItems: 5
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+
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+ reset-names:
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+ items:
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+ - const: init
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+ - const: cmn
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+ - const: lane
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+ - const: pcs_apb
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+ - const: pma_apb
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+
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+ rockchip,dp-lane-mux:
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+ $ref: /schemas/types.yaml#/definitions/uint32-array
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+ minItems: 2
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+ maxItems: 4
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+ description:
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+ An array of physical Tyep-C lanes indexes. Position of an entry determines
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+ the dp lane index, while the value of an entry indicater physical Type-C lane.
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+ The support dp lanes number are 2 or 4. e.g. for 2 lanes dp lanes map, we could
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+ have "rockchip,dp-lane-mux = <2, 3>;", assuming dp lane0 on Type-C phy lane2,
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+ dp lane1 on Type-C phy lane3. For 4 lanes dp lanes map, we could have
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+ "rockchip,dp-lane-mux = <0, 1, 2, 3>;", assuming dp lane0 on Type-C phy lane0,
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+ dp lane1 on Type-C phy lane1, dp lane2 on Type-C phy lane2, dp lane3 on Type-C
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+ phy lane3. If dp lane map by DisplayPort Alt mode, this property is not need.
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+
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+ rockchip,u2phy-grf:
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+ $ref: /schemas/types.yaml#/definitions/phandle
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+ description:
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+ Phandle to the syscon managing the 'usb2 phy general register files'.
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+
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+ rockchip,usb-grf:
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+ $ref: /schemas/types.yaml#/definitions/phandle
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+ description:
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+ Phandle to the syscon managing the 'usb general register files'.
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+
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+ rockchip,usbdpphy-grf:
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+ $ref: /schemas/types.yaml#/definitions/phandle
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+ description:
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+ Phandle to the syscon managing the 'usbdp phy general register files'.
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+
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+ rockchip,vo-grf:
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+ $ref: /schemas/types.yaml#/definitions/phandle
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+ description:
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+ Phandle to the syscon managing the 'video output general register files'.
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+ When select the dp lane mapping will request its phandle.
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+
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+ sbu1-dc-gpios:
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+ description:
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+ GPIO connected to the SBU1 line of the USB-C connector via a big resistor
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+ (~100K) to apply a DC offset for signalling the connector orientation.
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+
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+ sbu2-dc-gpios:
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+ description:
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+ GPIO connected to the SBU2 line of the USB-C connector via a big resistor
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+ (~100K) to apply a DC offset for signalling the connector orientation.
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+
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+ orientation-switch:
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+ description: Flag the port as possible handler of orientation switching
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+ type: boolean
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+
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+ mode-switch:
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+ description: Flag the port as possible handle of altmode switching
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+ type: boolean
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+
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+ dp-port:
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+ type: object
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+ additionalProperties: false
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+
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+ properties:
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+ "#phy-cells":
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+ const: 0
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+
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+ required:
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+ - "#phy-cells"
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+
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+ usb3-port:
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+ type: object
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+ additionalProperties: false
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+
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+ properties:
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+ "#phy-cells":
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+ const: 0
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+
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+ required:
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+ - "#phy-cells"
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+
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+ port:
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+ $ref: /schemas/graph.yaml#/properties/port
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+ description:
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+ A port node to link the PHY to a TypeC controller for the purpose of
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+ handling orientation switching.
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - resets
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+ - reset-names
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+ - dp-port
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+ - usb3-port
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/rk3588-cru.h>
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+
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+ usbdp_phy0: phy@fed80000 {
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+ compatible = "rockchip,rk3588-usbdp-phy";
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+ reg = <0x0 0xfed80000 0x0 0x10000>;
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+ rockchip,u2phy-grf = <&usb2phy0_grf>;
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+ rockchip,usb-grf = <&usb_grf>;
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+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
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+ rockchip,vo-grf = <&vo0_grf>;
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+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
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+ <&cru CLK_USBDP_PHY0_IMMORTAL>,
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+ <&cru PCLK_USBDPPHY0>;
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+ clock-names = "refclk", "immortal", "pclk";
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+ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
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+ <&cru SRST_USBDP_COMBO_PHY0_CMN>,
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+ <&cru SRST_USBDP_COMBO_PHY0_LANE>,
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+ <&cru SRST_USBDP_COMBO_PHY0_PCS>,
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+ <&cru SRST_P_USBDPPHY0>;
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+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
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+ status = "disabled";
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+
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+ usbdp_phy0_dp: dp-port {
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ usbdp_phy0_u3: usb3-port {
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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--
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2.34.1
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