141 lines
3.8 KiB
Diff
141 lines
3.8 KiB
Diff
--- a/arch/arm/dts/rk3328.dtsi
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+++ b/arch/arm/dts/rk3328.dtsi
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@@ -849,6 +849,47 @@
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};
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};
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+ usb3phy_grf: syscon@ff460000 {
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+ compatible = "rockchip,usb3phy-grf", "syscon";
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+ reg = <0x0 0xff460000 0x0 0x1000>;
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+ };
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+
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+ u3phy: usb3-phy@ff470000 {
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+ compatible = "rockchip,rk3328-u3phy";
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+ reg = <0x0 0xff470000 0x0 0x0>;
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+ rockchip,u3phygrf = <&usb3phy_grf>;
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+ rockchip,grf = <&grf>;
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+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "linestate";
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+ clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
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+ clock-names = "u3phy-otg", "u3phy-pipe";
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+ resets = <&cru SRST_USB3PHY_U2>,
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+ <&cru SRST_USB3PHY_U3>,
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+ <&cru SRST_USB3PHY_PIPE>,
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+ <&cru SRST_USB3OTG_UTMI>,
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+ <&cru SRST_USB3PHY_OTG_P>,
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+ <&cru SRST_USB3PHY_PIPE_P>;
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+ reset-names = "u3phy-u2-por", "u3phy-u3-por",
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+ "u3phy-pipe-mac", "u3phy-utmi-mac",
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+ "u3phy-utmi-apb", "u3phy-pipe-apb";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ status = "disabled";
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+
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+ u3phy_utmi: utmi@ff470000 {
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+ reg = <0x0 0xff470000 0x0 0x8000>;
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ u3phy_pipe: pipe@ff478000 {
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+ reg = <0x0 0xff478000 0x0 0x8000>;
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+ };
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+
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sdmmc: mmc@ff500000 {
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compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xff500000 0x0 0x4000>;
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@@ -858,6 +899,8 @@
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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max-frequency = <150000000>;
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+ resets = <&cru SRST_MMC0>;
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+ reset-names = "reset";
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status = "disabled";
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};
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@@ -870,6 +913,8 @@
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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max-frequency = <150000000>;
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+ resets = <&cru SRST_SDIO>;
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+ reset-names = "reset";
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status = "disabled";
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};
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@@ -882,6 +927,8 @@
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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max-frequency = <150000000>;
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+ resets = <&cru SRST_EMMC>;
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+ reset-names = "reset";
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status = "disabled";
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};
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@@ -964,23 +1011,49 @@
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status = "disabled";
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};
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+ sdmmc_ext: mmc@ff5f0000 {
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+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
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+ reg = <0x0 0xff5f0000 0x0 0x4000>;
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+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
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+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
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+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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+ fifo-depth = <0x100>;
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+ max-frequency = <150000000>;
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+ resets = <&cru SRST_SDMMCEXT>;
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+ reset-names = "reset";
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+ status = "disabled";
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+ };
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+
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usbdrd3: usb@ff600000 {
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- compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
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- reg = <0x0 0xff600000 0x0 0x100000>;
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- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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+ compatible = "rockchip,rk3328-dwc3";
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clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
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<&cru ACLK_USB3OTG>;
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clock-names = "ref_clk", "suspend_clk",
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"bus_clk";
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- dr_mode = "otg";
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- phy_type = "utmi_wide";
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- snps,dis-del-phy-power-chg-quirk;
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- snps,dis_enblslpm_quirk;
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- snps,dis-tx-ipgap-linecheck-quirk;
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- snps,dis-u2-freeclk-exists-quirk;
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- snps,dis_u2_susphy_quirk;
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- snps,dis_u3_susphy_quirk;
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- status = "disabled";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ status = "disabled";
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+
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+ usbdrd_dwc3: dwc3@ff600000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x0 0xff600000 0x0 0x100000>;
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+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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+ dr_mode = "host";
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+ phys = <&u3phy_utmi>, <&u3phy_pipe>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ phy_type = "utmi_wide";
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+ snps,dis_enblslpm_quirk;
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+ snps,dis-u2-freeclk-exists-quirk;
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+ snps,dis_u2_susphy_quirk;
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+ snps,dis-u3-autosuspend-quirk;
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+ snps,dis_u3_susphy_quirk;
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+ snps,dis-del-phy-power-chg-quirk;
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+ snps,tx-ipgap-linecheck-dis-quirk;
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+ snps,xhci-trb-ent-quirk;
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+ status = "disabled";
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+ };
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};
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/*
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