116 lines
3.7 KiB
Plaintext
116 lines
3.7 KiB
Plaintext
From 550e15099408decc58fb439edcd2e320570b8bf4 Mon Sep 17 00:00:00 2001
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From: jamess_huang <Jamess_Huang@asus.com>
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Date: Fri, 11 Aug 2017 17:47:45 +0800
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Subject: [PATCH 17/50] Fix HDMI some issues
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This patch:
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use 1080P display_timing when connect 4K HDMI screen.
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correct rockchip_mpll_config & rockchip_phy_config .mpixelclock.
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add some hdmi-to-vga support
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Change-Id: Ic7faf4dd7ea490051493397058aa5bad1d8788c1
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---
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common/Kconfig | 2 +-
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drivers/video/dw_hdmi.c | 8 ++++----
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drivers/video/rockchip/rk_vop.c | 14 ++++++++++++++
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include/dw_hdmi.h | 4 ++--
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4 files changed, 21 insertions(+), 7 deletions(-)
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diff --git a/common/Kconfig b/common/Kconfig
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index 361346b092..355e816c9d 100644
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--- a/common/Kconfig
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+++ b/common/Kconfig
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@@ -245,7 +245,7 @@ endmenu
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config BOOTDELAY
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int "delay in seconds before automatically booting"
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- default 2
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+ default 5
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depends on AUTOBOOT
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help
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Delay before automatically running bootcmd;
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diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
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index 6039d676c5..0d7a7c228d 100644
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--- a/drivers/video/dw_hdmi.c
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+++ b/drivers/video/dw_hdmi.c
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@@ -340,7 +340,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, u32 mpixelclock)
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hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
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hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
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- hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].curr, PHY_PLLCURRCTRL);
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+ hdmi_phy_i2c_write(hdmi, 0x0000, PHY_PLLCURRCTRL);
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hdmi_phy_i2c_write(hdmi, 0x0000, PHY_PLLPHBYCTRL);
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hdmi_phy_i2c_write(hdmi, 0x0006, PHY_PLLCLKBISTPHASE);
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@@ -560,8 +560,8 @@ static int hdmi_read_edid(struct dw_hdmi *hdmi, int block, u8 *buff)
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u32 n;
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/* set ddc i2c clk which devided from ddc_clk to 100khz */
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- hdmi_write(hdmi, hdmi->i2c_clk_high, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
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- hdmi_write(hdmi, hdmi->i2c_clk_low, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
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+ //hdmi_write(hdmi, hdmi->i2c_clk_high, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
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+ //hdmi_write(hdmi, hdmi->i2c_clk_low, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
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hdmi_mod(hdmi, HDMI_I2CM_DIV, HDMI_I2CM_DIV_FAST_STD_MODE,
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HDMI_I2CM_DIV_STD_MODE);
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@@ -663,7 +663,7 @@ int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi)
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if (hdmi_get_plug_in_status(hdmi))
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return 0;
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udelay(100);
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- } while (get_timer(start) < 300);
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+ } while (get_timer(start) < 5000);
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return -1;
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}
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diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
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index c979049b5b..7bcc3df69b 100644
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--- a/drivers/video/rockchip/rk_vop.c
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+++ b/drivers/video/rockchip/rk_vop.c
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@@ -277,6 +277,20 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node)
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return ret;
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}
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+ /* Use 1080p display_timing when connect 4K HDMI screen */
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+ if (timing.hactive.typ >= 3840) {
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+ timing.pixelclock.typ = 148500000;
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+ timing.hactive.typ = 1920;
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+ timing.vactive.typ = 1080;
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+ timing.hsync_len.typ = 44;
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+ timing.hback_porch.typ = 148;
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+ timing.vsync_len.typ = 5;
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+ timing.vback_porch.typ = 36;
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+ timing.hfront_porch.typ = 88;
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+ timing.vfront_porch.typ = 4;
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+ debug("Use default 1080P settings \n");
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+ }
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+
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ret = clk_get_by_index(dev, 1, &clk);
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if (!ret)
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ret = clk_set_rate(&clk, timing.pixelclock.typ);
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diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
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index 902abd4d44..c1f1fbff6a 100644
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--- a/include/dw_hdmi.h
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+++ b/include/dw_hdmi.h
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@@ -448,7 +448,7 @@ enum {
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};
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struct hdmi_mpll_config {
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- u64 mpixelclock;
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+ u32 mpixelclock;
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/* Mode of Operation and PLL Dividers Control Register */
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u32 cpce;
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/* PLL Gmp Control Register */
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@@ -458,7 +458,7 @@ struct hdmi_mpll_config {
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};
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struct hdmi_phy_config {
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- u64 mpixelclock;
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+ u32 mpixelclock;
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u32 sym_ctr; /* clock symbol and transmitter control */
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u32 term; /* transmission termination value */
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u32 vlev_ctr; /* voltage level control */
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--
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2.17.1
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