105 lines
3.3 KiB
Diff
105 lines
3.3 KiB
Diff
From a99411d3be343e87de6e89df7b96913d723b8b17 Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@armlinux.org.uk>
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Date: Tue, 2 Feb 2021 13:45:28 +0000
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Subject: PCI: pci-bridge-emul: re-arrange register tests
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Re-arrange the tests for which sets of registers are being accessed
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so that it is easier to add further regions later. No functional
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change.
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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---
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drivers/pci/pci-bridge-emul.c | 53 ++++++++++++++++++++++---------------------
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1 file changed, 27 insertions(+), 26 deletions(-)
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diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
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index fdaf86a888b7..9988078e7b0e 100644
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--- a/drivers/pci/pci-bridge-emul.c
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+++ b/drivers/pci/pci-bridge-emul.c
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@@ -328,25 +328,25 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
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__le32 *cfgspace;
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const struct pci_bridge_reg_behavior *behavior;
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- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
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- *value = 0;
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- return PCIBIOS_SUCCESSFUL;
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- }
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-
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- if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
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+ if (reg < PCI_BRIDGE_CONF_END) {
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+ /* Emulated PCI space */
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+ read_op = bridge->ops->read_base;
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+ cfgspace = (__le32 *) &bridge->conf;
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+ behavior = bridge->pci_regs_behavior;
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+ } else if (!bridge->has_pcie) {
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+ /* PCIe space is not implemented, and no PCI capabilities */
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*value = 0;
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return PCIBIOS_SUCCESSFUL;
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- }
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-
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- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
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+ } else if (reg < PCI_CAP_PCIE_END) {
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+ /* Our emulated PCIe capability */
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reg -= PCI_CAP_PCIE_START;
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read_op = bridge->ops->read_pcie;
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cfgspace = (__le32 *) &bridge->pcie_conf;
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behavior = bridge->pcie_cap_regs_behavior;
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} else {
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- read_op = bridge->ops->read_base;
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- cfgspace = (__le32 *) &bridge->conf;
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- behavior = bridge->pci_regs_behavior;
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+ /* Beyond our PCIe space */
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+ *value = 0;
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+ return PCIBIOS_SUCCESSFUL;
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}
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if (read_op)
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@@ -390,11 +390,23 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
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__le32 *cfgspace;
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const struct pci_bridge_reg_behavior *behavior;
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- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
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+ if (reg < PCI_BRIDGE_CONF_END) {
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+ /* Emulated PCI space */
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+ write_op = bridge->ops->write_base;
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+ cfgspace = (__le32 *) &bridge->conf;
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+ behavior = bridge->pci_regs_behavior;
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+ } else if (!bridge->has_pcie) {
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+ /* PCIe space is not implemented, and no PCI capabilities */
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return PCIBIOS_SUCCESSFUL;
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-
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- if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
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+ } else if (reg < PCI_CAP_PCIE_END) {
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+ /* Our emulated PCIe capability */
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+ reg -= PCI_CAP_PCIE_START;
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+ write_op = bridge->ops->write_pcie;
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+ cfgspace = (__le32 *) &bridge->pcie_conf;
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+ behavior = bridge->pcie_cap_regs_behavior;
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+ } else {
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return PCIBIOS_SUCCESSFUL;
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+ }
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shift = (where & 0x3) * 8;
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@@ -411,17 +423,6 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
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- reg -= PCI_CAP_PCIE_START;
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- write_op = bridge->ops->write_pcie;
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- cfgspace = (__le32 *) &bridge->pcie_conf;
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- behavior = bridge->pcie_cap_regs_behavior;
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- } else {
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- write_op = bridge->ops->write_base;
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- cfgspace = (__le32 *) &bridge->conf;
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- behavior = bridge->pci_regs_behavior;
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- }
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-
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/* Keep all bits, except the RW bits */
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new = old & (~mask | ~behavior[reg / 4].rw);
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--
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cgit v1.2.3
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