146 lines
4.6 KiB
Diff
146 lines
4.6 KiB
Diff
From bab91927c8694e5f3a7e834343d2ec7163da4988 Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@armlinux.org.uk>
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Date: Tue, 2 Feb 2021 13:57:04 +0000
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Subject: PCI: pci-bridge-emul: add support for PCIe extended capabilities
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Add support for PCIe extended capabilities, which we just redirect to
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the emulating driver.
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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---
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drivers/pci/pci-bridge-emul.c | 52 +++++++++++++++++++++++++++++++------------
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drivers/pci/pci-bridge-emul.h | 15 +++++++++++++
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2 files changed, 53 insertions(+), 14 deletions(-)
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diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
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index 9988078e7b0e..fbff7da94245 100644
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--- a/drivers/pci/pci-bridge-emul.c
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+++ b/drivers/pci/pci-bridge-emul.c
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@@ -343,10 +343,16 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
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read_op = bridge->ops->read_pcie;
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cfgspace = (__le32 *) &bridge->pcie_conf;
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behavior = bridge->pcie_cap_regs_behavior;
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- } else {
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- /* Beyond our PCIe space */
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+ } else if (reg < PCI_CFG_SPACE_SIZE) {
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+ /* Rest of PCI space not implemented */
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*value = 0;
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return PCIBIOS_SUCCESSFUL;
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+ } else {
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+ /* PCIe extended capability space */
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+ reg -= PCI_CFG_SPACE_SIZE;
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+ read_op = bridge->ops->read_ext;
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+ cfgspace = NULL;
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+ behavior = NULL;
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}
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if (read_op)
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@@ -354,15 +360,20 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
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else
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ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
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- if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
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- *value = le32_to_cpu(cfgspace[reg / 4]);
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+ if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) {
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+ if (cfgspace)
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+ *value = le32_to_cpu(cfgspace[reg / 4]);
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+ else
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+ *value = 0;
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+ }
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/*
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* Make sure we never return any reserved bit with a value
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* different from 0.
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*/
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- *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
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- behavior[reg / 4].w1c;
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+ if (behavior)
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+ *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
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+ behavior[reg / 4].w1c;
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if (size == 1)
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*value = (*value >> (8 * (where & 3))) & 0xff;
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@@ -404,8 +415,15 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
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write_op = bridge->ops->write_pcie;
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cfgspace = (__le32 *) &bridge->pcie_conf;
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behavior = bridge->pcie_cap_regs_behavior;
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- } else {
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+ } else if (reg < PCI_CFG_SPACE_SIZE) {
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+ /* Rest of PCI space not implemented */
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return PCIBIOS_SUCCESSFUL;
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+ } else {
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+ /* PCIe extended capability space */
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+ reg -= PCI_CFG_SPACE_SIZE;
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+ write_op = bridge->ops->write_ext;
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+ cfgspace = NULL;
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+ behavior = NULL;
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}
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shift = (where & 0x3) * 8;
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@@ -423,16 +441,22 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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- /* Keep all bits, except the RW bits */
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- new = old & (~mask | ~behavior[reg / 4].rw);
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+ if (behavior) {
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+ /* Keep all bits, except the RW bits */
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+ new = old & (~mask | ~behavior[reg / 4].rw);
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- /* Update the value of the RW bits */
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- new |= (value << shift) & (behavior[reg / 4].rw & mask);
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+ /* Update the value of the RW bits */
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+ new |= (value << shift) & (behavior[reg / 4].rw & mask);
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- /* Clear the W1C bits */
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- new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
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+ /* Clear the W1C bits */
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+ new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
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+ } else {
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+ new = old & ~mask;
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+ new |= (value << shift) & mask;
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+ }
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- cfgspace[reg / 4] = cpu_to_le32(new);
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+ if (cfgspace)
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+ cfgspace[reg / 4] = cpu_to_le32(new);
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if (write_op)
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write_op(bridge, reg, old, new, mask);
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diff --git a/drivers/pci/pci-bridge-emul.h b/drivers/pci/pci-bridge-emul.h
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index b31883022a8e..5f64560aaa26 100644
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--- a/drivers/pci/pci-bridge-emul.h
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+++ b/drivers/pci/pci-bridge-emul.h
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@@ -90,6 +90,14 @@ struct pci_bridge_emul_ops {
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*/
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pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
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int reg, u32 *value);
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+
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+ /*
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+ * Same as ->read_base(), except it is for reading from the
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+ * PCIe extended capability configuration space.
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+ */
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+ pci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *bridge,
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+ int reg, u32 *value);
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+
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/*
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* Called when writing to the regular PCI bridge configuration
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* space. old is the current value, new is the new value being
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@@ -105,6 +113,13 @@ struct pci_bridge_emul_ops {
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*/
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void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
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u32 old, u32 new, u32 mask);
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+
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+ /*
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+ * Same as ->write_base(), except it is for writing from the
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+ * PCIe extended capability configuration space.
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+ */
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+ void (*write_ext)(struct pci_bridge_emul *bridge, int reg,
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+ u32 old, u32 new, u32 mask);
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};
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struct pci_bridge_reg_behavior;
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--
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cgit v1.2.3
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