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build/patch/kernel/archive/rk322x-4.4/01-linux-0001-rockchip.patch

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From 92b97663794c1ad57aaf7e66ee418bfce635a494 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 17 Apr 2017 13:09:16 +0200
Subject: [PATCH] sound/usb/quirks-table: add Realtek ALC4040
---
sound/usb/quirks-table.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h
index 69bf5cf1e91e..00672a818145 100644
--- a/sound/usb/quirks-table.h
+++ b/sound/usb/quirks-table.h
@@ -3324,4 +3324,13 @@ AU0828_DEVICE(0x2040, 0x7270, "Hauppauge", "HVR-950Q"),
}
},
+{
+ USB_DEVICE(0x0bda, 0x481a),
+ .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
+ .vendor_name = "Realtek",
+ .product_name = "ALC4040",
+ .ifnum = QUIRK_NO_INTERFACE
+ }
+},
+
#undef USB_DEVICE_VENDOR_SPEC
From 0fcd82216c0161c9dd6b54ee505988c539df91fb Mon Sep 17 00:00:00 2001
From: LongChair <LongChair@hotmail.com>
Date: Fri, 21 Apr 2017 13:39:12 +0200
Subject: [PATCH] drm/rockchip: remove unsupported 4K freqs
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index a58edabe600c..7273561fe6b1 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -510,9 +510,15 @@ dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
return MODE_BAD;
hdmi = to_rockchip_hdmi(encoder);
- if (hdmi->dev_type == RK3368_HDMI && mode->clock > 340000 &&
+ if ((hdmi->dev_type == RK3368_HDMI || hdmi->dev_type == RK3328_HDMI) &&
+ mode->clock > 340000 &&
!drm_mode_is_420(&connector->display_info, mode))
return MODE_BAD;
+
+ /* Skip bad clocks for RK3288 */
+ if (hdmi->dev_type == RK3288_HDMI && (mode->clock < 27500 || mode->clock > 340000))
+ return MODE_CLOCK_RANGE;
+
/*
* ensure all drm display mode can work, if someone want support more
* resolutions, please limit the possible_crtc, only connect to
From 28e3e0508d53dd697fc3dd75588bba08adee1bb0 Mon Sep 17 00:00:00 2001
From: xuhuicong <xhc@rock-chips.com>
Date: Fri, 23 Jun 2017 18:56:17 +0800
Subject: [PATCH] drm/rockchip: hdmi: fix no sound some time
Change-Id: Ic9f931d9a5b7bca954363293a20ca242eb0bfa6f
Signed-off-by: xuhuicong <xhc@rock-chips.com>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 8cb2cb4e61a6..30b6bd979eb8 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1991,10 +1991,6 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
- inv_val |= hdmi->sink_is_hdmi ?
- HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
- HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
-
hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
hdisplay = mode->hdisplay;
@@ -2292,6 +2288,9 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
/* not for DVI mode */
if (hdmi->sink_is_hdmi) {
dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
+ hdmi_modb(hdmi, HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE,
+ HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE,
+ HDMI_FC_INVIDCONF);
/* HDMI Initialization Step F - Configure AVI InfoFrame */
hdmi_config_AVI(hdmi, mode);
From 16f51adab10ab06bfecbd0ed9e444329debb426d Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 18 Nov 2017 11:09:39 +0100
Subject: [PATCH] rockchip: vop: force skip lines if image too big
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 76610608c723..1418402c2668 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1653,6 +1653,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
int ymirror, xmirror;
uint32_t val;
bool rb_swap, global_alpha_en;
+ int skip_lines = 0;
#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
bool AFBC_flag = false;
@@ -1689,8 +1690,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
}
mode = &crtc->state->adjusted_mode;
+
+ /*
+ * force skip lines if image too big.
+ */
actual_w = drm_rect_width(src) >> 16;
- actual_h = drm_rect_height(src) >> 16;
+ if (actual_w == 3840 && is_yuv_support(fb->pixel_format))
+ skip_lines = 1;
+ actual_h = drm_rect_height(src) >> (16 + skip_lines);
act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
dsp_info = (drm_rect_height(dest) - 1) << 16;
@@ -1727,12 +1734,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
VOP_WIN_SET(vop, win, xmirror, xmirror);
VOP_WIN_SET(vop, win, ymirror, ymirror);
VOP_WIN_SET(vop, win, format, vop_plane_state->format);
- VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
+ VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> (2 - skip_lines));
VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
VOP_WIN_SET(vop, win, yrgb_mst1, vop_plane_state->yrgb_mst);
if (is_yuv_support(fb->pixel_format)) {
- VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
+ VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> (2 - skip_lines));
VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
}
VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
From d56d2c8dcd6dc828693bed0cf965d68e90431019 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 18 Nov 2017 23:17:24 +0100
Subject: [PATCH] gpu/arm/midgard: default to performance gpu governor
---
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_devfreq.c | 5 ++---
drivers/gpu/arm/midgard/mali_kbase_config_defaults.h | 3 +--
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/arm/midgard/backend/gpu/mali_kbase_devfreq.c b/drivers/gpu/arm/midgard/backend/gpu/mali_kbase_devfreq.c
index 1495f06cd9b9..a6d2e0121015 100644
--- a/drivers/gpu/arm/midgard/backend/gpu/mali_kbase_devfreq.c
+++ b/drivers/gpu/arm/midgard/backend/gpu/mali_kbase_devfreq.c
@@ -348,8 +348,7 @@ int kbase_devfreq_init(struct kbase_device *kbdev)
dp = &kbdev->devfreq_profile;
dp->initial_freq = kbdev->current_freq;
- /* .KP : set devfreq_dvfs_interval_in_ms */
- dp->polling_ms = 20;
+ dp->polling_ms = 100;
dp->target = kbase_devfreq_target;
dp->get_dev_status = kbase_devfreq_status;
dp->get_cur_freq = kbase_devfreq_cur_freq;
diff --git a/drivers/gpu/arm/midgard/mali_kbase_config_defaults.h b/drivers/gpu/arm/midgard/mali_kbase_config_defaults.h
index 1cf44b3500cf..a6a1a52f0463 100644
--- a/drivers/gpu/arm/midgard/mali_kbase_config_defaults.h
+++ b/drivers/gpu/arm/midgard/mali_kbase_config_defaults.h
@@ -109,8 +109,7 @@ enum {
/*
* Default period for DVFS sampling
*/
-// #define DEFAULT_PM_DVFS_PERIOD 100 /* 100ms */
-#define DEFAULT_PM_DVFS_PERIOD 20 /* 20 ms */
+#define DEFAULT_PM_DVFS_PERIOD 100 /* 100ms */
/*
* Power Management poweroff tick granuality. This is in nanoseconds to
From 955a2a87c8fa737d78c022afef1ed32fd6f06760 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 10 Dec 2017 14:16:09 +0100
Subject: [PATCH] uapi: install rockchip_drm header
---
include/uapi/drm/Kbuild | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/uapi/drm/Kbuild b/include/uapi/drm/Kbuild
index 38d437096c35..b7ae9969d41e 100644
--- a/include/uapi/drm/Kbuild
+++ b/include/uapi/drm/Kbuild
@@ -11,6 +11,7 @@ header-y += nouveau_drm.h
header-y += qxl_drm.h
header-y += r128_drm.h
header-y += radeon_drm.h
+header-y += rockchip_drm.h
header-y += savage_drm.h
header-y += sis_drm.h
header-y += tegra_drm.h
From b4da8f58954748a2d459d5e480156ee2703ea169 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 10 Dec 2017 18:03:53 +0100
Subject: [PATCH] phy: rockchip-inno-hdmi-phy: add vesa dmt pixel clocks
---
drivers/phy/rockchip/phy-rockchip-inno-hdmi-phy.c | 64 +++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi-phy.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi-phy.c
index 0161f80ab964..6cf391405ad6 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi-phy.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi-phy.c
@@ -278,6 +278,70 @@ static const struct pre_pll_config pre_pll_cfg_table[] = {
{594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
{593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
{594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
+ { 25175000, 25175000, 30, 1007, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 31500000, 31500000, 1, 21, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ { 33750000, 33750000, 1, 45, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 35500000, 35500000, 3, 71, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ { 36000000, 36000000, 1, 12, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ { 49500000, 49500000, 1, 33, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ { 50000000, 50000000, 3, 50, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ { 56250000, 56250000, 1, 75, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 68250000, 68250000, 1, 91, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 72000000, 72000000, 1, 24, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ { 73250000, 73250000, 3, 293, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 75000000, 75000000, 1, 25, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ { 78750000, 78750000, 1, 105, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 79500000, 79500000, 1, 53, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ { 85500000, 85500000, 1, 57, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ { 94500000, 94500000, 1, 63, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {101000000, 101000000, 3, 101, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {102250000, 102250000, 3, 409, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {106500000, 106500000, 1, 71, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {115500000, 115500000, 1, 77, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {117500000, 117500000, 3, 235, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {121750000, 121750000, 3, 487, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {122500000, 122500000, 3, 245, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {135000000, 135000000, 1, 45, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {136750000, 136750000, 3, 547, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {140250000, 140250000, 1, 187, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {146250000, 146250000, 1, 195, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {148250000, 148250000, 3, 593, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {154000000, 154000000, 3, 154, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {156000000, 156000000, 1, 52, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {156750000, 156750000, 1, 209, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {157000000, 157000000, 3, 157, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {157500000, 157500000, 1, 105, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {175500000, 175500000, 1, 117, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {179500000, 179500000, 3, 359, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {182750000, 182750000, 3, 731, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {187000000, 187000000, 3, 187, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {187250000, 187250000, 3, 749, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {189000000, 189000000, 1, 63, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {193250000, 193250000, 3, 773, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {202500000, 202500000, 1, 135, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {204750000, 204750000, 1, 273, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {208000000, 208000000, 3, 208, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {214750000, 214750000, 3, 859, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {218250000, 218250000, 1, 291, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {229500000, 229500000, 1, 153, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {234000000, 234000000, 1, 78, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {241500000, 241500000, 1, 161, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {245250000, 245250000, 1, 327, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {245500000, 245500000, 3, 491, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {261000000, 261000000, 1, 87, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {268250000, 268250000, 3, 1073, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {268500000, 268500000, 1, 179, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {281250000, 281250000, 1, 375, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {288000000, 288000000, 1, 96, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {312250000, 312250000, 3, 1249, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {317000000, 317000000, 3, 317, 0, 1, 1, 1, 0, 2, 2, 0, 0},
+ {333250000, 333250000, 3, 1333, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {348500000, 348500000, 3, 697, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {356500000, 356500000, 3, 713, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {380500000, 380500000, 3, 761, 1, 1, 1, 1, 2, 2, 2, 0, 0},
+ {443250000, 443250000, 1, 591, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {505250000, 505250000, 3, 2021, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ {552750000, 552750000, 1, 737, 1, 2, 2, 1, 2, 3, 4, 0, 0},
{ ~0UL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
From f3f9dc1c2c697f0c9fefd501731a07ef64a026b1 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Tue, 12 Dec 2017 00:37:27 +0100
Subject: [PATCH] clk: rockchip: fix round rate
---
drivers/clk/rockchip/clk-pll.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 0a9f31f2dd27..183114d824a7 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -364,6 +364,17 @@ static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
static long rockchip_pll_round_rate(struct clk_hw *hw,
unsigned long drate, unsigned long *prate)
{
+ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
+ const struct rockchip_pll_rate_table *rate;
+
+ /* Get required rate settings from table */
+ rate = rockchip_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_debug("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
return drate;
}
From 5a5f5ea8edcc75ca49961a458ac0380e60f30a4d Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 21 Jan 2018 17:20:00 +0100
Subject: [PATCH] drm: fix HDR metadata infoframe length
HDR metadata infoframe length is 26 bytes (not 30) according to [1]
(CTA-861-G: 6.9 Dynamic Range and Mastering InfoFrame)
Fixes activation of HDR mode on my LG OLED
[1] https://standards.cta.tech/kwspub/published_docs/CTA-861-G_FINAL_revised_2017.pdf
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +-
drivers/gpu/drm/drm_edid.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 30b6bd979eb8..ec002a4a7a7d 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1857,7 +1857,7 @@ static void hdmi_config_hdr_infoframe(struct dw_hdmi *hdmi)
return;
}
- hdmi_writeb(hdmi, 1, HDMI_FC_DRM_HB0);
+ hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
hdmi_writeb(hdmi, frame.eotf, HDMI_FC_DRM_PB0);
hdmi_writeb(hdmi, frame.metadata_type, HDMI_FC_DRM_PB1);
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index bfe671071d9f..e3a0f561e8f0 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4735,10 +4735,10 @@ drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
hdr_source_metadata = (struct hdr_static_metadata *)hdr_metadata;
- frame->length = sizeof(struct hdr_static_metadata);
+ frame->length = 26;
frame->eotf = hdr_source_metadata->eotf;
- frame->type = hdr_source_metadata->type;
+ frame->metadata_type = hdr_source_metadata->type;
for (i = 0; i < 3; i++) {
frame->display_primaries_x[i] =
From 19e9d690fe47e5e4b47760d060b11707bb44194b Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 11 Feb 2018 19:21:41 +0100
Subject: [PATCH] drm: bridge: dw-hdmi: default to underscan mode
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index ec002a4a7a7d..393bd5b28f07 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1691,7 +1691,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
break;
}
- frame.scan_mode = HDMI_SCAN_MODE_NONE;
+ frame.scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
/*
* The Designware IP uses a different byte format from standard
From b492ddc8ae2777350db224d39346966080a140d6 Mon Sep 17 00:00:00 2001
From: David Carrillo-Cisneros <davidcc@google.com>
Date: Tue, 18 Jul 2017 18:18:37 -0700
Subject: [PATCH] UPSTREAM: perf tools: Add EXCLUDE_EXTLIBS and EXTRA_PERFLIBS
to makefile
The goal is to allow users to override linking of libraries that
were automatically added to PERFLIBS.
EXCLUDE_EXTLIBS contains linker flags to be removed from LIBS
while EXTRA_PERFLIBS contains linker flags to be added.
My use case is to force certain library to be build statically,
e.g. for libelf:
EXCLUDE_EXTLIBS=-lelf EXTRA_PERFLIBS=path/libelf.a
Signed-off-by: David Carrillo-Cisneros <davidcc@google.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Elena Reshetova <elena.reshetova@intel.com>
Cc: Kees Kook <keescook@chromium.org>
Cc: Paul Turner <pjt@google.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Wang Nan <wangnan0@huawei.com>
Link: http://lkml.kernel.org/r/20170719011839.99399-3-davidcc@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
(cherry picked from commit cb281fea4b0a326d2a2104f8ffae2b6895c561fd)
---
tools/perf/Makefile.perf | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf
index fb1c9ddc3478..9b3b9bd50d54 100644
--- a/tools/perf/Makefile.perf
+++ b/tools/perf/Makefile.perf
@@ -33,6 +33,11 @@ include config/utilities.mak
#
# Define EXTRA_CFLAGS=-m64 or EXTRA_CFLAGS=-m32 as appropriate for cross-builds.
#
+# Define EXCLUDE_EXTLIBS=-lmylib to exclude libmylib from the auto-generated
+# EXTLIBS.
+#
+# Define EXTRA_PERFLIBS to pass extra libraries to PERFLIBS.
+#
# Define NO_DWARF if you do not want debug-info analysis feature at all.
#
# Define WERROR=0 to disable treating any warnings as errors.
@@ -289,7 +294,8 @@ ifdef ASCIIDOC8
export ASCIIDOC8
endif
-LIBS = -Wl,--whole-archive $(PERFLIBS) -Wl,--no-whole-archive -Wl,--start-group $(EXTLIBS) -Wl,--end-group
+EXTLIBS := $(call filter-out,$(EXCLUDE_EXTLIBS),$(EXTLIBS))
+LIBS = -Wl,--whole-archive $(PERFLIBS) $(EXTRA_PERFLIBS) -Wl,--no-whole-archive -Wl,--start-group $(EXTLIBS) -Wl,--end-group
export INSTALL SHELL_PATH
From 163448e6d6d5d0bbc9486d43a2d06c5d86e28d34 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Tue, 27 Feb 2018 20:49:00 +0100
Subject: [PATCH] net: wireless: rockchip_wlan: rtl8723bs: do not accept all
sdio wlan id
---
drivers/net/wireless/rockchip_wlan/rtl8723bs/Makefile | 2 +-
.../net/wireless/rockchip_wlan/rtl8723bs/os_dep/linux/sdio_intf.c | 8 ++++++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/net/wireless/rockchip_wlan/rtl8723bs/Makefile b/drivers/net/wireless/rockchip_wlan/rtl8723bs/Makefile
index fe9d5638a128..e8653b070efb 100644
--- a/drivers/net/wireless/rockchip_wlan/rtl8723bs/Makefile
+++ b/drivers/net/wireless/rockchip_wlan/rtl8723bs/Makefile
@@ -1347,7 +1347,7 @@ EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFO
EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
# default setting for Power control
-EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+#EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN
EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE
# default setting for Special function
diff --git a/drivers/net/wireless/rockchip_wlan/rtl8723bs/os_dep/linux/sdio_intf.c b/drivers/net/wireless/rockchip_wlan/rtl8723bs/os_dep/linux/sdio_intf.c
index b4654d229634..e49e5cb8f21a 100644
--- a/drivers/net/wireless/rockchip_wlan/rtl8723bs/os_dep/linux/sdio_intf.c
+++ b/drivers/net/wireless/rockchip_wlan/rtl8723bs/os_dep/linux/sdio_intf.c
@@ -45,6 +45,14 @@ static struct mmc_host *mmc_host = NULL;
static const struct sdio_device_id sdio_ids[] = {
#ifdef CONFIG_RTL8723B
+ { SDIO_DEVICE(0x024c, 0x0240), .driver_data = RTL8723B},
+ { SDIO_DEVICE(0x024c, 0x0241), .driver_data = RTL8723B},
+ { SDIO_DEVICE(0x024c, 0x0523), .driver_data = RTL8723B},
+ { SDIO_DEVICE(0x024c, 0x0524), .driver_data = RTL8723B},
+ { SDIO_DEVICE(0x024c, 0x0623), .driver_data = RTL8723B},
+ { SDIO_DEVICE(0x024c, 0x0624), .driver_data = RTL8723B},
+ { SDIO_DEVICE(0x024c, 0x0626), .driver_data = RTL8723B},
+ { SDIO_DEVICE(0x024c, 0x8753), .driver_data = RTL8723B},
{ SDIO_DEVICE(0x024c, 0xB723), .driver_data = RTL8723B},
#endif
#ifdef CONFIG_RTL8188E
From ba7c1fb0efcf29265c0c88d98f52919a21078e5b Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 2 Mar 2018 20:53:32 +0100
Subject: [PATCH] net: wireless: rockchip_wlan: bcmdhd: detect broadcom sdio
device id
---
drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmsdh_sdmmc_linux.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmsdh_sdmmc_linux.c b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmsdh_sdmmc_linux.c
index 8864582b1706..b5a388cc3cbe 100755
--- a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmsdh_sdmmc_linux.c
+++ b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/bcmsdh_sdmmc_linux.c
@@ -225,7 +225,7 @@ static const struct sdio_device_id bcmsdh_sdmmc_ids[] = {
{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4334) },
{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4324) },
{ SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_43239) },
- { SDIO_DEVICE_CLASS(SDIO_CLASS_NONE) },
+ { SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_ANY_ID) },
{ 0, 0, 0, 0 /* end: all zeroes */
},
};
From 922cc477bd191cbfddae005b27a2c89cb9c9623a Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 1 Jul 2018 23:17:47 +0200
Subject: [PATCH] drm/rockchip: clip yuv
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 ++
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 2 ++
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 3 +++
3 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 1418402c2668..0916b4284f88 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1731,6 +1731,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
s = to_rockchip_crtc_state(crtc->state);
spin_lock(&vop->reg_lock);
+ VOP_WIN_SET(vop, win, yuv_clip, 0);
VOP_WIN_SET(vop, win, xmirror, xmirror);
VOP_WIN_SET(vop, win, ymirror, ymirror);
VOP_WIN_SET(vop, win, format, vop_plane_state->format);
@@ -2544,6 +2545,7 @@ static void vop_update_csc(struct drm_crtc *crtc)
VOP_CTRL_SET(vop, dsp_data_swap, 0);
VOP_CTRL_SET(vop, out_mode, s->output_mode);
+ VOP_CTRL_SET(vop, yuv_clip, 0);
switch (s->bus_format) {
case MEDIA_BUS_FMT_RGB565_1X16:
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 618de17e608a..391998c7aa50 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -178,6 +178,7 @@ struct vop_ctrl {
struct vop_reg dsp_lut_en;
struct vop_reg out_mode;
+ struct vop_reg yuv_clip;
struct vop_reg xmirror;
struct vop_reg ymirror;
@@ -409,6 +410,7 @@ struct vop_win_phy {
struct vop_reg format;
struct vop_reg fmt_10;
struct vop_reg csc_mode;
+ struct vop_reg yuv_clip;
struct vop_reg xmirror;
struct vop_reg ymirror;
struct vop_reg rb_swap;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 9c96d5614e54..aeb1c7644bc9 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -119,6 +119,7 @@ static const struct vop_win_phy rk3288_win01_data = {
.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
.csc_mode = VOP_REG_VER(RK3288_WIN0_CTRL0, 0x3, 10, 3, 2, -1),
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
+ .yuv_clip = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 20),
.xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
.ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
@@ -286,6 +287,7 @@ static const struct vop_ctrl rk3288_ctrl_data = {
.bcsh_color_bar = VOP_REG(RK3288_BCSH_COLOR_BAR, 0xffffff, 8),
.bcsh_en = VOP_REG(RK3288_BCSH_COLOR_BAR, 0x1, 0),
+ .yuv_clip = VOP_REG(RK3288_DSP_CTRL0, 0x1, 21),
.xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
.ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
@@ -964,6 +966,7 @@ static const struct vop_ctrl rk3328_ctrl_data = {
.dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0),
.out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
+ .yuv_clip = VOP_REG(RK3328_DSP_CTRL0, 0x1, 21),
.xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22),
.ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23),
From 991811443d72d7915afdee23c30843669a347d7c Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 8 Jul 2018 12:38:00 +0200
Subject: [PATCH] drm/atomic: use active_only flag for connector atomic
begin/flush
---
drivers/gpu/drm/drm_atomic_helper.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index f77d4aa1e58b..4da489b54dc5 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1563,15 +1563,15 @@ void drm_atomic_helper_commit_planes(struct drm_device *dev,
for_each_connector_in_state(old_state, connector, old_conn_state, i) {
const struct drm_connector_helper_funcs *funcs;
- if (!connector->state->crtc)
- continue;
+ funcs = connector->helper_private;
- if (!connector->state->crtc->state->active)
+ if (!funcs || !funcs->atomic_begin)
continue;
- funcs = connector->helper_private;
+ if (!connector->state->crtc)
+ continue;
- if (!funcs || !funcs->atomic_begin)
+ if (active_only && !connector->state->crtc->state->active)
continue;
DRM_DEBUG_ATOMIC("flush beginning [CONNECTOR:%d:%s]\n",
@@ -1645,15 +1645,15 @@ void drm_atomic_helper_commit_planes(struct drm_device *dev,
for_each_connector_in_state(old_state, connector, old_conn_state, i) {
const struct drm_connector_helper_funcs *funcs;
- if (!connector->state->crtc)
- continue;
+ funcs = connector->helper_private;
- if (!connector->state->crtc->state->active)
+ if (!funcs || !funcs->atomic_flush)
continue;
- funcs = connector->helper_private;
+ if (!connector->state->crtc)
+ continue;
- if (!funcs || !funcs->atomic_flush)
+ if (active_only && !connector->state->crtc->state->active)
continue;
DRM_DEBUG_ATOMIC("flushing [CONNECTOR:%d:%s]\n",
From 8d514d5127fbb4d49247f893ac6b803cbdd3304d Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 22 Jul 2018 14:51:58 +0200
Subject: [PATCH] drm: rockchip: dw-hdmi: only force YCbCr422 when max tmds is
up to 340Mhz
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 7273561fe6b1..e2aad6e2149b 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -728,7 +728,9 @@ dw_hdmi_rockchip_select_output(struct drm_connector_state *conn_state,
/* BT2020 require color depth at lest 10bit */
*color_depth = 10;
/* We prefer use YCbCr422 to send 10bit */
- if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422 &&
+ info->max_tmds_clock <= 340000 &&
+ hdmi->dev_type != RK3288_HDMI)
*color_format = DRM_HDMI_OUTPUT_YCBCR422;
}
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -510,11 +510,18 @@
return MODE_BAD;
hdmi = to_rockchip_hdmi(encoder);
- if ((hdmi->dev_type == RK3368_HDMI || hdmi->dev_type == RK3328_HDMI) &&
+ if ((hdmi->dev_type == RK3368_HDMI || hdmi->dev_type == RK3328_HDMI ||
+ hdmi->dev_type == RK3228_HDMI) &&
mode->clock > 340000 &&
!drm_mode_is_420(&connector->display_info, mode))
return MODE_BAD;
+ /* Skip (detectable) fractional rates for RK3228 */
+ if (hdmi->dev_type == RK3228_HDMI &&
+ (mode->clock == 59341 || mode->clock == 74176 || mode->clock == 148352 ||
+ mode->clock == 296703 || mode->clock == 593407))
+ return MODE_BAD;
+
/* Skip bad clocks for RK3288 */
if (hdmi->dev_type == RK3288_HDMI && (mode->clock < 27500 || mode->clock > 340000))
return MODE_CLOCK_RANGE;
From 9d6de32c2e992b71e6634a284dc99ab1b3bd43e2 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 22 Jul 2018 15:09:16 +0200
Subject: [PATCH] drm: bridge: dw-hdmi: signal full range for rgb output
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 393bd5b28f07..91c5b8fc8fa0 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1693,6 +1693,14 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
frame.scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
+ if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
+ frame.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
+ frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_FULL;
+ } else {
+ frame.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED;
+ frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
+ }
+
/*
* The Designware IP uses a different byte format from standard
* AVI info frames, though generally the bits are in the correct
From 35c0ac957d5fcec21d807e801efed57a37c41d9d Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 28 Jul 2018 10:41:40 +0200
Subject: [PATCH] WIP: mm: dma-mapping: increase dma pool size
---
arch/arm/mm/dma-mapping.c | 2 +-
arch/arm64/mm/dma-mapping.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index d539dee3c78d..689961153d71 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -301,7 +301,7 @@ static void __dma_free_remap(void *cpu_addr, size_t size)
VM_ARM_DMA_CONSISTENT | VM_USERMAP);
}
-#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
+#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_2M
static struct gen_pool *atomic_pool;
static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE;
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
index 2b05653e8156..2ad8515cd4da 100644
--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
@@ -32,7 +32,7 @@
static struct gen_pool *atomic_pool;
-#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
+#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_2M
static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;
static int __init early_coherent_pool(char *p)
From 24a070f21767a8d381b81ab5fc5f39c2b9729b24 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 4 Aug 2018 15:19:39 +0200
Subject: [PATCH] drm: add picture_aspect_ratio to hdmi 1.4 4k modes
---
drivers/gpu/drm/drm_edid.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index f7d41950614e..69a1eb4ee382 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1233,25 +1233,25 @@ static const struct drm_display_mode edid_4k_modes[] = {
3840, 4016, 4104, 4400, 0,
2160, 2168, 2178, 2250, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
- .vrefresh = 30, },
+ .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
/* 2 - 3840x2160@25Hz */
{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
3840, 4896, 4984, 5280, 0,
2160, 2168, 2178, 2250, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
- .vrefresh = 25, },
+ .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
/* 3 - 3840x2160@24Hz */
{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
3840, 5116, 5204, 5500, 0,
2160, 2168, 2178, 2250, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
- .vrefresh = 24, },
+ .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
/* 4 - 4096x2160@24Hz (SMPTE) */
{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
4096, 5116, 5204, 5500, 0,
2160, 2168, 2178, 2250, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
- .vrefresh = 24, },
+ .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
};
/*** DDC fetch and block validation ***/
From daadd2b2e1bf5419694ebae5243e61e462885b03 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 4 Aug 2018 16:26:47 +0200
Subject: [PATCH] drm: bridge: dw-hdmi: signal none colorimetry for rgb output
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 91c5b8fc8fa0..8261ba15f98e 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1694,6 +1694,8 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
frame.scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
+ frame.colorimetry = HDMI_COLORIMETRY_NONE;
+ frame.extended_colorimetry = 0;
frame.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_FULL;
} else {
From 88c6dbd7a37b01d4029102c6fdad2b1fc24098e0 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 4 Aug 2018 16:27:08 +0200
Subject: [PATCH] drm: bridge: dw-hdmi: signal it content and content type
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 8261ba15f98e..cdfa295fc323 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1692,6 +1692,8 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
}
frame.scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
+ frame.content_type = HDMI_CONTENT_TYPE_GRAPHICS;
+ frame.itc = true;
if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
frame.colorimetry = HDMI_COLORIMETRY_NONE;
From 5d069752d8885584beaac3905a21c34a0bfa5f22 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 4 Aug 2018 16:27:40 +0200
Subject: [PATCH] drm: bridge: dw-hdmi: log infoframes
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index cdfa295fc323..25546a4471fb 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1705,6 +1705,8 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
}
+ hdmi_infoframe_log(KERN_INFO, hdmi->dev, &frame);
+
/*
* The Designware IP uses a different byte format from standard
* AVI info frames, though generally the bits are in the correct
@@ -1798,6 +1800,8 @@ static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
return;
}
+ hdmi_infoframe_log(KERN_INFO, hdmi->dev, &frame);
+
/* Set the length of HDMI vendor specific InfoFrame payload */
hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
@@ -1869,6 +1873,8 @@ static void hdmi_config_hdr_infoframe(struct dw_hdmi *hdmi)
return;
}
+ hdmi_infoframe_log(KERN_INFO, hdmi->dev, &frame);
+
hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
hdmi_writeb(hdmi, frame.eotf, HDMI_FC_DRM_PB0);
From 3f61791c437d217b760d9f64d38f69e7c2ac6987 Mon Sep 17 00:00:00 2001
From: Nickey Yang <nickey.yang@rock-chips.com>
Date: Mon, 17 Jul 2017 16:35:34 +0800
Subject: [PATCH] MINIARM: set npll be used for hdmi only
Change-Id: I8bebfb2cfb68e3dad172e5547d3886526ad5e912
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
---
arch/arm/boot/dts/rk3288.dtsi | 2 ++
drivers/clk/rockchip/clk-rk3288.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 1b7602f25f34..7e536c939cc0 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1303,6 +1303,8 @@
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vopb_mmu>;
+ assigned-clocks = <&cru DCLK_VOP0>;
+ assigned-clock-parents = <&cru PLL_NPLL>;
status = "disabled";
vopb_out: port {
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index ca6c2ad3de96..415df387a5d6 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -214,7 +214,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
RK3288_MODE_CON, 12, 8, 0, rk3288_pll_rates),
[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
- RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
+ RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates),
};
static struct clk_div_table div_hclk_cpu_t[] = {
@@ -429,7 +429,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 4, GFLAGS),
- COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(3), 1, GFLAGS),
COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
From 23a9cfafd5b8c641c2e9d2fdd1c299f19947c548 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 4 Aug 2018 14:51:14 +0200
Subject: [PATCH] clk: rockchip: rk3288: use npll table to to improve HDMI
compatibility
Based on https://github.com/TinkerBoard/debian_kernel/commit/3d90870530b8a2901681f7b7fa598ee7381e49f3
---
drivers/clk/rockchip/clk-rk3288.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 415df387a5d6..f748a292b7f4 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -105,6 +105,27 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
{ /* sentinel */ },
};
+static struct rockchip_pll_rate_table rk3288_npll_rates[] = {
+ RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 32),
+ RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32),
+ RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32),
+ RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32),
+ RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32),
+ RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32),
+ RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16),
+ RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32),
+ RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32),
+ RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32),
+ RK3066_PLL_RATE(148352000, 13, 1125, 14),
+ RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32),
+ RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32),
+ RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32),
+ RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32),
+ RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32),
+ RK3066_PLL_RATE(74176000, 26, 1125, 14),
+ { /* sentinel */ },
+};
+
#define RK3288_DIV_ACLK_CORE_M0_MASK 0xf
#define RK3288_DIV_ACLK_CORE_M0_SHIFT 0
#define RK3288_DIV_ACLK_CORE_MP_MASK 0xf
@@ -214,7 +235,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
RK3288_MODE_CON, 12, 8, 0, rk3288_pll_rates),
[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
- RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates),
+ RK3288_MODE_CON, 14, 9, 0, rk3288_npll_rates),
};
static struct clk_div_table div_hclk_cpu_t[] = {
From ba1e5834eef028ca22c2089a2bff453c9bee38af Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Kamil=20Trzci=C5=84ski?= <ayufan@ayufan.eu>
Date: Wed, 30 May 2018 13:06:14 +0200
Subject: [PATCH] ayufan: fan53555: support syr83x found in rockpro64
Change-Id: I7115081286692f4cbfbe5d11a05d40be112c3037
---
drivers/regulator/fan53555.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c
index 74e5ae2bc0d2..6b0854a3cae3 100644
--- a/drivers/regulator/fan53555.c
+++ b/drivers/regulator/fan53555.c
@@ -78,6 +78,7 @@ enum {
enum {
SILERGY_SYR82X = 8,
+ SILERGY_SYR83X = 9,
};
struct fan53555_device_info {
@@ -323,6 +324,7 @@ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di)
/* Init voltage range and step */
switch (di->chip_id) {
case SILERGY_SYR82X:
+ case SILERGY_SYR83X:
di->vsel_min = 712500;
di->vsel_step = 12500;
break;
From 99674f3279042bd694019c26309e4f2a44b6fe81 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 9 Sep 2018 12:33:23 +0200
Subject: [PATCH] WIP: video: rockchip: iep: fix compile issue
---
include/linux/rockchip-iovmm.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/linux/rockchip-iovmm.h b/include/linux/rockchip-iovmm.h
index 73e2ff159e86..d87b8d2c9904 100644
--- a/include/linux/rockchip-iovmm.h
+++ b/include/linux/rockchip-iovmm.h
@@ -10,6 +10,7 @@
#include <linux/list.h>
#include <linux/atomic.h>
#include <linux/spinlock.h>
+#include <linux/errno.h>
#define IEP_IOMMU_COMPATIBLE_NAME "rockchip,iep_mmu"
#define VIP_IOMMU_COMPATIBLE_NAME "rockchip,vip_mmu"
From 6de4ce0e92be7b66429efe88c406e30703639661 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 28 Oct 2018 21:43:01 +0100
Subject: [PATCH] clk: rockchip: rk3288: add more npll clocks
Fixes 2560x1440@60Hz, 1600x1200@60Hz, 1920x1200@60Hz, 1680x1050@60Hz and 1440x900@60Hz modes on my monitor
---
drivers/clk/rockchip/clk-rk3288.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index f748a292b7f4..d72c02afeb76 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -111,18 +111,34 @@ static struct rockchip_pll_rate_table rk3288_npll_rates[] = {
RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32),
RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32),
RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32),
+ RK3066_PLL_RATE(348500000, 8, 697, 6),
RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32),
RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16),
RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32),
RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32),
+ RK3066_PLL_RATE(241500000, 2, 161, 8),
+ RK3066_PLL_RATE(162000000, 1, 81, 12),
+ RK3066_PLL_RATE(154000000, 6, 539, 14),
RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32),
RK3066_PLL_RATE(148352000, 13, 1125, 14),
RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32),
+ RK3066_PLL_RATE(121750000, 6, 487, 16),
+ RK3066_PLL_RATE(119000000, 3, 238, 16),
RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32),
RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32),
+ RK3066_PLL_RATE(101000000, 3, 202, 16),
+ RK3066_PLL_RATE(88750000, 6, 355, 16),
RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32),
+ RK3066_PLL_RATE(83500000, 3, 167, 16),
+ RK3066_PLL_RATE(79500000, 1, 53, 16),
RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32),
RK3066_PLL_RATE(74176000, 26, 1125, 14),
+ RK3066_PLL_RATE(72000000, 1, 48, 16),
+ RK3066_PLL_RATE(71000000, 3, 142, 16),
+ RK3066_PLL_RATE(68250000, 2, 91, 16),
+ RK3066_PLL_RATE(65000000, 3, 130, 16),
+ RK3066_PLL_RATE(40000000, 3, 80, 16),
+ RK3066_PLL_RATE(33750000, 2, 45, 16),
{ /* sentinel */ },
};
From 06d1099d7f4cece7af7793ff68fabc08eb55935d Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 14 Nov 2018 06:08:01 +0100
Subject: [PATCH] drm: workaround for crash when trying to open render node
---
drivers/gpu/drm/drm_ioctl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 34757168ffaa..0914c886277f 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -57,6 +57,9 @@ static int drm_getunique(struct drm_device *dev, void *data,
struct drm_unique *u = data;
struct drm_master *master = file_priv->master;
+ if (!master)
+ return -EINVAL;
+
if (u->unique_len >= master->unique_len) {
if (copy_to_user(u->unique, master->unique, master->unique_len))
return -EFAULT;
From 309a27eaf2f4e429ef102e3eef70a2f908360c44 Mon Sep 17 00:00:00 2001
From: Nick <nick@khadas.com>
Date: Wed, 19 Sep 2018 22:14:58 +0800
Subject: [PATCH] bump PD voltage & current for board without charge IC
---
drivers/mfd/fusb302.c | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/mfd/fusb302.c b/drivers/mfd/fusb302.c
index 240cecac65b5..8fe4163214e0 100644
--- a/drivers/mfd/fusb302.c
+++ b/drivers/mfd/fusb302.c
@@ -217,8 +217,32 @@ static int fusb302_set_pos_power_by_charge_ic(struct fusb30x_chip *chip)
max_vol = 0;
max_cur = 0;
psy = power_supply_get_by_phandle(chip->dev->of_node, "charge-dev");
- if (!psy || IS_ERR(psy))
- return -1;
+ if (!psy || IS_ERR(psy)) {
+ int ret;
+ u32 value;
+
+ ret = of_property_read_u32(chip->dev->of_node, "max-input-voltage", &value);
+ if (ret) {
+ dev_err(chip->dev, "'max-input-voltage' not found!\n");
+ return -1;
+ }
+
+ max_vol = value / 1000;
+
+ ret = of_property_read_u32(chip->dev->of_node, "max-input-current", &value);
+
+ if (ret) {
+ dev_err(chip->dev, "'max-input-current' not found!\n");
+ return -1;
+ }
+
+ max_cur = value / 1000;
+
+ if (max_vol > 0 && max_cur > 0)
+ fusb_set_pos_power(chip, max_vol, max_cur);
+
+ return 0;
+ }
psp = POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT_MAX;
if (power_supply_get_property(psy, psp, &val) == 0)
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -646,7 +646,7 @@
{ .base = 0x00, .phy = &rk3288_win01_data,
.type = DRM_PLANE_TYPE_PRIMARY },
{ .base = 0x40, .phy = &rk3288_win01_data,
- .type = DRM_PLANE_TYPE_CURSOR },
+ .type = DRM_PLANE_TYPE_OVERLAY },
};
static const struct vop_data rk322x_vop = {
diff --git a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_linux.c b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_linux.c
index f3ad402..d8112c9 100644
--- a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_linux.c
+++ b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_linux.c
@@ -6962,7 +6962,7 @@ dhd_ethtool(dhd_info_t *dhd, void *uaddr)
/* Copy out any request driver name */
if (copy_from_user(&info, uaddr, sizeof(info)))
return -EFAULT;
- strncpy(drvname, info.driver, sizeof(info.driver));
+ strncpy(drvname, info.driver, sizeof(drvname));
drvname[sizeof(info.driver)-1] = '\0';
/* clear struct for return */
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