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build/patch/kernel/archive/rk322x-6.2/wifi-4003-ssv-6051-driver.patch

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From 3f30a652fb3e6ead83f65312d0240d5c9ea8c340 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Wed, 2 Nov 2022 15:40:06 +0000
Subject: [PATCH] add ssv6xxx wifi driver
---
drivers/net/wireless/Kconfig | 1 +
drivers/net/wireless/Makefile | 1 +
drivers/net/wireless/ssv6051/Kconfig | 11 +
drivers/net/wireless/ssv6051/Makefile | 26 +
drivers/net/wireless/ssv6051/Makefile.bak | 107 +
.../ssv6051/firmware/ssv6051-wifi.cfg | 91 +
drivers/net/wireless/ssv6051/hci/hctrl.h | 178 +
drivers/net/wireless/ssv6051/hci/ssv_hci.c | 967 +
drivers/net/wireless/ssv6051/hci/ssv_hci.h | 77 +
drivers/net/wireless/ssv6051/hwif/hwif.h | 84 +
drivers/net/wireless/ssv6051/hwif/sdio/sdio.c | 1254 ++
.../net/wireless/ssv6051/hwif/sdio/sdio_def.h | 80 +
drivers/net/wireless/ssv6051/include/cabrio.h | 28 +
.../net/wireless/ssv6051/include/ssv6200.h | 76 +
.../wireless/ssv6051/include/ssv6200_aux.h | 18221 ++++++++++++++++
.../wireless/ssv6051/include/ssv6200_common.h | 452 +
.../ssv6051/include/ssv6200_configuration.h | 317 +
.../wireless/ssv6051/include/ssv6200_reg.h | 9694 ++++++++
.../ssv6051/include/ssv6200_reg_sim.h | 176 +
.../net/wireless/ssv6051/include/ssv_cfg.h | 60 +
.../ssv6051/include/ssv_firmware_version.h | 25 +
.../wireless/ssv6051/include/ssv_version.h | 12 +
.../net/wireless/ssv6051/platform-config.mak | 97 +
drivers/net/wireless/ssv6051/rules.mak | 19 +
drivers/net/wireless/ssv6051/smac/ampdu.c | 2111 ++
drivers/net/wireless/ssv6051/smac/ampdu.h | 215 +
drivers/net/wireless/ssv6051/smac/ap.c | 598 +
drivers/net/wireless/ssv6051/smac/ap.h | 41 +
drivers/net/wireless/ssv6051/smac/dev.c | 3880 ++++
drivers/net/wireless/ssv6051/smac/dev.h | 445 +
drivers/net/wireless/ssv6051/smac/dev_tbl.h | 141 +
drivers/net/wireless/ssv6051/smac/drv_comm.h | 61 +
drivers/net/wireless/ssv6051/smac/efuse.c | 334 +
drivers/net/wireless/ssv6051/smac/efuse.h | 40 +
drivers/net/wireless/ssv6051/smac/init.c | 1347 ++
drivers/net/wireless/ssv6051/smac/init.h | 23 +
drivers/net/wireless/ssv6051/smac/lib.c | 33 +
drivers/net/wireless/ssv6051/smac/lib.h | 23 +
.../net/wireless/ssv6051/smac/linux_80211.h | 24 +
drivers/net/wireless/ssv6051/smac/p2p.c | 305 +
drivers/net/wireless/ssv6051/smac/p2p.h | 58 +
drivers/net/wireless/ssv6051/smac/sar.c | 208 +
drivers/net/wireless/ssv6051/smac/sar.h | 63 +
drivers/net/wireless/ssv6051/smac/sec.h | 52 +
drivers/net/wireless/ssv6051/smac/smartlink.c | 340 +
.../wireless/ssv6051/smac/ssv6xxx_debugfs.c | 223 +
.../wireless/ssv6051/smac/ssv6xxx_debugfs.h | 27 +
.../net/wireless/ssv6051/smac/ssv_cfgvendor.c | 1384 ++
.../net/wireless/ssv6051/smac/ssv_cfgvendor.h | 247 +
drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c | 546 +
drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h | 31 +
drivers/net/wireless/ssv6051/smac/ssv_pm.c | 19 +
drivers/net/wireless/ssv6051/smac/ssv_pm.h | 20 +
drivers/net/wireless/ssv6051/smac/ssv_rc.c | 1716 ++
drivers/net/wireless/ssv6051/smac/ssv_rc.h | 50 +
.../net/wireless/ssv6051/smac/ssv_rc_common.h | 175 +
.../wireless/ssv6051/ssv6051-generic-wlan.c | 76 +
.../net/wireless/ssv6051/ssvdevice/ssv_cmd.c | 1765 ++
.../net/wireless/ssv6051/ssvdevice/ssv_cmd.h | 50 +
.../wireless/ssv6051/ssvdevice/ssvdevice.c | 256 +
60 files changed, 48983 insertions(+)
create mode 100644 drivers/net/wireless/ssv6051/Kconfig
create mode 100644 drivers/net/wireless/ssv6051/Makefile
create mode 100644 drivers/net/wireless/ssv6051/Makefile.bak
create mode 100644 drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
create mode 100644 drivers/net/wireless/ssv6051/hci/hctrl.h
create mode 100644 drivers/net/wireless/ssv6051/hci/ssv_hci.c
create mode 100644 drivers/net/wireless/ssv6051/hci/ssv_hci.h
create mode 100644 drivers/net/wireless/ssv6051/hwif/hwif.h
create mode 100644 drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
create mode 100644 drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
create mode 100644 drivers/net/wireless/ssv6051/include/cabrio.h
create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200.h
create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_aux.h
create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_common.h
create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_reg.h
create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
create mode 100644 drivers/net/wireless/ssv6051/include/ssv_cfg.h
create mode 100644 drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
create mode 100644 drivers/net/wireless/ssv6051/include/ssv_version.h
create mode 100644 drivers/net/wireless/ssv6051/platform-config.mak
create mode 100644 drivers/net/wireless/ssv6051/rules.mak
create mode 100644 drivers/net/wireless/ssv6051/smac/ampdu.c
create mode 100644 drivers/net/wireless/ssv6051/smac/ampdu.h
create mode 100644 drivers/net/wireless/ssv6051/smac/ap.c
create mode 100644 drivers/net/wireless/ssv6051/smac/ap.h
create mode 100644 drivers/net/wireless/ssv6051/smac/dev.c
create mode 100644 drivers/net/wireless/ssv6051/smac/dev.h
create mode 100644 drivers/net/wireless/ssv6051/smac/dev_tbl.h
create mode 100644 drivers/net/wireless/ssv6051/smac/drv_comm.h
create mode 100644 drivers/net/wireless/ssv6051/smac/efuse.c
create mode 100644 drivers/net/wireless/ssv6051/smac/efuse.h
create mode 100644 drivers/net/wireless/ssv6051/smac/init.c
create mode 100644 drivers/net/wireless/ssv6051/smac/init.h
create mode 100644 drivers/net/wireless/ssv6051/smac/lib.c
create mode 100644 drivers/net/wireless/ssv6051/smac/lib.h
create mode 100644 drivers/net/wireless/ssv6051/smac/linux_80211.h
create mode 100644 drivers/net/wireless/ssv6051/smac/p2p.c
create mode 100644 drivers/net/wireless/ssv6051/smac/p2p.h
create mode 100644 drivers/net/wireless/ssv6051/smac/sar.c
create mode 100644 drivers/net/wireless/ssv6051/smac/sar.h
create mode 100644 drivers/net/wireless/ssv6051/smac/sec.h
create mode 100644 drivers/net/wireless/ssv6051/smac/smartlink.c
create mode 100644 drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
create mode 100644 drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_pm.c
create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_pm.h
create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc.c
create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc.h
create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
create mode 100644 drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
index de5e37846397..aa2cac9abdd3 100644
--- a/drivers/net/wireless/Kconfig
+++ b/drivers/net/wireless/Kconfig
@@ -18,6 +18,7 @@ menuconfig WLAN
if WLAN
+source "drivers/net/wireless/ssv6051/Kconfig"
source "drivers/net/wireless/admtek/Kconfig"
source "drivers/net/wireless/ath/Kconfig"
source "drivers/net/wireless/atmel/Kconfig"
diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
index 92ffd2cef51c..8b56a42e97a6 100644
--- a/drivers/net/wireless/Makefile
+++ b/drivers/net/wireless/Makefile
@@ -3,6 +3,7 @@
# Makefile for the Linux Wireless network device drivers.
#
+obj-$(CONFIG_SSV6051) += ssv6051/
obj-$(CONFIG_WLAN_VENDOR_ADMTEK) += admtek/
obj-$(CONFIG_WLAN_VENDOR_ATH) += ath/
obj-$(CONFIG_WLAN_VENDOR_ATMEL) += atmel/
diff --git a/drivers/net/wireless/ssv6051/Kconfig b/drivers/net/wireless/ssv6051/Kconfig
new file mode 100644
index 000000000000..7706ad52ed7b
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config SSV6051
+ tristate "South Silicon Valley (ssv) 6051 family WLAN support"
+ depends on MAC80211
+ depends on (MMC = y)
+ default n
+ select FW_LOADER
+ help
+ Enable South Silicon Valley (SSV) 6051 family support.
+
+
diff --git a/drivers/net/wireless/ssv6051/Makefile b/drivers/net/wireless/ssv6051/Makefile
new file mode 100644
index 000000000000..985d730f3d50
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/Makefile
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: ISC
+
+include $(src)/platform-config.mak
+
+ccflags-y += \
+ -I $(srctree)/$(src) \
+ -I $(srctree)/$(src)/include
+
+obj-$(CONFIG_SSV6051) += ssv6051.o
+ssv6051-objs += \
+ ssv6051-generic-wlan.o \
+ ssvdevice/ssvdevice.o \
+ ssvdevice/ssv_cmd.o \
+ hci/ssv_hci.o \
+ smac/init.o \
+ smac/dev.o \
+ smac/ssv_rc.o \
+ smac/ssv_ht_rc.o \
+ smac/ap.o \
+ smac/ampdu.o \
+ smac/efuse.o \
+ smac/ssv_pm.o \
+ smac/sar.o \
+ smac/ssv_cfgvendor.o \
+ hwif/sdio/sdio.o
+
diff --git a/drivers/net/wireless/ssv6051/Makefile.bak b/drivers/net/wireless/ssv6051/Makefile.bak
new file mode 100644
index 000000000000..2733fa4dd3b7
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/Makefile.bak
@@ -0,0 +1,107 @@
+KMODULE_NAME=ssv6051
+
+KBUILD_TOP := $(PWD)
+
+ifeq ($(KERNELRELEASE),)
+
+KVERS_UNAME ?= $(shell uname -r)
+KVERS_ARCH ?= $(shell arch)
+
+KBUILD ?= $(shell readlink -f /lib/modules/$(KVERS_UNAME)/build)
+
+ifeq (,$(KBUILD))
+$(error kernel build tree not found - set KBUILD to configured kernel)
+endif
+
+#KCONFIG := $(KBUILD)/config
+#ifeq (,$(wildcard $(KCONFIG)))
+#$(error No .config found in $(KBUILD), set KBUILD to configured kernel)
+#endif
+
+ifneq (,$(wildcard $(KBUILD)/include/linux/version.h))
+ifneq (,$(wildcard $(KBUILD)/include/generated/uapi/linux/version.h))
+$(error Multiple copied of version.h found, clean build tree)
+endif
+endif
+
+# Kernel Makefile doesn't always know the exact kernel version, so we
+# get it from the kernel headers instead and pass it to make.
+VERSION_H := $(KBUILD)/include/generated/utsrelease.h
+ifeq (,$(wildcard $(VERSION_H)))
+VERSION_H := $(KBUILD)/include/linux/utsrelease.h
+endif
+ifeq (,$(wildcard $(VERSION_H)))
+VERSION_H := $(KBUILD)/include/linux/version.h
+endif
+ifeq (,$(wildcard $(VERSION_H)))
+$(error Please run 'make modules_prepare' in $(KBUILD))
+endif
+
+KVERS := $(shell sed -ne 's/"//g;s/^\#define UTS_RELEASE //p' $(VERSION_H))
+
+ifeq (,$(KVERS))
+$(error Cannot find UTS_RELEASE in $(VERSION_H), please report)
+endif
+
+INST_DIR = /lib/modules/$(KVERS)/misc
+
+#include $(KCONFIG)
+
+endif
+
+include $(KBUILD_TOP)/platform-config.mak
+
+EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include #-Wno-error=missing-attributes
+DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
+
+OBJS := ssvdevice/ssvdevice.c \
+ ssvdevice/ssv_cmd.c \
+ hci/ssv_hci.c \
+ smac/init.c \
+ smac/dev.c \
+ smac/ssv_rc.c \
+ smac/ssv_ht_rc.c \
+ smac/ap.c \
+ smac/ampdu.c \
+ smac/efuse.c \
+ smac/ssv_pm.c \
+ smac/sar.c \
+ hwif/sdio/sdio.c \
+ ssv6051-generic-wlan.c
+
+ifeq ($(findstring -DCONFIG_SSV6XXX_DEBUGFS, $(ccflags-y)), -DCONFIG_SSV6XXX_DEBUGFS)
+OBJS += smac/ssv6xxx_debugfs.c
+endif
+
+ifeq ($(findstring -DCONFIG_SSV_VENDOR_EXT_SUPPORT, $(ccflags-y)), -DCONFIG_SSV_VENDOR_EXT_SUPPORT)
+OBJS += smac/ssv_cfgvendor.c
+endif
+
+ifeq ($(findstring -DCONFIG_SSV_SMARTLINK, $(ccflags-y)), -DCONFIG_SSV_SMARTLINK)
+OBJS += smac/smartlink.c
+endif
+
+$(KMODULE_NAME)-y += $(ASMS:.S=.o)
+$(KMODULE_NAME)-y += $(OBJS:.c=.o)
+
+obj-$(CONFIG_SSV6200_CORE) += $(KMODULE_NAME).o
+
+all: modules
+
+modules:
+ ARCH=arm $(MAKE) -C $(KBUILD) M=$(KBUILD_TOP)
+
+clean:
+ find -type f -iname '*.o' -exec rm {} \;
+ find -type f -iname '*.o.cmd' -exec rm {} \;
+ rm -f *.o *.ko .*.cmd *.mod.c *.symvers modules.order
+ rm -rf .tmp_versions
+
+install: modules
+ mkdir -p -m 755 $(DESTDIR)$(INST_DIR)
+ install -m 0644 $(KMODULE_NAME).ko $(DESTDIR)$(INST_DIR)
+ifndef DESTDIR
+ -/sbin/depmod -a $(KVERS)
+endif
+
+.PHONY: all modules clean install
diff --git a/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg b/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
new file mode 100644
index 000000000000..c072960f6dea
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
@@ -0,0 +1,91 @@
+############################################################
+# ROCKCHIP RK3X28 & RK322X
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /vendor/etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+# path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+# 0. => 00:33:33:33:33:33
+# 1. => Always random
+# 2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+xtal_clock = 24
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ht = on
+hw_cap_gf = off
+hw_cap_2ghz = on
+hw_cap_5ghz = off
+hw_cap_security = on
+hw_cap_sgi_20 = on
+hw_cap_sgi_40 = off
+hw_cap_ap = on
+hw_cap_p2p = on
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+################################################
+# Signal strength control
+# rssi control
+#rssi_ctl = 10
+
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+# register = CE010010:91919191
+# register = 00CC0010:00091919
+##################################################
diff --git a/drivers/net/wireless/ssv6051/hci/hctrl.h b/drivers/net/wireless/ssv6051/hci/hctrl.h
new file mode 100644
index 000000000000..95218c8040e7
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hci/hctrl.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _HCTRL_H_
+#define _HCTRL_H_
+#define MAX_FRAME_SIZE 4096
+#define SSV6XXX_INT_RX 0x00000001
+#define SSV6XXX_INT_TX 0x00000002
+#define SSV6XXX_INT_SOC 0x00000004
+#define SSV6XXX_INT_LOW_EDCA_0 0x00000008
+#define SSV6XXX_INT_LOW_EDCA_1 0x00000010
+#define SSV6XXX_INT_LOW_EDCA_2 0x00000020
+#define SSV6XXX_INT_LOW_EDCA_3 0x00000040
+#define SSV6XXX_INT_RESOURCE_LOW 0x00000080
+#define IFDEV(_ct) ((_ct)->shi->dev)
+#define IFOPS(_ct) ((_ct)->shi->if_ops)
+#define HCI_REG_READ(_ct,_adr,_val) IFOPS(_ct)->readreg(IFDEV(_ct), _adr, _val)
+#define HCI_REG_WRITE(_ct,_adr,_val) IFOPS(_ct)->writereg(IFDEV(_ct), _adr, _val)
+#define HCI_REG_SET_BITS(_ct,_reg,_set,_clr) \
+{ \
+ u32 _regval; \
+ if(HCI_REG_READ(_ct, _reg, &_regval)); \
+ _regval &= ~(_clr); \
+ _regval |= (_set); \
+ if(HCI_REG_WRITE(_ct, _reg, _regval)); \
+}
+#define IF_SEND(_ct,_bf,_len,_qid) IFOPS(_ct)->write(IFDEV(_ct), _bf, _len, _qid)
+#define IF_RECV(ct,bf,len) IFOPS(ct)->read(IFDEV(ct), bf, len)
+#define HCI_LOAD_FW(ct,_bf,open) IFOPS(ct)->load_fw(IFDEV(ct), _bf, open)
+#define HCI_IFC_RESET(ct) IFOPS(ct)->interface_reset(IFDEV(ct))
+struct ssv6xxx_hci_ctrl {
+ struct ssv6xxx_hci_info *shi;
+ spinlock_t int_lock;
+ u32 int_status;
+ u32 int_mask;
+ struct mutex txq_mask_lock;
+ u32 txq_mask;
+ struct ssv_hw_txq hw_txq[SSV_HW_TXQ_NUM];
+ struct mutex hci_mutex;
+ bool hci_start;
+ struct sk_buff *rx_buf;
+ u32 rx_pkt;
+ struct workqueue_struct *hci_work_queue;
+ struct work_struct hci_rx_work;
+ struct work_struct hci_tx_work;
+ u32 read_rs0_info_fail;
+ u32 read_rs1_info_fail;
+ u32 rx_work_running;
+ u32 isr_running;
+ u32 xmit_running;
+ u32 isr_summary_eable;
+ u32 isr_routine_time;
+ u32 isr_tx_time;
+ u32 isr_rx_time;
+ u32 isr_idle_time;
+ u32 isr_rx_idle_time;
+ u32 isr_miss_cnt;
+ unsigned long prev_isr_jiffes;
+ unsigned long prev_rx_isr_jiffes;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct dentry *debugfs_dir;
+ u32 isr_mib_enable;
+ u32 isr_mib_reset;
+ long long isr_total_time;
+ long long isr_tx_io_time;
+ long long isr_rx_io_time;
+ u32 isr_rx_io_count;
+ u32 isr_tx_io_count;
+ long long isr_rx_proc_time;
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ bool irq_enable;
+ u32 irq_count;
+ u32 invalid_irq_count;
+ u32 tx_irq_count;
+ u32 real_tx_irq_count;
+ u32 rx_irq_count;
+ u32 irq_rx_pkt_count;
+ u32 irq_tx_pkt_count;
+#endif
+#endif
+};
+struct ssv6xxx_hci_txq_info {
+ u32 tx_use_page:8;
+ u32 tx_use_id:6;
+ u32 txq0_size:4;
+ u32 txq1_size:4;
+ u32 txq2_size:5;
+ u32 txq3_size:5;
+};
+struct ssv6xxx_hci_txq_info2 {
+ u32 tx_use_page:9;
+ u32 tx_use_id:8;
+ u32 txq4_size:4;
+ u32 rsvd:11;
+};
+struct ssv6xxx_hw_resource {
+ u32 free_tx_page;
+ u32 free_tx_id;
+ int max_tx_frame[SSV_HW_TXQ_NUM];
+};
+static inline void ssv6xxx_hwif_irq_request(struct ssv6xxx_hci_ctrl *hctrl,
+ irq_handler_t irq_handler)
+{
+ if (hctrl->shi->if_ops->irq_request)
+ hctrl->shi->if_ops->irq_request(IFDEV(hctrl), irq_handler,
+ hctrl);
+}
+
+static inline void ssv6xxx_hwif_irq_enable(struct ssv6xxx_hci_ctrl *hctrl)
+{
+ if (hctrl->shi->if_ops->irq_enable)
+ hctrl->shi->if_ops->irq_enable(IFDEV(hctrl));
+}
+
+static inline void ssv6xxx_hwif_irq_disable(struct ssv6xxx_hci_ctrl *hctrl)
+{
+ if (hctrl->shi->if_ops->irq_disable)
+ hctrl->shi->if_ops->irq_disable(IFDEV(hctrl), false);
+}
+
+static inline int ssv6xxx_hwif_irq_getstatus(struct ssv6xxx_hci_ctrl *hctrl,
+ int *status)
+{
+ if (hctrl->shi->if_ops->irq_getstatus)
+ return hctrl->shi->if_ops->irq_getstatus(IFDEV(hctrl), status);
+ return 0;
+}
+
+static inline void ssv6xxx_hwif_irq_setmask(struct ssv6xxx_hci_ctrl *hctrl,
+ int mask)
+{
+ if (hctrl->shi->if_ops->irq_setmask)
+ hctrl->shi->if_ops->irq_setmask(IFDEV(hctrl), mask);
+}
+
+static inline void ssv6xxx_hwif_irq_trigger(struct ssv6xxx_hci_ctrl *hctrl)
+{
+ if (hctrl->shi->if_ops->irq_trigger)
+ hctrl->shi->if_ops->irq_trigger(IFDEV(hctrl));
+}
+
+static inline void ssv6xxx_hwif_pmu_wakeup(struct ssv6xxx_hci_ctrl *hctrl)
+{
+ if (hctrl->shi->if_ops->pmu_wakeup)
+ hctrl->shi->if_ops->pmu_wakeup(IFDEV(hctrl));
+}
+
+static inline int ssv6xxx_hwif_write_sram(struct ssv6xxx_hci_ctrl *hctrl,
+ u32 addr, u8 * data, u32 size)
+{
+ if (hctrl->shi->if_ops->write_sram)
+ return hctrl->shi->if_ops->write_sram(IFDEV(hctrl), addr, data,
+ size);
+ return 0;
+}
+
+#define HCI_IRQ_REQUEST(ct,hdle) ssv6xxx_hwif_irq_request(ct, hdle)
+#define HCI_IRQ_ENABLE(ct) ssv6xxx_hwif_irq_enable(ct)
+#define HCI_IRQ_DISABLE(ct) ssv6xxx_hwif_irq_disable(ct)
+#define HCI_IRQ_STATUS(ct,sts) ssv6xxx_hwif_irq_getstatus(ct, sts)
+#define HCI_IRQ_SET_MASK(ct,mk) ssv6xxx_hwif_irq_setmask(ct, mk)
+#define HCI_IRQ_TRIGGER(ct) ssv6xxx_hwif_irq_trigger(ct)
+#define HCI_PMU_WAKEUP(ct) ssv6xxx_hwif_pmu_wakeup(ct)
+#define HCI_SRAM_WRITE(_ct,_adr,_dat,_size) ssv6xxx_hwif_write_sram(_ct, _adr, _dat, _size);
+#endif
diff --git a/drivers/net/wireless/ssv6051/hci/ssv_hci.c b/drivers/net/wireless/ssv6051/hci/ssv_hci.c
new file mode 100644
index 000000000000..9fedbeb55754
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hci/ssv_hci.c
@@ -0,0 +1,967 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+#include <ssv6200.h>
+#include "hctrl.h"
+
+static struct ssv6xxx_hci_ctrl *ctrl_hci = NULL;
+
+struct sk_buff *ssv_skb_alloc(s32 len)
+{
+ struct sk_buff *skb;
+ skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL);
+ if (skb != NULL) {
+ skb_reserve(skb, SSV_SKB_info_size);
+ }
+ return skb;
+}
+
+void ssv_skb_free(struct sk_buff *skb)
+{
+ dev_kfree_skb_any(skb);
+}
+
+static int ssv6xxx_hci_irq_enable(void)
+{
+ HCI_IRQ_SET_MASK(ctrl_hci, ~(ctrl_hci->int_mask));
+ HCI_IRQ_ENABLE(ctrl_hci);
+ return 0;
+}
+
+static int ssv6xxx_hci_irq_disable(void)
+{
+ HCI_IRQ_SET_MASK(ctrl_hci, 0xffffffff);
+ HCI_IRQ_DISABLE(ctrl_hci);
+ return 0;
+}
+
+static void ssv6xxx_hci_irq_register(u32 irq_mask)
+{
+ unsigned long flags;
+ u32 regval;
+ mutex_lock(&ctrl_hci->hci_mutex);
+ spin_lock_irqsave(&ctrl_hci->int_lock, flags);
+ ctrl_hci->int_mask |= irq_mask;
+ regval = ~ctrl_hci->int_mask;
+ spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+ smp_mb();
+ HCI_IRQ_SET_MASK(ctrl_hci, regval);
+ mutex_unlock(&ctrl_hci->hci_mutex);
+}
+
+static inline u32 ssv6xxx_hci_get_int_bitno(int txqid)
+{
+ if (txqid == SSV_HW_TXQ_NUM - 1)
+ return 1;
+ else
+ return txqid + 3;
+}
+
+static int ssv6xxx_hci_start(void)
+{
+ ssv6xxx_hci_irq_enable();
+ ctrl_hci->hci_start = true;
+ HCI_IRQ_TRIGGER(ctrl_hci);
+ return 0;
+}
+
+static int ssv6xxx_hci_stop(void)
+{
+ ssv6xxx_hci_irq_disable();
+ ctrl_hci->hci_start = false;
+ return 0;
+}
+
+static int ssv6xxx_hci_read_word(u32 addr, u32 * regval)
+{
+ int ret = HCI_REG_READ(ctrl_hci, addr, regval);
+ return ret;
+}
+
+static int ssv6xxx_hci_write_word(u32 addr, u32 regval)
+{
+ return HCI_REG_WRITE(ctrl_hci, addr, regval);
+}
+
+static int ssv6xxx_hci_load_fw(u8 * firmware_name, u8 openfile)
+{
+ return HCI_LOAD_FW(ctrl_hci, firmware_name, openfile);
+}
+
+static int ssv6xxx_hci_write_sram(u32 addr, u8 * data, u32 size)
+{
+ return HCI_SRAM_WRITE(ctrl_hci, addr, data, size);
+}
+
+static int ssv6xxx_hci_pmu_wakeup(void)
+{
+ HCI_PMU_WAKEUP(ctrl_hci);
+ return 0;
+}
+
+static int ssv6xxx_hci_interface_reset(void)
+{
+ HCI_IFC_RESET(ctrl_hci);
+ return 0;
+}
+
+static int ssv6xxx_hci_send_cmd(struct sk_buff *skb)
+{
+ int ret;
+ ret = IF_SEND(ctrl_hci, (void *)skb->data, skb->len, 0);
+
+ if (ret < 0)
+ pr_warn("ssv6xxx_hci_send_cmd failed, ret=%d\n", ret);
+
+ return ret;
+}
+
+static int ssv6xxx_hci_enqueue(struct sk_buff *skb, int txqid, u32 tx_flags)
+{
+ struct ssv_hw_txq *hw_txq;
+ unsigned long flags;
+ u32 status;
+ int qlen = 0;
+ BUG_ON(txqid >= SSV_HW_TXQ_NUM || txqid < 0);
+ if (txqid >= SSV_HW_TXQ_NUM || txqid < 0)
+ return -1;
+ hw_txq = &ctrl_hci->hw_txq[txqid];
+ hw_txq->tx_flags = tx_flags;
+ if (tx_flags & HCI_FLAGS_ENQUEUE_HEAD)
+ skb_queue_head(&hw_txq->qhead, skb);
+ else
+ skb_queue_tail(&hw_txq->qhead, skb);
+ qlen = (int)skb_queue_len(&hw_txq->qhead);
+ if (!(tx_flags & HCI_FLAGS_NO_FLOWCTRL)) {
+ if (skb_queue_len(&hw_txq->qhead) >= hw_txq->max_qsize) {
+ ctrl_hci->shi->hci_tx_flow_ctrl_cb(ctrl_hci->
+ shi->tx_fctrl_cb_args,
+ hw_txq->txq_no, true,
+ 2000);
+ }
+ }
+
+ mutex_lock(&ctrl_hci->hci_mutex);
+ spin_lock_irqsave(&ctrl_hci->int_lock, flags);
+ status = ctrl_hci->int_mask;
+
+ if ((ctrl_hci->int_mask & SSV6XXX_INT_RESOURCE_LOW) == 0) {
+ if (ctrl_hci->shi->if_ops->trigger_tx_rx == NULL) {
+ u32 regval;
+ ctrl_hci->int_mask |= SSV6XXX_INT_RESOURCE_LOW;
+ regval = ~ctrl_hci->int_mask;
+ spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+ HCI_IRQ_SET_MASK(ctrl_hci, regval);
+ mutex_unlock(&ctrl_hci->hci_mutex);
+ } else {
+ ctrl_hci->int_status |= SSV6XXX_INT_RESOURCE_LOW;
+ smp_mb();
+ spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+ mutex_unlock(&ctrl_hci->hci_mutex);
+ ctrl_hci->shi->if_ops->trigger_tx_rx(ctrl_hci->
+ shi->dev);
+ }
+ } else {
+ spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+ mutex_unlock(&ctrl_hci->hci_mutex);
+ }
+
+ return qlen;
+}
+
+static bool ssv6xxx_hci_is_txq_empty(int txqid)
+{
+ struct ssv_hw_txq *hw_txq;
+ BUG_ON(txqid >= SSV_HW_TXQ_NUM);
+ if (txqid >= SSV_HW_TXQ_NUM)
+ return false;
+ hw_txq = &ctrl_hci->hw_txq[txqid];
+ if (skb_queue_len(&hw_txq->qhead) <= 0)
+ return true;
+ return false;
+}
+
+static int ssv6xxx_hci_txq_flush(u32 txq_mask)
+{
+ struct ssv_hw_txq *hw_txq;
+ struct sk_buff *skb = NULL;
+ int txqid;
+ for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
+ if ((txq_mask & (1 << txqid)) != 0)
+ continue;
+ hw_txq = &ctrl_hci->hw_txq[txqid];
+ while ((skb = skb_dequeue(&hw_txq->qhead))) {
+ ctrl_hci->shi->hci_tx_buf_free_cb(skb,
+ ctrl_hci->
+ shi->tx_buf_free_args);
+ }
+ }
+ return 0;
+}
+
+static int ssv6xxx_hci_txq_flush_by_sta(int aid)
+{
+ return 0;
+}
+
+static int ssv6xxx_hci_txq_pause(u32 txq_mask)
+{
+ struct ssv_hw_txq *hw_txq;
+ int txqid;
+ mutex_lock(&ctrl_hci->txq_mask_lock);
+ ctrl_hci->txq_mask |= (txq_mask & 0x1F);
+ for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
+ if ((ctrl_hci->txq_mask & (1 << txqid)) == 0)
+ continue;
+ hw_txq = &ctrl_hci->hw_txq[txqid];
+ hw_txq->paused = true;
+ }
+ HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN,
+ (ctrl_hci->txq_mask << 16), (0x1F << 16));
+ mutex_unlock(&ctrl_hci->txq_mask_lock);
+ return 0;
+}
+
+static int ssv6xxx_hci_txq_resume(u32 txq_mask)
+{
+ struct ssv_hw_txq *hw_txq;
+ int txqid;
+ mutex_lock(&ctrl_hci->txq_mask_lock);
+ ctrl_hci->txq_mask &= ~(txq_mask & 0x1F);
+ for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
+ if ((ctrl_hci->txq_mask & (1 << txqid)) != 0)
+ continue;
+ hw_txq = &ctrl_hci->hw_txq[txqid];
+ hw_txq->paused = false;
+ }
+ HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN,
+ (ctrl_hci->txq_mask << 16), (0x1F << 16));
+ mutex_unlock(&ctrl_hci->txq_mask_lock);
+ return 0;
+}
+
+static int ssv6xxx_hci_xmit(struct ssv_hw_txq *hw_txq, int max_count,
+ struct ssv6xxx_hw_resource *phw_resource)
+{
+ struct sk_buff_head tx_cb_list;
+ struct sk_buff *skb = NULL;
+ int tx_count, ret, page_count;
+ struct ssv6200_tx_desc *tx_desc = NULL;
+ ctrl_hci->xmit_running = 1;
+ skb_queue_head_init(&tx_cb_list);
+ for (tx_count = 0; tx_count < max_count; tx_count++) {
+ if (ctrl_hci->hci_start == false) {
+ pr_debug("ssv6xxx_hci_xmit - hci_start = false\n");
+ goto xmit_out;
+ }
+ skb = skb_dequeue(&hw_txq->qhead);
+ if (!skb) {
+ pr_debug("ssv6xxx_hci_xmit - queue empty\n");
+ goto xmit_out;
+ }
+ page_count = (skb->len + SSV6200_ALLOC_RSVD);
+ if (page_count & HW_MMU_PAGE_MASK)
+ page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
+ else
+ page_count = page_count >> HW_MMU_PAGE_SHIFT;
+ if (page_count > (SSV6200_PAGE_TX_THRESHOLD / 2))
+ pr_err("Asking page %d(%d) exceeds resource limit %d.\n",
+ page_count, skb->len,
+ (SSV6200_PAGE_TX_THRESHOLD / 2));
+ if ((phw_resource->free_tx_page < page_count)
+ || (phw_resource->free_tx_id <= 0)
+ || (phw_resource->max_tx_frame[hw_txq->txq_no] <= 0)) {
+ skb_queue_head(&hw_txq->qhead, skb);
+ break;
+ }
+ phw_resource->free_tx_page -= page_count;
+ phw_resource->free_tx_id--;
+ phw_resource->max_tx_frame[hw_txq->txq_no]--;
+ tx_desc = (struct ssv6200_tx_desc *)skb->data;
+
+ if (ctrl_hci->shi->hci_skb_update_cb != NULL
+ && tx_desc->reason != ID_TRAP_SW_TXTPUT) {
+ ctrl_hci->shi->hci_skb_update_cb(skb,
+ ctrl_hci->
+ shi->skb_update_args);
+ }
+
+ ret =
+ IF_SEND(ctrl_hci, (void *)skb->data, skb->len,
+ hw_txq->txq_no);
+ if (ret < 0) {
+ pr_err("ssv6xxx_hci_xmit failure\n");
+ skb_queue_head(&hw_txq->qhead, skb);
+ break;
+ }
+ if (tx_desc->reason != ID_TRAP_SW_TXTPUT)
+ skb_queue_tail(&tx_cb_list, skb);
+ else
+ ssv_skb_free(skb);
+ hw_txq->tx_pkt++;
+
+ if (!(hw_txq->tx_flags & HCI_FLAGS_NO_FLOWCTRL)) {
+ if (skb_queue_len(&hw_txq->qhead) < hw_txq->resum_thres) {
+ ctrl_hci->shi->
+ hci_tx_flow_ctrl_cb
+ (ctrl_hci->shi->tx_fctrl_cb_args,
+ hw_txq->txq_no, false, 2000);
+ }
+ }
+ }
+ xmit_out:
+ if (ctrl_hci->shi->hci_tx_cb && tx_desc
+ && tx_desc->reason != ID_TRAP_SW_TXTPUT) {
+ ctrl_hci->shi->hci_tx_cb(&tx_cb_list,
+ ctrl_hci->shi->tx_cb_args);
+ }
+ ctrl_hci->xmit_running = 0;
+ return tx_count;
+}
+
+static int ssv6xxx_hci_tx_handler(void *dev, int max_count)
+{
+ struct ssv6xxx_hci_txq_info txq_info;
+ struct ssv6xxx_hci_txq_info2 txq_info2;
+ struct ssv6xxx_hw_resource hw_resource;
+ struct ssv_hw_txq *hw_txq = dev;
+ int ret, tx_count = 0;
+ max_count = skb_queue_len(&hw_txq->qhead);
+ if (max_count == 0)
+ return 0;
+ if (hw_txq->txq_no == 4) {
+ ret =
+ HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO2,
+ (u32 *) & txq_info2);
+ if (ret < 0) {
+ ctrl_hci->read_rs1_info_fail++;
+ return 0;
+ }
+ //BUG_ON(SSV6200_PAGE_TX_THRESHOLD < txq_info2.tx_use_page);
+ //BUG_ON(SSV6200_ID_TX_THRESHOLD < txq_info2.tx_use_id);
+ if (SSV6200_PAGE_TX_THRESHOLD < txq_info2.tx_use_page)
+ return 0;
+ if (SSV6200_ID_TX_THRESHOLD < txq_info2.tx_use_page)
+ return 0;
+ hw_resource.free_tx_page =
+ SSV6200_PAGE_TX_THRESHOLD - txq_info2.tx_use_page;
+ hw_resource.free_tx_id =
+ SSV6200_ID_TX_THRESHOLD - txq_info2.tx_use_id;
+ hw_resource.max_tx_frame[4] =
+ SSV6200_ID_MANAGER_QUEUE - txq_info2.txq4_size;
+ } else {
+ ret =
+ HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO,
+ (u32 *) & txq_info);
+ if (ret < 0) {
+ ctrl_hci->read_rs0_info_fail++;
+ return 0;
+ }
+ //BUG_ON(SSV6200_PAGE_TX_THRESHOLD < txq_info.tx_use_page);
+ //BUG_ON(SSV6200_ID_TX_THRESHOLD < txq_info.tx_use_id);
+ if (SSV6200_PAGE_TX_THRESHOLD < txq_info.tx_use_page)
+ return 0;
+ if (SSV6200_ID_TX_THRESHOLD < txq_info.tx_use_page)
+ return 0;
+ hw_resource.free_tx_page =
+ SSV6200_PAGE_TX_THRESHOLD - txq_info.tx_use_page;
+ hw_resource.free_tx_id =
+ SSV6200_ID_TX_THRESHOLD - txq_info.tx_use_id;
+ hw_resource.max_tx_frame[0] =
+ SSV6200_ID_AC_BK_OUT_QUEUE - txq_info.txq0_size;
+ hw_resource.max_tx_frame[1] =
+ SSV6200_ID_AC_BE_OUT_QUEUE - txq_info.txq1_size;
+ hw_resource.max_tx_frame[2] =
+ SSV6200_ID_AC_VI_OUT_QUEUE - txq_info.txq2_size;
+ hw_resource.max_tx_frame[3] =
+ SSV6200_ID_AC_VO_OUT_QUEUE - txq_info.txq3_size;
+ BUG_ON(hw_resource.max_tx_frame[3] < 0);
+ BUG_ON(hw_resource.max_tx_frame[2] < 0);
+ BUG_ON(hw_resource.max_tx_frame[1] < 0);
+ BUG_ON(hw_resource.max_tx_frame[0] < 0);
+ }
+ {
+ tx_count = ssv6xxx_hci_xmit(hw_txq, max_count, &hw_resource);
+ }
+ if ((ctrl_hci->shi->hci_tx_q_empty_cb != NULL)
+ && (skb_queue_len(&hw_txq->qhead) == 0)) {
+ ctrl_hci->shi->hci_tx_q_empty_cb(hw_txq->txq_no,
+ ctrl_hci->
+ shi->tx_q_empty_args);
+ }
+ return tx_count;
+}
+
+void ssv6xxx_hci_tx_work(struct work_struct *work)
+{
+ ssv6xxx_hci_irq_register(SSV6XXX_INT_RESOURCE_LOW);
+}
+
+static int _do_rx(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
+{
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ struct sk_buff_head rx_list;
+#endif
+ struct sk_buff *rx_mpdu;
+ int rx_cnt, ret = 0;
+ size_t dlen;
+ u32 status = isr_status;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
+ struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ skb_queue_head_init(&rx_list);
+#endif
+ for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32); rx_cnt++) {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable)
+ getnstimeofday(&rx_io_start_time);
+#endif
+ ret = IF_RECV(hctl, hctl->rx_buf->data, &dlen);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable)
+ getnstimeofday(&rx_io_end_time);
+#endif
+ if (ret < 0 || dlen <= 0) {
+ pr_warn("%s(): IF_RECV() retruns %d (dlen=%d)\n",
+ __FUNCTION__, ret, (int)dlen);
+ if (ret != -84 || dlen > MAX_FRAME_SIZE)
+ break;
+ }
+ rx_mpdu = hctl->rx_buf;
+ hctl->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
+ if (hctl->rx_buf == NULL) {
+ pr_err("RX buffer allocation failure!\n");
+ hctl->rx_buf = rx_mpdu;
+ break;
+ }
+ hctl->rx_pkt++;
+ skb_put(rx_mpdu, dlen);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable)
+ getnstimeofday(&rx_proc_start_time);
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ __skb_queue_tail(&rx_list, rx_mpdu);
+#else
+ hctl->shi->hci_rx_cb(rx_mpdu, hctl->shi->rx_cb_args);
+#endif
+ HCI_IRQ_STATUS(hctl, &status);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable) {
+ getnstimeofday(&rx_proc_end_time);
+ hctl->isr_rx_io_count++;
+ rx_io_diff_time =
+ timespec_sub(rx_io_end_time, rx_io_start_time);
+ hctl->isr_rx_io_time +=
+ timespec_to_ns(&rx_io_diff_time);
+ rx_proc_diff_time =
+ timespec_sub(rx_proc_end_time, rx_proc_start_time);
+ hctl->isr_rx_proc_time +=
+ timespec_to_ns(&rx_proc_diff_time);
+ }
+#endif
+ }
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable)
+ getnstimeofday(&rx_proc_start_time);
+#endif
+ hctl->shi->hci_rx_cb(&rx_list, hctl->shi->rx_cb_args);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable) {
+ getnstimeofday(&rx_proc_end_time);
+ rx_proc_diff_time =
+ timespec_sub(rx_proc_end_time, rx_proc_start_time);
+ hctl->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time);
+ }
+#endif
+#endif
+ return ret;
+}
+
+static void ssv6xxx_hci_rx_work(struct work_struct *work)
+{
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ struct sk_buff_head rx_list;
+#endif
+ struct sk_buff *rx_mpdu;
+ int rx_cnt, ret;
+ size_t dlen;
+ u32 status;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
+ struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
+#endif
+ ctrl_hci->rx_work_running = 1;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ skb_queue_head_init(&rx_list);
+#endif
+ status = SSV6XXX_INT_RX;
+ for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32); rx_cnt++) {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (ctrl_hci->isr_mib_enable)
+ getnstimeofday(&rx_io_start_time);
+#endif
+ ret = IF_RECV(ctrl_hci, ctrl_hci->rx_buf->data, &dlen);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (ctrl_hci->isr_mib_enable)
+ getnstimeofday(&rx_io_end_time);
+#endif
+ if (ret < 0 || dlen <= 0) {
+ pr_warn("%s(): IF_RECV() retruns %d (dlen=%d)\n",
+ __FUNCTION__, ret, (int)dlen);
+ if (ret != -84 || dlen > MAX_FRAME_SIZE)
+ break;
+ }
+ rx_mpdu = ctrl_hci->rx_buf;
+ ctrl_hci->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
+ if (ctrl_hci->rx_buf == NULL) {
+ pr_err("RX buffer allocation failure!\n");
+ ctrl_hci->rx_buf = rx_mpdu;
+ break;
+ }
+ ctrl_hci->rx_pkt++;
+ skb_put(rx_mpdu, dlen);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (ctrl_hci->isr_mib_enable)
+ getnstimeofday(&rx_proc_start_time);
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ __skb_queue_tail(&rx_list, rx_mpdu);
+#else
+ ctrl_hci->shi->hci_rx_cb(rx_mpdu, ctrl_hci->shi->rx_cb_args);
+#endif
+ HCI_IRQ_STATUS(ctrl_hci, &status);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (ctrl_hci->isr_mib_enable) {
+ getnstimeofday(&rx_proc_end_time);
+ ctrl_hci->isr_rx_io_count++;
+ rx_io_diff_time =
+ timespec_sub(rx_io_end_time, rx_io_start_time);
+ ctrl_hci->isr_rx_io_time +=
+ timespec_to_ns(&rx_io_diff_time);
+ rx_proc_diff_time =
+ timespec_sub(rx_proc_end_time, rx_proc_start_time);
+ ctrl_hci->isr_rx_proc_time +=
+ timespec_to_ns(&rx_proc_diff_time);
+ }
+#endif
+ }
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (ctrl_hci->isr_mib_enable)
+ getnstimeofday(&rx_proc_start_time);
+#endif
+ ctrl_hci->shi->hci_rx_cb(&rx_list, ctrl_hci->shi->rx_cb_args);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (ctrl_hci->isr_mib_enable) {
+ getnstimeofday(&rx_proc_end_time);
+ rx_proc_diff_time =
+ timespec_sub(rx_proc_end_time, rx_proc_start_time);
+ ctrl_hci->isr_rx_proc_time +=
+ timespec_to_ns(&rx_proc_diff_time);
+ }
+#endif
+#endif
+ ctrl_hci->rx_work_running = 0;
+}
+
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+static void ssv6xxx_isr_mib_reset(void)
+{
+ ctrl_hci->isr_mib_reset = 0;
+ ctrl_hci->isr_total_time = 0;
+ ctrl_hci->isr_rx_io_time = 0;
+ ctrl_hci->isr_tx_io_time = 0;
+ ctrl_hci->isr_rx_io_count = 0;
+ ctrl_hci->isr_tx_io_count = 0;
+ ctrl_hci->isr_rx_proc_time = 0;
+}
+
+static int hw_txq_len_open(struct inode *inode, struct file *filp)
+{
+ filp->private_data = inode->i_private;
+ return 0;
+}
+
+static ssize_t hw_txq_len_read(struct file *filp, char __user * buffer,
+ size_t count, loff_t * ppos)
+{
+ ssize_t ret;
+ struct ssv6xxx_hci_ctrl *hctl =
+ (struct ssv6xxx_hci_ctrl *)filp->private_data;
+ char *summary_buf = kzalloc(1024, GFP_KERNEL);
+ char *prn_ptr = summary_buf;
+ int prt_size;
+ int buf_size = 1024;
+ int i = 0;
+ if (!summary_buf)
+ return -ENOMEM;
+ for (i = 0; i < SSV_HW_TXQ_NUM; i++) {
+ prt_size =
+ snprintf(prn_ptr, buf_size, "\n\rhw_txq%d_len: %d", i,
+ skb_queue_len(&hctl->hw_txq[i].qhead));
+ prn_ptr += prt_size;
+ buf_size -= prt_size;
+ }
+ buf_size = 1024 - buf_size;
+ ret =
+ simple_read_from_buffer(buffer, count, ppos, summary_buf, buf_size);
+ kfree(summary_buf);
+ return ret;
+}
+
+struct file_operations hw_txq_len_fops = {
+ .owner = THIS_MODULE,
+ .open = hw_txq_len_open,
+ .read = hw_txq_len_read,
+};
+
+bool ssv6xxx_hci_init_debugfs(struct dentry *dev_deugfs_dir)
+{
+ ctrl_hci->debugfs_dir = debugfs_create_dir("hci", dev_deugfs_dir);
+ if (ctrl_hci->debugfs_dir == NULL) {
+ dev_err(ctrl_hci->shi->dev,
+ "Failed to create HCI debugfs directory.\n");
+ return false;
+ }
+ debugfs_create_u32("TXQ_mask", 00444, ctrl_hci->debugfs_dir,
+ &ctrl_hci->txq_mask);
+ debugfs_create_u32("hci_isr_mib_enable", 00644, ctrl_hci->debugfs_dir,
+ &ctrl_hci->isr_mib_enable);
+ debugfs_create_u32("hci_isr_mib_reset", 00644, ctrl_hci->debugfs_dir,
+ &ctrl_hci->isr_mib_reset);
+ debugfs_create_u64("isr_total_time", 00444, ctrl_hci->debugfs_dir,
+ &ctrl_hci->isr_total_time);
+ debugfs_create_u64("tx_io_time", 00444, ctrl_hci->debugfs_dir,
+ &ctrl_hci->isr_tx_io_time);
+ debugfs_create_u64("rx_io_time", 00444, ctrl_hci->debugfs_dir,
+ &ctrl_hci->isr_rx_io_time);
+ debugfs_create_u32("tx_io_count", 00444, ctrl_hci->debugfs_dir,
+ &ctrl_hci->isr_tx_io_count);
+ debugfs_create_u32("rx_io_count", 00444, ctrl_hci->debugfs_dir,
+ &ctrl_hci->isr_rx_io_count);
+ debugfs_create_u64("rx_proc_time", 00444, ctrl_hci->debugfs_dir,
+ &ctrl_hci->isr_rx_proc_time);
+ debugfs_create_file("hw_txq_len", 00444, ctrl_hci->debugfs_dir,
+ ctrl_hci, &hw_txq_len_fops);
+ return true;
+}
+
+void ssv6xxx_hci_deinit_debugfs(void)
+{
+ if (ctrl_hci->debugfs_dir == NULL)
+ return;
+ ctrl_hci->debugfs_dir = NULL;
+}
+#endif
+static int _isr_do_rx(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
+{
+ int status;
+ u32 before = jiffies;
+
+ if (hctl->isr_summary_eable && hctl->prev_rx_isr_jiffes) {
+ if (hctl->isr_rx_idle_time) {
+ hctl->isr_rx_idle_time +=
+ (jiffies - hctl->prev_rx_isr_jiffes);
+ hctl->isr_rx_idle_time = hctl->isr_rx_idle_time >> 1;
+ } else {
+ hctl->isr_rx_idle_time +=
+ (jiffies - hctl->prev_rx_isr_jiffes);
+ }
+ }
+ status = _do_rx(hctl, isr_status);
+ if (hctl->isr_summary_eable) {
+ if (hctl->isr_rx_time) {
+ hctl->isr_rx_time += (jiffies - before);
+ hctl->isr_rx_time = hctl->isr_rx_time >> 1;
+ } else {
+ hctl->isr_rx_time += (jiffies - before);
+ }
+ hctl->prev_rx_isr_jiffes = jiffies;
+ }
+ return status;
+}
+
+static int _do_tx(struct ssv6xxx_hci_ctrl *hctl, u32 status)
+{
+ int q_num;
+ int tx_count = 0;
+ u32 to_disable_int = 1;
+ unsigned long flags;
+ struct ssv_hw_txq *hw_txq;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct timespec tx_io_start_time, tx_io_end_time, tx_io_diff_time;
+#endif
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ if ((!(status & SSV6XXX_INT_RX)) && htcl->irq_enable)
+ hctl->tx_irq_count++;
+#endif
+ if ((status & SSV6XXX_INT_RESOURCE_LOW) == 0)
+ return 0;
+ for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
+ u32 before = jiffies;
+ hw_txq = &hctl->hw_txq[q_num];
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable)
+ getnstimeofday(&tx_io_start_time);
+#endif
+ tx_count += ssv6xxx_hci_tx_handler(hw_txq, 999);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (hctl->isr_mib_enable) {
+ getnstimeofday(&tx_io_end_time);
+ tx_io_diff_time =
+ timespec_sub(tx_io_end_time, tx_io_start_time);
+ hctl->isr_tx_io_time +=
+ timespec_to_ns(&tx_io_diff_time);
+ }
+#endif
+ if (hctl->isr_summary_eable) {
+ if (hctl->isr_tx_time) {
+ hctl->isr_tx_time += (jiffies - before);
+ hctl->isr_tx_time = hctl->isr_tx_time >> 1;
+ } else {
+ hctl->isr_tx_time += (jiffies - before);
+ }
+ }
+ }
+ mutex_lock(&hctl->hci_mutex);
+ spin_lock_irqsave(&hctl->int_lock, flags);
+ for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
+ hw_txq = &hctl->hw_txq[q_num];
+ if (skb_queue_len(&hw_txq->qhead) > 0) {
+ to_disable_int = 0;
+ break;
+ }
+ }
+ if (to_disable_int) {
+ u32 reg_val;
+ hctl->int_mask &= ~(SSV6XXX_INT_RESOURCE_LOW | SSV6XXX_INT_TX);
+ reg_val = ~hctl->int_mask;
+ spin_unlock_irqrestore(&hctl->int_lock, flags);
+ HCI_IRQ_SET_MASK(hctl, reg_val);
+ } else {
+ spin_unlock_irqrestore(&hctl->int_lock, flags);
+ }
+ mutex_unlock(&hctl->hci_mutex);
+ return tx_count;
+}
+
+irqreturn_t ssv6xxx_hci_isr(int irq, void *args)
+{
+ struct ssv6xxx_hci_ctrl *hctl = args;
+ u32 status;
+ unsigned long flags;
+ int ret = IRQ_HANDLED;
+ bool dbg_isr_miss = true;
+ if (ctrl_hci->isr_summary_eable && ctrl_hci->prev_isr_jiffes) {
+ if (ctrl_hci->isr_idle_time) {
+ ctrl_hci->isr_idle_time +=
+ (jiffies - ctrl_hci->prev_isr_jiffes);
+ ctrl_hci->isr_idle_time = ctrl_hci->isr_idle_time >> 1;
+ } else {
+ ctrl_hci->isr_idle_time +=
+ (jiffies - ctrl_hci->prev_isr_jiffes);
+ }
+ }
+ BUG_ON(!args);
+ do {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct timespec start_time, end_time, diff_time;
+ if (hctl->isr_mib_reset)
+ ssv6xxx_isr_mib_reset();
+ if (hctl->isr_mib_enable)
+ getnstimeofday(&start_time);
+#endif
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ if (ctrl_hci->irq_enable)
+ ctrl_hci->irq_count++;
+#endif
+ mutex_lock(&hctl->hci_mutex);
+ if (hctl->int_status) {
+ u32 regval;
+ spin_lock_irqsave(&hctl->int_lock, flags);
+ hctl->int_mask |= hctl->int_status;
+ hctl->int_status = 0;
+ regval = ~ctrl_hci->int_mask;
+ smp_mb();
+ spin_unlock_irqrestore(&hctl->int_lock, flags);
+ HCI_IRQ_SET_MASK(hctl, regval);
+ }
+ ret = HCI_IRQ_STATUS(hctl, &status);
+ if ((ret < 0) || ((status & hctl->int_mask) == 0)) {
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ if (ctrl_hci->irq_enable)
+ ctrl_hci->invalid_irq_count++;
+#endif
+ mutex_unlock(&hctl->hci_mutex);
+ ret = IRQ_NONE;
+ break;
+ }
+ spin_lock_irqsave(&hctl->int_lock, flags);
+ status &= hctl->int_mask;
+ spin_unlock_irqrestore(&hctl->int_lock, flags);
+ mutex_unlock(&hctl->hci_mutex);
+ ctrl_hci->isr_running = 1;
+ if (status & SSV6XXX_INT_RX) {
+ ret = _isr_do_rx(hctl, status);
+ if (ret < 0) {
+ ret = IRQ_NONE;
+ break;
+ }
+ dbg_isr_miss = false;
+ }
+ if (_do_tx(hctl, status)) {
+ dbg_isr_miss = false;
+ }
+ ctrl_hci->isr_running = 0;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (ctrl_hci->isr_mib_enable) {
+ getnstimeofday(&end_time);
+ diff_time = timespec_sub(end_time, start_time);
+ ctrl_hci->isr_total_time += timespec_to_ns(&diff_time);
+ }
+#endif
+ } while (1);
+ if (ctrl_hci->isr_summary_eable) {
+ if (dbg_isr_miss)
+ ctrl_hci->isr_miss_cnt++;
+ ctrl_hci->prev_isr_jiffes = jiffies;
+ }
+ return ret;
+}
+
+static struct ssv6xxx_hci_ops hci_ops = {
+ .hci_start = ssv6xxx_hci_start,
+ .hci_stop = ssv6xxx_hci_stop,
+ .hci_read_word = ssv6xxx_hci_read_word,
+ .hci_write_word = ssv6xxx_hci_write_word,
+ .hci_tx = ssv6xxx_hci_enqueue,
+ .hci_tx_pause = ssv6xxx_hci_txq_pause,
+ .hci_tx_resume = ssv6xxx_hci_txq_resume,
+ .hci_txq_flush = ssv6xxx_hci_txq_flush,
+ .hci_txq_flush_by_sta = ssv6xxx_hci_txq_flush_by_sta,
+ .hci_txq_empty = ssv6xxx_hci_is_txq_empty,
+ .hci_load_fw = ssv6xxx_hci_load_fw,
+ .hci_pmu_wakeup = ssv6xxx_hci_pmu_wakeup,
+ .hci_send_cmd = ssv6xxx_hci_send_cmd,
+ .hci_write_sram = ssv6xxx_hci_write_sram,
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ .hci_init_debugfs = ssv6xxx_hci_init_debugfs,
+ .hci_deinit_debugfs = ssv6xxx_hci_deinit_debugfs,
+#endif
+ .hci_interface_reset = ssv6xxx_hci_interface_reset,
+};
+
+int ssv6xxx_hci_deregister(void)
+{
+ u32 regval;
+ pr_debug("%s(): \n", __FUNCTION__);
+ if (ctrl_hci->shi == NULL)
+ return -1;
+ regval = 1;
+ ssv6xxx_hci_irq_disable();
+ flush_workqueue(ctrl_hci->hci_work_queue);
+ destroy_workqueue(ctrl_hci->hci_work_queue);
+ ctrl_hci->shi = NULL;
+ return 0;
+}
+
+EXPORT_SYMBOL(ssv6xxx_hci_deregister);
+int ssv6xxx_hci_register(struct ssv6xxx_hci_info *shi)
+{
+ int i;
+ if (shi == NULL || ctrl_hci->shi)
+ return -1;
+ shi->hci_ops = &hci_ops;
+ ctrl_hci->shi = shi;
+ ctrl_hci->txq_mask = 0;
+ mutex_init(&ctrl_hci->txq_mask_lock);
+ mutex_init(&ctrl_hci->hci_mutex);
+ spin_lock_init(&ctrl_hci->int_lock);
+
+ for (i = 0; i < SSV_HW_TXQ_NUM; i++) {
+ memset(&ctrl_hci->hw_txq[i], 0, sizeof(struct ssv_hw_txq));
+ skb_queue_head_init(&ctrl_hci->hw_txq[i].qhead);
+ ctrl_hci->hw_txq[i].txq_no = (u32) i;
+ ctrl_hci->hw_txq[i].max_qsize = SSV_HW_TXQ_MAX_SIZE;
+ ctrl_hci->hw_txq[i].resum_thres = SSV_HW_TXQ_RESUME_THRES;
+ }
+ ctrl_hci->hci_work_queue =
+ create_singlethread_workqueue("ssv6xxx_hci_wq");
+ INIT_WORK(&ctrl_hci->hci_rx_work, ssv6xxx_hci_rx_work);
+ INIT_WORK(&ctrl_hci->hci_tx_work, ssv6xxx_hci_tx_work);
+ ctrl_hci->int_mask = SSV6XXX_INT_RX | SSV6XXX_INT_RESOURCE_LOW;
+ ctrl_hci->int_status = 0;
+ HCI_IRQ_SET_MASK(ctrl_hci, 0xFFFFFFFF);
+ ssv6xxx_hci_irq_disable();
+ HCI_IRQ_REQUEST(ctrl_hci, ssv6xxx_hci_isr);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ ctrl_hci->debugfs_dir = NULL;
+ ctrl_hci->isr_mib_enable = false;
+ ctrl_hci->isr_mib_reset = 0;
+ ctrl_hci->isr_total_time = 0;
+ ctrl_hci->isr_rx_io_time = 0;
+ ctrl_hci->isr_tx_io_time = 0;
+ ctrl_hci->isr_rx_io_count = 0;
+ ctrl_hci->isr_tx_io_count = 0;
+ ctrl_hci->isr_rx_proc_time = 0;
+#endif
+ return 0;
+}
+
+EXPORT_SYMBOL(ssv6xxx_hci_register);
+int ssv6xxx_hci_init(void)
+{
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+ extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
+#endif
+ ctrl_hci = kzalloc(sizeof(*ctrl_hci), GFP_KERNEL);
+ if (ctrl_hci == NULL)
+ return -ENOMEM;
+ memset((void *)ctrl_hci, 0, sizeof(*ctrl_hci));
+ ctrl_hci->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
+ if (ctrl_hci->rx_buf == NULL) {
+ kfree(ctrl_hci);
+ return -ENOMEM;
+ }
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+ ssv_dbg_ctrl_hci = ctrl_hci;
+#endif
+ return 0;
+}
+
+void ssv6xxx_hci_exit(void)
+{
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+ extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
+#endif
+ kfree(ctrl_hci);
+ ctrl_hci = NULL;
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+ ssv_dbg_ctrl_hci = NULL;
+#endif
+}
+
+EXPORT_SYMBOL(ssv6xxx_hci_init);
+EXPORT_SYMBOL(ssv6xxx_hci_exit);
diff --git a/drivers/net/wireless/ssv6051/hci/ssv_hci.h b/drivers/net/wireless/ssv6051/hci/ssv_hci.h
new file mode 100644
index 000000000000..dd166c607d5d
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hci/ssv_hci.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_HCI_H_
+#define _SSV_HCI_H_
+#define SSV_HW_TXQ_NUM 5
+#define SSV_HW_TXQ_MAX_SIZE 64
+#define SSV_HW_TXQ_RESUME_THRES ((SSV_HW_TXQ_MAX_SIZE >> 2) *3)
+#define HCI_FLAGS_ENQUEUE_HEAD 0x00000001
+#define HCI_FLAGS_NO_FLOWCTRL 0x00000002
+struct ssv_hw_txq {
+ u32 txq_no;
+ struct sk_buff_head qhead;
+ int max_qsize;
+ int resum_thres;
+ bool paused;
+ u32 tx_pkt;
+ u32 tx_flags;
+};
+struct ssv6xxx_hci_ops {
+ int (*hci_start)(void);
+ int (*hci_stop)(void);
+ int (*hci_read_word)(u32 addr, u32 * regval);
+ int (*hci_write_word)(u32 addr, u32 regval);
+ int (*hci_load_fw)(u8 * firmware_name, u8 openfile);
+ int (*hci_tx)(struct sk_buff *, int, u32);
+ int (*hci_tx_pause)(u32 txq_mask);
+ int (*hci_tx_resume)(u32 txq_mask);
+ int (*hci_txq_flush)(u32 txq_mask);
+ int (*hci_txq_flush_by_sta)(int aid);
+ bool (*hci_txq_empty)(int txqid);
+ int (*hci_pmu_wakeup)(void);
+ int (*hci_send_cmd)(struct sk_buff *);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ bool (*hci_init_debugfs)(struct dentry * dev_deugfs_dir);
+ void (*hci_deinit_debugfs)(void);
+#endif
+ int (*hci_write_sram)(u32 addr, u8 * data, u32 size);
+ int (*hci_interface_reset)(void);
+};
+struct ssv6xxx_hci_info {
+ struct device *dev;
+ struct ssv6xxx_hwif_ops *if_ops;
+ struct ssv6xxx_hci_ops *hci_ops;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ int (*hci_rx_cb)(struct sk_buff_head *, void *);
+#else
+ int (*hci_rx_cb)(struct sk_buff *, void *);
+#endif
+ void *rx_cb_args;
+ void (*hci_tx_cb)(struct sk_buff_head *, void *);
+ void *tx_cb_args;
+ int (*hci_tx_flow_ctrl_cb)(void *, int, bool, int debug);
+ void *tx_fctrl_cb_args;
+ void (*hci_tx_buf_free_cb)(struct sk_buff *, void *);
+ void *tx_buf_free_args;
+ void (*hci_skb_update_cb)(struct sk_buff *, void *);
+ void *skb_update_args;
+ void (*hci_tx_q_empty_cb)(u32 txq_no, void *);
+ void *tx_q_empty_args;
+};
+int ssv6xxx_hci_deregister(void);
+int ssv6xxx_hci_register(struct ssv6xxx_hci_info *);
+#endif
diff --git a/drivers/net/wireless/ssv6051/hwif/hwif.h b/drivers/net/wireless/ssv6051/hwif/hwif.h
new file mode 100644
index 000000000000..6b5263d157d8
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hwif/hwif.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _LINUX_SSVCABRIO_PLATFORM_H
+#define _LINUX_SSVCABRIO_PLATFORM_H
+#include <linux/mmc/host.h>
+#include <hwif/sdio/sdio_def.h>
+#define SSVCABRIO_PLAT_EEP_MAX_WORDS 2048
+#define SSV_REG_WRITE(dev,reg,val) \
+ (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
+#define SSV_REG_READ(dev,reg,buf) \
+ (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
+#if 0
+#define SSV_REG_WRITE(sh,reg,val) \
+ (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
+#define SSV_REG_READ(sh,reg,buf) \
+ (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
+#define SSV_REG_CONFIRM(sh,reg,val) \
+{ \
+ u32 regval; \
+ SSV_REG_READ(sh, reg, &regval); \
+ if (regval != (val)) { \
+ printk("[0x%08x]: 0x%08x!=0x%08x\n",\
+ (reg), (val), regval); \
+ return -1; \
+ } \
+}
+#define SSV_REG_SET_BITS(sh,reg,set,clr) \
+{ \
+ u32 reg_val; \
+ SSV_REG_READ(sh, reg, &reg_val); \
+ reg_val &= ~(clr); \
+ reg_val |= (set); \
+ SSV_REG_WRITE(sh, reg, reg_val); \
+}
+#endif
+struct ssv6xxx_hwif_ops {
+ int __must_check (*read)(struct device *child, void *buf,size_t *size);
+ int __must_check (*write)(struct device *child, void *buf, size_t len,u8 queue_num);
+ int __must_check (*readreg)(struct device *child, u32 addr, u32 *buf);
+ int __must_check (*writereg)(struct device *child, u32 addr, u32 buf);
+ int (*trigger_tx_rx)(struct device *child);
+ int (*irq_getmask)(struct device *child, u32 *mask);
+ void (*irq_setmask)(struct device *child,int mask);
+ void (*irq_enable)(struct device *child);
+ void (*irq_disable)(struct device *child,bool iswaitirq);
+ int (*irq_getstatus)(struct device *child,int *status);
+ void (*irq_request)(struct device *child,irq_handler_t irq_handler,void *irq_dev);
+ void (*irq_trigger)(struct device *child);
+ void (*pmu_wakeup)(struct device *child);
+ int __must_check (*load_fw)(struct device *child, u8 *firmware_name, u8 openfile);
+ int (*cmd52_read)(struct device *child, u32 addr, u32 *value);
+ int (*cmd52_write)(struct device *child, u32 addr, u32 value);
+ bool (*support_scatter)(struct device *child);
+ int (*rw_scatter)(struct device *child, struct sdio_scatter_req *scat_req);
+ bool (*is_ready)(struct device *child);
+ int (*write_sram)(struct device *child, u32 addr, u8 *data, u32 size);
+ void (*interface_reset)(struct device *child);
+};
+struct ssv6xxx_if_debug {
+ struct device *dev;
+ struct platform_device *pdev;
+};
+struct ssv6xxx_platform_data {
+ atomic_t irq_handling;
+ bool is_enabled;
+ unsigned short vendor;
+ unsigned short device;
+ struct ssv6xxx_hwif_ops *ops;
+};
+#endif
diff --git a/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c b/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
new file mode 100644
index 000000000000..273777cd0485
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
@@ -0,0 +1,1254 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include "sdio_def.h"
+#include <linux/pm_runtime.h>
+#include <linux/version.h>
+#include <linux/firmware.h>
+#include <linux/reboot.h>
+#include <ssv6200.h>
+#include <linux/skbuff.h>
+
+#define LOW_SPEED_SDIO_CLOCK (25000000)
+#define HIGH_SPEED_SDIO_CLOCK (37500000)
+#define MAX_RX_FRAME_SIZE 0x900
+#define SSV_VENDOR_ID 0x3030
+#define SSV_CABRIO_DEVID 0x3030
+#define ENABLE_FW_SELF_CHECK 1
+#define FW_BLOCK_SIZE 0x8000
+#define CHECKSUM_BLOCK_SIZE 1024
+#define FW_CHECKSUM_INIT (0x12345678)
+#define FW_STATUS_REG ADR_TX_SEG
+#define FW_STATUS_MASK (0x00FF0000)
+
+#define ret_if_not_ready(value) \
+ do { \
+ if ((wlan_data.is_enabled == false) || \
+ (glue == NULL) || (glue->dev_ready == false)) { \
+ pr_warn("ret_if_not_ready() called when not ready"); \
+ return value; }\
+ } while(0)
+
+static int ssv6xxx_sdio_trigger_pmu(struct device *dev);
+static void ssv6xxx_sdio_reset(struct device *child);
+
+static void ssv6xxx_high_sdio_clk(struct sdio_func *func);
+static void ssv6xxx_low_sdio_clk(struct sdio_func *func);
+extern void *ssv6xxx_ifdebug_info[];
+extern int ssv_devicetype;
+extern void ssv6xxx_deinit_prepare(void);
+
+static struct ssv6xxx_platform_data wlan_data;
+
+static int ssv6xxx_sdio_status = 0;
+u32 sdio_sr_bhvr = SUSPEND_RESUME_0;
+EXPORT_SYMBOL(sdio_sr_bhvr);
+
+u32 shutdown_flags = SSV_SYS_REBOOT;
+
+struct ssv6xxx_sdio_glue {
+ struct device *dev;
+ struct platform_device *core;
+ struct sk_buff *dma_skb;
+#ifdef CONFIG_PM
+ struct sk_buff *cmd_skb;
+#endif
+ unsigned int ioport_data;
+ unsigned int ioport_reg;
+ irq_handler_t irq_handler;
+ void *irq_dev;
+ bool dev_ready;
+};
+
+static const struct sdio_device_id ssv6xxx_sdio_devices[] = {
+ {SDIO_DEVICE(SSV_VENDOR_ID, SSV_CABRIO_DEVID)},
+ {}
+};
+
+MODULE_DEVICE_TABLE(sdio, ssv6xxx_sdio_devices);
+
+static bool ssv6xxx_is_ready(struct device *child)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+
+ ret_if_not_ready(false);
+
+ return true;
+}
+
+static int ssv6xxx_sdio_cmd52_read(struct device *child, u32 addr, u32 * value)
+{
+ int ret;
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+
+ ret_if_not_ready(-1);
+
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ *value = sdio_readb(func, addr, &ret);
+ sdio_release_host(func);
+
+ return ret;
+}
+
+static int ssv6xxx_sdio_cmd52_write(struct device *child, u32 addr, u32 value)
+{
+ int ret;
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+
+ ret_if_not_ready(-1);
+
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ sdio_writeb(func, value, addr, &ret);
+ sdio_release_host(func);
+
+ return ret;
+}
+
+static int __must_check
+ssv6xxx_sdio_read_reg(struct device *child, u32 addr, u32 * buf)
+{
+ int ret;
+
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ u32 data;
+
+ ret_if_not_ready(-1);
+
+ func = dev_to_sdio_func(glue->dev);
+
+ sdio_claim_host(func);
+
+ data = addr;
+
+ sdio_writel(func, addr, glue->ioport_reg, &ret);
+
+ if (unlikely(ret)) {
+ dev_err(child->parent, "sdio read reg write address failed (%d)\n", ret);
+ goto io_err;
+ }
+
+ data = sdio_readl(func, glue->ioport_reg, &ret);
+
+ if (unlikely(ret)) {
+ *buf = 0xffffffff;
+ dev_err(child->parent, "sdio read reg from I/O failed (%d)\n", ret);
+ goto io_err;
+ }
+
+ *buf = data;
+
+io_err:
+ sdio_release_host(func);
+
+ return ret;
+}
+
+#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+static int ssv6xxx_sdio_trigger_tx_rx(struct device *child)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ struct mmc_host *host;
+
+ if (glue == NULL)
+ return -1;
+
+ func = dev_to_sdio_func(glue->dev);
+ host = func->card->host;
+ mmc_signal_sdio_irq(host);
+
+ return 0;
+
+}
+#endif
+
+static int __must_check
+ssv6xxx_sdio_write_reg(struct device *child, u32 addr, u32 buf)
+{
+ int ret;
+
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+
+ u32 data[2];
+
+ ret_if_not_ready(-1);
+
+ func = dev_to_sdio_func(glue->dev);
+
+ sdio_claim_host(func);
+ data[0] = addr;
+ data[1] = buf;
+
+ ret = sdio_memcpy_toio(func, glue->ioport_reg, data, sizeof(data));
+ sdio_release_host(func);
+
+ return ret;
+}
+
+static int
+ssv6xxx_sdio_write_sram(struct device *child, u32 addr, u8 * data, u32 size)
+{
+ int ret = 0;
+ struct ssv6xxx_sdio_glue *glue;
+ struct sdio_func *func = NULL;
+ glue = dev_get_drvdata(child->parent);
+
+ ret_if_not_ready(-1);
+
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+
+ ret |= ssv6xxx_sdio_write_reg(child, 0xc0000860, addr);
+ if (unlikely(ret))
+ goto out;
+
+ sdio_writeb(func, 0x2, REG_Fn1_STATUS, &ret);
+ if (unlikely(ret))
+ goto out;
+
+ ret = sdio_memcpy_toio(func, glue->ioport_data, data, size);
+ if (unlikely(ret))
+ goto out;
+
+ sdio_writeb(func, 0, REG_Fn1_STATUS, &ret);
+ if (unlikely(ret))
+ goto out;
+
+out:
+ sdio_release_host(func);
+ return ret;
+
+}
+
+struct file *ssv6xxx_open_firmware(char *user_mainfw)
+{
+ struct file *fp;
+ fp = filp_open(user_mainfw, O_RDONLY, 0);
+
+ if (IS_ERR(fp))
+ fp = NULL;
+
+ return fp;
+}
+
+int ssv6xxx_read_fw_block(char *buf, int len, struct file *fp)
+{
+
+ int read;
+ loff_t pos;
+
+ pos = fp->f_pos;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
+ read = kernel_read(fp, (void *)buf, len, &pos);
+#else
+ read = kernel_read(fp, pos, buf, len);
+#endif
+
+ if (read > 0)
+ fp->f_pos += read;
+
+ return read;
+
+}
+
+void ssv6xxx_close_firmware(struct file *fp)
+{
+ if (fp)
+ filp_close(fp, NULL);
+}
+
+static int
+ssv6xxx_sdio_upload_firmware(struct device *child, const u8 *firmware, u32 firmware_length)
+{
+ int ret;
+ u32 clk_en;
+ u32 word_count, i;
+ u32 block_size;
+ u8 *buffer;
+ u32 sram_ptr = 0;
+ u32 block_count = 0;
+ u32 firmware_ptr = 0;
+
+ u32 checksum = FW_CHECKSUM_INIT;
+ u32 fw_checksum, fw_blkcnt;
+
+ struct ssv6xxx_sdio_glue *glue;
+
+ glue = dev_get_drvdata(child->parent);
+
+ if ((wlan_data.is_enabled == false) &&
+ (glue == NULL) &&
+ (glue->dev_ready == false))
+ goto out;
+
+ buffer = (u8 *)kzalloc(FW_BLOCK_SIZE, GFP_KERNEL);
+ if (buffer == NULL) {
+ dev_err(child, "Failed to allocate buffer for firmware.\n");
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ dev_dbg(child, "preparing registers and clock for firmware upload\n");
+
+ ret = ssv6xxx_sdio_write_reg(child, ADR_BRG_SW_RST, 0x0);
+ if (unlikely(ret))
+ goto out;
+
+ ret = ssv6xxx_sdio_write_reg(child, ADR_BOOT, 0x01);
+ if (unlikely(ret))
+ goto out;
+
+ ret = ssv6xxx_sdio_read_reg(child, ADR_PLATFORM_CLOCK_ENABLE, &clk_en);
+ if (unlikely(ret))
+ goto out;
+
+ ret = ssv6xxx_sdio_write_reg(child, ADR_PLATFORM_CLOCK_ENABLE, clk_en | (1 << 2));
+ if (unlikely(ret))
+ goto out;
+
+ dev_dbg(child, "begin writing firmware\n");
+
+ while (firmware_length > 0) {
+
+ memset(buffer, 0xA5, FW_BLOCK_SIZE);
+
+ block_size = firmware_length;
+ if (block_size > FW_BLOCK_SIZE)
+ block_size = FW_BLOCK_SIZE;
+
+ memcpy(buffer, &firmware[firmware_ptr], block_size);
+
+ firmware_ptr += block_size;
+ firmware_length -= block_size;
+
+ /*
+ * Uploading to chip sram and checksumming happens in chunks of CHECKSUM_BLOCK_SIZE,
+ * so we round the block size accordingly and use that valueù
+ */
+ block_size = DIV_ROUND_UP(block_size, CHECKSUM_BLOCK_SIZE) * CHECKSUM_BLOCK_SIZE;
+ ret = ssv6xxx_sdio_write_sram(child, sram_ptr, (u8 *)buffer, block_size);
+
+ if (ret) {
+ dev_err(child, "firmware upload failed\n");
+ goto out;
+ }
+
+ sram_ptr += block_size;
+
+ word_count = block_size / sizeof(u32);
+ for (i = 0; i < word_count; i++)
+ checksum += ((u32 *)buffer)[i];
+
+ }
+
+ checksum = ((checksum >> 24) +
+ (checksum >> 16) +
+ (checksum >> 8) +
+ checksum) & 0x0FF;
+ checksum <<= 16;
+
+ block_count = DIV_ROUND_UP(sram_ptr, CHECKSUM_BLOCK_SIZE);
+ ret = ssv6xxx_sdio_write_reg(child, FW_STATUS_REG, (block_count << 16));
+ if (unlikely(ret))
+ goto out;
+
+ ret = ssv6xxx_sdio_read_reg(child, FW_STATUS_REG, &fw_blkcnt);
+ if (unlikely(ret))
+ goto out;
+
+ ret = ssv6xxx_sdio_write_reg(child, ADR_BRG_SW_RST, 0x1);
+ if (unlikely(ret))
+ goto out;
+
+ dev_info(child, "firmware upload complete (wrote %d blocks, verified %d blocks)\n", block_count, fw_blkcnt >> 16);
+
+ msleep(50);
+
+ ret = ssv6xxx_sdio_read_reg(child, FW_STATUS_REG, &fw_checksum);
+ fw_checksum = fw_checksum & FW_STATUS_MASK;
+
+ if (fw_checksum == checksum) {
+ dev_dbg(child, "firmware check ok, checksum=0x%x\n", checksum);
+ ret = ssv6xxx_sdio_write_reg(child, FW_STATUS_REG, (~checksum & FW_STATUS_MASK));
+ if (unlikely(ret))
+ dev_warn(child, "could not clear checksum condition");
+ } else {
+ dev_err(child, "firmware checksum mismatch, local=0x%x, sram=0x%x\n", checksum, fw_checksum);
+ }
+
+ msleep(50);
+
+ ret = 0;
+
+ out:
+
+ if (buffer)
+ kfree(buffer);
+
+ return ret;
+
+}
+
+static int
+ssv6xxx_sdio_load_firmware(struct device *child, u8 *firmware_name, u8 openfile)
+{
+
+ int ret;
+ const struct firmware *firmware = NULL;
+ struct sdio_func *func;
+ struct ssv6xxx_sdio_glue *glue;
+
+ glue = dev_get_drvdata(child->parent);
+
+ ret = request_firmware(&firmware, firmware_name, glue->dev);
+
+ if (ret) {
+ dev_err(child, "could not find firmware file %s, err=%d\n", firmware_name, ret);
+ goto out;
+ }
+
+ ret = ssv6xxx_sdio_upload_firmware(child, firmware->data, firmware->size);
+
+ if (ret) {
+ dev_err(child, "could not upload firmware to device, err=%d\n", ret);
+ goto out;
+ }
+
+ if (glue != NULL) {
+ func = dev_to_sdio_func(glue->dev);
+ ssv6xxx_high_sdio_clk(func);
+ }
+
+out:
+ if (firmware != NULL)
+ release_firmware(firmware);
+
+ return ret;
+
+}
+
+static int ssv6xxx_sdio_irq_getstatus(struct device *child, int *status)
+{
+ int ret = (-1);
+ struct ssv6xxx_sdio_glue *glue;
+ struct sdio_func *func;
+ glue = dev_get_drvdata(child->parent);
+
+ ret_if_not_ready(-1);
+
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ *status = sdio_readb(func, REG_INT_STATUS, &ret);
+ sdio_release_host(func);
+
+ return ret;
+
+}
+
+static int __must_check
+ssv6xxx_sdio_read(struct device *child, void *buf, size_t *size)
+{
+
+ int ret;
+ u32 data_size;
+
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+
+ ret_if_not_ready(-1);
+
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+
+ data_size = sdio_readb(func, REG_CARD_PKT_LEN_0, &ret);
+
+ if (unlikely(ret)) {
+ dev_err(child->parent, "sdio read high byte len failed, ret=%d\n", ret);
+ goto out;
+ }
+
+ data_size = data_size | (sdio_readb(func, REG_CARD_PKT_LEN_1, &ret) << 0x8);
+
+ if (unlikely(ret)) {
+ dev_err(child->parent, "sdio read low len failed ret[%d]\n", ret);
+ goto out;
+ }
+
+ ret = sdio_memcpy_fromio(func, buf, glue->ioport_data, sdio_align_size(func, data_size));
+
+ if (unlikely(ret)) {
+ dev_err(child->parent, "sdio read failed size ret[%d]\n", ret);
+ goto out;
+ }
+
+ *size = data_size;
+
+out:
+
+ sdio_release_host(func);
+
+ return ret;
+}
+
+static int __must_check
+ssv6xxx_sdio_write(struct device *child, void *buf, size_t len, u8 queue_num)
+{
+ int ret;
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ void *ptr;
+
+ ret_if_not_ready(-1);
+
+#ifdef CONFIG_ARM64
+ if (((u64) buf) & 3) {
+#else
+ if (((u32) buf) & 3) {
+#endif
+ memcpy(glue->dma_skb->data, buf, len);
+ ptr = glue->dma_skb->data;
+ } else
+ ptr = buf;
+
+ func = dev_to_sdio_func(glue->dev);
+
+ sdio_claim_host(func);
+
+ len = sdio_align_size(func, len);
+ ret = sdio_memcpy_toio(func, glue->ioport_data, ptr, len);
+
+ if (unlikely(ret))
+ dev_err(glue->dev, "sdio write failed, ret=%d\n", ret);
+
+ sdio_release_host(func);
+
+ return ret;
+
+}
+
+static void ssv6xxx_sdio_irq_handler(struct sdio_func *func)
+{
+ int status;
+ struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+ struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+
+ ret_if_not_ready();
+
+ if (glue->irq_handler == NULL)
+ return;
+
+ atomic_set(&pwlan_data->irq_handling, 1);
+ sdio_release_host(func);
+ if (glue->irq_handler != NULL)
+ status = glue->irq_handler(0, glue->irq_dev);
+ sdio_claim_host(func);
+ atomic_set(&pwlan_data->irq_handling, 0);
+
+}
+
+static void ssv6xxx_sdio_irq_setmask(struct device *child, int mask)
+{
+ int err_ret;
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+
+ ret_if_not_ready();
+
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ sdio_writeb(func, mask, REG_INT_MASK, &err_ret);
+ sdio_release_host(func);
+
+}
+
+static void ssv6xxx_sdio_irq_trigger(struct device *child)
+{
+ int err_ret;
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+
+ ret_if_not_ready();
+
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ sdio_writeb(func, 0x2, REG_INT_TRIGGER, &err_ret);
+ sdio_release_host(func);
+
+}
+
+static int ssv6xxx_sdio_irq_getmask(struct device *child, u32 * mask)
+{
+ u8 imask = 0;
+ int ret = (-1);
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+
+ ret_if_not_ready(-1);
+
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ imask = sdio_readb(func, REG_INT_MASK, &ret);
+ *mask = imask;
+ sdio_release_host(func);
+
+ return ret;
+
+}
+
+static void ssv6xxx_sdio_irq_enable(struct device *child)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ int ret;
+ struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+ if ((pwlan_data->is_enabled == false)
+ || (glue == NULL) || (glue->dev_ready == false))
+ return;
+
+ func = dev_to_sdio_func(glue->dev);
+ sdio_claim_host(func);
+ ret = sdio_claim_irq(func, ssv6xxx_sdio_irq_handler);
+ if (ret)
+ dev_err(child->parent, "Failed to claim sdio irq: %d\n",
+ ret);
+ sdio_release_host(func);
+
+ dev_dbg(child, "ssv6xxx_sdio_irq_enable\n");
+
+}
+
+static void ssv6xxx_sdio_irq_disable(struct device *child, bool iswaitirq)
+{
+ struct ssv6xxx_sdio_glue *glue = NULL;
+ struct sdio_func *func;
+ struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+ int ret;
+
+ dev_dbg(child, "ssv6xxx_sdio_irq_disable\n");
+
+ if ((wlan_data.is_enabled == false) || (child->parent == NULL))
+ return;
+
+ glue = dev_get_drvdata(child->parent);
+
+
+ if ((glue == NULL) || (glue->dev_ready == false)
+ || (glue->dev == NULL))
+ return;
+
+ func = dev_to_sdio_func(glue->dev);
+
+ if (func == NULL) {
+ dev_dbg(child, "sdio func == NULL\n");
+ return;
+ }
+
+ sdio_claim_host(func);
+ while (atomic_read(&pwlan_data->irq_handling)) {
+ sdio_release_host(func);
+ schedule_timeout(HZ / 10);
+ sdio_claim_host(func);
+ }
+ ret = sdio_release_irq(func);
+
+ if (ret)
+ dev_err(child->parent,
+ "Failed to release sdio irq: %d\n", ret);
+
+ sdio_release_host(func);
+
+}
+
+static void
+ssv6xxx_sdio_irq_request(struct device *child, irq_handler_t irq_handler,
+ void *irq_dev)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ bool isIrqEn = false;
+
+ ret_if_not_ready();
+
+ func = dev_to_sdio_func(glue->dev);
+ glue->irq_handler = irq_handler;
+ glue->irq_dev = irq_dev;
+ if (isIrqEn) {
+ ssv6xxx_sdio_irq_enable(child);
+ }
+
+}
+
+static void
+ssv6xxx_sdio_read_parameter(struct sdio_func *func,
+ struct ssv6xxx_sdio_glue *glue)
+{
+ int err_ret;
+ sdio_claim_host(func);
+ glue->ioport_data = 0;
+ glue->ioport_data =
+ glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_0, &err_ret)
+ << (8 * 0));
+ glue->ioport_data =
+ glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_1, &err_ret)
+ << (8 * 1));
+ glue->ioport_data =
+ glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_2, &err_ret)
+ << (8 * 2));
+ glue->ioport_reg = 0;
+ glue->ioport_reg =
+ glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_0, &err_ret) <<
+ (8 * 0));
+ glue->ioport_reg =
+ glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_1, &err_ret) <<
+ (8 * 1));
+ glue->ioport_reg =
+ glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_2, &err_ret) <<
+ (8 * 2));
+ dev_dbg(&func->dev, "ioport_data=0x%x ioport_reg=0x%x\n",
+ glue->ioport_data, glue->ioport_reg);
+ err_ret = sdio_set_block_size(func, CONFIG_PLATFORM_SDIO_BLOCK_SIZE);
+ if (err_ret != 0) {
+ dev_warn(&func->dev, "SDIO setting SDIO_DEF_BLOCK_SIZE fail!!\n");
+ }
+ sdio_writeb(func, CONFIG_PLATFORM_SDIO_OUTPUT_TIMING,
+ REG_OUTPUT_TIMING_REG, &err_ret);
+ sdio_writeb(func, 0x00, REG_Fn1_STATUS, &err_ret);
+ sdio_release_host(func);
+}
+
+static void ssv6xxx_do_sdio_wakeup(struct sdio_func *func)
+{
+ int err_ret;
+ if (func != NULL) {
+ sdio_claim_host(func);
+ sdio_writeb(func, 0x01, REG_PMU_WAKEUP, &err_ret);
+ mdelay(10);
+ sdio_writeb(func, 0x00, REG_PMU_WAKEUP, &err_ret);
+ sdio_release_host(func);
+ }
+}
+
+static void ssv6xxx_sdio_pmu_wakeup(struct device *child)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ if (glue != NULL) {
+ func = dev_to_sdio_func(glue->dev);
+ ssv6xxx_do_sdio_wakeup(func);
+ }
+}
+
+static bool ssv6xxx_sdio_support_scatter(struct device *child)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+
+ if (!glue) {
+ dev_err(child->parent, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
+ return false;
+ }
+
+ func = dev_to_sdio_func(glue->dev);
+
+ if (func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
+ dev_err(child->parent,
+ "host controller only supports scatter of :%d entries, driver need: %d\n",
+ func->card->host->max_segs,
+ MAX_SCATTER_ENTRIES_PER_REQ);
+ return false;
+ }
+
+ return true;
+
+}
+
+static void
+ssv6xxx_sdio_setup_scat_data(struct sdio_scatter_req *scat_req,
+ struct mmc_data *data)
+{
+ struct scatterlist *sg;
+ int i;
+ data->blksz = SDIO_DEF_BLOCK_SIZE;
+ data->blocks = scat_req->len / SDIO_DEF_BLOCK_SIZE;
+ pr_debug
+ ("scatter: (%s) (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
+ (scat_req->req & SDIO_WRITE) ? "WR" : "RD", data->blksz,
+ data->blocks, scat_req->len, scat_req->scat_entries);
+ data->flags =
+ (scat_req->req & SDIO_WRITE) ? MMC_DATA_WRITE : MMC_DATA_READ;
+ sg = scat_req->sgentries;
+ sg_init_table(sg, scat_req->scat_entries);
+ for (i = 0; i < scat_req->scat_entries; i++, sg++) {
+ pr_debug("%d: addr:0x%p, len:%d\n",
+ i, scat_req->scat_list[i].buf,
+ scat_req->scat_list[i].len);
+ sg_set_buf(sg, scat_req->scat_list[i].buf,
+ scat_req->scat_list[i].len);
+ }
+ data->sg = scat_req->sgentries;
+ data->sg_len = scat_req->scat_entries;
+}
+
+static inline void
+ssv6xxx_sdio_set_cmd53_arg(u32 * arg, u8 rw, u8 func,
+ u8 mode, u8 opcode, u32 addr, u16 blksz)
+{
+ *arg = (((rw & 1) << 31) |
+ ((func & 0x7) << 28) |
+ ((mode & 1) << 27) |
+ ((opcode & 1) << 26) | ((addr & 0x1FFFF) << 9) | (blksz &
+ 0x1FF));
+}
+
+static int
+ssv6xxx_sdio_rw_scatter(struct device *child, struct sdio_scatter_req *scat_req)
+{
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func;
+ struct mmc_request mmc_req;
+ struct mmc_command cmd;
+ struct mmc_data data;
+ u8 opcode, rw;
+ int status = 1;
+
+ if (!glue) {
+ dev_err(child->parent, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
+ return 1;
+ }
+
+ func = dev_to_sdio_func(glue->dev);
+ memset(&mmc_req, 0, sizeof(struct mmc_request));
+ memset(&cmd, 0, sizeof(struct mmc_command));
+ memset(&data, 0, sizeof(struct mmc_data));
+ ssv6xxx_sdio_setup_scat_data(scat_req, &data);
+ opcode = 0;
+ rw = (scat_req->req & SDIO_WRITE) ? CMD53_ARG_WRITE :
+ CMD53_ARG_READ;
+ ssv6xxx_sdio_set_cmd53_arg(&cmd.arg, rw, func->num,
+ CMD53_ARG_BLOCK_BASIS, opcode,
+ glue->ioport_data, data.blocks);
+ cmd.opcode = SD_IO_RW_EXTENDED;
+ cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
+ mmc_req.cmd = &cmd;
+ mmc_req.data = &data;
+ mmc_set_data_timeout(&data, func->card);
+ mmc_wait_for_req(func->card->host, &mmc_req);
+
+ status = cmd.error ? cmd.error : data.error;
+
+ if (cmd.error)
+ return cmd.error;
+
+ if (data.error)
+ return data.error;
+
+ return status;
+
+}
+
+static void ssv6xxx_set_sdio_clk(struct sdio_func *func, u32 sdio_hz)
+{
+ struct mmc_host *host;
+ host = func->card->host;
+ if (sdio_hz < host->f_min)
+ sdio_hz = host->f_min;
+ else if (sdio_hz > host->f_max)
+ sdio_hz = host->f_max;
+ dev_dbg(&func->dev, "%s:set sdio clk %dHz\n", __FUNCTION__, sdio_hz);
+ sdio_claim_host(func);
+ host->ios.clock = sdio_hz;
+ host->ops->set_ios(host, &host->ios);
+ mdelay(20);
+ sdio_release_host(func);
+}
+
+static void ssv6xxx_low_sdio_clk(struct sdio_func *func)
+{
+ ssv6xxx_set_sdio_clk(func, LOW_SPEED_SDIO_CLOCK);
+}
+
+static void ssv6xxx_high_sdio_clk(struct sdio_func *func)
+{
+#ifndef SDIO_USE_SLOW_CLOCK
+ ssv6xxx_set_sdio_clk(func, HIGH_SPEED_SDIO_CLOCK);
+#endif
+}
+
+static struct ssv6xxx_hwif_ops sdio_ops = {
+ .read = ssv6xxx_sdio_read,
+ .write = ssv6xxx_sdio_write,
+ .readreg = ssv6xxx_sdio_read_reg,
+ .writereg = ssv6xxx_sdio_write_reg,
+#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+ .trigger_tx_rx = ssv6xxx_sdio_trigger_tx_rx,
+#endif
+ .irq_getmask = ssv6xxx_sdio_irq_getmask,
+ .irq_setmask = ssv6xxx_sdio_irq_setmask,
+ .irq_enable = ssv6xxx_sdio_irq_enable,
+ .irq_disable = ssv6xxx_sdio_irq_disable,
+ .irq_getstatus = ssv6xxx_sdio_irq_getstatus,
+ .irq_request = ssv6xxx_sdio_irq_request,
+ .irq_trigger = ssv6xxx_sdio_irq_trigger,
+ .pmu_wakeup = ssv6xxx_sdio_pmu_wakeup,
+ .load_fw = ssv6xxx_sdio_load_firmware,
+ .cmd52_read = ssv6xxx_sdio_cmd52_read,
+ .cmd52_write = ssv6xxx_sdio_cmd52_write,
+ .support_scatter = ssv6xxx_sdio_support_scatter,
+ .rw_scatter = ssv6xxx_sdio_rw_scatter,
+ .is_ready = ssv6xxx_is_ready,
+ .write_sram = ssv6xxx_sdio_write_sram,
+ .interface_reset = ssv6xxx_sdio_reset,
+};
+
+static int
+ssv6xxx_sdio_power_on(struct ssv6xxx_platform_data *pdata,
+ struct sdio_func *func)
+{
+ int ret = 0;
+ if (pdata->is_enabled == true)
+ return 0;
+
+ dev_dbg(&func->dev, "ssv6xxx_sdio_power_on\n");
+
+ sdio_claim_host(func);
+ ret = sdio_enable_func(func);
+ sdio_release_host(func);
+
+ if (ret) {
+ dev_err(&func->dev, "Unable to enable sdio func: %d)\n", ret);
+ return ret;
+ }
+
+ msleep(10);
+ pdata->is_enabled = true;
+
+ return ret;
+}
+
+static int
+ssv6xxx_sdio_power_off(struct ssv6xxx_platform_data *pdata,
+ struct sdio_func *func)
+{
+ int ret;
+ if (pdata->is_enabled == false)
+ return 0;
+ dev_dbg(&func->dev, "ssv6xxx_sdio_power_off\n");
+ sdio_claim_host(func);
+ ret = sdio_disable_func(func);
+ sdio_release_host(func);
+ if (ret)
+ return ret;
+ pdata->is_enabled = false;
+ return ret;
+}
+
+int ssv6xxx_get_dev_status(void)
+{
+ return ssv6xxx_sdio_status;
+}
+
+EXPORT_SYMBOL(ssv6xxx_get_dev_status);
+
+static int
+ssv6xxx_sdio_probe(struct sdio_func *func, const struct sdio_device_id *id)
+{
+ struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+ struct ssv6xxx_sdio_glue *glue;
+ int ret;
+ const char *chip_family = "ssv6200";
+
+ if (ssv_devicetype != 0) {
+ dev_info(&func->dev, "Not using SSV6200 normal SDIO driver.\n");
+ return -ENODEV;
+ }
+
+ if (func->num != 0x01)
+ return -ENODEV;
+
+ glue = kzalloc(sizeof(*glue), GFP_KERNEL);
+
+ if (!glue) {
+ dev_err(&func->dev, "can't allocate glue\n");
+ return -ENOMEM;
+ }
+
+ ssv6xxx_sdio_status = 1;
+ ssv6xxx_low_sdio_clk(func);
+
+ glue->dma_skb = __dev_alloc_skb(SDIO_DMA_BUFFER_LEN, GFP_KERNEL);
+
+#ifdef CONFIG_PM
+ glue->cmd_skb = __dev_alloc_skb(SDIO_COMMAND_BUFFER_LEN, GFP_KERNEL);
+#endif
+ memset(pwlan_data, 0, sizeof(struct ssv6xxx_platform_data));
+ atomic_set(&pwlan_data->irq_handling, 0);
+ glue->dev = &func->dev;
+ func->card->quirks |= MMC_QUIRK_LENIENT_FN0;
+ func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
+ glue->dev_ready = true;
+ pwlan_data->vendor = func->vendor;
+ pwlan_data->device = func->device;
+ dev_info(glue->dev, "device id: %x:%x\n", pwlan_data->vendor,
+ pwlan_data->device);
+ pwlan_data->ops = &sdio_ops;
+ sdio_set_drvdata(func, glue);
+#ifdef CONFIG_PM
+ ssv6xxx_do_sdio_wakeup(func);
+#endif
+ ssv6xxx_sdio_power_on(pwlan_data, func);
+ ssv6xxx_sdio_read_parameter(func, glue);
+ glue->core = platform_device_alloc(chip_family, -1);
+
+ if (!glue->core) {
+ dev_err(glue->dev, "can't allocate platform_device");
+ ret = -ENOMEM;
+ goto out_free_glue;
+ }
+
+ glue->core->dev.parent = &func->dev;
+
+ ret = platform_device_add_data(glue->core, pwlan_data,
+ sizeof(*pwlan_data));
+
+ if (ret) {
+ dev_err(glue->dev, "can't add platform data\n");
+ goto out_dev_put;
+ }
+
+ ret = platform_device_add(glue->core);
+
+ if (ret) {
+ dev_err(glue->dev, "can't add platform device\n");
+ goto out_dev_put;
+ }
+
+ ssv6xxx_sdio_irq_setmask(&glue->core->dev, 0xff);
+
+ ssv6xxx_ifdebug_info[0] = (void *)&glue->core->dev;
+ ssv6xxx_ifdebug_info[1] = (void *)glue->core;
+ ssv6xxx_ifdebug_info[2] = (void *)&sdio_ops;
+ return 0;
+
+ out_dev_put:
+ platform_device_put(glue->core);
+ out_free_glue:
+ kfree(glue);
+
+ return ret;
+
+}
+
+static void ssv6xxx_sdio_remove(struct sdio_func *func)
+{
+ struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+ struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+
+ dev_dbg(&func->dev, "ssv6xxx_sdio_remove enter\n");
+
+ ssv6xxx_sdio_status = 0;
+
+ if (glue) {
+ dev_dbg(&func->dev, "ssv6xxx_sdio_remove - ssv6xxx_sdio_irq_disable\n");
+ ssv6xxx_sdio_irq_disable(&glue->core->dev, false);
+ glue->dev_ready = false;
+ ssv6xxx_low_sdio_clk(func);
+
+ if (glue->dma_skb != NULL)
+ dev_kfree_skb(glue->dma_skb);
+
+ dev_dbg(&func->dev, "ssv6xxx_sdio_remove - disable mask\n");
+ ssv6xxx_sdio_irq_setmask(&glue->core->dev, 0xff);
+#ifdef CONFIG_PM
+ ssv6xxx_sdio_trigger_pmu(glue->dev);
+ if (glue->cmd_skb != NULL)
+ dev_kfree_skb(glue->cmd_skb);
+#endif
+ ssv6xxx_sdio_power_off(pwlan_data, func);
+ dev_dbg(&func->dev, "platform_device_del \n");
+ platform_device_del(glue->core);
+ dev_dbg(&func->dev, "platform_device_put \n");
+ platform_device_put(glue->core);
+ kfree(glue);
+ }
+
+ sdio_set_drvdata(func, NULL);
+ dev_dbg(&func->dev, "ssv6xxx_sdio_remove leave\n");
+
+}
+
+static int ssv6xxx_sdio_trigger_pmu(struct device *dev)
+{
+
+ int ret = 0;
+
+#ifdef CONFIG_PM
+ struct sdio_func *func = dev_to_sdio_func(dev);
+ struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+ struct cfg_host_cmd *host_cmd;
+ int writesize;
+ void *tempPointer;
+
+ if (ssv6xxx_sdio_write_reg
+ (dev, ADR_RX_FLOW_MNG, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
+ if (ssv6xxx_sdio_write_reg
+ (dev, ADR_RX_FLOW_DATA, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
+ if (ssv6xxx_sdio_write_reg
+ (dev, ADR_RX_FLOW_CTRL, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
+
+ host_cmd = (struct cfg_host_cmd *)glue->cmd_skb->data;
+ host_cmd->c_type = HOST_CMD;
+ host_cmd->RSVD0 = 0;
+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_PS;
+ host_cmd->len = sizeof(struct cfg_host_cmd);
+
+ host_cmd->dummy = 0;
+
+ {
+ tempPointer = glue->cmd_skb->data;
+ sdio_claim_host(func);
+ writesize = sdio_align_size(func, sizeof(struct cfg_host_cmd));
+ do {
+ ret =
+ sdio_memcpy_toio(func, glue->ioport_data,
+ tempPointer, writesize);
+ if (ret == -EILSEQ || ret == -ETIMEDOUT) {
+ ret = -1;
+ break;
+ } else {
+ if (ret)
+ dev_err(glue->dev,
+ "Unexpected return value ret=[%d]\n",
+ ret);
+ }
+ }
+ while (ret == -EILSEQ || ret == -ETIMEDOUT);
+ sdio_release_host(func);
+ if (ret)
+ dev_err(glue->dev, "sdio write failed (%d)\n", ret);
+ }
+
+#endif
+
+ return ret;
+
+}
+
+static void ssv6xxx_sdio_reset(struct device *child)
+{
+
+#ifdef CONFIG_PM
+ struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+ struct sdio_func *func = dev_to_sdio_func(glue->dev);
+ dev_dbg(child, "%s\n", __FUNCTION__);
+ if (glue == NULL || glue->dev == NULL || func == NULL)
+ return;
+ ssv6xxx_sdio_trigger_pmu(glue->dev);
+ ssv6xxx_do_sdio_wakeup(func);
+#endif
+
+ return;
+
+}
+
+#ifdef CONFIG_PM
+static int ssv6xxx_sdio_suspend(struct device *dev)
+{
+ struct sdio_func *func = dev_to_sdio_func(dev);
+ mmc_pm_flag_t flags = sdio_get_host_pm_caps(func);
+ {
+ int ret = 0;
+ dev_info(dev, "%s: suspend: PM flags = 0x%x\n",
+ sdio_func_id(func), flags);
+ ssv6xxx_low_sdio_clk(func);
+ ret = ssv6xxx_sdio_trigger_pmu(dev);
+ if (ret)
+ dev_warn(dev, "ssv6xxx_sdio_trigger_pmu fail!!\n");
+ if (!(flags & MMC_PM_KEEP_POWER)) {
+ dev_err(dev,
+ "%s: cannot remain alive while host is suspended\n",
+ sdio_func_id(func));
+ }
+ ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
+ if (ret)
+ return ret;
+ mdelay(10);
+ return ret;
+ }
+}
+
+static int ssv6xxx_sdio_resume(struct device *dev)
+{
+ struct sdio_func *func = dev_to_sdio_func(dev);
+ {
+ dev_dbg(dev, "ssv6xxx_sdio_resume\n");
+ {
+ ssv6xxx_do_sdio_wakeup(func);
+ mdelay(10);
+ ssv6xxx_high_sdio_clk(func);
+ mdelay(10);
+ }
+ }
+ return 0;
+}
+
+static const struct dev_pm_ops ssv6xxx_sdio_pm_ops = {
+ .suspend = ssv6xxx_sdio_suspend,
+ .resume = ssv6xxx_sdio_resume,
+};
+#endif
+
+struct sdio_driver ssv6xxx_sdio_driver = {
+ .name = "ssv6051",
+ .id_table = ssv6xxx_sdio_devices,
+ .probe = ssv6xxx_sdio_probe,
+ .remove = ssv6xxx_sdio_remove,
+#ifdef CONFIG_PM
+ .drv = {
+ .pm = &ssv6xxx_sdio_pm_ops,
+ },
+#endif
+};
+
+EXPORT_SYMBOL(ssv6xxx_sdio_driver);
+
+int ssv6xxx_sdio_init(void)
+{
+ return sdio_register_driver(&ssv6xxx_sdio_driver);
+}
+
+void ssv6xxx_sdio_exit(void)
+{
+ pr_info("ssv6xxx_sdio_exit\n");
+ sdio_unregister_driver(&ssv6xxx_sdio_driver);
+}
+
+EXPORT_SYMBOL(ssv6xxx_sdio_init);
+EXPORT_SYMBOL(ssv6xxx_sdio_exit);
diff --git a/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h b/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
new file mode 100644
index 000000000000..57aefd3bf9fa
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SDIO_DEF_H_
+#define _SDIO_DEF_H_
+#include <linux/scatterlist.h>
+#define BASE_SDIO 0
+#define REG_DATA_IO_PORT_0 (BASE_SDIO + 0x00)
+#define REG_DATA_IO_PORT_1 (BASE_SDIO + 0x01)
+#define REG_DATA_IO_PORT_2 (BASE_SDIO + 0x02)
+#define REG_INT_MASK (BASE_SDIO + 0x04)
+#define REG_INT_STATUS (BASE_SDIO + 0x08)
+#define REG_INT_TRIGGER (BASE_SDIO + 0x09)
+#define REG_Fn1_STATUS (BASE_SDIO + 0x0c)
+#define REG_CARD_PKT_LEN_0 (BASE_SDIO + 0x10)
+#define REG_CARD_PKT_LEN_1 (BASE_SDIO + 0x11)
+#define REG_CARD_FW_DL_STATUS (BASE_SDIO + 0x12)
+#define REG_CARD_SELF_TEST (BASE_SDIO + 0x13)
+#define REG_CARD_RCA_0 (BASE_SDIO + 0x20)
+#define REG_CARD_RCA_1 (BASE_SDIO + 0x21)
+#define REG_SDIO_FIFO_WR_THLD_0 (BASE_SDIO + 0x24)
+#define REG_SDIO_FIFO_WR_THLD_1 (BASE_SDIO + 0x25)
+#define REG_OUTPUT_TIMING_REG (BASE_SDIO + 0x55)
+#define REG_PMU_WAKEUP (BASE_SDIO + 0x67)
+#define REG_REG_IO_PORT_0 (BASE_SDIO + 0x70)
+#define REG_REG_IO_PORT_1 (BASE_SDIO + 0x71)
+#define REG_REG_IO_PORT_2 (BASE_SDIO + 0x72)
+#define REG_SDIO_TX_ALLOC_SIZE (BASE_SDIO + 0x98)
+#define REG_SDIO_TX_ALLOC_SHIFT (BASE_SDIO + 0x99)
+#define REG_SDIO_TX_ALLOC_STATE (BASE_SDIO + 0x9a)
+#define REG_SDIO_TX_INFORM_0 (BASE_SDIO + 0x9c)
+#define REG_SDIO_TX_INFORM_1 (BASE_SDIO + 0x9d)
+#define REG_SDIO_TX_INFORM_2 (BASE_SDIO + 0x9e)
+#define SDIO_DEF_BLOCK_SIZE 0x80
+#if (SDIO_DEF_BLOCK_SIZE % 8)
+#error Wrong SDIO_DEF_BLOCK_SIZE value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
+#endif
+#define SDIO_DEF_OUTPUT_TIMING 0
+#define SDIO_DEF_BLOCK_MODE_THRD 128
+#if (SDIO_DEF_BLOCK_MODE_THRD % 8)
+#error Wrong SDIO_DEF_BLOCK_MODE_THRD value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
+#endif
+#define SDIO_DEF_FORCE_BLOCK_MODE 0
+#define MAX_SCATTER_ENTRIES_PER_REQ 8
+struct sdio_scatter_item {
+ u8 *buf;
+ int len;
+};
+struct sdio_scatter_req {
+ u32 req;
+ u32 len;
+ int scat_entries;
+ struct sdio_scatter_item scat_list[MAX_SCATTER_ENTRIES_PER_REQ];
+ struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
+};
+#define SDIO_READ 0x00000001
+#define SDIO_WRITE 0x00000002
+#define CMD53_ARG_READ 0
+#define CMD53_ARG_WRITE 1
+#define CMD53_ARG_BLOCK_BASIS 1
+#define CMD53_ARG_FIXED_ADDRESS 0
+#define CMD53_ARG_INCR_ADDRESS 1
+#define SDIO_DMA_BUFFER_LEN 2048
+#ifdef CONFIG_PM
+#define SDIO_COMMAND_BUFFER_LEN 256
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/cabrio.h b/drivers/net/wireless/ssv6051/include/cabrio.h
new file mode 100644
index 000000000000..0b1327865c6b
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/cabrio.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CABRIO_H
+#define CABRIO_H
+#define SSV_VENDOR_ID 0x3030
+#define SSV_CABRIO_DEVID 0x3030
+#define SSV_SUBVENDOR_ID_NOG 0x0e11
+#define SSV_SUBVENDOR_ID_NEW_A 0x7065
+#define SSV_CABRIO_MAGIC 0x19641014
+#define SSV_AMPDU_LIMIT_MAX (64 * 1024 - 1)
+#define SSV_DEFAULT_NOISE_FLOOR -95
+#define SSVCABRIO_RSSI_BAD -128
+#define SSVCABRIO_NUM_CHANNELS 38
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200.h b/drivers/net/wireless/ssv6051/include/ssv6200.h
new file mode 100644
index 000000000000..22eaceaf285d
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV6200_H_
+#define _SSV6200_H_
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <net/mac80211.h>
+#ifdef ECLIPSE
+#include <ssv_mod_conf.h>
+#endif
+#include <ssv6200_reg.h>
+#include <ssv6200_aux.h>
+#include <hwif/hwif.h>
+#include <hci/ssv_hci.h>
+#include "ssv6200_common.h"
+#define SSV6200_TOTAL_ID 128
+#ifndef HUW_DRV
+#define SSV6200_ID_TX_THRESHOLD 19
+#define SSV6200_ID_RX_THRESHOLD 60
+#define SSV6200_PAGE_TX_THRESHOLD 115
+#define SSV6200_PAGE_RX_THRESHOLD 115
+#define SSV6XXX_AMPDU_DIVIDER (2)
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD - (SSV6200_PAGE_TX_THRESHOLD/SSV6XXX_AMPDU_DIVIDER))
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#else
+#undef SSV6200_ID_TX_THRESHOLD
+#undef SSV6200_ID_RX_THRESHOLD
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER
+#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER
+#define SSV6200_ID_TX_THRESHOLD 31
+#define SSV6200_ID_RX_THRESHOLD 31
+#define SSV6200_PAGE_TX_THRESHOLD 61
+#define SSV6200_PAGE_RX_THRESHOLD 61
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER 45
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#endif
+#define SSV6200_ID_NUMBER (128)
+#define PACKET_ADDR_2_ID(addr) ((addr >> 16) & 0x7F)
+#define SSV6200_ID_AC_RESERVED 1
+#define SSV6200_ID_AC_BK_OUT_QUEUE 8
+#define SSV6200_ID_AC_BE_OUT_QUEUE 15
+#define SSV6200_ID_AC_VI_OUT_QUEUE 16
+#define SSV6200_ID_AC_VO_OUT_QUEUE 16
+#define SSV6200_ID_MANAGER_QUEUE 8
+#define HW_MMU_PAGE_SHIFT 0x8
+#define HW_MMU_PAGE_MASK 0xff
+#define SSV6200_BT_PRI_SMP_TIME 0
+#define SSV6200_BT_STA_SMP_TIME (SSV6200_BT_PRI_SMP_TIME+0)
+#define SSV6200_WLAN_REMAIN_TIME 0
+#define BT_2WIRE_EN_MSK 0x00000400
+struct txResourceControl {
+ u32 txUsePage:8;
+ u32 txUseID:6;
+ u32 edca0:4;
+ u32 edca1:4;
+ u32 edca2:5;
+ u32 edca3:5;
+};
+#include <ssv_cfg.h>
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_aux.h b/drivers/net/wireless/ssv6051/include/ssv6200_aux.h
new file mode 100644
index 000000000000..03ec3f07d330
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_aux.h
@@ -0,0 +1,18221 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define MCU_ENABLE_MSK 0x00000001
+#define MCU_ENABLE_I_MSK 0xfffffffe
+#define MCU_ENABLE_SFT 0
+#define MCU_ENABLE_HI 0
+#define MCU_ENABLE_SZ 1
+#define MAC_SW_RST_MSK 0x00000002
+#define MAC_SW_RST_I_MSK 0xfffffffd
+#define MAC_SW_RST_SFT 1
+#define MAC_SW_RST_HI 1
+#define MAC_SW_RST_SZ 1
+#define MCU_SW_RST_MSK 0x00000004
+#define MCU_SW_RST_I_MSK 0xfffffffb
+#define MCU_SW_RST_SFT 2
+#define MCU_SW_RST_HI 2
+#define MCU_SW_RST_SZ 1
+#define SDIO_SW_RST_MSK 0x00000008
+#define SDIO_SW_RST_I_MSK 0xfffffff7
+#define SDIO_SW_RST_SFT 3
+#define SDIO_SW_RST_HI 3
+#define SDIO_SW_RST_SZ 1
+#define SPI_SLV_SW_RST_MSK 0x00000010
+#define SPI_SLV_SW_RST_I_MSK 0xffffffef
+#define SPI_SLV_SW_RST_SFT 4
+#define SPI_SLV_SW_RST_HI 4
+#define SPI_SLV_SW_RST_SZ 1
+#define UART_SW_RST_MSK 0x00000020
+#define UART_SW_RST_I_MSK 0xffffffdf
+#define UART_SW_RST_SFT 5
+#define UART_SW_RST_HI 5
+#define UART_SW_RST_SZ 1
+#define DMA_SW_RST_MSK 0x00000040
+#define DMA_SW_RST_I_MSK 0xffffffbf
+#define DMA_SW_RST_SFT 6
+#define DMA_SW_RST_HI 6
+#define DMA_SW_RST_SZ 1
+#define WDT_SW_RST_MSK 0x00000080
+#define WDT_SW_RST_I_MSK 0xffffff7f
+#define WDT_SW_RST_SFT 7
+#define WDT_SW_RST_HI 7
+#define WDT_SW_RST_SZ 1
+#define I2C_SLV_SW_RST_MSK 0x00000100
+#define I2C_SLV_SW_RST_I_MSK 0xfffffeff
+#define I2C_SLV_SW_RST_SFT 8
+#define I2C_SLV_SW_RST_HI 8
+#define I2C_SLV_SW_RST_SZ 1
+#define INT_CTL_SW_RST_MSK 0x00000200
+#define INT_CTL_SW_RST_I_MSK 0xfffffdff
+#define INT_CTL_SW_RST_SFT 9
+#define INT_CTL_SW_RST_HI 9
+#define INT_CTL_SW_RST_SZ 1
+#define BTCX_SW_RST_MSK 0x00000400
+#define BTCX_SW_RST_I_MSK 0xfffffbff
+#define BTCX_SW_RST_SFT 10
+#define BTCX_SW_RST_HI 10
+#define BTCX_SW_RST_SZ 1
+#define GPIO_SW_RST_MSK 0x00000800
+#define GPIO_SW_RST_I_MSK 0xfffff7ff
+#define GPIO_SW_RST_SFT 11
+#define GPIO_SW_RST_HI 11
+#define GPIO_SW_RST_SZ 1
+#define US0TMR_SW_RST_MSK 0x00001000
+#define US0TMR_SW_RST_I_MSK 0xffffefff
+#define US0TMR_SW_RST_SFT 12
+#define US0TMR_SW_RST_HI 12
+#define US0TMR_SW_RST_SZ 1
+#define US1TMR_SW_RST_MSK 0x00002000
+#define US1TMR_SW_RST_I_MSK 0xffffdfff
+#define US1TMR_SW_RST_SFT 13
+#define US1TMR_SW_RST_HI 13
+#define US1TMR_SW_RST_SZ 1
+#define US2TMR_SW_RST_MSK 0x00004000
+#define US2TMR_SW_RST_I_MSK 0xffffbfff
+#define US2TMR_SW_RST_SFT 14
+#define US2TMR_SW_RST_HI 14
+#define US2TMR_SW_RST_SZ 1
+#define US3TMR_SW_RST_MSK 0x00008000
+#define US3TMR_SW_RST_I_MSK 0xffff7fff
+#define US3TMR_SW_RST_SFT 15
+#define US3TMR_SW_RST_HI 15
+#define US3TMR_SW_RST_SZ 1
+#define MS0TMR_SW_RST_MSK 0x00010000
+#define MS0TMR_SW_RST_I_MSK 0xfffeffff
+#define MS0TMR_SW_RST_SFT 16
+#define MS0TMR_SW_RST_HI 16
+#define MS0TMR_SW_RST_SZ 1
+#define MS1TMR_SW_RST_MSK 0x00020000
+#define MS1TMR_SW_RST_I_MSK 0xfffdffff
+#define MS1TMR_SW_RST_SFT 17
+#define MS1TMR_SW_RST_HI 17
+#define MS1TMR_SW_RST_SZ 1
+#define MS2TMR_SW_RST_MSK 0x00040000
+#define MS2TMR_SW_RST_I_MSK 0xfffbffff
+#define MS2TMR_SW_RST_SFT 18
+#define MS2TMR_SW_RST_HI 18
+#define MS2TMR_SW_RST_SZ 1
+#define MS3TMR_SW_RST_MSK 0x00080000
+#define MS3TMR_SW_RST_I_MSK 0xfff7ffff
+#define MS3TMR_SW_RST_SFT 19
+#define MS3TMR_SW_RST_HI 19
+#define MS3TMR_SW_RST_SZ 1
+#define RF_BB_SW_RST_MSK 0x00100000
+#define RF_BB_SW_RST_I_MSK 0xffefffff
+#define RF_BB_SW_RST_SFT 20
+#define RF_BB_SW_RST_HI 20
+#define RF_BB_SW_RST_SZ 1
+#define SYS_ALL_RST_MSK 0x00200000
+#define SYS_ALL_RST_I_MSK 0xffdfffff
+#define SYS_ALL_RST_SFT 21
+#define SYS_ALL_RST_HI 21
+#define SYS_ALL_RST_SZ 1
+#define DAT_UART_SW_RST_MSK 0x00400000
+#define DAT_UART_SW_RST_I_MSK 0xffbfffff
+#define DAT_UART_SW_RST_SFT 22
+#define DAT_UART_SW_RST_HI 22
+#define DAT_UART_SW_RST_SZ 1
+#define I2C_MST_SW_RST_MSK 0x00800000
+#define I2C_MST_SW_RST_I_MSK 0xff7fffff
+#define I2C_MST_SW_RST_SFT 23
+#define I2C_MST_SW_RST_HI 23
+#define I2C_MST_SW_RST_SZ 1
+#define RG_REBOOT_MSK 0x00000001
+#define RG_REBOOT_I_MSK 0xfffffffe
+#define RG_REBOOT_SFT 0
+#define RG_REBOOT_HI 0
+#define RG_REBOOT_SZ 1
+#define TRAP_IMG_FLS_MSK 0x00010000
+#define TRAP_IMG_FLS_I_MSK 0xfffeffff
+#define TRAP_IMG_FLS_SFT 16
+#define TRAP_IMG_FLS_HI 16
+#define TRAP_IMG_FLS_SZ 1
+#define TRAP_REBOOT_MSK 0x00020000
+#define TRAP_REBOOT_I_MSK 0xfffdffff
+#define TRAP_REBOOT_SFT 17
+#define TRAP_REBOOT_HI 17
+#define TRAP_REBOOT_SZ 1
+#define TRAP_BOOT_FLS_MSK 0x00040000
+#define TRAP_BOOT_FLS_I_MSK 0xfffbffff
+#define TRAP_BOOT_FLS_SFT 18
+#define TRAP_BOOT_FLS_HI 18
+#define TRAP_BOOT_FLS_SZ 1
+#define CHIP_ID_31_0_MSK 0xffffffff
+#define CHIP_ID_31_0_I_MSK 0x00000000
+#define CHIP_ID_31_0_SFT 0
+#define CHIP_ID_31_0_HI 31
+#define CHIP_ID_31_0_SZ 32
+#define CHIP_ID_63_32_MSK 0xffffffff
+#define CHIP_ID_63_32_I_MSK 0x00000000
+#define CHIP_ID_63_32_SFT 0
+#define CHIP_ID_63_32_HI 31
+#define CHIP_ID_63_32_SZ 32
+#define CHIP_ID_95_64_MSK 0xffffffff
+#define CHIP_ID_95_64_I_MSK 0x00000000
+#define CHIP_ID_95_64_SFT 0
+#define CHIP_ID_95_64_HI 31
+#define CHIP_ID_95_64_SZ 32
+#define CHIP_ID_127_96_MSK 0xffffffff
+#define CHIP_ID_127_96_I_MSK 0x00000000
+#define CHIP_ID_127_96_SFT 0
+#define CHIP_ID_127_96_HI 31
+#define CHIP_ID_127_96_SZ 32
+#define CK_SEL_1_0_MSK 0x00000003
+#define CK_SEL_1_0_I_MSK 0xfffffffc
+#define CK_SEL_1_0_SFT 0
+#define CK_SEL_1_0_HI 1
+#define CK_SEL_1_0_SZ 2
+#define CK_SEL_2_MSK 0x00000004
+#define CK_SEL_2_I_MSK 0xfffffffb
+#define CK_SEL_2_SFT 2
+#define CK_SEL_2_HI 2
+#define CK_SEL_2_SZ 1
+#define SYS_CLK_EN_MSK 0x00000001
+#define SYS_CLK_EN_I_MSK 0xfffffffe
+#define SYS_CLK_EN_SFT 0
+#define SYS_CLK_EN_HI 0
+#define SYS_CLK_EN_SZ 1
+#define MAC_CLK_EN_MSK 0x00000002
+#define MAC_CLK_EN_I_MSK 0xfffffffd
+#define MAC_CLK_EN_SFT 1
+#define MAC_CLK_EN_HI 1
+#define MAC_CLK_EN_SZ 1
+#define MCU_CLK_EN_MSK 0x00000004
+#define MCU_CLK_EN_I_MSK 0xfffffffb
+#define MCU_CLK_EN_SFT 2
+#define MCU_CLK_EN_HI 2
+#define MCU_CLK_EN_SZ 1
+#define SDIO_CLK_EN_MSK 0x00000008
+#define SDIO_CLK_EN_I_MSK 0xfffffff7
+#define SDIO_CLK_EN_SFT 3
+#define SDIO_CLK_EN_HI 3
+#define SDIO_CLK_EN_SZ 1
+#define SPI_SLV_CLK_EN_MSK 0x00000010
+#define SPI_SLV_CLK_EN_I_MSK 0xffffffef
+#define SPI_SLV_CLK_EN_SFT 4
+#define SPI_SLV_CLK_EN_HI 4
+#define SPI_SLV_CLK_EN_SZ 1
+#define UART_CLK_EN_MSK 0x00000020
+#define UART_CLK_EN_I_MSK 0xffffffdf
+#define UART_CLK_EN_SFT 5
+#define UART_CLK_EN_HI 5
+#define UART_CLK_EN_SZ 1
+#define DMA_CLK_EN_MSK 0x00000040
+#define DMA_CLK_EN_I_MSK 0xffffffbf
+#define DMA_CLK_EN_SFT 6
+#define DMA_CLK_EN_HI 6
+#define DMA_CLK_EN_SZ 1
+#define WDT_CLK_EN_MSK 0x00000080
+#define WDT_CLK_EN_I_MSK 0xffffff7f
+#define WDT_CLK_EN_SFT 7
+#define WDT_CLK_EN_HI 7
+#define WDT_CLK_EN_SZ 1
+#define I2C_SLV_CLK_EN_MSK 0x00000100
+#define I2C_SLV_CLK_EN_I_MSK 0xfffffeff
+#define I2C_SLV_CLK_EN_SFT 8
+#define I2C_SLV_CLK_EN_HI 8
+#define I2C_SLV_CLK_EN_SZ 1
+#define INT_CTL_CLK_EN_MSK 0x00000200
+#define INT_CTL_CLK_EN_I_MSK 0xfffffdff
+#define INT_CTL_CLK_EN_SFT 9
+#define INT_CTL_CLK_EN_HI 9
+#define INT_CTL_CLK_EN_SZ 1
+#define BTCX_CLK_EN_MSK 0x00000400
+#define BTCX_CLK_EN_I_MSK 0xfffffbff
+#define BTCX_CLK_EN_SFT 10
+#define BTCX_CLK_EN_HI 10
+#define BTCX_CLK_EN_SZ 1
+#define GPIO_CLK_EN_MSK 0x00000800
+#define GPIO_CLK_EN_I_MSK 0xfffff7ff
+#define GPIO_CLK_EN_SFT 11
+#define GPIO_CLK_EN_HI 11
+#define GPIO_CLK_EN_SZ 1
+#define US0TMR_CLK_EN_MSK 0x00001000
+#define US0TMR_CLK_EN_I_MSK 0xffffefff
+#define US0TMR_CLK_EN_SFT 12
+#define US0TMR_CLK_EN_HI 12
+#define US0TMR_CLK_EN_SZ 1
+#define US1TMR_CLK_EN_MSK 0x00002000
+#define US1TMR_CLK_EN_I_MSK 0xffffdfff
+#define US1TMR_CLK_EN_SFT 13
+#define US1TMR_CLK_EN_HI 13
+#define US1TMR_CLK_EN_SZ 1
+#define US2TMR_CLK_EN_MSK 0x00004000
+#define US2TMR_CLK_EN_I_MSK 0xffffbfff
+#define US2TMR_CLK_EN_SFT 14
+#define US2TMR_CLK_EN_HI 14
+#define US2TMR_CLK_EN_SZ 1
+#define US3TMR_CLK_EN_MSK 0x00008000
+#define US3TMR_CLK_EN_I_MSK 0xffff7fff
+#define US3TMR_CLK_EN_SFT 15
+#define US3TMR_CLK_EN_HI 15
+#define US3TMR_CLK_EN_SZ 1
+#define MS0TMR_CLK_EN_MSK 0x00010000
+#define MS0TMR_CLK_EN_I_MSK 0xfffeffff
+#define MS0TMR_CLK_EN_SFT 16
+#define MS0TMR_CLK_EN_HI 16
+#define MS0TMR_CLK_EN_SZ 1
+#define MS1TMR_CLK_EN_MSK 0x00020000
+#define MS1TMR_CLK_EN_I_MSK 0xfffdffff
+#define MS1TMR_CLK_EN_SFT 17
+#define MS1TMR_CLK_EN_HI 17
+#define MS1TMR_CLK_EN_SZ 1
+#define MS2TMR_CLK_EN_MSK 0x00040000
+#define MS2TMR_CLK_EN_I_MSK 0xfffbffff
+#define MS2TMR_CLK_EN_SFT 18
+#define MS2TMR_CLK_EN_HI 18
+#define MS2TMR_CLK_EN_SZ 1
+#define MS3TMR_CLK_EN_MSK 0x00080000
+#define MS3TMR_CLK_EN_I_MSK 0xfff7ffff
+#define MS3TMR_CLK_EN_SFT 19
+#define MS3TMR_CLK_EN_HI 19
+#define MS3TMR_CLK_EN_SZ 1
+#define BIST_CLK_EN_MSK 0x00100000
+#define BIST_CLK_EN_I_MSK 0xffefffff
+#define BIST_CLK_EN_SFT 20
+#define BIST_CLK_EN_HI 20
+#define BIST_CLK_EN_SZ 1
+#define I2C_MST_CLK_EN_MSK 0x00800000
+#define I2C_MST_CLK_EN_I_MSK 0xff7fffff
+#define I2C_MST_CLK_EN_SFT 23
+#define I2C_MST_CLK_EN_HI 23
+#define I2C_MST_CLK_EN_SZ 1
+#define BTCX_CSR_CLK_EN_MSK 0x00000400
+#define BTCX_CSR_CLK_EN_I_MSK 0xfffffbff
+#define BTCX_CSR_CLK_EN_SFT 10
+#define BTCX_CSR_CLK_EN_HI 10
+#define BTCX_CSR_CLK_EN_SZ 1
+#define MCU_DBG_SEL_MSK 0x0000003f
+#define MCU_DBG_SEL_I_MSK 0xffffffc0
+#define MCU_DBG_SEL_SFT 0
+#define MCU_DBG_SEL_HI 5
+#define MCU_DBG_SEL_SZ 6
+#define MCU_STOP_NOGRANT_MSK 0x00000100
+#define MCU_STOP_NOGRANT_I_MSK 0xfffffeff
+#define MCU_STOP_NOGRANT_SFT 8
+#define MCU_STOP_NOGRANT_HI 8
+#define MCU_STOP_NOGRANT_SZ 1
+#define MCU_STOP_ANYTIME_MSK 0x00000200
+#define MCU_STOP_ANYTIME_I_MSK 0xfffffdff
+#define MCU_STOP_ANYTIME_SFT 9
+#define MCU_STOP_ANYTIME_HI 9
+#define MCU_STOP_ANYTIME_SZ 1
+#define MCU_DBG_DATA_MSK 0xffffffff
+#define MCU_DBG_DATA_I_MSK 0x00000000
+#define MCU_DBG_DATA_SFT 0
+#define MCU_DBG_DATA_HI 31
+#define MCU_DBG_DATA_SZ 32
+#define AHB_SW_RST_MSK 0x00000001
+#define AHB_SW_RST_I_MSK 0xfffffffe
+#define AHB_SW_RST_SFT 0
+#define AHB_SW_RST_HI 0
+#define AHB_SW_RST_SZ 1
+#define AHB_ERR_RST_MSK 0x00000002
+#define AHB_ERR_RST_I_MSK 0xfffffffd
+#define AHB_ERR_RST_SFT 1
+#define AHB_ERR_RST_HI 1
+#define AHB_ERR_RST_SZ 1
+#define REG_AHB_DEBUG_MX_MSK 0x00000030
+#define REG_AHB_DEBUG_MX_I_MSK 0xffffffcf
+#define REG_AHB_DEBUG_MX_SFT 4
+#define REG_AHB_DEBUG_MX_HI 5
+#define REG_AHB_DEBUG_MX_SZ 2
+#define REG_PKT_W_NBRT_MSK 0x00000100
+#define REG_PKT_W_NBRT_I_MSK 0xfffffeff
+#define REG_PKT_W_NBRT_SFT 8
+#define REG_PKT_W_NBRT_HI 8
+#define REG_PKT_W_NBRT_SZ 1
+#define REG_PKT_R_NBRT_MSK 0x00000200
+#define REG_PKT_R_NBRT_I_MSK 0xfffffdff
+#define REG_PKT_R_NBRT_SFT 9
+#define REG_PKT_R_NBRT_HI 9
+#define REG_PKT_R_NBRT_SZ 1
+#define IQ_SRAM_SEL_0_MSK 0x00001000
+#define IQ_SRAM_SEL_0_I_MSK 0xffffefff
+#define IQ_SRAM_SEL_0_SFT 12
+#define IQ_SRAM_SEL_0_HI 12
+#define IQ_SRAM_SEL_0_SZ 1
+#define IQ_SRAM_SEL_1_MSK 0x00002000
+#define IQ_SRAM_SEL_1_I_MSK 0xffffdfff
+#define IQ_SRAM_SEL_1_SFT 13
+#define IQ_SRAM_SEL_1_HI 13
+#define IQ_SRAM_SEL_1_SZ 1
+#define IQ_SRAM_SEL_2_MSK 0x00004000
+#define IQ_SRAM_SEL_2_I_MSK 0xffffbfff
+#define IQ_SRAM_SEL_2_SFT 14
+#define IQ_SRAM_SEL_2_HI 14
+#define IQ_SRAM_SEL_2_SZ 1
+#define AHB_STATUS_MSK 0xffff0000
+#define AHB_STATUS_I_MSK 0x0000ffff
+#define AHB_STATUS_SFT 16
+#define AHB_STATUS_HI 31
+#define AHB_STATUS_SZ 16
+#define PARALLEL_DR_MSK 0x00000001
+#define PARALLEL_DR_I_MSK 0xfffffffe
+#define PARALLEL_DR_SFT 0
+#define PARALLEL_DR_HI 0
+#define PARALLEL_DR_SZ 1
+#define MBRUN_MSK 0x00000010
+#define MBRUN_I_MSK 0xffffffef
+#define MBRUN_SFT 4
+#define MBRUN_HI 4
+#define MBRUN_SZ 1
+#define SHIFT_DR_MSK 0x00000100
+#define SHIFT_DR_I_MSK 0xfffffeff
+#define SHIFT_DR_SFT 8
+#define SHIFT_DR_HI 8
+#define SHIFT_DR_SZ 1
+#define MODE_REG_SI_MSK 0x00000200
+#define MODE_REG_SI_I_MSK 0xfffffdff
+#define MODE_REG_SI_SFT 9
+#define MODE_REG_SI_HI 9
+#define MODE_REG_SI_SZ 1
+#define SIMULATION_MODE_MSK 0x00000400
+#define SIMULATION_MODE_I_MSK 0xfffffbff
+#define SIMULATION_MODE_SFT 10
+#define SIMULATION_MODE_HI 10
+#define SIMULATION_MODE_SZ 1
+#define DBIST_MODE_MSK 0x00000800
+#define DBIST_MODE_I_MSK 0xfffff7ff
+#define DBIST_MODE_SFT 11
+#define DBIST_MODE_HI 11
+#define DBIST_MODE_SZ 1
+#define MODE_REG_IN_MSK 0x001fffff
+#define MODE_REG_IN_I_MSK 0xffe00000
+#define MODE_REG_IN_SFT 0
+#define MODE_REG_IN_HI 20
+#define MODE_REG_IN_SZ 21
+#define MODE_REG_OUT_MCU_MSK 0x001fffff
+#define MODE_REG_OUT_MCU_I_MSK 0xffe00000
+#define MODE_REG_OUT_MCU_SFT 0
+#define MODE_REG_OUT_MCU_HI 20
+#define MODE_REG_OUT_MCU_SZ 21
+#define MODE_REG_SO_MCU_MSK 0x80000000
+#define MODE_REG_SO_MCU_I_MSK 0x7fffffff
+#define MODE_REG_SO_MCU_SFT 31
+#define MODE_REG_SO_MCU_HI 31
+#define MODE_REG_SO_MCU_SZ 1
+#define MONITOR_BUS_MCU_31_0_MSK 0xffffffff
+#define MONITOR_BUS_MCU_31_0_I_MSK 0x00000000
+#define MONITOR_BUS_MCU_31_0_SFT 0
+#define MONITOR_BUS_MCU_31_0_HI 31
+#define MONITOR_BUS_MCU_31_0_SZ 32
+#define MONITOR_BUS_MCU_33_32_MSK 0x00000003
+#define MONITOR_BUS_MCU_33_32_I_MSK 0xfffffffc
+#define MONITOR_BUS_MCU_33_32_SFT 0
+#define MONITOR_BUS_MCU_33_32_HI 1
+#define MONITOR_BUS_MCU_33_32_SZ 2
+#define TB_ADR_SEL_MSK 0x0000ffff
+#define TB_ADR_SEL_I_MSK 0xffff0000
+#define TB_ADR_SEL_SFT 0
+#define TB_ADR_SEL_HI 15
+#define TB_ADR_SEL_SZ 16
+#define TB_CS_MSK 0x80000000
+#define TB_CS_I_MSK 0x7fffffff
+#define TB_CS_SFT 31
+#define TB_CS_HI 31
+#define TB_CS_SZ 1
+#define TB_RDATA_MSK 0xffffffff
+#define TB_RDATA_I_MSK 0x00000000
+#define TB_RDATA_SFT 0
+#define TB_RDATA_HI 31
+#define TB_RDATA_SZ 32
+#define UART_W2B_EN_MSK 0x00000001
+#define UART_W2B_EN_I_MSK 0xfffffffe
+#define UART_W2B_EN_SFT 0
+#define UART_W2B_EN_HI 0
+#define UART_W2B_EN_SZ 1
+#define DATA_UART_W2B_EN_MSK 0x00000010
+#define DATA_UART_W2B_EN_I_MSK 0xffffffef
+#define DATA_UART_W2B_EN_SFT 4
+#define DATA_UART_W2B_EN_HI 4
+#define DATA_UART_W2B_EN_SZ 1
+#define AHB_ILL_ADDR_MSK 0xffffffff
+#define AHB_ILL_ADDR_I_MSK 0x00000000
+#define AHB_ILL_ADDR_SFT 0
+#define AHB_ILL_ADDR_HI 31
+#define AHB_ILL_ADDR_SZ 32
+#define AHB_FEN_ADDR_MSK 0xffffffff
+#define AHB_FEN_ADDR_I_MSK 0x00000000
+#define AHB_FEN_ADDR_SFT 0
+#define AHB_FEN_ADDR_HI 31
+#define AHB_FEN_ADDR_SZ 32
+#define ILL_ADDR_CLR_MSK 0x00000001
+#define ILL_ADDR_CLR_I_MSK 0xfffffffe
+#define ILL_ADDR_CLR_SFT 0
+#define ILL_ADDR_CLR_HI 0
+#define ILL_ADDR_CLR_SZ 1
+#define FENCE_HIT_CLR_MSK 0x00000002
+#define FENCE_HIT_CLR_I_MSK 0xfffffffd
+#define FENCE_HIT_CLR_SFT 1
+#define FENCE_HIT_CLR_HI 1
+#define FENCE_HIT_CLR_SZ 1
+#define ILL_ADDR_INT_MSK 0x00000010
+#define ILL_ADDR_INT_I_MSK 0xffffffef
+#define ILL_ADDR_INT_SFT 4
+#define ILL_ADDR_INT_HI 4
+#define ILL_ADDR_INT_SZ 1
+#define FENCE_HIT_INT_MSK 0x00000020
+#define FENCE_HIT_INT_I_MSK 0xffffffdf
+#define FENCE_HIT_INT_SFT 5
+#define FENCE_HIT_INT_HI 5
+#define FENCE_HIT_INT_SZ 1
+#define PWM_INI_VALUE_P_A_MSK 0x000000ff
+#define PWM_INI_VALUE_P_A_I_MSK 0xffffff00
+#define PWM_INI_VALUE_P_A_SFT 0
+#define PWM_INI_VALUE_P_A_HI 7
+#define PWM_INI_VALUE_P_A_SZ 8
+#define PWM_INI_VALUE_N_A_MSK 0x0000ff00
+#define PWM_INI_VALUE_N_A_I_MSK 0xffff00ff
+#define PWM_INI_VALUE_N_A_SFT 8
+#define PWM_INI_VALUE_N_A_HI 15
+#define PWM_INI_VALUE_N_A_SZ 8
+#define PWM_POST_SCALER_A_MSK 0x000f0000
+#define PWM_POST_SCALER_A_I_MSK 0xfff0ffff
+#define PWM_POST_SCALER_A_SFT 16
+#define PWM_POST_SCALER_A_HI 19
+#define PWM_POST_SCALER_A_SZ 4
+#define PWM_ALWAYSON_A_MSK 0x20000000
+#define PWM_ALWAYSON_A_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_A_SFT 29
+#define PWM_ALWAYSON_A_HI 29
+#define PWM_ALWAYSON_A_SZ 1
+#define PWM_INVERT_A_MSK 0x40000000
+#define PWM_INVERT_A_I_MSK 0xbfffffff
+#define PWM_INVERT_A_SFT 30
+#define PWM_INVERT_A_HI 30
+#define PWM_INVERT_A_SZ 1
+#define PWM_ENABLE_A_MSK 0x80000000
+#define PWM_ENABLE_A_I_MSK 0x7fffffff
+#define PWM_ENABLE_A_SFT 31
+#define PWM_ENABLE_A_HI 31
+#define PWM_ENABLE_A_SZ 1
+#define PWM_INI_VALUE_P_B_MSK 0x000000ff
+#define PWM_INI_VALUE_P_B_I_MSK 0xffffff00
+#define PWM_INI_VALUE_P_B_SFT 0
+#define PWM_INI_VALUE_P_B_HI 7
+#define PWM_INI_VALUE_P_B_SZ 8
+#define PWM_INI_VALUE_N_B_MSK 0x0000ff00
+#define PWM_INI_VALUE_N_B_I_MSK 0xffff00ff
+#define PWM_INI_VALUE_N_B_SFT 8
+#define PWM_INI_VALUE_N_B_HI 15
+#define PWM_INI_VALUE_N_B_SZ 8
+#define PWM_POST_SCALER_B_MSK 0x000f0000
+#define PWM_POST_SCALER_B_I_MSK 0xfff0ffff
+#define PWM_POST_SCALER_B_SFT 16
+#define PWM_POST_SCALER_B_HI 19
+#define PWM_POST_SCALER_B_SZ 4
+#define PWM_ALWAYSON_B_MSK 0x20000000
+#define PWM_ALWAYSON_B_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_B_SFT 29
+#define PWM_ALWAYSON_B_HI 29
+#define PWM_ALWAYSON_B_SZ 1
+#define PWM_INVERT_B_MSK 0x40000000
+#define PWM_INVERT_B_I_MSK 0xbfffffff
+#define PWM_INVERT_B_SFT 30
+#define PWM_INVERT_B_HI 30
+#define PWM_INVERT_B_SZ 1
+#define PWM_ENABLE_B_MSK 0x80000000
+#define PWM_ENABLE_B_I_MSK 0x7fffffff
+#define PWM_ENABLE_B_SFT 31
+#define PWM_ENABLE_B_HI 31
+#define PWM_ENABLE_B_SZ 1
+#define HBUSREQ_LOCK_MSK 0x00001fff
+#define HBUSREQ_LOCK_I_MSK 0xffffe000
+#define HBUSREQ_LOCK_SFT 0
+#define HBUSREQ_LOCK_HI 12
+#define HBUSREQ_LOCK_SZ 13
+#define HBURST_LOCK_MSK 0x00001fff
+#define HBURST_LOCK_I_MSK 0xffffe000
+#define HBURST_LOCK_SFT 0
+#define HBURST_LOCK_HI 12
+#define HBURST_LOCK_SZ 13
+#define PRESCALER_USTIMER_MSK 0x000001ff
+#define PRESCALER_USTIMER_I_MSK 0xfffffe00
+#define PRESCALER_USTIMER_SFT 0
+#define PRESCALER_USTIMER_HI 8
+#define PRESCALER_USTIMER_SZ 9
+#define MODE_REG_IN_MMU_MSK 0x0000ffff
+#define MODE_REG_IN_MMU_I_MSK 0xffff0000
+#define MODE_REG_IN_MMU_SFT 0
+#define MODE_REG_IN_MMU_HI 15
+#define MODE_REG_IN_MMU_SZ 16
+#define MODE_REG_OUT_MMU_MSK 0x0000ffff
+#define MODE_REG_OUT_MMU_I_MSK 0xffff0000
+#define MODE_REG_OUT_MMU_SFT 0
+#define MODE_REG_OUT_MMU_HI 15
+#define MODE_REG_OUT_MMU_SZ 16
+#define MODE_REG_SO_MMU_MSK 0x80000000
+#define MODE_REG_SO_MMU_I_MSK 0x7fffffff
+#define MODE_REG_SO_MMU_SFT 31
+#define MODE_REG_SO_MMU_HI 31
+#define MODE_REG_SO_MMU_SZ 1
+#define MONITOR_BUS_MMU_MSK 0x0007ffff
+#define MONITOR_BUS_MMU_I_MSK 0xfff80000
+#define MONITOR_BUS_MMU_SFT 0
+#define MONITOR_BUS_MMU_HI 18
+#define MONITOR_BUS_MMU_SZ 19
+#define TEST_MODE0_MSK 0x00000001
+#define TEST_MODE0_I_MSK 0xfffffffe
+#define TEST_MODE0_SFT 0
+#define TEST_MODE0_HI 0
+#define TEST_MODE0_SZ 1
+#define TEST_MODE1_MSK 0x00000002
+#define TEST_MODE1_I_MSK 0xfffffffd
+#define TEST_MODE1_SFT 1
+#define TEST_MODE1_HI 1
+#define TEST_MODE1_SZ 1
+#define TEST_MODE2_MSK 0x00000004
+#define TEST_MODE2_I_MSK 0xfffffffb
+#define TEST_MODE2_SFT 2
+#define TEST_MODE2_HI 2
+#define TEST_MODE2_SZ 1
+#define TEST_MODE3_MSK 0x00000008
+#define TEST_MODE3_I_MSK 0xfffffff7
+#define TEST_MODE3_SFT 3
+#define TEST_MODE3_HI 3
+#define TEST_MODE3_SZ 1
+#define TEST_MODE4_MSK 0x00000010
+#define TEST_MODE4_I_MSK 0xffffffef
+#define TEST_MODE4_SFT 4
+#define TEST_MODE4_HI 4
+#define TEST_MODE4_SZ 1
+#define TEST_MODE_ALL_MSK 0x00000020
+#define TEST_MODE_ALL_I_MSK 0xffffffdf
+#define TEST_MODE_ALL_SFT 5
+#define TEST_MODE_ALL_HI 5
+#define TEST_MODE_ALL_SZ 1
+#define WDT_INIT_MSK 0x00000001
+#define WDT_INIT_I_MSK 0xfffffffe
+#define WDT_INIT_SFT 0
+#define WDT_INIT_HI 0
+#define WDT_INIT_SZ 1
+#define SD_HOST_INIT_MSK 0x00000002
+#define SD_HOST_INIT_I_MSK 0xfffffffd
+#define SD_HOST_INIT_SFT 1
+#define SD_HOST_INIT_HI 1
+#define SD_HOST_INIT_SZ 1
+#define ALLOW_SD_RESET_MSK 0x00000001
+#define ALLOW_SD_RESET_I_MSK 0xfffffffe
+#define ALLOW_SD_RESET_SFT 0
+#define ALLOW_SD_RESET_HI 0
+#define ALLOW_SD_RESET_SZ 1
+#define UART_NRTS_MSK 0x00000001
+#define UART_NRTS_I_MSK 0xfffffffe
+#define UART_NRTS_SFT 0
+#define UART_NRTS_HI 0
+#define UART_NRTS_SZ 1
+#define UART_NCTS_MSK 0x00000002
+#define UART_NCTS_I_MSK 0xfffffffd
+#define UART_NCTS_SFT 1
+#define UART_NCTS_HI 1
+#define UART_NCTS_SZ 1
+#define TU0_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU0_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU0_TM_INIT_VALUE_SFT 0
+#define TU0_TM_INIT_VALUE_HI 15
+#define TU0_TM_INIT_VALUE_SZ 16
+#define TU0_TM_MODE_MSK 0x00010000
+#define TU0_TM_MODE_I_MSK 0xfffeffff
+#define TU0_TM_MODE_SFT 16
+#define TU0_TM_MODE_HI 16
+#define TU0_TM_MODE_SZ 1
+#define TU0_TM_INT_STS_DONE_MSK 0x00020000
+#define TU0_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU0_TM_INT_STS_DONE_SFT 17
+#define TU0_TM_INT_STS_DONE_HI 17
+#define TU0_TM_INT_STS_DONE_SZ 1
+#define TU0_TM_INT_MASK_MSK 0x00040000
+#define TU0_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU0_TM_INT_MASK_SFT 18
+#define TU0_TM_INT_MASK_HI 18
+#define TU0_TM_INT_MASK_SZ 1
+#define TU0_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU0_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU0_TM_CUR_VALUE_SFT 0
+#define TU0_TM_CUR_VALUE_HI 15
+#define TU0_TM_CUR_VALUE_SZ 16
+#define TU1_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU1_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU1_TM_INIT_VALUE_SFT 0
+#define TU1_TM_INIT_VALUE_HI 15
+#define TU1_TM_INIT_VALUE_SZ 16
+#define TU1_TM_MODE_MSK 0x00010000
+#define TU1_TM_MODE_I_MSK 0xfffeffff
+#define TU1_TM_MODE_SFT 16
+#define TU1_TM_MODE_HI 16
+#define TU1_TM_MODE_SZ 1
+#define TU1_TM_INT_STS_DONE_MSK 0x00020000
+#define TU1_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU1_TM_INT_STS_DONE_SFT 17
+#define TU1_TM_INT_STS_DONE_HI 17
+#define TU1_TM_INT_STS_DONE_SZ 1
+#define TU1_TM_INT_MASK_MSK 0x00040000
+#define TU1_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU1_TM_INT_MASK_SFT 18
+#define TU1_TM_INT_MASK_HI 18
+#define TU1_TM_INT_MASK_SZ 1
+#define TU1_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU1_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU1_TM_CUR_VALUE_SFT 0
+#define TU1_TM_CUR_VALUE_HI 15
+#define TU1_TM_CUR_VALUE_SZ 16
+#define TU2_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU2_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU2_TM_INIT_VALUE_SFT 0
+#define TU2_TM_INIT_VALUE_HI 15
+#define TU2_TM_INIT_VALUE_SZ 16
+#define TU2_TM_MODE_MSK 0x00010000
+#define TU2_TM_MODE_I_MSK 0xfffeffff
+#define TU2_TM_MODE_SFT 16
+#define TU2_TM_MODE_HI 16
+#define TU2_TM_MODE_SZ 1
+#define TU2_TM_INT_STS_DONE_MSK 0x00020000
+#define TU2_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU2_TM_INT_STS_DONE_SFT 17
+#define TU2_TM_INT_STS_DONE_HI 17
+#define TU2_TM_INT_STS_DONE_SZ 1
+#define TU2_TM_INT_MASK_MSK 0x00040000
+#define TU2_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU2_TM_INT_MASK_SFT 18
+#define TU2_TM_INT_MASK_HI 18
+#define TU2_TM_INT_MASK_SZ 1
+#define TU2_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU2_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU2_TM_CUR_VALUE_SFT 0
+#define TU2_TM_CUR_VALUE_HI 15
+#define TU2_TM_CUR_VALUE_SZ 16
+#define TU3_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU3_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU3_TM_INIT_VALUE_SFT 0
+#define TU3_TM_INIT_VALUE_HI 15
+#define TU3_TM_INIT_VALUE_SZ 16
+#define TU3_TM_MODE_MSK 0x00010000
+#define TU3_TM_MODE_I_MSK 0xfffeffff
+#define TU3_TM_MODE_SFT 16
+#define TU3_TM_MODE_HI 16
+#define TU3_TM_MODE_SZ 1
+#define TU3_TM_INT_STS_DONE_MSK 0x00020000
+#define TU3_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU3_TM_INT_STS_DONE_SFT 17
+#define TU3_TM_INT_STS_DONE_HI 17
+#define TU3_TM_INT_STS_DONE_SZ 1
+#define TU3_TM_INT_MASK_MSK 0x00040000
+#define TU3_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU3_TM_INT_MASK_SFT 18
+#define TU3_TM_INT_MASK_HI 18
+#define TU3_TM_INT_MASK_SZ 1
+#define TU3_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU3_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU3_TM_CUR_VALUE_SFT 0
+#define TU3_TM_CUR_VALUE_HI 15
+#define TU3_TM_CUR_VALUE_SZ 16
+#define TM0_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM0_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM0_TM_INIT_VALUE_SFT 0
+#define TM0_TM_INIT_VALUE_HI 15
+#define TM0_TM_INIT_VALUE_SZ 16
+#define TM0_TM_MODE_MSK 0x00010000
+#define TM0_TM_MODE_I_MSK 0xfffeffff
+#define TM0_TM_MODE_SFT 16
+#define TM0_TM_MODE_HI 16
+#define TM0_TM_MODE_SZ 1
+#define TM0_TM_INT_STS_DONE_MSK 0x00020000
+#define TM0_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM0_TM_INT_STS_DONE_SFT 17
+#define TM0_TM_INT_STS_DONE_HI 17
+#define TM0_TM_INT_STS_DONE_SZ 1
+#define TM0_TM_INT_MASK_MSK 0x00040000
+#define TM0_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM0_TM_INT_MASK_SFT 18
+#define TM0_TM_INT_MASK_HI 18
+#define TM0_TM_INT_MASK_SZ 1
+#define TM0_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM0_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM0_TM_CUR_VALUE_SFT 0
+#define TM0_TM_CUR_VALUE_HI 15
+#define TM0_TM_CUR_VALUE_SZ 16
+#define TM1_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM1_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM1_TM_INIT_VALUE_SFT 0
+#define TM1_TM_INIT_VALUE_HI 15
+#define TM1_TM_INIT_VALUE_SZ 16
+#define TM1_TM_MODE_MSK 0x00010000
+#define TM1_TM_MODE_I_MSK 0xfffeffff
+#define TM1_TM_MODE_SFT 16
+#define TM1_TM_MODE_HI 16
+#define TM1_TM_MODE_SZ 1
+#define TM1_TM_INT_STS_DONE_MSK 0x00020000
+#define TM1_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM1_TM_INT_STS_DONE_SFT 17
+#define TM1_TM_INT_STS_DONE_HI 17
+#define TM1_TM_INT_STS_DONE_SZ 1
+#define TM1_TM_INT_MASK_MSK 0x00040000
+#define TM1_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM1_TM_INT_MASK_SFT 18
+#define TM1_TM_INT_MASK_HI 18
+#define TM1_TM_INT_MASK_SZ 1
+#define TM1_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM1_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM1_TM_CUR_VALUE_SFT 0
+#define TM1_TM_CUR_VALUE_HI 15
+#define TM1_TM_CUR_VALUE_SZ 16
+#define TM2_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM2_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM2_TM_INIT_VALUE_SFT 0
+#define TM2_TM_INIT_VALUE_HI 15
+#define TM2_TM_INIT_VALUE_SZ 16
+#define TM2_TM_MODE_MSK 0x00010000
+#define TM2_TM_MODE_I_MSK 0xfffeffff
+#define TM2_TM_MODE_SFT 16
+#define TM2_TM_MODE_HI 16
+#define TM2_TM_MODE_SZ 1
+#define TM2_TM_INT_STS_DONE_MSK 0x00020000
+#define TM2_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM2_TM_INT_STS_DONE_SFT 17
+#define TM2_TM_INT_STS_DONE_HI 17
+#define TM2_TM_INT_STS_DONE_SZ 1
+#define TM2_TM_INT_MASK_MSK 0x00040000
+#define TM2_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM2_TM_INT_MASK_SFT 18
+#define TM2_TM_INT_MASK_HI 18
+#define TM2_TM_INT_MASK_SZ 1
+#define TM2_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM2_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM2_TM_CUR_VALUE_SFT 0
+#define TM2_TM_CUR_VALUE_HI 15
+#define TM2_TM_CUR_VALUE_SZ 16
+#define TM3_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM3_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM3_TM_INIT_VALUE_SFT 0
+#define TM3_TM_INIT_VALUE_HI 15
+#define TM3_TM_INIT_VALUE_SZ 16
+#define TM3_TM_MODE_MSK 0x00010000
+#define TM3_TM_MODE_I_MSK 0xfffeffff
+#define TM3_TM_MODE_SFT 16
+#define TM3_TM_MODE_HI 16
+#define TM3_TM_MODE_SZ 1
+#define TM3_TM_INT_STS_DONE_MSK 0x00020000
+#define TM3_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM3_TM_INT_STS_DONE_SFT 17
+#define TM3_TM_INT_STS_DONE_HI 17
+#define TM3_TM_INT_STS_DONE_SZ 1
+#define TM3_TM_INT_MASK_MSK 0x00040000
+#define TM3_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM3_TM_INT_MASK_SFT 18
+#define TM3_TM_INT_MASK_HI 18
+#define TM3_TM_INT_MASK_SZ 1
+#define TM3_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM3_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM3_TM_CUR_VALUE_SFT 0
+#define TM3_TM_CUR_VALUE_HI 15
+#define TM3_TM_CUR_VALUE_SZ 16
+#define MCU_WDT_TIME_CNT_MSK 0x0000ffff
+#define MCU_WDT_TIME_CNT_I_MSK 0xffff0000
+#define MCU_WDT_TIME_CNT_SFT 0
+#define MCU_WDT_TIME_CNT_HI 15
+#define MCU_WDT_TIME_CNT_SZ 16
+#define MCU_WDT_STATUS_MSK 0x00020000
+#define MCU_WDT_STATUS_I_MSK 0xfffdffff
+#define MCU_WDT_STATUS_SFT 17
+#define MCU_WDT_STATUS_HI 17
+#define MCU_WDT_STATUS_SZ 1
+#define MCU_WDOG_ENA_MSK 0x80000000
+#define MCU_WDOG_ENA_I_MSK 0x7fffffff
+#define MCU_WDOG_ENA_SFT 31
+#define MCU_WDOG_ENA_HI 31
+#define MCU_WDOG_ENA_SZ 1
+#define SYS_WDT_TIME_CNT_MSK 0x0000ffff
+#define SYS_WDT_TIME_CNT_I_MSK 0xffff0000
+#define SYS_WDT_TIME_CNT_SFT 0
+#define SYS_WDT_TIME_CNT_HI 15
+#define SYS_WDT_TIME_CNT_SZ 16
+#define SYS_WDT_STATUS_MSK 0x00020000
+#define SYS_WDT_STATUS_I_MSK 0xfffdffff
+#define SYS_WDT_STATUS_SFT 17
+#define SYS_WDT_STATUS_HI 17
+#define SYS_WDT_STATUS_SZ 1
+#define SYS_WDOG_ENA_MSK 0x80000000
+#define SYS_WDOG_ENA_I_MSK 0x7fffffff
+#define SYS_WDOG_ENA_SFT 31
+#define SYS_WDOG_ENA_HI 31
+#define SYS_WDOG_ENA_SZ 1
+#define XLNA_EN_O_OE_MSK 0x00000001
+#define XLNA_EN_O_OE_I_MSK 0xfffffffe
+#define XLNA_EN_O_OE_SFT 0
+#define XLNA_EN_O_OE_HI 0
+#define XLNA_EN_O_OE_SZ 1
+#define XLNA_EN_O_PE_MSK 0x00000002
+#define XLNA_EN_O_PE_I_MSK 0xfffffffd
+#define XLNA_EN_O_PE_SFT 1
+#define XLNA_EN_O_PE_HI 1
+#define XLNA_EN_O_PE_SZ 1
+#define PAD6_IE_MSK 0x00000008
+#define PAD6_IE_I_MSK 0xfffffff7
+#define PAD6_IE_SFT 3
+#define PAD6_IE_HI 3
+#define PAD6_IE_SZ 1
+#define PAD6_SEL_I_MSK 0x00000030
+#define PAD6_SEL_I_I_MSK 0xffffffcf
+#define PAD6_SEL_I_SFT 4
+#define PAD6_SEL_I_HI 5
+#define PAD6_SEL_I_SZ 2
+#define PAD6_OD_MSK 0x00000100
+#define PAD6_OD_I_MSK 0xfffffeff
+#define PAD6_OD_SFT 8
+#define PAD6_OD_HI 8
+#define PAD6_OD_SZ 1
+#define PAD6_SEL_O_MSK 0x00001000
+#define PAD6_SEL_O_I_MSK 0xffffefff
+#define PAD6_SEL_O_SFT 12
+#define PAD6_SEL_O_HI 12
+#define PAD6_SEL_O_SZ 1
+#define XLNA_EN_O_C_MSK 0x10000000
+#define XLNA_EN_O_C_I_MSK 0xefffffff
+#define XLNA_EN_O_C_SFT 28
+#define XLNA_EN_O_C_HI 28
+#define XLNA_EN_O_C_SZ 1
+#define WIFI_TX_SW_O_OE_MSK 0x00000001
+#define WIFI_TX_SW_O_OE_I_MSK 0xfffffffe
+#define WIFI_TX_SW_O_OE_SFT 0
+#define WIFI_TX_SW_O_OE_HI 0
+#define WIFI_TX_SW_O_OE_SZ 1
+#define WIFI_TX_SW_O_PE_MSK 0x00000002
+#define WIFI_TX_SW_O_PE_I_MSK 0xfffffffd
+#define WIFI_TX_SW_O_PE_SFT 1
+#define WIFI_TX_SW_O_PE_HI 1
+#define WIFI_TX_SW_O_PE_SZ 1
+#define PAD7_IE_MSK 0x00000008
+#define PAD7_IE_I_MSK 0xfffffff7
+#define PAD7_IE_SFT 3
+#define PAD7_IE_HI 3
+#define PAD7_IE_SZ 1
+#define PAD7_SEL_I_MSK 0x00000030
+#define PAD7_SEL_I_I_MSK 0xffffffcf
+#define PAD7_SEL_I_SFT 4
+#define PAD7_SEL_I_HI 5
+#define PAD7_SEL_I_SZ 2
+#define PAD7_OD_MSK 0x00000100
+#define PAD7_OD_I_MSK 0xfffffeff
+#define PAD7_OD_SFT 8
+#define PAD7_OD_HI 8
+#define PAD7_OD_SZ 1
+#define PAD7_SEL_O_MSK 0x00001000
+#define PAD7_SEL_O_I_MSK 0xffffefff
+#define PAD7_SEL_O_SFT 12
+#define PAD7_SEL_O_HI 12
+#define PAD7_SEL_O_SZ 1
+#define WIFI_TX_SW_O_C_MSK 0x10000000
+#define WIFI_TX_SW_O_C_I_MSK 0xefffffff
+#define WIFI_TX_SW_O_C_SFT 28
+#define WIFI_TX_SW_O_C_HI 28
+#define WIFI_TX_SW_O_C_SZ 1
+#define WIFI_RX_SW_O_OE_MSK 0x00000001
+#define WIFI_RX_SW_O_OE_I_MSK 0xfffffffe
+#define WIFI_RX_SW_O_OE_SFT 0
+#define WIFI_RX_SW_O_OE_HI 0
+#define WIFI_RX_SW_O_OE_SZ 1
+#define WIFI_RX_SW_O_PE_MSK 0x00000002
+#define WIFI_RX_SW_O_PE_I_MSK 0xfffffffd
+#define WIFI_RX_SW_O_PE_SFT 1
+#define WIFI_RX_SW_O_PE_HI 1
+#define WIFI_RX_SW_O_PE_SZ 1
+#define PAD8_IE_MSK 0x00000008
+#define PAD8_IE_I_MSK 0xfffffff7
+#define PAD8_IE_SFT 3
+#define PAD8_IE_HI 3
+#define PAD8_IE_SZ 1
+#define PAD8_SEL_I_MSK 0x00000030
+#define PAD8_SEL_I_I_MSK 0xffffffcf
+#define PAD8_SEL_I_SFT 4
+#define PAD8_SEL_I_HI 5
+#define PAD8_SEL_I_SZ 2
+#define PAD8_OD_MSK 0x00000100
+#define PAD8_OD_I_MSK 0xfffffeff
+#define PAD8_OD_SFT 8
+#define PAD8_OD_HI 8
+#define PAD8_OD_SZ 1
+#define WIFI_RX_SW_O_C_MSK 0x10000000
+#define WIFI_RX_SW_O_C_I_MSK 0xefffffff
+#define WIFI_RX_SW_O_C_SFT 28
+#define WIFI_RX_SW_O_C_HI 28
+#define WIFI_RX_SW_O_C_SZ 1
+#define BT_SW_O_OE_MSK 0x00000001
+#define BT_SW_O_OE_I_MSK 0xfffffffe
+#define BT_SW_O_OE_SFT 0
+#define BT_SW_O_OE_HI 0
+#define BT_SW_O_OE_SZ 1
+#define BT_SW_O_PE_MSK 0x00000002
+#define BT_SW_O_PE_I_MSK 0xfffffffd
+#define BT_SW_O_PE_SFT 1
+#define BT_SW_O_PE_HI 1
+#define BT_SW_O_PE_SZ 1
+#define PAD9_IE_MSK 0x00000008
+#define PAD9_IE_I_MSK 0xfffffff7
+#define PAD9_IE_SFT 3
+#define PAD9_IE_HI 3
+#define PAD9_IE_SZ 1
+#define PAD9_SEL_I_MSK 0x00000030
+#define PAD9_SEL_I_I_MSK 0xffffffcf
+#define PAD9_SEL_I_SFT 4
+#define PAD9_SEL_I_HI 5
+#define PAD9_SEL_I_SZ 2
+#define PAD9_OD_MSK 0x00000100
+#define PAD9_OD_I_MSK 0xfffffeff
+#define PAD9_OD_SFT 8
+#define PAD9_OD_HI 8
+#define PAD9_OD_SZ 1
+#define PAD9_SEL_O_MSK 0x00001000
+#define PAD9_SEL_O_I_MSK 0xffffefff
+#define PAD9_SEL_O_SFT 12
+#define PAD9_SEL_O_HI 12
+#define PAD9_SEL_O_SZ 1
+#define BT_SW_O_C_MSK 0x10000000
+#define BT_SW_O_C_I_MSK 0xefffffff
+#define BT_SW_O_C_SFT 28
+#define BT_SW_O_C_HI 28
+#define BT_SW_O_C_SZ 1
+#define XPA_EN_O_OE_MSK 0x00000001
+#define XPA_EN_O_OE_I_MSK 0xfffffffe
+#define XPA_EN_O_OE_SFT 0
+#define XPA_EN_O_OE_HI 0
+#define XPA_EN_O_OE_SZ 1
+#define XPA_EN_O_PE_MSK 0x00000002
+#define XPA_EN_O_PE_I_MSK 0xfffffffd
+#define XPA_EN_O_PE_SFT 1
+#define XPA_EN_O_PE_HI 1
+#define XPA_EN_O_PE_SZ 1
+#define PAD11_IE_MSK 0x00000008
+#define PAD11_IE_I_MSK 0xfffffff7
+#define PAD11_IE_SFT 3
+#define PAD11_IE_HI 3
+#define PAD11_IE_SZ 1
+#define PAD11_SEL_I_MSK 0x00000030
+#define PAD11_SEL_I_I_MSK 0xffffffcf
+#define PAD11_SEL_I_SFT 4
+#define PAD11_SEL_I_HI 5
+#define PAD11_SEL_I_SZ 2
+#define PAD11_OD_MSK 0x00000100
+#define PAD11_OD_I_MSK 0xfffffeff
+#define PAD11_OD_SFT 8
+#define PAD11_OD_HI 8
+#define PAD11_OD_SZ 1
+#define PAD11_SEL_O_MSK 0x00001000
+#define PAD11_SEL_O_I_MSK 0xffffefff
+#define PAD11_SEL_O_SFT 12
+#define PAD11_SEL_O_HI 12
+#define PAD11_SEL_O_SZ 1
+#define XPA_EN_O_C_MSK 0x10000000
+#define XPA_EN_O_C_I_MSK 0xefffffff
+#define XPA_EN_O_C_SFT 28
+#define XPA_EN_O_C_HI 28
+#define XPA_EN_O_C_SZ 1
+#define PAD15_OE_MSK 0x00000001
+#define PAD15_OE_I_MSK 0xfffffffe
+#define PAD15_OE_SFT 0
+#define PAD15_OE_HI 0
+#define PAD15_OE_SZ 1
+#define PAD15_PE_MSK 0x00000002
+#define PAD15_PE_I_MSK 0xfffffffd
+#define PAD15_PE_SFT 1
+#define PAD15_PE_HI 1
+#define PAD15_PE_SZ 1
+#define PAD15_DS_MSK 0x00000004
+#define PAD15_DS_I_MSK 0xfffffffb
+#define PAD15_DS_SFT 2
+#define PAD15_DS_HI 2
+#define PAD15_DS_SZ 1
+#define PAD15_IE_MSK 0x00000008
+#define PAD15_IE_I_MSK 0xfffffff7
+#define PAD15_IE_SFT 3
+#define PAD15_IE_HI 3
+#define PAD15_IE_SZ 1
+#define PAD15_SEL_I_MSK 0x00000030
+#define PAD15_SEL_I_I_MSK 0xffffffcf
+#define PAD15_SEL_I_SFT 4
+#define PAD15_SEL_I_HI 5
+#define PAD15_SEL_I_SZ 2
+#define PAD15_OD_MSK 0x00000100
+#define PAD15_OD_I_MSK 0xfffffeff
+#define PAD15_OD_SFT 8
+#define PAD15_OD_HI 8
+#define PAD15_OD_SZ 1
+#define PAD15_SEL_O_MSK 0x00001000
+#define PAD15_SEL_O_I_MSK 0xffffefff
+#define PAD15_SEL_O_SFT 12
+#define PAD15_SEL_O_HI 12
+#define PAD15_SEL_O_SZ 1
+#define TEST_1_ID_MSK 0x10000000
+#define TEST_1_ID_I_MSK 0xefffffff
+#define TEST_1_ID_SFT 28
+#define TEST_1_ID_HI 28
+#define TEST_1_ID_SZ 1
+#define PAD16_OE_MSK 0x00000001
+#define PAD16_OE_I_MSK 0xfffffffe
+#define PAD16_OE_SFT 0
+#define PAD16_OE_HI 0
+#define PAD16_OE_SZ 1
+#define PAD16_PE_MSK 0x00000002
+#define PAD16_PE_I_MSK 0xfffffffd
+#define PAD16_PE_SFT 1
+#define PAD16_PE_HI 1
+#define PAD16_PE_SZ 1
+#define PAD16_DS_MSK 0x00000004
+#define PAD16_DS_I_MSK 0xfffffffb
+#define PAD16_DS_SFT 2
+#define PAD16_DS_HI 2
+#define PAD16_DS_SZ 1
+#define PAD16_IE_MSK 0x00000008
+#define PAD16_IE_I_MSK 0xfffffff7
+#define PAD16_IE_SFT 3
+#define PAD16_IE_HI 3
+#define PAD16_IE_SZ 1
+#define PAD16_SEL_I_MSK 0x00000030
+#define PAD16_SEL_I_I_MSK 0xffffffcf
+#define PAD16_SEL_I_SFT 4
+#define PAD16_SEL_I_HI 5
+#define PAD16_SEL_I_SZ 2
+#define PAD16_OD_MSK 0x00000100
+#define PAD16_OD_I_MSK 0xfffffeff
+#define PAD16_OD_SFT 8
+#define PAD16_OD_HI 8
+#define PAD16_OD_SZ 1
+#define PAD16_SEL_O_MSK 0x00001000
+#define PAD16_SEL_O_I_MSK 0xffffefff
+#define PAD16_SEL_O_SFT 12
+#define PAD16_SEL_O_HI 12
+#define PAD16_SEL_O_SZ 1
+#define TEST_2_ID_MSK 0x10000000
+#define TEST_2_ID_I_MSK 0xefffffff
+#define TEST_2_ID_SFT 28
+#define TEST_2_ID_HI 28
+#define TEST_2_ID_SZ 1
+#define PAD17_OE_MSK 0x00000001
+#define PAD17_OE_I_MSK 0xfffffffe
+#define PAD17_OE_SFT 0
+#define PAD17_OE_HI 0
+#define PAD17_OE_SZ 1
+#define PAD17_PE_MSK 0x00000002
+#define PAD17_PE_I_MSK 0xfffffffd
+#define PAD17_PE_SFT 1
+#define PAD17_PE_HI 1
+#define PAD17_PE_SZ 1
+#define PAD17_DS_MSK 0x00000004
+#define PAD17_DS_I_MSK 0xfffffffb
+#define PAD17_DS_SFT 2
+#define PAD17_DS_HI 2
+#define PAD17_DS_SZ 1
+#define PAD17_IE_MSK 0x00000008
+#define PAD17_IE_I_MSK 0xfffffff7
+#define PAD17_IE_SFT 3
+#define PAD17_IE_HI 3
+#define PAD17_IE_SZ 1
+#define PAD17_SEL_I_MSK 0x00000030
+#define PAD17_SEL_I_I_MSK 0xffffffcf
+#define PAD17_SEL_I_SFT 4
+#define PAD17_SEL_I_HI 5
+#define PAD17_SEL_I_SZ 2
+#define PAD17_OD_MSK 0x00000100
+#define PAD17_OD_I_MSK 0xfffffeff
+#define PAD17_OD_SFT 8
+#define PAD17_OD_HI 8
+#define PAD17_OD_SZ 1
+#define PAD17_SEL_O_MSK 0x00001000
+#define PAD17_SEL_O_I_MSK 0xffffefff
+#define PAD17_SEL_O_SFT 12
+#define PAD17_SEL_O_HI 12
+#define PAD17_SEL_O_SZ 1
+#define TEST_3_ID_MSK 0x10000000
+#define TEST_3_ID_I_MSK 0xefffffff
+#define TEST_3_ID_SFT 28
+#define TEST_3_ID_HI 28
+#define TEST_3_ID_SZ 1
+#define PAD18_OE_MSK 0x00000001
+#define PAD18_OE_I_MSK 0xfffffffe
+#define PAD18_OE_SFT 0
+#define PAD18_OE_HI 0
+#define PAD18_OE_SZ 1
+#define PAD18_PE_MSK 0x00000002
+#define PAD18_PE_I_MSK 0xfffffffd
+#define PAD18_PE_SFT 1
+#define PAD18_PE_HI 1
+#define PAD18_PE_SZ 1
+#define PAD18_DS_MSK 0x00000004
+#define PAD18_DS_I_MSK 0xfffffffb
+#define PAD18_DS_SFT 2
+#define PAD18_DS_HI 2
+#define PAD18_DS_SZ 1
+#define PAD18_IE_MSK 0x00000008
+#define PAD18_IE_I_MSK 0xfffffff7
+#define PAD18_IE_SFT 3
+#define PAD18_IE_HI 3
+#define PAD18_IE_SZ 1
+#define PAD18_SEL_I_MSK 0x00000030
+#define PAD18_SEL_I_I_MSK 0xffffffcf
+#define PAD18_SEL_I_SFT 4
+#define PAD18_SEL_I_HI 5
+#define PAD18_SEL_I_SZ 2
+#define PAD18_OD_MSK 0x00000100
+#define PAD18_OD_I_MSK 0xfffffeff
+#define PAD18_OD_SFT 8
+#define PAD18_OD_HI 8
+#define PAD18_OD_SZ 1
+#define PAD18_SEL_O_MSK 0x00003000
+#define PAD18_SEL_O_I_MSK 0xffffcfff
+#define PAD18_SEL_O_SFT 12
+#define PAD18_SEL_O_HI 13
+#define PAD18_SEL_O_SZ 2
+#define TEST_4_ID_MSK 0x10000000
+#define TEST_4_ID_I_MSK 0xefffffff
+#define TEST_4_ID_SFT 28
+#define TEST_4_ID_HI 28
+#define TEST_4_ID_SZ 1
+#define PAD19_OE_MSK 0x00000001
+#define PAD19_OE_I_MSK 0xfffffffe
+#define PAD19_OE_SFT 0
+#define PAD19_OE_HI 0
+#define PAD19_OE_SZ 1
+#define PAD19_PE_MSK 0x00000002
+#define PAD19_PE_I_MSK 0xfffffffd
+#define PAD19_PE_SFT 1
+#define PAD19_PE_HI 1
+#define PAD19_PE_SZ 1
+#define PAD19_DS_MSK 0x00000004
+#define PAD19_DS_I_MSK 0xfffffffb
+#define PAD19_DS_SFT 2
+#define PAD19_DS_HI 2
+#define PAD19_DS_SZ 1
+#define PAD19_IE_MSK 0x00000008
+#define PAD19_IE_I_MSK 0xfffffff7
+#define PAD19_IE_SFT 3
+#define PAD19_IE_HI 3
+#define PAD19_IE_SZ 1
+#define PAD19_SEL_I_MSK 0x00000030
+#define PAD19_SEL_I_I_MSK 0xffffffcf
+#define PAD19_SEL_I_SFT 4
+#define PAD19_SEL_I_HI 5
+#define PAD19_SEL_I_SZ 2
+#define PAD19_OD_MSK 0x00000100
+#define PAD19_OD_I_MSK 0xfffffeff
+#define PAD19_OD_SFT 8
+#define PAD19_OD_HI 8
+#define PAD19_OD_SZ 1
+#define PAD19_SEL_O_MSK 0x00007000
+#define PAD19_SEL_O_I_MSK 0xffff8fff
+#define PAD19_SEL_O_SFT 12
+#define PAD19_SEL_O_HI 14
+#define PAD19_SEL_O_SZ 3
+#define SHORT_TO_20_ID_MSK 0x10000000
+#define SHORT_TO_20_ID_I_MSK 0xefffffff
+#define SHORT_TO_20_ID_SFT 28
+#define SHORT_TO_20_ID_HI 28
+#define SHORT_TO_20_ID_SZ 1
+#define PAD20_OE_MSK 0x00000001
+#define PAD20_OE_I_MSK 0xfffffffe
+#define PAD20_OE_SFT 0
+#define PAD20_OE_HI 0
+#define PAD20_OE_SZ 1
+#define PAD20_PE_MSK 0x00000002
+#define PAD20_PE_I_MSK 0xfffffffd
+#define PAD20_PE_SFT 1
+#define PAD20_PE_HI 1
+#define PAD20_PE_SZ 1
+#define PAD20_DS_MSK 0x00000004
+#define PAD20_DS_I_MSK 0xfffffffb
+#define PAD20_DS_SFT 2
+#define PAD20_DS_HI 2
+#define PAD20_DS_SZ 1
+#define PAD20_IE_MSK 0x00000008
+#define PAD20_IE_I_MSK 0xfffffff7
+#define PAD20_IE_SFT 3
+#define PAD20_IE_HI 3
+#define PAD20_IE_SZ 1
+#define PAD20_SEL_I_MSK 0x000000f0
+#define PAD20_SEL_I_I_MSK 0xffffff0f
+#define PAD20_SEL_I_SFT 4
+#define PAD20_SEL_I_HI 7
+#define PAD20_SEL_I_SZ 4
+#define PAD20_OD_MSK 0x00000100
+#define PAD20_OD_I_MSK 0xfffffeff
+#define PAD20_OD_SFT 8
+#define PAD20_OD_HI 8
+#define PAD20_OD_SZ 1
+#define PAD20_SEL_O_MSK 0x00003000
+#define PAD20_SEL_O_I_MSK 0xffffcfff
+#define PAD20_SEL_O_SFT 12
+#define PAD20_SEL_O_HI 13
+#define PAD20_SEL_O_SZ 2
+#define STRAP0_MSK 0x08000000
+#define STRAP0_I_MSK 0xf7ffffff
+#define STRAP0_SFT 27
+#define STRAP0_HI 27
+#define STRAP0_SZ 1
+#define GPIO_TEST_1_ID_MSK 0x10000000
+#define GPIO_TEST_1_ID_I_MSK 0xefffffff
+#define GPIO_TEST_1_ID_SFT 28
+#define GPIO_TEST_1_ID_HI 28
+#define GPIO_TEST_1_ID_SZ 1
+#define PAD21_OE_MSK 0x00000001
+#define PAD21_OE_I_MSK 0xfffffffe
+#define PAD21_OE_SFT 0
+#define PAD21_OE_HI 0
+#define PAD21_OE_SZ 1
+#define PAD21_PE_MSK 0x00000002
+#define PAD21_PE_I_MSK 0xfffffffd
+#define PAD21_PE_SFT 1
+#define PAD21_PE_HI 1
+#define PAD21_PE_SZ 1
+#define PAD21_DS_MSK 0x00000004
+#define PAD21_DS_I_MSK 0xfffffffb
+#define PAD21_DS_SFT 2
+#define PAD21_DS_HI 2
+#define PAD21_DS_SZ 1
+#define PAD21_IE_MSK 0x00000008
+#define PAD21_IE_I_MSK 0xfffffff7
+#define PAD21_IE_SFT 3
+#define PAD21_IE_HI 3
+#define PAD21_IE_SZ 1
+#define PAD21_SEL_I_MSK 0x00000070
+#define PAD21_SEL_I_I_MSK 0xffffff8f
+#define PAD21_SEL_I_SFT 4
+#define PAD21_SEL_I_HI 6
+#define PAD21_SEL_I_SZ 3
+#define PAD21_OD_MSK 0x00000100
+#define PAD21_OD_I_MSK 0xfffffeff
+#define PAD21_OD_SFT 8
+#define PAD21_OD_HI 8
+#define PAD21_OD_SZ 1
+#define PAD21_SEL_O_MSK 0x00003000
+#define PAD21_SEL_O_I_MSK 0xffffcfff
+#define PAD21_SEL_O_SFT 12
+#define PAD21_SEL_O_HI 13
+#define PAD21_SEL_O_SZ 2
+#define STRAP3_MSK 0x08000000
+#define STRAP3_I_MSK 0xf7ffffff
+#define STRAP3_SFT 27
+#define STRAP3_HI 27
+#define STRAP3_SZ 1
+#define GPIO_TEST_2_ID_MSK 0x10000000
+#define GPIO_TEST_2_ID_I_MSK 0xefffffff
+#define GPIO_TEST_2_ID_SFT 28
+#define GPIO_TEST_2_ID_HI 28
+#define GPIO_TEST_2_ID_SZ 1
+#define PAD22_OE_MSK 0x00000001
+#define PAD22_OE_I_MSK 0xfffffffe
+#define PAD22_OE_SFT 0
+#define PAD22_OE_HI 0
+#define PAD22_OE_SZ 1
+#define PAD22_PE_MSK 0x00000002
+#define PAD22_PE_I_MSK 0xfffffffd
+#define PAD22_PE_SFT 1
+#define PAD22_PE_HI 1
+#define PAD22_PE_SZ 1
+#define PAD22_DS_MSK 0x00000004
+#define PAD22_DS_I_MSK 0xfffffffb
+#define PAD22_DS_SFT 2
+#define PAD22_DS_HI 2
+#define PAD22_DS_SZ 1
+#define PAD22_IE_MSK 0x00000008
+#define PAD22_IE_I_MSK 0xfffffff7
+#define PAD22_IE_SFT 3
+#define PAD22_IE_HI 3
+#define PAD22_IE_SZ 1
+#define PAD22_SEL_I_MSK 0x00000070
+#define PAD22_SEL_I_I_MSK 0xffffff8f
+#define PAD22_SEL_I_SFT 4
+#define PAD22_SEL_I_HI 6
+#define PAD22_SEL_I_SZ 3
+#define PAD22_OD_MSK 0x00000100
+#define PAD22_OD_I_MSK 0xfffffeff
+#define PAD22_OD_SFT 8
+#define PAD22_OD_HI 8
+#define PAD22_OD_SZ 1
+#define PAD22_SEL_O_MSK 0x00007000
+#define PAD22_SEL_O_I_MSK 0xffff8fff
+#define PAD22_SEL_O_SFT 12
+#define PAD22_SEL_O_HI 14
+#define PAD22_SEL_O_SZ 3
+#define PAD22_SEL_OE_MSK 0x00100000
+#define PAD22_SEL_OE_I_MSK 0xffefffff
+#define PAD22_SEL_OE_SFT 20
+#define PAD22_SEL_OE_HI 20
+#define PAD22_SEL_OE_SZ 1
+#define GPIO_TEST_3_ID_MSK 0x10000000
+#define GPIO_TEST_3_ID_I_MSK 0xefffffff
+#define GPIO_TEST_3_ID_SFT 28
+#define GPIO_TEST_3_ID_HI 28
+#define GPIO_TEST_3_ID_SZ 1
+#define PAD24_OE_MSK 0x00000001
+#define PAD24_OE_I_MSK 0xfffffffe
+#define PAD24_OE_SFT 0
+#define PAD24_OE_HI 0
+#define PAD24_OE_SZ 1
+#define PAD24_PE_MSK 0x00000002
+#define PAD24_PE_I_MSK 0xfffffffd
+#define PAD24_PE_SFT 1
+#define PAD24_PE_HI 1
+#define PAD24_PE_SZ 1
+#define PAD24_DS_MSK 0x00000004
+#define PAD24_DS_I_MSK 0xfffffffb
+#define PAD24_DS_SFT 2
+#define PAD24_DS_HI 2
+#define PAD24_DS_SZ 1
+#define PAD24_IE_MSK 0x00000008
+#define PAD24_IE_I_MSK 0xfffffff7
+#define PAD24_IE_SFT 3
+#define PAD24_IE_HI 3
+#define PAD24_IE_SZ 1
+#define PAD24_SEL_I_MSK 0x00000030
+#define PAD24_SEL_I_I_MSK 0xffffffcf
+#define PAD24_SEL_I_SFT 4
+#define PAD24_SEL_I_HI 5
+#define PAD24_SEL_I_SZ 2
+#define PAD24_OD_MSK 0x00000100
+#define PAD24_OD_I_MSK 0xfffffeff
+#define PAD24_OD_SFT 8
+#define PAD24_OD_HI 8
+#define PAD24_OD_SZ 1
+#define PAD24_SEL_O_MSK 0x00007000
+#define PAD24_SEL_O_I_MSK 0xffff8fff
+#define PAD24_SEL_O_SFT 12
+#define PAD24_SEL_O_HI 14
+#define PAD24_SEL_O_SZ 3
+#define GPIO_TEST_4_ID_MSK 0x10000000
+#define GPIO_TEST_4_ID_I_MSK 0xefffffff
+#define GPIO_TEST_4_ID_SFT 28
+#define GPIO_TEST_4_ID_HI 28
+#define GPIO_TEST_4_ID_SZ 1
+#define PAD25_OE_MSK 0x00000001
+#define PAD25_OE_I_MSK 0xfffffffe
+#define PAD25_OE_SFT 0
+#define PAD25_OE_HI 0
+#define PAD25_OE_SZ 1
+#define PAD25_PE_MSK 0x00000002
+#define PAD25_PE_I_MSK 0xfffffffd
+#define PAD25_PE_SFT 1
+#define PAD25_PE_HI 1
+#define PAD25_PE_SZ 1
+#define PAD25_DS_MSK 0x00000004
+#define PAD25_DS_I_MSK 0xfffffffb
+#define PAD25_DS_SFT 2
+#define PAD25_DS_HI 2
+#define PAD25_DS_SZ 1
+#define PAD25_IE_MSK 0x00000008
+#define PAD25_IE_I_MSK 0xfffffff7
+#define PAD25_IE_SFT 3
+#define PAD25_IE_HI 3
+#define PAD25_IE_SZ 1
+#define PAD25_SEL_I_MSK 0x00000070
+#define PAD25_SEL_I_I_MSK 0xffffff8f
+#define PAD25_SEL_I_SFT 4
+#define PAD25_SEL_I_HI 6
+#define PAD25_SEL_I_SZ 3
+#define PAD25_OD_MSK 0x00000100
+#define PAD25_OD_I_MSK 0xfffffeff
+#define PAD25_OD_SFT 8
+#define PAD25_OD_HI 8
+#define PAD25_OD_SZ 1
+#define PAD25_SEL_O_MSK 0x00007000
+#define PAD25_SEL_O_I_MSK 0xffff8fff
+#define PAD25_SEL_O_SFT 12
+#define PAD25_SEL_O_HI 14
+#define PAD25_SEL_O_SZ 3
+#define PAD25_SEL_OE_MSK 0x00100000
+#define PAD25_SEL_OE_I_MSK 0xffefffff
+#define PAD25_SEL_OE_SFT 20
+#define PAD25_SEL_OE_HI 20
+#define PAD25_SEL_OE_SZ 1
+#define STRAP1_MSK 0x08000000
+#define STRAP1_I_MSK 0xf7ffffff
+#define STRAP1_SFT 27
+#define STRAP1_HI 27
+#define STRAP1_SZ 1
+#define GPIO_1_ID_MSK 0x10000000
+#define GPIO_1_ID_I_MSK 0xefffffff
+#define GPIO_1_ID_SFT 28
+#define GPIO_1_ID_HI 28
+#define GPIO_1_ID_SZ 1
+#define PAD27_OE_MSK 0x00000001
+#define PAD27_OE_I_MSK 0xfffffffe
+#define PAD27_OE_SFT 0
+#define PAD27_OE_HI 0
+#define PAD27_OE_SZ 1
+#define PAD27_PE_MSK 0x00000002
+#define PAD27_PE_I_MSK 0xfffffffd
+#define PAD27_PE_SFT 1
+#define PAD27_PE_HI 1
+#define PAD27_PE_SZ 1
+#define PAD27_DS_MSK 0x00000004
+#define PAD27_DS_I_MSK 0xfffffffb
+#define PAD27_DS_SFT 2
+#define PAD27_DS_HI 2
+#define PAD27_DS_SZ 1
+#define PAD27_IE_MSK 0x00000008
+#define PAD27_IE_I_MSK 0xfffffff7
+#define PAD27_IE_SFT 3
+#define PAD27_IE_HI 3
+#define PAD27_IE_SZ 1
+#define PAD27_SEL_I_MSK 0x00000070
+#define PAD27_SEL_I_I_MSK 0xffffff8f
+#define PAD27_SEL_I_SFT 4
+#define PAD27_SEL_I_HI 6
+#define PAD27_SEL_I_SZ 3
+#define PAD27_OD_MSK 0x00000100
+#define PAD27_OD_I_MSK 0xfffffeff
+#define PAD27_OD_SFT 8
+#define PAD27_OD_HI 8
+#define PAD27_OD_SZ 1
+#define PAD27_SEL_O_MSK 0x00007000
+#define PAD27_SEL_O_I_MSK 0xffff8fff
+#define PAD27_SEL_O_SFT 12
+#define PAD27_SEL_O_HI 14
+#define PAD27_SEL_O_SZ 3
+#define GPIO_2_ID_MSK 0x10000000
+#define GPIO_2_ID_I_MSK 0xefffffff
+#define GPIO_2_ID_SFT 28
+#define GPIO_2_ID_HI 28
+#define GPIO_2_ID_SZ 1
+#define PAD28_OE_MSK 0x00000001
+#define PAD28_OE_I_MSK 0xfffffffe
+#define PAD28_OE_SFT 0
+#define PAD28_OE_HI 0
+#define PAD28_OE_SZ 1
+#define PAD28_PE_MSK 0x00000002
+#define PAD28_PE_I_MSK 0xfffffffd
+#define PAD28_PE_SFT 1
+#define PAD28_PE_HI 1
+#define PAD28_PE_SZ 1
+#define PAD28_DS_MSK 0x00000004
+#define PAD28_DS_I_MSK 0xfffffffb
+#define PAD28_DS_SFT 2
+#define PAD28_DS_HI 2
+#define PAD28_DS_SZ 1
+#define PAD28_IE_MSK 0x00000008
+#define PAD28_IE_I_MSK 0xfffffff7
+#define PAD28_IE_SFT 3
+#define PAD28_IE_HI 3
+#define PAD28_IE_SZ 1
+#define PAD28_SEL_I_MSK 0x00000070
+#define PAD28_SEL_I_I_MSK 0xffffff8f
+#define PAD28_SEL_I_SFT 4
+#define PAD28_SEL_I_HI 6
+#define PAD28_SEL_I_SZ 3
+#define PAD28_OD_MSK 0x00000100
+#define PAD28_OD_I_MSK 0xfffffeff
+#define PAD28_OD_SFT 8
+#define PAD28_OD_HI 8
+#define PAD28_OD_SZ 1
+#define PAD28_SEL_O_MSK 0x0000f000
+#define PAD28_SEL_O_I_MSK 0xffff0fff
+#define PAD28_SEL_O_SFT 12
+#define PAD28_SEL_O_HI 15
+#define PAD28_SEL_O_SZ 4
+#define PAD28_SEL_OE_MSK 0x00100000
+#define PAD28_SEL_OE_I_MSK 0xffefffff
+#define PAD28_SEL_OE_SFT 20
+#define PAD28_SEL_OE_HI 20
+#define PAD28_SEL_OE_SZ 1
+#define GPIO_3_ID_MSK 0x10000000
+#define GPIO_3_ID_I_MSK 0xefffffff
+#define GPIO_3_ID_SFT 28
+#define GPIO_3_ID_HI 28
+#define GPIO_3_ID_SZ 1
+#define PAD29_OE_MSK 0x00000001
+#define PAD29_OE_I_MSK 0xfffffffe
+#define PAD29_OE_SFT 0
+#define PAD29_OE_HI 0
+#define PAD29_OE_SZ 1
+#define PAD29_PE_MSK 0x00000002
+#define PAD29_PE_I_MSK 0xfffffffd
+#define PAD29_PE_SFT 1
+#define PAD29_PE_HI 1
+#define PAD29_PE_SZ 1
+#define PAD29_DS_MSK 0x00000004
+#define PAD29_DS_I_MSK 0xfffffffb
+#define PAD29_DS_SFT 2
+#define PAD29_DS_HI 2
+#define PAD29_DS_SZ 1
+#define PAD29_IE_MSK 0x00000008
+#define PAD29_IE_I_MSK 0xfffffff7
+#define PAD29_IE_SFT 3
+#define PAD29_IE_HI 3
+#define PAD29_IE_SZ 1
+#define PAD29_SEL_I_MSK 0x00000070
+#define PAD29_SEL_I_I_MSK 0xffffff8f
+#define PAD29_SEL_I_SFT 4
+#define PAD29_SEL_I_HI 6
+#define PAD29_SEL_I_SZ 3
+#define PAD29_OD_MSK 0x00000100
+#define PAD29_OD_I_MSK 0xfffffeff
+#define PAD29_OD_SFT 8
+#define PAD29_OD_HI 8
+#define PAD29_OD_SZ 1
+#define PAD29_SEL_O_MSK 0x00007000
+#define PAD29_SEL_O_I_MSK 0xffff8fff
+#define PAD29_SEL_O_SFT 12
+#define PAD29_SEL_O_HI 14
+#define PAD29_SEL_O_SZ 3
+#define GPIO_TEST_5_ID_MSK 0x10000000
+#define GPIO_TEST_5_ID_I_MSK 0xefffffff
+#define GPIO_TEST_5_ID_SFT 28
+#define GPIO_TEST_5_ID_HI 28
+#define GPIO_TEST_5_ID_SZ 1
+#define PAD30_OE_MSK 0x00000001
+#define PAD30_OE_I_MSK 0xfffffffe
+#define PAD30_OE_SFT 0
+#define PAD30_OE_HI 0
+#define PAD30_OE_SZ 1
+#define PAD30_PE_MSK 0x00000002
+#define PAD30_PE_I_MSK 0xfffffffd
+#define PAD30_PE_SFT 1
+#define PAD30_PE_HI 1
+#define PAD30_PE_SZ 1
+#define PAD30_DS_MSK 0x00000004
+#define PAD30_DS_I_MSK 0xfffffffb
+#define PAD30_DS_SFT 2
+#define PAD30_DS_HI 2
+#define PAD30_DS_SZ 1
+#define PAD30_IE_MSK 0x00000008
+#define PAD30_IE_I_MSK 0xfffffff7
+#define PAD30_IE_SFT 3
+#define PAD30_IE_HI 3
+#define PAD30_IE_SZ 1
+#define PAD30_SEL_I_MSK 0x00000030
+#define PAD30_SEL_I_I_MSK 0xffffffcf
+#define PAD30_SEL_I_SFT 4
+#define PAD30_SEL_I_HI 5
+#define PAD30_SEL_I_SZ 2
+#define PAD30_OD_MSK 0x00000100
+#define PAD30_OD_I_MSK 0xfffffeff
+#define PAD30_OD_SFT 8
+#define PAD30_OD_HI 8
+#define PAD30_OD_SZ 1
+#define PAD30_SEL_O_MSK 0x00003000
+#define PAD30_SEL_O_I_MSK 0xffffcfff
+#define PAD30_SEL_O_SFT 12
+#define PAD30_SEL_O_HI 13
+#define PAD30_SEL_O_SZ 2
+#define TEST_6_ID_MSK 0x10000000
+#define TEST_6_ID_I_MSK 0xefffffff
+#define TEST_6_ID_SFT 28
+#define TEST_6_ID_HI 28
+#define TEST_6_ID_SZ 1
+#define PAD31_OE_MSK 0x00000001
+#define PAD31_OE_I_MSK 0xfffffffe
+#define PAD31_OE_SFT 0
+#define PAD31_OE_HI 0
+#define PAD31_OE_SZ 1
+#define PAD31_PE_MSK 0x00000002
+#define PAD31_PE_I_MSK 0xfffffffd
+#define PAD31_PE_SFT 1
+#define PAD31_PE_HI 1
+#define PAD31_PE_SZ 1
+#define PAD31_DS_MSK 0x00000004
+#define PAD31_DS_I_MSK 0xfffffffb
+#define PAD31_DS_SFT 2
+#define PAD31_DS_HI 2
+#define PAD31_DS_SZ 1
+#define PAD31_IE_MSK 0x00000008
+#define PAD31_IE_I_MSK 0xfffffff7
+#define PAD31_IE_SFT 3
+#define PAD31_IE_HI 3
+#define PAD31_IE_SZ 1
+#define PAD31_SEL_I_MSK 0x00000030
+#define PAD31_SEL_I_I_MSK 0xffffffcf
+#define PAD31_SEL_I_SFT 4
+#define PAD31_SEL_I_HI 5
+#define PAD31_SEL_I_SZ 2
+#define PAD31_OD_MSK 0x00000100
+#define PAD31_OD_I_MSK 0xfffffeff
+#define PAD31_OD_SFT 8
+#define PAD31_OD_HI 8
+#define PAD31_OD_SZ 1
+#define PAD31_SEL_O_MSK 0x00003000
+#define PAD31_SEL_O_I_MSK 0xffffcfff
+#define PAD31_SEL_O_SFT 12
+#define PAD31_SEL_O_HI 13
+#define PAD31_SEL_O_SZ 2
+#define TEST_7_ID_MSK 0x10000000
+#define TEST_7_ID_I_MSK 0xefffffff
+#define TEST_7_ID_SFT 28
+#define TEST_7_ID_HI 28
+#define TEST_7_ID_SZ 1
+#define PAD32_OE_MSK 0x00000001
+#define PAD32_OE_I_MSK 0xfffffffe
+#define PAD32_OE_SFT 0
+#define PAD32_OE_HI 0
+#define PAD32_OE_SZ 1
+#define PAD32_PE_MSK 0x00000002
+#define PAD32_PE_I_MSK 0xfffffffd
+#define PAD32_PE_SFT 1
+#define PAD32_PE_HI 1
+#define PAD32_PE_SZ 1
+#define PAD32_DS_MSK 0x00000004
+#define PAD32_DS_I_MSK 0xfffffffb
+#define PAD32_DS_SFT 2
+#define PAD32_DS_HI 2
+#define PAD32_DS_SZ 1
+#define PAD32_IE_MSK 0x00000008
+#define PAD32_IE_I_MSK 0xfffffff7
+#define PAD32_IE_SFT 3
+#define PAD32_IE_HI 3
+#define PAD32_IE_SZ 1
+#define PAD32_SEL_I_MSK 0x00000030
+#define PAD32_SEL_I_I_MSK 0xffffffcf
+#define PAD32_SEL_I_SFT 4
+#define PAD32_SEL_I_HI 5
+#define PAD32_SEL_I_SZ 2
+#define PAD32_OD_MSK 0x00000100
+#define PAD32_OD_I_MSK 0xfffffeff
+#define PAD32_OD_SFT 8
+#define PAD32_OD_HI 8
+#define PAD32_OD_SZ 1
+#define PAD32_SEL_O_MSK 0x00003000
+#define PAD32_SEL_O_I_MSK 0xffffcfff
+#define PAD32_SEL_O_SFT 12
+#define PAD32_SEL_O_HI 13
+#define PAD32_SEL_O_SZ 2
+#define TEST_8_ID_MSK 0x10000000
+#define TEST_8_ID_I_MSK 0xefffffff
+#define TEST_8_ID_SFT 28
+#define TEST_8_ID_HI 28
+#define TEST_8_ID_SZ 1
+#define PAD33_OE_MSK 0x00000001
+#define PAD33_OE_I_MSK 0xfffffffe
+#define PAD33_OE_SFT 0
+#define PAD33_OE_HI 0
+#define PAD33_OE_SZ 1
+#define PAD33_PE_MSK 0x00000002
+#define PAD33_PE_I_MSK 0xfffffffd
+#define PAD33_PE_SFT 1
+#define PAD33_PE_HI 1
+#define PAD33_PE_SZ 1
+#define PAD33_DS_MSK 0x00000004
+#define PAD33_DS_I_MSK 0xfffffffb
+#define PAD33_DS_SFT 2
+#define PAD33_DS_HI 2
+#define PAD33_DS_SZ 1
+#define PAD33_IE_MSK 0x00000008
+#define PAD33_IE_I_MSK 0xfffffff7
+#define PAD33_IE_SFT 3
+#define PAD33_IE_HI 3
+#define PAD33_IE_SZ 1
+#define PAD33_SEL_I_MSK 0x00000030
+#define PAD33_SEL_I_I_MSK 0xffffffcf
+#define PAD33_SEL_I_SFT 4
+#define PAD33_SEL_I_HI 5
+#define PAD33_SEL_I_SZ 2
+#define PAD33_OD_MSK 0x00000100
+#define PAD33_OD_I_MSK 0xfffffeff
+#define PAD33_OD_SFT 8
+#define PAD33_OD_HI 8
+#define PAD33_OD_SZ 1
+#define PAD33_SEL_O_MSK 0x00003000
+#define PAD33_SEL_O_I_MSK 0xffffcfff
+#define PAD33_SEL_O_SFT 12
+#define PAD33_SEL_O_HI 13
+#define PAD33_SEL_O_SZ 2
+#define TEST_9_ID_MSK 0x10000000
+#define TEST_9_ID_I_MSK 0xefffffff
+#define TEST_9_ID_SFT 28
+#define TEST_9_ID_HI 28
+#define TEST_9_ID_SZ 1
+#define PAD34_OE_MSK 0x00000001
+#define PAD34_OE_I_MSK 0xfffffffe
+#define PAD34_OE_SFT 0
+#define PAD34_OE_HI 0
+#define PAD34_OE_SZ 1
+#define PAD34_PE_MSK 0x00000002
+#define PAD34_PE_I_MSK 0xfffffffd
+#define PAD34_PE_SFT 1
+#define PAD34_PE_HI 1
+#define PAD34_PE_SZ 1
+#define PAD34_DS_MSK 0x00000004
+#define PAD34_DS_I_MSK 0xfffffffb
+#define PAD34_DS_SFT 2
+#define PAD34_DS_HI 2
+#define PAD34_DS_SZ 1
+#define PAD34_IE_MSK 0x00000008
+#define PAD34_IE_I_MSK 0xfffffff7
+#define PAD34_IE_SFT 3
+#define PAD34_IE_HI 3
+#define PAD34_IE_SZ 1
+#define PAD34_SEL_I_MSK 0x00000030
+#define PAD34_SEL_I_I_MSK 0xffffffcf
+#define PAD34_SEL_I_SFT 4
+#define PAD34_SEL_I_HI 5
+#define PAD34_SEL_I_SZ 2
+#define PAD34_OD_MSK 0x00000100
+#define PAD34_OD_I_MSK 0xfffffeff
+#define PAD34_OD_SFT 8
+#define PAD34_OD_HI 8
+#define PAD34_OD_SZ 1
+#define PAD34_SEL_O_MSK 0x00003000
+#define PAD34_SEL_O_I_MSK 0xffffcfff
+#define PAD34_SEL_O_SFT 12
+#define PAD34_SEL_O_HI 13
+#define PAD34_SEL_O_SZ 2
+#define TEST_10_ID_MSK 0x10000000
+#define TEST_10_ID_I_MSK 0xefffffff
+#define TEST_10_ID_SFT 28
+#define TEST_10_ID_HI 28
+#define TEST_10_ID_SZ 1
+#define PAD42_OE_MSK 0x00000001
+#define PAD42_OE_I_MSK 0xfffffffe
+#define PAD42_OE_SFT 0
+#define PAD42_OE_HI 0
+#define PAD42_OE_SZ 1
+#define PAD42_PE_MSK 0x00000002
+#define PAD42_PE_I_MSK 0xfffffffd
+#define PAD42_PE_SFT 1
+#define PAD42_PE_HI 1
+#define PAD42_PE_SZ 1
+#define PAD42_DS_MSK 0x00000004
+#define PAD42_DS_I_MSK 0xfffffffb
+#define PAD42_DS_SFT 2
+#define PAD42_DS_HI 2
+#define PAD42_DS_SZ 1
+#define PAD42_IE_MSK 0x00000008
+#define PAD42_IE_I_MSK 0xfffffff7
+#define PAD42_IE_SFT 3
+#define PAD42_IE_HI 3
+#define PAD42_IE_SZ 1
+#define PAD42_SEL_I_MSK 0x00000030
+#define PAD42_SEL_I_I_MSK 0xffffffcf
+#define PAD42_SEL_I_SFT 4
+#define PAD42_SEL_I_HI 5
+#define PAD42_SEL_I_SZ 2
+#define PAD42_OD_MSK 0x00000100
+#define PAD42_OD_I_MSK 0xfffffeff
+#define PAD42_OD_SFT 8
+#define PAD42_OD_HI 8
+#define PAD42_OD_SZ 1
+#define PAD42_SEL_O_MSK 0x00001000
+#define PAD42_SEL_O_I_MSK 0xffffefff
+#define PAD42_SEL_O_SFT 12
+#define PAD42_SEL_O_HI 12
+#define PAD42_SEL_O_SZ 1
+#define TEST_11_ID_MSK 0x10000000
+#define TEST_11_ID_I_MSK 0xefffffff
+#define TEST_11_ID_SFT 28
+#define TEST_11_ID_HI 28
+#define TEST_11_ID_SZ 1
+#define PAD43_OE_MSK 0x00000001
+#define PAD43_OE_I_MSK 0xfffffffe
+#define PAD43_OE_SFT 0
+#define PAD43_OE_HI 0
+#define PAD43_OE_SZ 1
+#define PAD43_PE_MSK 0x00000002
+#define PAD43_PE_I_MSK 0xfffffffd
+#define PAD43_PE_SFT 1
+#define PAD43_PE_HI 1
+#define PAD43_PE_SZ 1
+#define PAD43_DS_MSK 0x00000004
+#define PAD43_DS_I_MSK 0xfffffffb
+#define PAD43_DS_SFT 2
+#define PAD43_DS_HI 2
+#define PAD43_DS_SZ 1
+#define PAD43_IE_MSK 0x00000008
+#define PAD43_IE_I_MSK 0xfffffff7
+#define PAD43_IE_SFT 3
+#define PAD43_IE_HI 3
+#define PAD43_IE_SZ 1
+#define PAD43_SEL_I_MSK 0x00000030
+#define PAD43_SEL_I_I_MSK 0xffffffcf
+#define PAD43_SEL_I_SFT 4
+#define PAD43_SEL_I_HI 5
+#define PAD43_SEL_I_SZ 2
+#define PAD43_OD_MSK 0x00000100
+#define PAD43_OD_I_MSK 0xfffffeff
+#define PAD43_OD_SFT 8
+#define PAD43_OD_HI 8
+#define PAD43_OD_SZ 1
+#define PAD43_SEL_O_MSK 0x00001000
+#define PAD43_SEL_O_I_MSK 0xffffefff
+#define PAD43_SEL_O_SFT 12
+#define PAD43_SEL_O_HI 12
+#define PAD43_SEL_O_SZ 1
+#define TEST_12_ID_MSK 0x10000000
+#define TEST_12_ID_I_MSK 0xefffffff
+#define TEST_12_ID_SFT 28
+#define TEST_12_ID_HI 28
+#define TEST_12_ID_SZ 1
+#define PAD44_OE_MSK 0x00000001
+#define PAD44_OE_I_MSK 0xfffffffe
+#define PAD44_OE_SFT 0
+#define PAD44_OE_HI 0
+#define PAD44_OE_SZ 1
+#define PAD44_PE_MSK 0x00000002
+#define PAD44_PE_I_MSK 0xfffffffd
+#define PAD44_PE_SFT 1
+#define PAD44_PE_HI 1
+#define PAD44_PE_SZ 1
+#define PAD44_DS_MSK 0x00000004
+#define PAD44_DS_I_MSK 0xfffffffb
+#define PAD44_DS_SFT 2
+#define PAD44_DS_HI 2
+#define PAD44_DS_SZ 1
+#define PAD44_IE_MSK 0x00000008
+#define PAD44_IE_I_MSK 0xfffffff7
+#define PAD44_IE_SFT 3
+#define PAD44_IE_HI 3
+#define PAD44_IE_SZ 1
+#define PAD44_SEL_I_MSK 0x00000030
+#define PAD44_SEL_I_I_MSK 0xffffffcf
+#define PAD44_SEL_I_SFT 4
+#define PAD44_SEL_I_HI 5
+#define PAD44_SEL_I_SZ 2
+#define PAD44_OD_MSK 0x00000100
+#define PAD44_OD_I_MSK 0xfffffeff
+#define PAD44_OD_SFT 8
+#define PAD44_OD_HI 8
+#define PAD44_OD_SZ 1
+#define PAD44_SEL_O_MSK 0x00003000
+#define PAD44_SEL_O_I_MSK 0xffffcfff
+#define PAD44_SEL_O_SFT 12
+#define PAD44_SEL_O_HI 13
+#define PAD44_SEL_O_SZ 2
+#define TEST_13_ID_MSK 0x10000000
+#define TEST_13_ID_I_MSK 0xefffffff
+#define TEST_13_ID_SFT 28
+#define TEST_13_ID_HI 28
+#define TEST_13_ID_SZ 1
+#define PAD45_OE_MSK 0x00000001
+#define PAD45_OE_I_MSK 0xfffffffe
+#define PAD45_OE_SFT 0
+#define PAD45_OE_HI 0
+#define PAD45_OE_SZ 1
+#define PAD45_PE_MSK 0x00000002
+#define PAD45_PE_I_MSK 0xfffffffd
+#define PAD45_PE_SFT 1
+#define PAD45_PE_HI 1
+#define PAD45_PE_SZ 1
+#define PAD45_DS_MSK 0x00000004
+#define PAD45_DS_I_MSK 0xfffffffb
+#define PAD45_DS_SFT 2
+#define PAD45_DS_HI 2
+#define PAD45_DS_SZ 1
+#define PAD45_IE_MSK 0x00000008
+#define PAD45_IE_I_MSK 0xfffffff7
+#define PAD45_IE_SFT 3
+#define PAD45_IE_HI 3
+#define PAD45_IE_SZ 1
+#define PAD45_SEL_I_MSK 0x00000030
+#define PAD45_SEL_I_I_MSK 0xffffffcf
+#define PAD45_SEL_I_SFT 4
+#define PAD45_SEL_I_HI 5
+#define PAD45_SEL_I_SZ 2
+#define PAD45_OD_MSK 0x00000100
+#define PAD45_OD_I_MSK 0xfffffeff
+#define PAD45_OD_SFT 8
+#define PAD45_OD_HI 8
+#define PAD45_OD_SZ 1
+#define PAD45_SEL_O_MSK 0x00003000
+#define PAD45_SEL_O_I_MSK 0xffffcfff
+#define PAD45_SEL_O_SFT 12
+#define PAD45_SEL_O_HI 13
+#define PAD45_SEL_O_SZ 2
+#define TEST_14_ID_MSK 0x10000000
+#define TEST_14_ID_I_MSK 0xefffffff
+#define TEST_14_ID_SFT 28
+#define TEST_14_ID_HI 28
+#define TEST_14_ID_SZ 1
+#define PAD46_OE_MSK 0x00000001
+#define PAD46_OE_I_MSK 0xfffffffe
+#define PAD46_OE_SFT 0
+#define PAD46_OE_HI 0
+#define PAD46_OE_SZ 1
+#define PAD46_PE_MSK 0x00000002
+#define PAD46_PE_I_MSK 0xfffffffd
+#define PAD46_PE_SFT 1
+#define PAD46_PE_HI 1
+#define PAD46_PE_SZ 1
+#define PAD46_DS_MSK 0x00000004
+#define PAD46_DS_I_MSK 0xfffffffb
+#define PAD46_DS_SFT 2
+#define PAD46_DS_HI 2
+#define PAD46_DS_SZ 1
+#define PAD46_IE_MSK 0x00000008
+#define PAD46_IE_I_MSK 0xfffffff7
+#define PAD46_IE_SFT 3
+#define PAD46_IE_HI 3
+#define PAD46_IE_SZ 1
+#define PAD46_SEL_I_MSK 0x00000030
+#define PAD46_SEL_I_I_MSK 0xffffffcf
+#define PAD46_SEL_I_SFT 4
+#define PAD46_SEL_I_HI 5
+#define PAD46_SEL_I_SZ 2
+#define PAD46_OD_MSK 0x00000100
+#define PAD46_OD_I_MSK 0xfffffeff
+#define PAD46_OD_SFT 8
+#define PAD46_OD_HI 8
+#define PAD46_OD_SZ 1
+#define PAD46_SEL_O_MSK 0x00003000
+#define PAD46_SEL_O_I_MSK 0xffffcfff
+#define PAD46_SEL_O_SFT 12
+#define PAD46_SEL_O_HI 13
+#define PAD46_SEL_O_SZ 2
+#define TEST_15_ID_MSK 0x10000000
+#define TEST_15_ID_I_MSK 0xefffffff
+#define TEST_15_ID_SFT 28
+#define TEST_15_ID_HI 28
+#define TEST_15_ID_SZ 1
+#define PAD47_OE_MSK 0x00000001
+#define PAD47_OE_I_MSK 0xfffffffe
+#define PAD47_OE_SFT 0
+#define PAD47_OE_HI 0
+#define PAD47_OE_SZ 1
+#define PAD47_PE_MSK 0x00000002
+#define PAD47_PE_I_MSK 0xfffffffd
+#define PAD47_PE_SFT 1
+#define PAD47_PE_HI 1
+#define PAD47_PE_SZ 1
+#define PAD47_DS_MSK 0x00000004
+#define PAD47_DS_I_MSK 0xfffffffb
+#define PAD47_DS_SFT 2
+#define PAD47_DS_HI 2
+#define PAD47_DS_SZ 1
+#define PAD47_SEL_I_MSK 0x00000030
+#define PAD47_SEL_I_I_MSK 0xffffffcf
+#define PAD47_SEL_I_SFT 4
+#define PAD47_SEL_I_HI 5
+#define PAD47_SEL_I_SZ 2
+#define PAD47_OD_MSK 0x00000100
+#define PAD47_OD_I_MSK 0xfffffeff
+#define PAD47_OD_SFT 8
+#define PAD47_OD_HI 8
+#define PAD47_OD_SZ 1
+#define PAD47_SEL_O_MSK 0x00003000
+#define PAD47_SEL_O_I_MSK 0xffffcfff
+#define PAD47_SEL_O_SFT 12
+#define PAD47_SEL_O_HI 13
+#define PAD47_SEL_O_SZ 2
+#define PAD47_SEL_OE_MSK 0x00100000
+#define PAD47_SEL_OE_I_MSK 0xffefffff
+#define PAD47_SEL_OE_SFT 20
+#define PAD47_SEL_OE_HI 20
+#define PAD47_SEL_OE_SZ 1
+#define GPIO_9_ID_MSK 0x10000000
+#define GPIO_9_ID_I_MSK 0xefffffff
+#define GPIO_9_ID_SFT 28
+#define GPIO_9_ID_HI 28
+#define GPIO_9_ID_SZ 1
+#define PAD48_OE_MSK 0x00000001
+#define PAD48_OE_I_MSK 0xfffffffe
+#define PAD48_OE_SFT 0
+#define PAD48_OE_HI 0
+#define PAD48_OE_SZ 1
+#define PAD48_PE_MSK 0x00000002
+#define PAD48_PE_I_MSK 0xfffffffd
+#define PAD48_PE_SFT 1
+#define PAD48_PE_HI 1
+#define PAD48_PE_SZ 1
+#define PAD48_DS_MSK 0x00000004
+#define PAD48_DS_I_MSK 0xfffffffb
+#define PAD48_DS_SFT 2
+#define PAD48_DS_HI 2
+#define PAD48_DS_SZ 1
+#define PAD48_IE_MSK 0x00000008
+#define PAD48_IE_I_MSK 0xfffffff7
+#define PAD48_IE_SFT 3
+#define PAD48_IE_HI 3
+#define PAD48_IE_SZ 1
+#define PAD48_SEL_I_MSK 0x00000070
+#define PAD48_SEL_I_I_MSK 0xffffff8f
+#define PAD48_SEL_I_SFT 4
+#define PAD48_SEL_I_HI 6
+#define PAD48_SEL_I_SZ 3
+#define PAD48_OD_MSK 0x00000100
+#define PAD48_OD_I_MSK 0xfffffeff
+#define PAD48_OD_SFT 8
+#define PAD48_OD_HI 8
+#define PAD48_OD_SZ 1
+#define PAD48_PE_SEL_MSK 0x00000800
+#define PAD48_PE_SEL_I_MSK 0xfffff7ff
+#define PAD48_PE_SEL_SFT 11
+#define PAD48_PE_SEL_HI 11
+#define PAD48_PE_SEL_SZ 1
+#define PAD48_SEL_O_MSK 0x00003000
+#define PAD48_SEL_O_I_MSK 0xffffcfff
+#define PAD48_SEL_O_SFT 12
+#define PAD48_SEL_O_HI 13
+#define PAD48_SEL_O_SZ 2
+#define PAD48_SEL_OE_MSK 0x00100000
+#define PAD48_SEL_OE_I_MSK 0xffefffff
+#define PAD48_SEL_OE_SFT 20
+#define PAD48_SEL_OE_HI 20
+#define PAD48_SEL_OE_SZ 1
+#define GPIO_10_ID_MSK 0x10000000
+#define GPIO_10_ID_I_MSK 0xefffffff
+#define GPIO_10_ID_SFT 28
+#define GPIO_10_ID_HI 28
+#define GPIO_10_ID_SZ 1
+#define PAD49_OE_MSK 0x00000001
+#define PAD49_OE_I_MSK 0xfffffffe
+#define PAD49_OE_SFT 0
+#define PAD49_OE_HI 0
+#define PAD49_OE_SZ 1
+#define PAD49_PE_MSK 0x00000002
+#define PAD49_PE_I_MSK 0xfffffffd
+#define PAD49_PE_SFT 1
+#define PAD49_PE_HI 1
+#define PAD49_PE_SZ 1
+#define PAD49_DS_MSK 0x00000004
+#define PAD49_DS_I_MSK 0xfffffffb
+#define PAD49_DS_SFT 2
+#define PAD49_DS_HI 2
+#define PAD49_DS_SZ 1
+#define PAD49_IE_MSK 0x00000008
+#define PAD49_IE_I_MSK 0xfffffff7
+#define PAD49_IE_SFT 3
+#define PAD49_IE_HI 3
+#define PAD49_IE_SZ 1
+#define PAD49_SEL_I_MSK 0x00000070
+#define PAD49_SEL_I_I_MSK 0xffffff8f
+#define PAD49_SEL_I_SFT 4
+#define PAD49_SEL_I_HI 6
+#define PAD49_SEL_I_SZ 3
+#define PAD49_OD_MSK 0x00000100
+#define PAD49_OD_I_MSK 0xfffffeff
+#define PAD49_OD_SFT 8
+#define PAD49_OD_HI 8
+#define PAD49_OD_SZ 1
+#define PAD49_SEL_O_MSK 0x00003000
+#define PAD49_SEL_O_I_MSK 0xffffcfff
+#define PAD49_SEL_O_SFT 12
+#define PAD49_SEL_O_HI 13
+#define PAD49_SEL_O_SZ 2
+#define PAD49_SEL_OE_MSK 0x00100000
+#define PAD49_SEL_OE_I_MSK 0xffefffff
+#define PAD49_SEL_OE_SFT 20
+#define PAD49_SEL_OE_HI 20
+#define PAD49_SEL_OE_SZ 1
+#define GPIO_11_ID_MSK 0x10000000
+#define GPIO_11_ID_I_MSK 0xefffffff
+#define GPIO_11_ID_SFT 28
+#define GPIO_11_ID_HI 28
+#define GPIO_11_ID_SZ 1
+#define PAD50_OE_MSK 0x00000001
+#define PAD50_OE_I_MSK 0xfffffffe
+#define PAD50_OE_SFT 0
+#define PAD50_OE_HI 0
+#define PAD50_OE_SZ 1
+#define PAD50_PE_MSK 0x00000002
+#define PAD50_PE_I_MSK 0xfffffffd
+#define PAD50_PE_SFT 1
+#define PAD50_PE_HI 1
+#define PAD50_PE_SZ 1
+#define PAD50_DS_MSK 0x00000004
+#define PAD50_DS_I_MSK 0xfffffffb
+#define PAD50_DS_SFT 2
+#define PAD50_DS_HI 2
+#define PAD50_DS_SZ 1
+#define PAD50_IE_MSK 0x00000008
+#define PAD50_IE_I_MSK 0xfffffff7
+#define PAD50_IE_SFT 3
+#define PAD50_IE_HI 3
+#define PAD50_IE_SZ 1
+#define PAD50_SEL_I_MSK 0x00000070
+#define PAD50_SEL_I_I_MSK 0xffffff8f
+#define PAD50_SEL_I_SFT 4
+#define PAD50_SEL_I_HI 6
+#define PAD50_SEL_I_SZ 3
+#define PAD50_OD_MSK 0x00000100
+#define PAD50_OD_I_MSK 0xfffffeff
+#define PAD50_OD_SFT 8
+#define PAD50_OD_HI 8
+#define PAD50_OD_SZ 1
+#define PAD50_SEL_O_MSK 0x00003000
+#define PAD50_SEL_O_I_MSK 0xffffcfff
+#define PAD50_SEL_O_SFT 12
+#define PAD50_SEL_O_HI 13
+#define PAD50_SEL_O_SZ 2
+#define PAD50_SEL_OE_MSK 0x00100000
+#define PAD50_SEL_OE_I_MSK 0xffefffff
+#define PAD50_SEL_OE_SFT 20
+#define PAD50_SEL_OE_HI 20
+#define PAD50_SEL_OE_SZ 1
+#define GPIO_12_ID_MSK 0x10000000
+#define GPIO_12_ID_I_MSK 0xefffffff
+#define GPIO_12_ID_SFT 28
+#define GPIO_12_ID_HI 28
+#define GPIO_12_ID_SZ 1
+#define PAD51_OE_MSK 0x00000001
+#define PAD51_OE_I_MSK 0xfffffffe
+#define PAD51_OE_SFT 0
+#define PAD51_OE_HI 0
+#define PAD51_OE_SZ 1
+#define PAD51_PE_MSK 0x00000002
+#define PAD51_PE_I_MSK 0xfffffffd
+#define PAD51_PE_SFT 1
+#define PAD51_PE_HI 1
+#define PAD51_PE_SZ 1
+#define PAD51_DS_MSK 0x00000004
+#define PAD51_DS_I_MSK 0xfffffffb
+#define PAD51_DS_SFT 2
+#define PAD51_DS_HI 2
+#define PAD51_DS_SZ 1
+#define PAD51_IE_MSK 0x00000008
+#define PAD51_IE_I_MSK 0xfffffff7
+#define PAD51_IE_SFT 3
+#define PAD51_IE_HI 3
+#define PAD51_IE_SZ 1
+#define PAD51_SEL_I_MSK 0x00000030
+#define PAD51_SEL_I_I_MSK 0xffffffcf
+#define PAD51_SEL_I_SFT 4
+#define PAD51_SEL_I_HI 5
+#define PAD51_SEL_I_SZ 2
+#define PAD51_OD_MSK 0x00000100
+#define PAD51_OD_I_MSK 0xfffffeff
+#define PAD51_OD_SFT 8
+#define PAD51_OD_HI 8
+#define PAD51_OD_SZ 1
+#define PAD51_SEL_O_MSK 0x00001000
+#define PAD51_SEL_O_I_MSK 0xffffefff
+#define PAD51_SEL_O_SFT 12
+#define PAD51_SEL_O_HI 12
+#define PAD51_SEL_O_SZ 1
+#define PAD51_SEL_OE_MSK 0x00100000
+#define PAD51_SEL_OE_I_MSK 0xffefffff
+#define PAD51_SEL_OE_SFT 20
+#define PAD51_SEL_OE_HI 20
+#define PAD51_SEL_OE_SZ 1
+#define GPIO_13_ID_MSK 0x10000000
+#define GPIO_13_ID_I_MSK 0xefffffff
+#define GPIO_13_ID_SFT 28
+#define GPIO_13_ID_HI 28
+#define GPIO_13_ID_SZ 1
+#define PAD52_OE_MSK 0x00000001
+#define PAD52_OE_I_MSK 0xfffffffe
+#define PAD52_OE_SFT 0
+#define PAD52_OE_HI 0
+#define PAD52_OE_SZ 1
+#define PAD52_PE_MSK 0x00000002
+#define PAD52_PE_I_MSK 0xfffffffd
+#define PAD52_PE_SFT 1
+#define PAD52_PE_HI 1
+#define PAD52_PE_SZ 1
+#define PAD52_DS_MSK 0x00000004
+#define PAD52_DS_I_MSK 0xfffffffb
+#define PAD52_DS_SFT 2
+#define PAD52_DS_HI 2
+#define PAD52_DS_SZ 1
+#define PAD52_SEL_I_MSK 0x00000030
+#define PAD52_SEL_I_I_MSK 0xffffffcf
+#define PAD52_SEL_I_SFT 4
+#define PAD52_SEL_I_HI 5
+#define PAD52_SEL_I_SZ 2
+#define PAD52_OD_MSK 0x00000100
+#define PAD52_OD_I_MSK 0xfffffeff
+#define PAD52_OD_SFT 8
+#define PAD52_OD_HI 8
+#define PAD52_OD_SZ 1
+#define PAD52_SEL_O_MSK 0x00001000
+#define PAD52_SEL_O_I_MSK 0xffffefff
+#define PAD52_SEL_O_SFT 12
+#define PAD52_SEL_O_HI 12
+#define PAD52_SEL_O_SZ 1
+#define PAD52_SEL_OE_MSK 0x00100000
+#define PAD52_SEL_OE_I_MSK 0xffefffff
+#define PAD52_SEL_OE_SFT 20
+#define PAD52_SEL_OE_HI 20
+#define PAD52_SEL_OE_SZ 1
+#define GPIO_14_ID_MSK 0x10000000
+#define GPIO_14_ID_I_MSK 0xefffffff
+#define GPIO_14_ID_SFT 28
+#define GPIO_14_ID_HI 28
+#define GPIO_14_ID_SZ 1
+#define PAD53_OE_MSK 0x00000001
+#define PAD53_OE_I_MSK 0xfffffffe
+#define PAD53_OE_SFT 0
+#define PAD53_OE_HI 0
+#define PAD53_OE_SZ 1
+#define PAD53_PE_MSK 0x00000002
+#define PAD53_PE_I_MSK 0xfffffffd
+#define PAD53_PE_SFT 1
+#define PAD53_PE_HI 1
+#define PAD53_PE_SZ 1
+#define PAD53_DS_MSK 0x00000004
+#define PAD53_DS_I_MSK 0xfffffffb
+#define PAD53_DS_SFT 2
+#define PAD53_DS_HI 2
+#define PAD53_DS_SZ 1
+#define PAD53_IE_MSK 0x00000008
+#define PAD53_IE_I_MSK 0xfffffff7
+#define PAD53_IE_SFT 3
+#define PAD53_IE_HI 3
+#define PAD53_IE_SZ 1
+#define PAD53_SEL_I_MSK 0x00000030
+#define PAD53_SEL_I_I_MSK 0xffffffcf
+#define PAD53_SEL_I_SFT 4
+#define PAD53_SEL_I_HI 5
+#define PAD53_SEL_I_SZ 2
+#define PAD53_OD_MSK 0x00000100
+#define PAD53_OD_I_MSK 0xfffffeff
+#define PAD53_OD_SFT 8
+#define PAD53_OD_HI 8
+#define PAD53_OD_SZ 1
+#define PAD53_SEL_O_MSK 0x00001000
+#define PAD53_SEL_O_I_MSK 0xffffefff
+#define PAD53_SEL_O_SFT 12
+#define PAD53_SEL_O_HI 12
+#define PAD53_SEL_O_SZ 1
+#define JTAG_TMS_ID_MSK 0x10000000
+#define JTAG_TMS_ID_I_MSK 0xefffffff
+#define JTAG_TMS_ID_SFT 28
+#define JTAG_TMS_ID_HI 28
+#define JTAG_TMS_ID_SZ 1
+#define PAD54_OE_MSK 0x00000001
+#define PAD54_OE_I_MSK 0xfffffffe
+#define PAD54_OE_SFT 0
+#define PAD54_OE_HI 0
+#define PAD54_OE_SZ 1
+#define PAD54_PE_MSK 0x00000002
+#define PAD54_PE_I_MSK 0xfffffffd
+#define PAD54_PE_SFT 1
+#define PAD54_PE_HI 1
+#define PAD54_PE_SZ 1
+#define PAD54_DS_MSK 0x00000004
+#define PAD54_DS_I_MSK 0xfffffffb
+#define PAD54_DS_SFT 2
+#define PAD54_DS_HI 2
+#define PAD54_DS_SZ 1
+#define PAD54_OD_MSK 0x00000100
+#define PAD54_OD_I_MSK 0xfffffeff
+#define PAD54_OD_SFT 8
+#define PAD54_OD_HI 8
+#define PAD54_OD_SZ 1
+#define PAD54_SEL_O_MSK 0x00003000
+#define PAD54_SEL_O_I_MSK 0xffffcfff
+#define PAD54_SEL_O_SFT 12
+#define PAD54_SEL_O_HI 13
+#define PAD54_SEL_O_SZ 2
+#define JTAG_TCK_ID_MSK 0x10000000
+#define JTAG_TCK_ID_I_MSK 0xefffffff
+#define JTAG_TCK_ID_SFT 28
+#define JTAG_TCK_ID_HI 28
+#define JTAG_TCK_ID_SZ 1
+#define PAD56_PE_MSK 0x00000002
+#define PAD56_PE_I_MSK 0xfffffffd
+#define PAD56_PE_SFT 1
+#define PAD56_PE_HI 1
+#define PAD56_PE_SZ 1
+#define PAD56_DS_MSK 0x00000004
+#define PAD56_DS_I_MSK 0xfffffffb
+#define PAD56_DS_SFT 2
+#define PAD56_DS_HI 2
+#define PAD56_DS_SZ 1
+#define PAD56_SEL_I_MSK 0x00000010
+#define PAD56_SEL_I_I_MSK 0xffffffef
+#define PAD56_SEL_I_SFT 4
+#define PAD56_SEL_I_HI 4
+#define PAD56_SEL_I_SZ 1
+#define PAD56_OD_MSK 0x00000100
+#define PAD56_OD_I_MSK 0xfffffeff
+#define PAD56_OD_SFT 8
+#define PAD56_OD_HI 8
+#define PAD56_OD_SZ 1
+#define JTAG_TDI_ID_MSK 0x10000000
+#define JTAG_TDI_ID_I_MSK 0xefffffff
+#define JTAG_TDI_ID_SFT 28
+#define JTAG_TDI_ID_HI 28
+#define JTAG_TDI_ID_SZ 1
+#define PAD57_OE_MSK 0x00000001
+#define PAD57_OE_I_MSK 0xfffffffe
+#define PAD57_OE_SFT 0
+#define PAD57_OE_HI 0
+#define PAD57_OE_SZ 1
+#define PAD57_PE_MSK 0x00000002
+#define PAD57_PE_I_MSK 0xfffffffd
+#define PAD57_PE_SFT 1
+#define PAD57_PE_HI 1
+#define PAD57_PE_SZ 1
+#define PAD57_DS_MSK 0x00000004
+#define PAD57_DS_I_MSK 0xfffffffb
+#define PAD57_DS_SFT 2
+#define PAD57_DS_HI 2
+#define PAD57_DS_SZ 1
+#define PAD57_IE_MSK 0x00000008
+#define PAD57_IE_I_MSK 0xfffffff7
+#define PAD57_IE_SFT 3
+#define PAD57_IE_HI 3
+#define PAD57_IE_SZ 1
+#define PAD57_SEL_I_MSK 0x00000030
+#define PAD57_SEL_I_I_MSK 0xffffffcf
+#define PAD57_SEL_I_SFT 4
+#define PAD57_SEL_I_HI 5
+#define PAD57_SEL_I_SZ 2
+#define PAD57_OD_MSK 0x00000100
+#define PAD57_OD_I_MSK 0xfffffeff
+#define PAD57_OD_SFT 8
+#define PAD57_OD_HI 8
+#define PAD57_OD_SZ 1
+#define PAD57_SEL_O_MSK 0x00003000
+#define PAD57_SEL_O_I_MSK 0xffffcfff
+#define PAD57_SEL_O_SFT 12
+#define PAD57_SEL_O_HI 13
+#define PAD57_SEL_O_SZ 2
+#define PAD57_SEL_OE_MSK 0x00100000
+#define PAD57_SEL_OE_I_MSK 0xffefffff
+#define PAD57_SEL_OE_SFT 20
+#define PAD57_SEL_OE_HI 20
+#define PAD57_SEL_OE_SZ 1
+#define JTAG_TDO_ID_MSK 0x10000000
+#define JTAG_TDO_ID_I_MSK 0xefffffff
+#define JTAG_TDO_ID_SFT 28
+#define JTAG_TDO_ID_HI 28
+#define JTAG_TDO_ID_SZ 1
+#define PAD58_OE_MSK 0x00000001
+#define PAD58_OE_I_MSK 0xfffffffe
+#define PAD58_OE_SFT 0
+#define PAD58_OE_HI 0
+#define PAD58_OE_SZ 1
+#define PAD58_PE_MSK 0x00000002
+#define PAD58_PE_I_MSK 0xfffffffd
+#define PAD58_PE_SFT 1
+#define PAD58_PE_HI 1
+#define PAD58_PE_SZ 1
+#define PAD58_DS_MSK 0x00000004
+#define PAD58_DS_I_MSK 0xfffffffb
+#define PAD58_DS_SFT 2
+#define PAD58_DS_HI 2
+#define PAD58_DS_SZ 1
+#define PAD58_IE_MSK 0x00000008
+#define PAD58_IE_I_MSK 0xfffffff7
+#define PAD58_IE_SFT 3
+#define PAD58_IE_HI 3
+#define PAD58_IE_SZ 1
+#define PAD58_SEL_I_MSK 0x00000030
+#define PAD58_SEL_I_I_MSK 0xffffffcf
+#define PAD58_SEL_I_SFT 4
+#define PAD58_SEL_I_HI 5
+#define PAD58_SEL_I_SZ 2
+#define PAD58_OD_MSK 0x00000100
+#define PAD58_OD_I_MSK 0xfffffeff
+#define PAD58_OD_SFT 8
+#define PAD58_OD_HI 8
+#define PAD58_OD_SZ 1
+#define PAD58_SEL_O_MSK 0x00001000
+#define PAD58_SEL_O_I_MSK 0xffffefff
+#define PAD58_SEL_O_SFT 12
+#define PAD58_SEL_O_HI 12
+#define PAD58_SEL_O_SZ 1
+#define TEST_16_ID_MSK 0x10000000
+#define TEST_16_ID_I_MSK 0xefffffff
+#define TEST_16_ID_SFT 28
+#define TEST_16_ID_HI 28
+#define TEST_16_ID_SZ 1
+#define PAD59_OE_MSK 0x00000001
+#define PAD59_OE_I_MSK 0xfffffffe
+#define PAD59_OE_SFT 0
+#define PAD59_OE_HI 0
+#define PAD59_OE_SZ 1
+#define PAD59_PE_MSK 0x00000002
+#define PAD59_PE_I_MSK 0xfffffffd
+#define PAD59_PE_SFT 1
+#define PAD59_PE_HI 1
+#define PAD59_PE_SZ 1
+#define PAD59_DS_MSK 0x00000004
+#define PAD59_DS_I_MSK 0xfffffffb
+#define PAD59_DS_SFT 2
+#define PAD59_DS_HI 2
+#define PAD59_DS_SZ 1
+#define PAD59_IE_MSK 0x00000008
+#define PAD59_IE_I_MSK 0xfffffff7
+#define PAD59_IE_SFT 3
+#define PAD59_IE_HI 3
+#define PAD59_IE_SZ 1
+#define PAD59_SEL_I_MSK 0x00000030
+#define PAD59_SEL_I_I_MSK 0xffffffcf
+#define PAD59_SEL_I_SFT 4
+#define PAD59_SEL_I_HI 5
+#define PAD59_SEL_I_SZ 2
+#define PAD59_OD_MSK 0x00000100
+#define PAD59_OD_I_MSK 0xfffffeff
+#define PAD59_OD_SFT 8
+#define PAD59_OD_HI 8
+#define PAD59_OD_SZ 1
+#define PAD59_SEL_O_MSK 0x00001000
+#define PAD59_SEL_O_I_MSK 0xffffefff
+#define PAD59_SEL_O_SFT 12
+#define PAD59_SEL_O_HI 12
+#define PAD59_SEL_O_SZ 1
+#define TEST_17_ID_MSK 0x10000000
+#define TEST_17_ID_I_MSK 0xefffffff
+#define TEST_17_ID_SFT 28
+#define TEST_17_ID_HI 28
+#define TEST_17_ID_SZ 1
+#define PAD60_OE_MSK 0x00000001
+#define PAD60_OE_I_MSK 0xfffffffe
+#define PAD60_OE_SFT 0
+#define PAD60_OE_HI 0
+#define PAD60_OE_SZ 1
+#define PAD60_PE_MSK 0x00000002
+#define PAD60_PE_I_MSK 0xfffffffd
+#define PAD60_PE_SFT 1
+#define PAD60_PE_HI 1
+#define PAD60_PE_SZ 1
+#define PAD60_DS_MSK 0x00000004
+#define PAD60_DS_I_MSK 0xfffffffb
+#define PAD60_DS_SFT 2
+#define PAD60_DS_HI 2
+#define PAD60_DS_SZ 1
+#define PAD60_IE_MSK 0x00000008
+#define PAD60_IE_I_MSK 0xfffffff7
+#define PAD60_IE_SFT 3
+#define PAD60_IE_HI 3
+#define PAD60_IE_SZ 1
+#define PAD60_SEL_I_MSK 0x00000030
+#define PAD60_SEL_I_I_MSK 0xffffffcf
+#define PAD60_SEL_I_SFT 4
+#define PAD60_SEL_I_HI 5
+#define PAD60_SEL_I_SZ 2
+#define PAD60_OD_MSK 0x00000100
+#define PAD60_OD_I_MSK 0xfffffeff
+#define PAD60_OD_SFT 8
+#define PAD60_OD_HI 8
+#define PAD60_OD_SZ 1
+#define PAD60_SEL_O_MSK 0x00001000
+#define PAD60_SEL_O_I_MSK 0xffffefff
+#define PAD60_SEL_O_SFT 12
+#define PAD60_SEL_O_HI 12
+#define PAD60_SEL_O_SZ 1
+#define TEST_18_ID_MSK 0x10000000
+#define TEST_18_ID_I_MSK 0xefffffff
+#define TEST_18_ID_SFT 28
+#define TEST_18_ID_HI 28
+#define TEST_18_ID_SZ 1
+#define PAD61_OE_MSK 0x00000001
+#define PAD61_OE_I_MSK 0xfffffffe
+#define PAD61_OE_SFT 0
+#define PAD61_OE_HI 0
+#define PAD61_OE_SZ 1
+#define PAD61_PE_MSK 0x00000002
+#define PAD61_PE_I_MSK 0xfffffffd
+#define PAD61_PE_SFT 1
+#define PAD61_PE_HI 1
+#define PAD61_PE_SZ 1
+#define PAD61_DS_MSK 0x00000004
+#define PAD61_DS_I_MSK 0xfffffffb
+#define PAD61_DS_SFT 2
+#define PAD61_DS_HI 2
+#define PAD61_DS_SZ 1
+#define PAD61_IE_MSK 0x00000008
+#define PAD61_IE_I_MSK 0xfffffff7
+#define PAD61_IE_SFT 3
+#define PAD61_IE_HI 3
+#define PAD61_IE_SZ 1
+#define PAD61_SEL_I_MSK 0x00000010
+#define PAD61_SEL_I_I_MSK 0xffffffef
+#define PAD61_SEL_I_SFT 4
+#define PAD61_SEL_I_HI 4
+#define PAD61_SEL_I_SZ 1
+#define PAD61_OD_MSK 0x00000100
+#define PAD61_OD_I_MSK 0xfffffeff
+#define PAD61_OD_SFT 8
+#define PAD61_OD_HI 8
+#define PAD61_OD_SZ 1
+#define PAD61_SEL_O_MSK 0x00003000
+#define PAD61_SEL_O_I_MSK 0xffffcfff
+#define PAD61_SEL_O_SFT 12
+#define PAD61_SEL_O_HI 13
+#define PAD61_SEL_O_SZ 2
+#define TEST_19_ID_MSK 0x10000000
+#define TEST_19_ID_I_MSK 0xefffffff
+#define TEST_19_ID_SFT 28
+#define TEST_19_ID_HI 28
+#define TEST_19_ID_SZ 1
+#define PAD62_OE_MSK 0x00000001
+#define PAD62_OE_I_MSK 0xfffffffe
+#define PAD62_OE_SFT 0
+#define PAD62_OE_HI 0
+#define PAD62_OE_SZ 1
+#define PAD62_PE_MSK 0x00000002
+#define PAD62_PE_I_MSK 0xfffffffd
+#define PAD62_PE_SFT 1
+#define PAD62_PE_HI 1
+#define PAD62_PE_SZ 1
+#define PAD62_DS_MSK 0x00000004
+#define PAD62_DS_I_MSK 0xfffffffb
+#define PAD62_DS_SFT 2
+#define PAD62_DS_HI 2
+#define PAD62_DS_SZ 1
+#define PAD62_IE_MSK 0x00000008
+#define PAD62_IE_I_MSK 0xfffffff7
+#define PAD62_IE_SFT 3
+#define PAD62_IE_HI 3
+#define PAD62_IE_SZ 1
+#define PAD62_SEL_I_MSK 0x00000010
+#define PAD62_SEL_I_I_MSK 0xffffffef
+#define PAD62_SEL_I_SFT 4
+#define PAD62_SEL_I_HI 4
+#define PAD62_SEL_I_SZ 1
+#define PAD62_OD_MSK 0x00000100
+#define PAD62_OD_I_MSK 0xfffffeff
+#define PAD62_OD_SFT 8
+#define PAD62_OD_HI 8
+#define PAD62_OD_SZ 1
+#define PAD62_SEL_O_MSK 0x00001000
+#define PAD62_SEL_O_I_MSK 0xffffefff
+#define PAD62_SEL_O_SFT 12
+#define PAD62_SEL_O_HI 12
+#define PAD62_SEL_O_SZ 1
+#define TEST_20_ID_MSK 0x10000000
+#define TEST_20_ID_I_MSK 0xefffffff
+#define TEST_20_ID_SFT 28
+#define TEST_20_ID_HI 28
+#define TEST_20_ID_SZ 1
+#define PAD64_OE_MSK 0x00000001
+#define PAD64_OE_I_MSK 0xfffffffe
+#define PAD64_OE_SFT 0
+#define PAD64_OE_HI 0
+#define PAD64_OE_SZ 1
+#define PAD64_PE_MSK 0x00000002
+#define PAD64_PE_I_MSK 0xfffffffd
+#define PAD64_PE_SFT 1
+#define PAD64_PE_HI 1
+#define PAD64_PE_SZ 1
+#define PAD64_DS_MSK 0x00000004
+#define PAD64_DS_I_MSK 0xfffffffb
+#define PAD64_DS_SFT 2
+#define PAD64_DS_HI 2
+#define PAD64_DS_SZ 1
+#define PAD64_IE_MSK 0x00000008
+#define PAD64_IE_I_MSK 0xfffffff7
+#define PAD64_IE_SFT 3
+#define PAD64_IE_HI 3
+#define PAD64_IE_SZ 1
+#define PAD64_SEL_I_MSK 0x00000070
+#define PAD64_SEL_I_I_MSK 0xffffff8f
+#define PAD64_SEL_I_SFT 4
+#define PAD64_SEL_I_HI 6
+#define PAD64_SEL_I_SZ 3
+#define PAD64_OD_MSK 0x00000100
+#define PAD64_OD_I_MSK 0xfffffeff
+#define PAD64_OD_SFT 8
+#define PAD64_OD_HI 8
+#define PAD64_OD_SZ 1
+#define PAD64_SEL_O_MSK 0x00003000
+#define PAD64_SEL_O_I_MSK 0xffffcfff
+#define PAD64_SEL_O_SFT 12
+#define PAD64_SEL_O_HI 13
+#define PAD64_SEL_O_SZ 2
+#define PAD64_SEL_OE_MSK 0x00100000
+#define PAD64_SEL_OE_I_MSK 0xffefffff
+#define PAD64_SEL_OE_SFT 20
+#define PAD64_SEL_OE_HI 20
+#define PAD64_SEL_OE_SZ 1
+#define GPIO_15_IP_ID_MSK 0x10000000
+#define GPIO_15_IP_ID_I_MSK 0xefffffff
+#define GPIO_15_IP_ID_SFT 28
+#define GPIO_15_IP_ID_HI 28
+#define GPIO_15_IP_ID_SZ 1
+#define PAD65_OE_MSK 0x00000001
+#define PAD65_OE_I_MSK 0xfffffffe
+#define PAD65_OE_SFT 0
+#define PAD65_OE_HI 0
+#define PAD65_OE_SZ 1
+#define PAD65_PE_MSK 0x00000002
+#define PAD65_PE_I_MSK 0xfffffffd
+#define PAD65_PE_SFT 1
+#define PAD65_PE_HI 1
+#define PAD65_PE_SZ 1
+#define PAD65_DS_MSK 0x00000004
+#define PAD65_DS_I_MSK 0xfffffffb
+#define PAD65_DS_SFT 2
+#define PAD65_DS_HI 2
+#define PAD65_DS_SZ 1
+#define PAD65_IE_MSK 0x00000008
+#define PAD65_IE_I_MSK 0xfffffff7
+#define PAD65_IE_SFT 3
+#define PAD65_IE_HI 3
+#define PAD65_IE_SZ 1
+#define PAD65_SEL_I_MSK 0x00000070
+#define PAD65_SEL_I_I_MSK 0xffffff8f
+#define PAD65_SEL_I_SFT 4
+#define PAD65_SEL_I_HI 6
+#define PAD65_SEL_I_SZ 3
+#define PAD65_OD_MSK 0x00000100
+#define PAD65_OD_I_MSK 0xfffffeff
+#define PAD65_OD_SFT 8
+#define PAD65_OD_HI 8
+#define PAD65_OD_SZ 1
+#define PAD65_SEL_O_MSK 0x00001000
+#define PAD65_SEL_O_I_MSK 0xffffefff
+#define PAD65_SEL_O_SFT 12
+#define PAD65_SEL_O_HI 12
+#define PAD65_SEL_O_SZ 1
+#define GPIO_TEST_7_IN_ID_MSK 0x10000000
+#define GPIO_TEST_7_IN_ID_I_MSK 0xefffffff
+#define GPIO_TEST_7_IN_ID_SFT 28
+#define GPIO_TEST_7_IN_ID_HI 28
+#define GPIO_TEST_7_IN_ID_SZ 1
+#define PAD66_OE_MSK 0x00000001
+#define PAD66_OE_I_MSK 0xfffffffe
+#define PAD66_OE_SFT 0
+#define PAD66_OE_HI 0
+#define PAD66_OE_SZ 1
+#define PAD66_PE_MSK 0x00000002
+#define PAD66_PE_I_MSK 0xfffffffd
+#define PAD66_PE_SFT 1
+#define PAD66_PE_HI 1
+#define PAD66_PE_SZ 1
+#define PAD66_DS_MSK 0x00000004
+#define PAD66_DS_I_MSK 0xfffffffb
+#define PAD66_DS_SFT 2
+#define PAD66_DS_HI 2
+#define PAD66_DS_SZ 1
+#define PAD66_IE_MSK 0x00000008
+#define PAD66_IE_I_MSK 0xfffffff7
+#define PAD66_IE_SFT 3
+#define PAD66_IE_HI 3
+#define PAD66_IE_SZ 1
+#define PAD66_SEL_I_MSK 0x00000030
+#define PAD66_SEL_I_I_MSK 0xffffffcf
+#define PAD66_SEL_I_SFT 4
+#define PAD66_SEL_I_HI 5
+#define PAD66_SEL_I_SZ 2
+#define PAD66_OD_MSK 0x00000100
+#define PAD66_OD_I_MSK 0xfffffeff
+#define PAD66_OD_SFT 8
+#define PAD66_OD_HI 8
+#define PAD66_OD_SZ 1
+#define PAD66_SEL_O_MSK 0x00003000
+#define PAD66_SEL_O_I_MSK 0xffffcfff
+#define PAD66_SEL_O_SFT 12
+#define PAD66_SEL_O_HI 13
+#define PAD66_SEL_O_SZ 2
+#define GPIO_17_QP_ID_MSK 0x10000000
+#define GPIO_17_QP_ID_I_MSK 0xefffffff
+#define GPIO_17_QP_ID_SFT 28
+#define GPIO_17_QP_ID_HI 28
+#define GPIO_17_QP_ID_SZ 1
+#define PAD68_OE_MSK 0x00000001
+#define PAD68_OE_I_MSK 0xfffffffe
+#define PAD68_OE_SFT 0
+#define PAD68_OE_HI 0
+#define PAD68_OE_SZ 1
+#define PAD68_PE_MSK 0x00000002
+#define PAD68_PE_I_MSK 0xfffffffd
+#define PAD68_PE_SFT 1
+#define PAD68_PE_HI 1
+#define PAD68_PE_SZ 1
+#define PAD68_DS_MSK 0x00000004
+#define PAD68_DS_I_MSK 0xfffffffb
+#define PAD68_DS_SFT 2
+#define PAD68_DS_HI 2
+#define PAD68_DS_SZ 1
+#define PAD68_IE_MSK 0x00000008
+#define PAD68_IE_I_MSK 0xfffffff7
+#define PAD68_IE_SFT 3
+#define PAD68_IE_HI 3
+#define PAD68_IE_SZ 1
+#define PAD68_OD_MSK 0x00000100
+#define PAD68_OD_I_MSK 0xfffffeff
+#define PAD68_OD_SFT 8
+#define PAD68_OD_HI 8
+#define PAD68_OD_SZ 1
+#define PAD68_SEL_O_MSK 0x00001000
+#define PAD68_SEL_O_I_MSK 0xffffefff
+#define PAD68_SEL_O_SFT 12
+#define PAD68_SEL_O_HI 12
+#define PAD68_SEL_O_SZ 1
+#define GPIO_19_ID_MSK 0x10000000
+#define GPIO_19_ID_I_MSK 0xefffffff
+#define GPIO_19_ID_SFT 28
+#define GPIO_19_ID_HI 28
+#define GPIO_19_ID_SZ 1
+#define PAD67_OE_MSK 0x00000001
+#define PAD67_OE_I_MSK 0xfffffffe
+#define PAD67_OE_SFT 0
+#define PAD67_OE_HI 0
+#define PAD67_OE_SZ 1
+#define PAD67_PE_MSK 0x00000002
+#define PAD67_PE_I_MSK 0xfffffffd
+#define PAD67_PE_SFT 1
+#define PAD67_PE_HI 1
+#define PAD67_PE_SZ 1
+#define PAD67_DS_MSK 0x00000004
+#define PAD67_DS_I_MSK 0xfffffffb
+#define PAD67_DS_SFT 2
+#define PAD67_DS_HI 2
+#define PAD67_DS_SZ 1
+#define PAD67_IE_MSK 0x00000008
+#define PAD67_IE_I_MSK 0xfffffff7
+#define PAD67_IE_SFT 3
+#define PAD67_IE_HI 3
+#define PAD67_IE_SZ 1
+#define PAD67_SEL_I_MSK 0x00000070
+#define PAD67_SEL_I_I_MSK 0xffffff8f
+#define PAD67_SEL_I_SFT 4
+#define PAD67_SEL_I_HI 6
+#define PAD67_SEL_I_SZ 3
+#define PAD67_OD_MSK 0x00000100
+#define PAD67_OD_I_MSK 0xfffffeff
+#define PAD67_OD_SFT 8
+#define PAD67_OD_HI 8
+#define PAD67_OD_SZ 1
+#define PAD67_SEL_O_MSK 0x00003000
+#define PAD67_SEL_O_I_MSK 0xffffcfff
+#define PAD67_SEL_O_SFT 12
+#define PAD67_SEL_O_HI 13
+#define PAD67_SEL_O_SZ 2
+#define GPIO_TEST_8_QN_ID_MSK 0x10000000
+#define GPIO_TEST_8_QN_ID_I_MSK 0xefffffff
+#define GPIO_TEST_8_QN_ID_SFT 28
+#define GPIO_TEST_8_QN_ID_HI 28
+#define GPIO_TEST_8_QN_ID_SZ 1
+#define PAD69_OE_MSK 0x00000001
+#define PAD69_OE_I_MSK 0xfffffffe
+#define PAD69_OE_SFT 0
+#define PAD69_OE_HI 0
+#define PAD69_OE_SZ 1
+#define PAD69_PE_MSK 0x00000002
+#define PAD69_PE_I_MSK 0xfffffffd
+#define PAD69_PE_SFT 1
+#define PAD69_PE_HI 1
+#define PAD69_PE_SZ 1
+#define PAD69_DS_MSK 0x00000004
+#define PAD69_DS_I_MSK 0xfffffffb
+#define PAD69_DS_SFT 2
+#define PAD69_DS_HI 2
+#define PAD69_DS_SZ 1
+#define PAD69_IE_MSK 0x00000008
+#define PAD69_IE_I_MSK 0xfffffff7
+#define PAD69_IE_SFT 3
+#define PAD69_IE_HI 3
+#define PAD69_IE_SZ 1
+#define PAD69_SEL_I_MSK 0x00000030
+#define PAD69_SEL_I_I_MSK 0xffffffcf
+#define PAD69_SEL_I_SFT 4
+#define PAD69_SEL_I_HI 5
+#define PAD69_SEL_I_SZ 2
+#define PAD69_OD_MSK 0x00000100
+#define PAD69_OD_I_MSK 0xfffffeff
+#define PAD69_OD_SFT 8
+#define PAD69_OD_HI 8
+#define PAD69_OD_SZ 1
+#define PAD69_SEL_O_MSK 0x00001000
+#define PAD69_SEL_O_I_MSK 0xffffefff
+#define PAD69_SEL_O_SFT 12
+#define PAD69_SEL_O_HI 12
+#define PAD69_SEL_O_SZ 1
+#define STRAP2_MSK 0x08000000
+#define STRAP2_I_MSK 0xf7ffffff
+#define STRAP2_SFT 27
+#define STRAP2_HI 27
+#define STRAP2_SZ 1
+#define GPIO_20_ID_MSK 0x10000000
+#define GPIO_20_ID_I_MSK 0xefffffff
+#define GPIO_20_ID_SFT 28
+#define GPIO_20_ID_HI 28
+#define GPIO_20_ID_SZ 1
+#define PAD70_OE_MSK 0x00000001
+#define PAD70_OE_I_MSK 0xfffffffe
+#define PAD70_OE_SFT 0
+#define PAD70_OE_HI 0
+#define PAD70_OE_SZ 1
+#define PAD70_PE_MSK 0x00000002
+#define PAD70_PE_I_MSK 0xfffffffd
+#define PAD70_PE_SFT 1
+#define PAD70_PE_HI 1
+#define PAD70_PE_SZ 1
+#define PAD70_DS_MSK 0x00000004
+#define PAD70_DS_I_MSK 0xfffffffb
+#define PAD70_DS_SFT 2
+#define PAD70_DS_HI 2
+#define PAD70_DS_SZ 1
+#define PAD70_IE_MSK 0x00000008
+#define PAD70_IE_I_MSK 0xfffffff7
+#define PAD70_IE_SFT 3
+#define PAD70_IE_HI 3
+#define PAD70_IE_SZ 1
+#define PAD70_SEL_I_MSK 0x00000030
+#define PAD70_SEL_I_I_MSK 0xffffffcf
+#define PAD70_SEL_I_SFT 4
+#define PAD70_SEL_I_HI 5
+#define PAD70_SEL_I_SZ 2
+#define PAD70_OD_MSK 0x00000100
+#define PAD70_OD_I_MSK 0xfffffeff
+#define PAD70_OD_SFT 8
+#define PAD70_OD_HI 8
+#define PAD70_OD_SZ 1
+#define PAD70_SEL_O_MSK 0x00007000
+#define PAD70_SEL_O_I_MSK 0xffff8fff
+#define PAD70_SEL_O_SFT 12
+#define PAD70_SEL_O_HI 14
+#define PAD70_SEL_O_SZ 3
+#define GPIO_21_ID_MSK 0x10000000
+#define GPIO_21_ID_I_MSK 0xefffffff
+#define GPIO_21_ID_SFT 28
+#define GPIO_21_ID_HI 28
+#define GPIO_21_ID_SZ 1
+#define PAD231_OE_MSK 0x00000001
+#define PAD231_OE_I_MSK 0xfffffffe
+#define PAD231_OE_SFT 0
+#define PAD231_OE_HI 0
+#define PAD231_OE_SZ 1
+#define PAD231_PE_MSK 0x00000002
+#define PAD231_PE_I_MSK 0xfffffffd
+#define PAD231_PE_SFT 1
+#define PAD231_PE_HI 1
+#define PAD231_PE_SZ 1
+#define PAD231_DS_MSK 0x00000004
+#define PAD231_DS_I_MSK 0xfffffffb
+#define PAD231_DS_SFT 2
+#define PAD231_DS_HI 2
+#define PAD231_DS_SZ 1
+#define PAD231_IE_MSK 0x00000008
+#define PAD231_IE_I_MSK 0xfffffff7
+#define PAD231_IE_SFT 3
+#define PAD231_IE_HI 3
+#define PAD231_IE_SZ 1
+#define PAD231_OD_MSK 0x00000100
+#define PAD231_OD_I_MSK 0xfffffeff
+#define PAD231_OD_SFT 8
+#define PAD231_OD_HI 8
+#define PAD231_OD_SZ 1
+#define PIN_40_OR_56_ID_MSK 0x10000000
+#define PIN_40_OR_56_ID_I_MSK 0xefffffff
+#define PIN_40_OR_56_ID_SFT 28
+#define PIN_40_OR_56_ID_HI 28
+#define PIN_40_OR_56_ID_SZ 1
+#define MP_PHY2RX_DATA__0_SEL_MSK 0x00000001
+#define MP_PHY2RX_DATA__0_SEL_I_MSK 0xfffffffe
+#define MP_PHY2RX_DATA__0_SEL_SFT 0
+#define MP_PHY2RX_DATA__0_SEL_HI 0
+#define MP_PHY2RX_DATA__0_SEL_SZ 1
+#define MP_PHY2RX_DATA__1_SEL_MSK 0x00000002
+#define MP_PHY2RX_DATA__1_SEL_I_MSK 0xfffffffd
+#define MP_PHY2RX_DATA__1_SEL_SFT 1
+#define MP_PHY2RX_DATA__1_SEL_HI 1
+#define MP_PHY2RX_DATA__1_SEL_SZ 1
+#define MP_TX_FF_RPTR__1_SEL_MSK 0x00000004
+#define MP_TX_FF_RPTR__1_SEL_I_MSK 0xfffffffb
+#define MP_TX_FF_RPTR__1_SEL_SFT 2
+#define MP_TX_FF_RPTR__1_SEL_HI 2
+#define MP_TX_FF_RPTR__1_SEL_SZ 1
+#define MP_RX_FF_WPTR__2_SEL_MSK 0x00000008
+#define MP_RX_FF_WPTR__2_SEL_I_MSK 0xfffffff7
+#define MP_RX_FF_WPTR__2_SEL_SFT 3
+#define MP_RX_FF_WPTR__2_SEL_HI 3
+#define MP_RX_FF_WPTR__2_SEL_SZ 1
+#define MP_RX_FF_WPTR__1_SEL_MSK 0x00000010
+#define MP_RX_FF_WPTR__1_SEL_I_MSK 0xffffffef
+#define MP_RX_FF_WPTR__1_SEL_SFT 4
+#define MP_RX_FF_WPTR__1_SEL_HI 4
+#define MP_RX_FF_WPTR__1_SEL_SZ 1
+#define MP_RX_FF_WPTR__0_SEL_MSK 0x00000020
+#define MP_RX_FF_WPTR__0_SEL_I_MSK 0xffffffdf
+#define MP_RX_FF_WPTR__0_SEL_SFT 5
+#define MP_RX_FF_WPTR__0_SEL_HI 5
+#define MP_RX_FF_WPTR__0_SEL_SZ 1
+#define MP_PHY2RX_DATA__2_SEL_MSK 0x00000040
+#define MP_PHY2RX_DATA__2_SEL_I_MSK 0xffffffbf
+#define MP_PHY2RX_DATA__2_SEL_SFT 6
+#define MP_PHY2RX_DATA__2_SEL_HI 6
+#define MP_PHY2RX_DATA__2_SEL_SZ 1
+#define MP_PHY2RX_DATA__4_SEL_MSK 0x00000080
+#define MP_PHY2RX_DATA__4_SEL_I_MSK 0xffffff7f
+#define MP_PHY2RX_DATA__4_SEL_SFT 7
+#define MP_PHY2RX_DATA__4_SEL_HI 7
+#define MP_PHY2RX_DATA__4_SEL_SZ 1
+#define I2CM_SDA_ID_SEL_MSK 0x00000300
+#define I2CM_SDA_ID_SEL_I_MSK 0xfffffcff
+#define I2CM_SDA_ID_SEL_SFT 8
+#define I2CM_SDA_ID_SEL_HI 9
+#define I2CM_SDA_ID_SEL_SZ 2
+#define CRYSTAL_OUT_REQ_SEL_MSK 0x00000400
+#define CRYSTAL_OUT_REQ_SEL_I_MSK 0xfffffbff
+#define CRYSTAL_OUT_REQ_SEL_SFT 10
+#define CRYSTAL_OUT_REQ_SEL_HI 10
+#define CRYSTAL_OUT_REQ_SEL_SZ 1
+#define MP_PHY2RX_DATA__5_SEL_MSK 0x00000800
+#define MP_PHY2RX_DATA__5_SEL_I_MSK 0xfffff7ff
+#define MP_PHY2RX_DATA__5_SEL_SFT 11
+#define MP_PHY2RX_DATA__5_SEL_HI 11
+#define MP_PHY2RX_DATA__5_SEL_SZ 1
+#define MP_PHY2RX_DATA__3_SEL_MSK 0x00001000
+#define MP_PHY2RX_DATA__3_SEL_I_MSK 0xffffefff
+#define MP_PHY2RX_DATA__3_SEL_SFT 12
+#define MP_PHY2RX_DATA__3_SEL_HI 12
+#define MP_PHY2RX_DATA__3_SEL_SZ 1
+#define UART_RXD_SEL_MSK 0x00006000
+#define UART_RXD_SEL_I_MSK 0xffff9fff
+#define UART_RXD_SEL_SFT 13
+#define UART_RXD_SEL_HI 14
+#define UART_RXD_SEL_SZ 2
+#define MP_PHY2RX_DATA__6_SEL_MSK 0x00008000
+#define MP_PHY2RX_DATA__6_SEL_I_MSK 0xffff7fff
+#define MP_PHY2RX_DATA__6_SEL_SFT 15
+#define MP_PHY2RX_DATA__6_SEL_HI 15
+#define MP_PHY2RX_DATA__6_SEL_SZ 1
+#define DAT_UART_NCTS_SEL_MSK 0x00010000
+#define DAT_UART_NCTS_SEL_I_MSK 0xfffeffff
+#define DAT_UART_NCTS_SEL_SFT 16
+#define DAT_UART_NCTS_SEL_HI 16
+#define DAT_UART_NCTS_SEL_SZ 1
+#define GPIO_LOG_STOP_SEL_MSK 0x000e0000
+#define GPIO_LOG_STOP_SEL_I_MSK 0xfff1ffff
+#define GPIO_LOG_STOP_SEL_SFT 17
+#define GPIO_LOG_STOP_SEL_HI 19
+#define GPIO_LOG_STOP_SEL_SZ 3
+#define MP_TX_FF_RPTR__0_SEL_MSK 0x00100000
+#define MP_TX_FF_RPTR__0_SEL_I_MSK 0xffefffff
+#define MP_TX_FF_RPTR__0_SEL_SFT 20
+#define MP_TX_FF_RPTR__0_SEL_HI 20
+#define MP_TX_FF_RPTR__0_SEL_SZ 1
+#define MP_PHY_RX_WRST_N_SEL_MSK 0x00200000
+#define MP_PHY_RX_WRST_N_SEL_I_MSK 0xffdfffff
+#define MP_PHY_RX_WRST_N_SEL_SFT 21
+#define MP_PHY_RX_WRST_N_SEL_HI 21
+#define MP_PHY_RX_WRST_N_SEL_SZ 1
+#define EXT_32K_SEL_MSK 0x00c00000
+#define EXT_32K_SEL_I_MSK 0xff3fffff
+#define EXT_32K_SEL_SFT 22
+#define EXT_32K_SEL_HI 23
+#define EXT_32K_SEL_SZ 2
+#define MP_PHY2RX_DATA__7_SEL_MSK 0x01000000
+#define MP_PHY2RX_DATA__7_SEL_I_MSK 0xfeffffff
+#define MP_PHY2RX_DATA__7_SEL_SFT 24
+#define MP_PHY2RX_DATA__7_SEL_HI 24
+#define MP_PHY2RX_DATA__7_SEL_SZ 1
+#define MP_TX_FF_RPTR__2_SEL_MSK 0x02000000
+#define MP_TX_FF_RPTR__2_SEL_I_MSK 0xfdffffff
+#define MP_TX_FF_RPTR__2_SEL_SFT 25
+#define MP_TX_FF_RPTR__2_SEL_HI 25
+#define MP_TX_FF_RPTR__2_SEL_SZ 1
+#define PMUINT_WAKE_SEL_MSK 0x1c000000
+#define PMUINT_WAKE_SEL_I_MSK 0xe3ffffff
+#define PMUINT_WAKE_SEL_SFT 26
+#define PMUINT_WAKE_SEL_HI 28
+#define PMUINT_WAKE_SEL_SZ 3
+#define I2CM_SCL_ID_SEL_MSK 0x20000000
+#define I2CM_SCL_ID_SEL_I_MSK 0xdfffffff
+#define I2CM_SCL_ID_SEL_SFT 29
+#define I2CM_SCL_ID_SEL_HI 29
+#define I2CM_SCL_ID_SEL_SZ 1
+#define MP_MRX_RX_EN_SEL_MSK 0x40000000
+#define MP_MRX_RX_EN_SEL_I_MSK 0xbfffffff
+#define MP_MRX_RX_EN_SEL_SFT 30
+#define MP_MRX_RX_EN_SEL_HI 30
+#define MP_MRX_RX_EN_SEL_SZ 1
+#define DAT_UART_RXD_SEL_0_MSK 0x80000000
+#define DAT_UART_RXD_SEL_0_I_MSK 0x7fffffff
+#define DAT_UART_RXD_SEL_0_SFT 31
+#define DAT_UART_RXD_SEL_0_HI 31
+#define DAT_UART_RXD_SEL_0_SZ 1
+#define DAT_UART_RXD_SEL_1_MSK 0x00000001
+#define DAT_UART_RXD_SEL_1_I_MSK 0xfffffffe
+#define DAT_UART_RXD_SEL_1_SFT 0
+#define DAT_UART_RXD_SEL_1_HI 0
+#define DAT_UART_RXD_SEL_1_SZ 1
+#define SPI_DI_SEL_MSK 0x00000002
+#define SPI_DI_SEL_I_MSK 0xfffffffd
+#define SPI_DI_SEL_SFT 1
+#define SPI_DI_SEL_HI 1
+#define SPI_DI_SEL_SZ 1
+#define IO_PORT_REG_MSK 0x0001ffff
+#define IO_PORT_REG_I_MSK 0xfffe0000
+#define IO_PORT_REG_SFT 0
+#define IO_PORT_REG_HI 16
+#define IO_PORT_REG_SZ 17
+#define MASK_RX_INT_MSK 0x00000001
+#define MASK_RX_INT_I_MSK 0xfffffffe
+#define MASK_RX_INT_SFT 0
+#define MASK_RX_INT_HI 0
+#define MASK_RX_INT_SZ 1
+#define MASK_TX_INT_MSK 0x00000002
+#define MASK_TX_INT_I_MSK 0xfffffffd
+#define MASK_TX_INT_SFT 1
+#define MASK_TX_INT_HI 1
+#define MASK_TX_INT_SZ 1
+#define MASK_SOC_SYSTEM_INT_MSK 0x00000004
+#define MASK_SOC_SYSTEM_INT_I_MSK 0xfffffffb
+#define MASK_SOC_SYSTEM_INT_SFT 2
+#define MASK_SOC_SYSTEM_INT_HI 2
+#define MASK_SOC_SYSTEM_INT_SZ 1
+#define EDCA0_LOW_THR_INT_MASK_MSK 0x00000008
+#define EDCA0_LOW_THR_INT_MASK_I_MSK 0xfffffff7
+#define EDCA0_LOW_THR_INT_MASK_SFT 3
+#define EDCA0_LOW_THR_INT_MASK_HI 3
+#define EDCA0_LOW_THR_INT_MASK_SZ 1
+#define EDCA1_LOW_THR_INT_MASK_MSK 0x00000010
+#define EDCA1_LOW_THR_INT_MASK_I_MSK 0xffffffef
+#define EDCA1_LOW_THR_INT_MASK_SFT 4
+#define EDCA1_LOW_THR_INT_MASK_HI 4
+#define EDCA1_LOW_THR_INT_MASK_SZ 1
+#define EDCA2_LOW_THR_INT_MASK_MSK 0x00000020
+#define EDCA2_LOW_THR_INT_MASK_I_MSK 0xffffffdf
+#define EDCA2_LOW_THR_INT_MASK_SFT 5
+#define EDCA2_LOW_THR_INT_MASK_HI 5
+#define EDCA2_LOW_THR_INT_MASK_SZ 1
+#define EDCA3_LOW_THR_INT_MASK_MSK 0x00000040
+#define EDCA3_LOW_THR_INT_MASK_I_MSK 0xffffffbf
+#define EDCA3_LOW_THR_INT_MASK_SFT 6
+#define EDCA3_LOW_THR_INT_MASK_HI 6
+#define EDCA3_LOW_THR_INT_MASK_SZ 1
+#define TX_LIMIT_INT_MASK_MSK 0x00000080
+#define TX_LIMIT_INT_MASK_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_MASK_SFT 7
+#define TX_LIMIT_INT_MASK_HI 7
+#define TX_LIMIT_INT_MASK_SZ 1
+#define RX_INT_MSK 0x00000001
+#define RX_INT_I_MSK 0xfffffffe
+#define RX_INT_SFT 0
+#define RX_INT_HI 0
+#define RX_INT_SZ 1
+#define TX_COMPLETE_INT_MSK 0x00000002
+#define TX_COMPLETE_INT_I_MSK 0xfffffffd
+#define TX_COMPLETE_INT_SFT 1
+#define TX_COMPLETE_INT_HI 1
+#define TX_COMPLETE_INT_SZ 1
+#define SOC_SYSTEM_INT_STATUS_MSK 0x00000004
+#define SOC_SYSTEM_INT_STATUS_I_MSK 0xfffffffb
+#define SOC_SYSTEM_INT_STATUS_SFT 2
+#define SOC_SYSTEM_INT_STATUS_HI 2
+#define SOC_SYSTEM_INT_STATUS_SZ 1
+#define EDCA0_LOW_THR_INT_STS_MSK 0x00000008
+#define EDCA0_LOW_THR_INT_STS_I_MSK 0xfffffff7
+#define EDCA0_LOW_THR_INT_STS_SFT 3
+#define EDCA0_LOW_THR_INT_STS_HI 3
+#define EDCA0_LOW_THR_INT_STS_SZ 1
+#define EDCA1_LOW_THR_INT_STS_MSK 0x00000010
+#define EDCA1_LOW_THR_INT_STS_I_MSK 0xffffffef
+#define EDCA1_LOW_THR_INT_STS_SFT 4
+#define EDCA1_LOW_THR_INT_STS_HI 4
+#define EDCA1_LOW_THR_INT_STS_SZ 1
+#define EDCA2_LOW_THR_INT_STS_MSK 0x00000020
+#define EDCA2_LOW_THR_INT_STS_I_MSK 0xffffffdf
+#define EDCA2_LOW_THR_INT_STS_SFT 5
+#define EDCA2_LOW_THR_INT_STS_HI 5
+#define EDCA2_LOW_THR_INT_STS_SZ 1
+#define EDCA3_LOW_THR_INT_STS_MSK 0x00000040
+#define EDCA3_LOW_THR_INT_STS_I_MSK 0xffffffbf
+#define EDCA3_LOW_THR_INT_STS_SFT 6
+#define EDCA3_LOW_THR_INT_STS_HI 6
+#define EDCA3_LOW_THR_INT_STS_SZ 1
+#define TX_LIMIT_INT_STS_MSK 0x00000080
+#define TX_LIMIT_INT_STS_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_STS_SFT 7
+#define TX_LIMIT_INT_STS_HI 7
+#define TX_LIMIT_INT_STS_SZ 1
+#define HOST_TRIGGERED_RX_INT_MSK 0x00000100
+#define HOST_TRIGGERED_RX_INT_I_MSK 0xfffffeff
+#define HOST_TRIGGERED_RX_INT_SFT 8
+#define HOST_TRIGGERED_RX_INT_HI 8
+#define HOST_TRIGGERED_RX_INT_SZ 1
+#define HOST_TRIGGERED_TX_INT_MSK 0x00000200
+#define HOST_TRIGGERED_TX_INT_I_MSK 0xfffffdff
+#define HOST_TRIGGERED_TX_INT_SFT 9
+#define HOST_TRIGGERED_TX_INT_HI 9
+#define HOST_TRIGGERED_TX_INT_SZ 1
+#define SOC_TRIGGER_RX_INT_MSK 0x00000400
+#define SOC_TRIGGER_RX_INT_I_MSK 0xfffffbff
+#define SOC_TRIGGER_RX_INT_SFT 10
+#define SOC_TRIGGER_RX_INT_HI 10
+#define SOC_TRIGGER_RX_INT_SZ 1
+#define SOC_TRIGGER_TX_INT_MSK 0x00000800
+#define SOC_TRIGGER_TX_INT_I_MSK 0xfffff7ff
+#define SOC_TRIGGER_TX_INT_SFT 11
+#define SOC_TRIGGER_TX_INT_HI 11
+#define SOC_TRIGGER_TX_INT_SZ 1
+#define RDY_FOR_TX_RX_MSK 0x00000001
+#define RDY_FOR_TX_RX_I_MSK 0xfffffffe
+#define RDY_FOR_TX_RX_SFT 0
+#define RDY_FOR_TX_RX_HI 0
+#define RDY_FOR_TX_RX_SZ 1
+#define RDY_FOR_FW_DOWNLOAD_MSK 0x00000002
+#define RDY_FOR_FW_DOWNLOAD_I_MSK 0xfffffffd
+#define RDY_FOR_FW_DOWNLOAD_SFT 1
+#define RDY_FOR_FW_DOWNLOAD_HI 1
+#define RDY_FOR_FW_DOWNLOAD_SZ 1
+#define ILLEGAL_CMD_RESP_OPTION_MSK 0x00000004
+#define ILLEGAL_CMD_RESP_OPTION_I_MSK 0xfffffffb
+#define ILLEGAL_CMD_RESP_OPTION_SFT 2
+#define ILLEGAL_CMD_RESP_OPTION_HI 2
+#define ILLEGAL_CMD_RESP_OPTION_SZ 1
+#define SDIO_TRX_DATA_SEQUENCE_MSK 0x00000008
+#define SDIO_TRX_DATA_SEQUENCE_I_MSK 0xfffffff7
+#define SDIO_TRX_DATA_SEQUENCE_SFT 3
+#define SDIO_TRX_DATA_SEQUENCE_HI 3
+#define SDIO_TRX_DATA_SEQUENCE_SZ 1
+#define GPIO_INT_TRIGGER_OPTION_MSK 0x00000010
+#define GPIO_INT_TRIGGER_OPTION_I_MSK 0xffffffef
+#define GPIO_INT_TRIGGER_OPTION_SFT 4
+#define GPIO_INT_TRIGGER_OPTION_HI 4
+#define GPIO_INT_TRIGGER_OPTION_SZ 1
+#define TRIGGER_FUNCTION_SETTING_MSK 0x00000060
+#define TRIGGER_FUNCTION_SETTING_I_MSK 0xffffff9f
+#define TRIGGER_FUNCTION_SETTING_SFT 5
+#define TRIGGER_FUNCTION_SETTING_HI 6
+#define TRIGGER_FUNCTION_SETTING_SZ 2
+#define CMD52_ABORT_RESPONSE_MSK 0x00000080
+#define CMD52_ABORT_RESPONSE_I_MSK 0xffffff7f
+#define CMD52_ABORT_RESPONSE_SFT 7
+#define CMD52_ABORT_RESPONSE_HI 7
+#define CMD52_ABORT_RESPONSE_SZ 1
+#define RX_PACKET_LENGTH_MSK 0x0000ffff
+#define RX_PACKET_LENGTH_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH_SFT 0
+#define RX_PACKET_LENGTH_HI 15
+#define RX_PACKET_LENGTH_SZ 16
+#define CARD_FW_DL_STATUS_MSK 0x00ff0000
+#define CARD_FW_DL_STATUS_I_MSK 0xff00ffff
+#define CARD_FW_DL_STATUS_SFT 16
+#define CARD_FW_DL_STATUS_HI 23
+#define CARD_FW_DL_STATUS_SZ 8
+#define TX_RX_LOOP_BACK_TEST_MSK 0x01000000
+#define TX_RX_LOOP_BACK_TEST_I_MSK 0xfeffffff
+#define TX_RX_LOOP_BACK_TEST_SFT 24
+#define TX_RX_LOOP_BACK_TEST_HI 24
+#define TX_RX_LOOP_BACK_TEST_SZ 1
+#define SDIO_LOOP_BACK_TEST_MSK 0x02000000
+#define SDIO_LOOP_BACK_TEST_I_MSK 0xfdffffff
+#define SDIO_LOOP_BACK_TEST_SFT 25
+#define SDIO_LOOP_BACK_TEST_HI 25
+#define SDIO_LOOP_BACK_TEST_SZ 1
+#define CMD52_ABORT_ACTIVE_MSK 0x10000000
+#define CMD52_ABORT_ACTIVE_I_MSK 0xefffffff
+#define CMD52_ABORT_ACTIVE_SFT 28
+#define CMD52_ABORT_ACTIVE_HI 28
+#define CMD52_ABORT_ACTIVE_SZ 1
+#define CMD52_RESET_ACTIVE_MSK 0x20000000
+#define CMD52_RESET_ACTIVE_I_MSK 0xdfffffff
+#define CMD52_RESET_ACTIVE_SFT 29
+#define CMD52_RESET_ACTIVE_HI 29
+#define CMD52_RESET_ACTIVE_SZ 1
+#define SDIO_PARTIAL_RESET_ACTIVE_MSK 0x40000000
+#define SDIO_PARTIAL_RESET_ACTIVE_I_MSK 0xbfffffff
+#define SDIO_PARTIAL_RESET_ACTIVE_SFT 30
+#define SDIO_PARTIAL_RESET_ACTIVE_HI 30
+#define SDIO_PARTIAL_RESET_ACTIVE_SZ 1
+#define SDIO_ALL_RESE_ACTIVE_MSK 0x80000000
+#define SDIO_ALL_RESE_ACTIVE_I_MSK 0x7fffffff
+#define SDIO_ALL_RESE_ACTIVE_SFT 31
+#define SDIO_ALL_RESE_ACTIVE_HI 31
+#define SDIO_ALL_RESE_ACTIVE_SZ 1
+#define RX_PACKET_LENGTH2_MSK 0x0000ffff
+#define RX_PACKET_LENGTH2_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH2_SFT 0
+#define RX_PACKET_LENGTH2_HI 15
+#define RX_PACKET_LENGTH2_SZ 16
+#define RX_INT1_MSK 0x00010000
+#define RX_INT1_I_MSK 0xfffeffff
+#define RX_INT1_SFT 16
+#define RX_INT1_HI 16
+#define RX_INT1_SZ 1
+#define TX_DONE_MSK 0x00020000
+#define TX_DONE_I_MSK 0xfffdffff
+#define TX_DONE_SFT 17
+#define TX_DONE_HI 17
+#define TX_DONE_SZ 1
+#define HCI_TRX_FINISH_MSK 0x00040000
+#define HCI_TRX_FINISH_I_MSK 0xfffbffff
+#define HCI_TRX_FINISH_SFT 18
+#define HCI_TRX_FINISH_HI 18
+#define HCI_TRX_FINISH_SZ 1
+#define ALLOCATE_STATUS_MSK 0x00080000
+#define ALLOCATE_STATUS_I_MSK 0xfff7ffff
+#define ALLOCATE_STATUS_SFT 19
+#define ALLOCATE_STATUS_HI 19
+#define ALLOCATE_STATUS_SZ 1
+#define HCI_INPUT_FF_CNT_MSK 0x00f00000
+#define HCI_INPUT_FF_CNT_I_MSK 0xff0fffff
+#define HCI_INPUT_FF_CNT_SFT 20
+#define HCI_INPUT_FF_CNT_HI 23
+#define HCI_INPUT_FF_CNT_SZ 4
+#define HCI_OUTPUT_FF_CNT_MSK 0x1f000000
+#define HCI_OUTPUT_FF_CNT_I_MSK 0xe0ffffff
+#define HCI_OUTPUT_FF_CNT_SFT 24
+#define HCI_OUTPUT_FF_CNT_HI 28
+#define HCI_OUTPUT_FF_CNT_SZ 5
+#define AHB_HANG4_MSK 0x20000000
+#define AHB_HANG4_I_MSK 0xdfffffff
+#define AHB_HANG4_SFT 29
+#define AHB_HANG4_HI 29
+#define AHB_HANG4_SZ 1
+#define HCI_IN_QUE_EMPTY_MSK 0x40000000
+#define HCI_IN_QUE_EMPTY_I_MSK 0xbfffffff
+#define HCI_IN_QUE_EMPTY_SFT 30
+#define HCI_IN_QUE_EMPTY_HI 30
+#define HCI_IN_QUE_EMPTY_SZ 1
+#define SYSTEM_INT_MSK 0x80000000
+#define SYSTEM_INT_I_MSK 0x7fffffff
+#define SYSTEM_INT_SFT 31
+#define SYSTEM_INT_HI 31
+#define SYSTEM_INT_SZ 1
+#define CARD_RCA_REG_MSK 0x0000ffff
+#define CARD_RCA_REG_I_MSK 0xffff0000
+#define CARD_RCA_REG_SFT 0
+#define CARD_RCA_REG_HI 15
+#define CARD_RCA_REG_SZ 16
+#define SDIO_FIFO_WR_THLD_REG_MSK 0x000001ff
+#define SDIO_FIFO_WR_THLD_REG_I_MSK 0xfffffe00
+#define SDIO_FIFO_WR_THLD_REG_SFT 0
+#define SDIO_FIFO_WR_THLD_REG_HI 8
+#define SDIO_FIFO_WR_THLD_REG_SZ 9
+#define SDIO_FIFO_WR_LIMIT_REG_MSK 0x000001ff
+#define SDIO_FIFO_WR_LIMIT_REG_I_MSK 0xfffffe00
+#define SDIO_FIFO_WR_LIMIT_REG_SFT 0
+#define SDIO_FIFO_WR_LIMIT_REG_HI 8
+#define SDIO_FIFO_WR_LIMIT_REG_SZ 9
+#define SDIO_TX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
+#define SDIO_TX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
+#define SDIO_TX_DATA_BATCH_SIZE_REG_SFT 0
+#define SDIO_TX_DATA_BATCH_SIZE_REG_HI 8
+#define SDIO_TX_DATA_BATCH_SIZE_REG_SZ 9
+#define SDIO_THLD_FOR_CMD53RD_REG_MSK 0x000001ff
+#define SDIO_THLD_FOR_CMD53RD_REG_I_MSK 0xfffffe00
+#define SDIO_THLD_FOR_CMD53RD_REG_SFT 0
+#define SDIO_THLD_FOR_CMD53RD_REG_HI 8
+#define SDIO_THLD_FOR_CMD53RD_REG_SZ 9
+#define SDIO_RX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
+#define SDIO_RX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
+#define SDIO_RX_DATA_BATCH_SIZE_REG_SFT 0
+#define SDIO_RX_DATA_BATCH_SIZE_REG_HI 8
+#define SDIO_RX_DATA_BATCH_SIZE_REG_SZ 9
+#define START_BYTE_VALUE_MSK 0x000000ff
+#define START_BYTE_VALUE_I_MSK 0xffffff00
+#define START_BYTE_VALUE_SFT 0
+#define START_BYTE_VALUE_HI 7
+#define START_BYTE_VALUE_SZ 8
+#define END_BYTE_VALUE_MSK 0x0000ff00
+#define END_BYTE_VALUE_I_MSK 0xffff00ff
+#define END_BYTE_VALUE_SFT 8
+#define END_BYTE_VALUE_HI 15
+#define END_BYTE_VALUE_SZ 8
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_MSK 0x000000ff
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_I_MSK 0xffffff00
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SFT 0
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_HI 7
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SZ 8
+#define SDIO_LAST_CMD_INDEX_REG_MSK 0x0000003f
+#define SDIO_LAST_CMD_INDEX_REG_I_MSK 0xffffffc0
+#define SDIO_LAST_CMD_INDEX_REG_SFT 0
+#define SDIO_LAST_CMD_INDEX_REG_HI 5
+#define SDIO_LAST_CMD_INDEX_REG_SZ 6
+#define SDIO_LAST_CMD_CRC_REG_MSK 0x00007f00
+#define SDIO_LAST_CMD_CRC_REG_I_MSK 0xffff80ff
+#define SDIO_LAST_CMD_CRC_REG_SFT 8
+#define SDIO_LAST_CMD_CRC_REG_HI 14
+#define SDIO_LAST_CMD_CRC_REG_SZ 7
+#define SDIO_LAST_CMD_ARG_REG_MSK 0xffffffff
+#define SDIO_LAST_CMD_ARG_REG_I_MSK 0x00000000
+#define SDIO_LAST_CMD_ARG_REG_SFT 0
+#define SDIO_LAST_CMD_ARG_REG_HI 31
+#define SDIO_LAST_CMD_ARG_REG_SZ 32
+#define SDIO_BUS_STATE_REG_MSK 0x0000001f
+#define SDIO_BUS_STATE_REG_I_MSK 0xffffffe0
+#define SDIO_BUS_STATE_REG_SFT 0
+#define SDIO_BUS_STATE_REG_HI 4
+#define SDIO_BUS_STATE_REG_SZ 5
+#define SDIO_BUSY_LONG_CNT_MSK 0xffff0000
+#define SDIO_BUSY_LONG_CNT_I_MSK 0x0000ffff
+#define SDIO_BUSY_LONG_CNT_SFT 16
+#define SDIO_BUSY_LONG_CNT_HI 31
+#define SDIO_BUSY_LONG_CNT_SZ 16
+#define SDIO_CARD_STATUS_REG_MSK 0xffffffff
+#define SDIO_CARD_STATUS_REG_I_MSK 0x00000000
+#define SDIO_CARD_STATUS_REG_SFT 0
+#define SDIO_CARD_STATUS_REG_HI 31
+#define SDIO_CARD_STATUS_REG_SZ 32
+#define R5_RESPONSE_FLAG_MSK 0x000000ff
+#define R5_RESPONSE_FLAG_I_MSK 0xffffff00
+#define R5_RESPONSE_FLAG_SFT 0
+#define R5_RESPONSE_FLAG_HI 7
+#define R5_RESPONSE_FLAG_SZ 8
+#define RESP_OUT_EDGE_MSK 0x00000100
+#define RESP_OUT_EDGE_I_MSK 0xfffffeff
+#define RESP_OUT_EDGE_SFT 8
+#define RESP_OUT_EDGE_HI 8
+#define RESP_OUT_EDGE_SZ 1
+#define DAT_OUT_EDGE_MSK 0x00000200
+#define DAT_OUT_EDGE_I_MSK 0xfffffdff
+#define DAT_OUT_EDGE_SFT 9
+#define DAT_OUT_EDGE_HI 9
+#define DAT_OUT_EDGE_SZ 1
+#define MCU_TO_SDIO_INFO_MASK_MSK 0x00010000
+#define MCU_TO_SDIO_INFO_MASK_I_MSK 0xfffeffff
+#define MCU_TO_SDIO_INFO_MASK_SFT 16
+#define MCU_TO_SDIO_INFO_MASK_HI 16
+#define MCU_TO_SDIO_INFO_MASK_SZ 1
+#define INT_THROUGH_PIN_MSK 0x00020000
+#define INT_THROUGH_PIN_I_MSK 0xfffdffff
+#define INT_THROUGH_PIN_SFT 17
+#define INT_THROUGH_PIN_HI 17
+#define INT_THROUGH_PIN_SZ 1
+#define WRITE_DATA_MSK 0x000000ff
+#define WRITE_DATA_I_MSK 0xffffff00
+#define WRITE_DATA_SFT 0
+#define WRITE_DATA_HI 7
+#define WRITE_DATA_SZ 8
+#define WRITE_ADDRESS_MSK 0x0000ff00
+#define WRITE_ADDRESS_I_MSK 0xffff00ff
+#define WRITE_ADDRESS_SFT 8
+#define WRITE_ADDRESS_HI 15
+#define WRITE_ADDRESS_SZ 8
+#define READ_DATA_MSK 0x00ff0000
+#define READ_DATA_I_MSK 0xff00ffff
+#define READ_DATA_SFT 16
+#define READ_DATA_HI 23
+#define READ_DATA_SZ 8
+#define READ_ADDRESS_MSK 0xff000000
+#define READ_ADDRESS_I_MSK 0x00ffffff
+#define READ_ADDRESS_SFT 24
+#define READ_ADDRESS_HI 31
+#define READ_ADDRESS_SZ 8
+#define FN1_DMA_START_ADDR_REG_MSK 0xffffffff
+#define FN1_DMA_START_ADDR_REG_I_MSK 0x00000000
+#define FN1_DMA_START_ADDR_REG_SFT 0
+#define FN1_DMA_START_ADDR_REG_HI 31
+#define FN1_DMA_START_ADDR_REG_SZ 32
+#define SDIO_TO_MCU_INFO_MSK 0x000000ff
+#define SDIO_TO_MCU_INFO_I_MSK 0xffffff00
+#define SDIO_TO_MCU_INFO_SFT 0
+#define SDIO_TO_MCU_INFO_HI 7
+#define SDIO_TO_MCU_INFO_SZ 8
+#define SDIO_PARTIAL_RESET_MSK 0x00000100
+#define SDIO_PARTIAL_RESET_I_MSK 0xfffffeff
+#define SDIO_PARTIAL_RESET_SFT 8
+#define SDIO_PARTIAL_RESET_HI 8
+#define SDIO_PARTIAL_RESET_SZ 1
+#define SDIO_ALL_RESET_MSK 0x00000200
+#define SDIO_ALL_RESET_I_MSK 0xfffffdff
+#define SDIO_ALL_RESET_SFT 9
+#define SDIO_ALL_RESET_HI 9
+#define SDIO_ALL_RESET_SZ 1
+#define PERI_MAC_ALL_RESET_MSK 0x00000400
+#define PERI_MAC_ALL_RESET_I_MSK 0xfffffbff
+#define PERI_MAC_ALL_RESET_SFT 10
+#define PERI_MAC_ALL_RESET_HI 10
+#define PERI_MAC_ALL_RESET_SZ 1
+#define MAC_ALL_RESET_MSK 0x00000800
+#define MAC_ALL_RESET_I_MSK 0xfffff7ff
+#define MAC_ALL_RESET_SFT 11
+#define MAC_ALL_RESET_HI 11
+#define MAC_ALL_RESET_SZ 1
+#define AHB_BRIDGE_RESET_MSK 0x00001000
+#define AHB_BRIDGE_RESET_I_MSK 0xffffefff
+#define AHB_BRIDGE_RESET_SFT 12
+#define AHB_BRIDGE_RESET_HI 12
+#define AHB_BRIDGE_RESET_SZ 1
+#define IO_REG_PORT_REG_MSK 0x0001ffff
+#define IO_REG_PORT_REG_I_MSK 0xfffe0000
+#define IO_REG_PORT_REG_SFT 0
+#define IO_REG_PORT_REG_HI 16
+#define IO_REG_PORT_REG_SZ 17
+#define SDIO_FIFO_EMPTY_CNT_MSK 0x0000ffff
+#define SDIO_FIFO_EMPTY_CNT_I_MSK 0xffff0000
+#define SDIO_FIFO_EMPTY_CNT_SFT 0
+#define SDIO_FIFO_EMPTY_CNT_HI 15
+#define SDIO_FIFO_EMPTY_CNT_SZ 16
+#define SDIO_FIFO_FULL_CNT_MSK 0xffff0000
+#define SDIO_FIFO_FULL_CNT_I_MSK 0x0000ffff
+#define SDIO_FIFO_FULL_CNT_SFT 16
+#define SDIO_FIFO_FULL_CNT_HI 31
+#define SDIO_FIFO_FULL_CNT_SZ 16
+#define SDIO_CRC7_ERROR_CNT_MSK 0x0000ffff
+#define SDIO_CRC7_ERROR_CNT_I_MSK 0xffff0000
+#define SDIO_CRC7_ERROR_CNT_SFT 0
+#define SDIO_CRC7_ERROR_CNT_HI 15
+#define SDIO_CRC7_ERROR_CNT_SZ 16
+#define SDIO_CRC16_ERROR_CNT_MSK 0xffff0000
+#define SDIO_CRC16_ERROR_CNT_I_MSK 0x0000ffff
+#define SDIO_CRC16_ERROR_CNT_SFT 16
+#define SDIO_CRC16_ERROR_CNT_HI 31
+#define SDIO_CRC16_ERROR_CNT_SZ 16
+#define SDIO_RD_BLOCK_CNT_MSK 0x000001ff
+#define SDIO_RD_BLOCK_CNT_I_MSK 0xfffffe00
+#define SDIO_RD_BLOCK_CNT_SFT 0
+#define SDIO_RD_BLOCK_CNT_HI 8
+#define SDIO_RD_BLOCK_CNT_SZ 9
+#define SDIO_WR_BLOCK_CNT_MSK 0x01ff0000
+#define SDIO_WR_BLOCK_CNT_I_MSK 0xfe00ffff
+#define SDIO_WR_BLOCK_CNT_SFT 16
+#define SDIO_WR_BLOCK_CNT_HI 24
+#define SDIO_WR_BLOCK_CNT_SZ 9
+#define CMD52_RD_ABORT_CNT_MSK 0x000f0000
+#define CMD52_RD_ABORT_CNT_I_MSK 0xfff0ffff
+#define CMD52_RD_ABORT_CNT_SFT 16
+#define CMD52_RD_ABORT_CNT_HI 19
+#define CMD52_RD_ABORT_CNT_SZ 4
+#define CMD52_WR_ABORT_CNT_MSK 0x00f00000
+#define CMD52_WR_ABORT_CNT_I_MSK 0xff0fffff
+#define CMD52_WR_ABORT_CNT_SFT 20
+#define CMD52_WR_ABORT_CNT_HI 23
+#define CMD52_WR_ABORT_CNT_SZ 4
+#define SDIO_FIFO_WR_PTR_REG_MSK 0x000000ff
+#define SDIO_FIFO_WR_PTR_REG_I_MSK 0xffffff00
+#define SDIO_FIFO_WR_PTR_REG_SFT 0
+#define SDIO_FIFO_WR_PTR_REG_HI 7
+#define SDIO_FIFO_WR_PTR_REG_SZ 8
+#define SDIO_FIFO_RD_PTR_REG_MSK 0x0000ff00
+#define SDIO_FIFO_RD_PTR_REG_I_MSK 0xffff00ff
+#define SDIO_FIFO_RD_PTR_REG_SFT 8
+#define SDIO_FIFO_RD_PTR_REG_HI 15
+#define SDIO_FIFO_RD_PTR_REG_SZ 8
+#define SDIO_READ_DATA_CTRL_MSK 0x00010000
+#define SDIO_READ_DATA_CTRL_I_MSK 0xfffeffff
+#define SDIO_READ_DATA_CTRL_SFT 16
+#define SDIO_READ_DATA_CTRL_HI 16
+#define SDIO_READ_DATA_CTRL_SZ 1
+#define TX_SIZE_BEFORE_SHIFT_MSK 0x000000ff
+#define TX_SIZE_BEFORE_SHIFT_I_MSK 0xffffff00
+#define TX_SIZE_BEFORE_SHIFT_SFT 0
+#define TX_SIZE_BEFORE_SHIFT_HI 7
+#define TX_SIZE_BEFORE_SHIFT_SZ 8
+#define TX_SIZE_SHIFT_BITS_MSK 0x00000700
+#define TX_SIZE_SHIFT_BITS_I_MSK 0xfffff8ff
+#define TX_SIZE_SHIFT_BITS_SFT 8
+#define TX_SIZE_SHIFT_BITS_HI 10
+#define TX_SIZE_SHIFT_BITS_SZ 3
+#define SDIO_TX_ALLOC_STATE_MSK 0x00001000
+#define SDIO_TX_ALLOC_STATE_I_MSK 0xffffefff
+#define SDIO_TX_ALLOC_STATE_SFT 12
+#define SDIO_TX_ALLOC_STATE_HI 12
+#define SDIO_TX_ALLOC_STATE_SZ 1
+#define ALLOCATE_STATUS2_MSK 0x00010000
+#define ALLOCATE_STATUS2_I_MSK 0xfffeffff
+#define ALLOCATE_STATUS2_SFT 16
+#define ALLOCATE_STATUS2_HI 16
+#define ALLOCATE_STATUS2_SZ 1
+#define NO_ALLOCATE_SEND_ERROR_MSK 0x00020000
+#define NO_ALLOCATE_SEND_ERROR_I_MSK 0xfffdffff
+#define NO_ALLOCATE_SEND_ERROR_SFT 17
+#define NO_ALLOCATE_SEND_ERROR_HI 17
+#define NO_ALLOCATE_SEND_ERROR_SZ 1
+#define DOUBLE_ALLOCATE_ERROR_MSK 0x00040000
+#define DOUBLE_ALLOCATE_ERROR_I_MSK 0xfffbffff
+#define DOUBLE_ALLOCATE_ERROR_SFT 18
+#define DOUBLE_ALLOCATE_ERROR_HI 18
+#define DOUBLE_ALLOCATE_ERROR_SZ 1
+#define TX_DONE_STATUS_MSK 0x00080000
+#define TX_DONE_STATUS_I_MSK 0xfff7ffff
+#define TX_DONE_STATUS_SFT 19
+#define TX_DONE_STATUS_HI 19
+#define TX_DONE_STATUS_SZ 1
+#define AHB_HANG2_MSK 0x00100000
+#define AHB_HANG2_I_MSK 0xffefffff
+#define AHB_HANG2_SFT 20
+#define AHB_HANG2_HI 20
+#define AHB_HANG2_SZ 1
+#define HCI_TRX_FINISH2_MSK 0x00200000
+#define HCI_TRX_FINISH2_I_MSK 0xffdfffff
+#define HCI_TRX_FINISH2_SFT 21
+#define HCI_TRX_FINISH2_HI 21
+#define HCI_TRX_FINISH2_SZ 1
+#define INTR_RX_MSK 0x00400000
+#define INTR_RX_I_MSK 0xffbfffff
+#define INTR_RX_SFT 22
+#define INTR_RX_HI 22
+#define INTR_RX_SZ 1
+#define HCI_INPUT_QUEUE_FULL_MSK 0x00800000
+#define HCI_INPUT_QUEUE_FULL_I_MSK 0xff7fffff
+#define HCI_INPUT_QUEUE_FULL_SFT 23
+#define HCI_INPUT_QUEUE_FULL_HI 23
+#define HCI_INPUT_QUEUE_FULL_SZ 1
+#define ALLOCATESTATUS_MSK 0x00000001
+#define ALLOCATESTATUS_I_MSK 0xfffffffe
+#define ALLOCATESTATUS_SFT 0
+#define ALLOCATESTATUS_HI 0
+#define ALLOCATESTATUS_SZ 1
+#define HCI_TRX_FINISH3_MSK 0x00000002
+#define HCI_TRX_FINISH3_I_MSK 0xfffffffd
+#define HCI_TRX_FINISH3_SFT 1
+#define HCI_TRX_FINISH3_HI 1
+#define HCI_TRX_FINISH3_SZ 1
+#define HCI_IN_QUE_EMPTY2_MSK 0x00000004
+#define HCI_IN_QUE_EMPTY2_I_MSK 0xfffffffb
+#define HCI_IN_QUE_EMPTY2_SFT 2
+#define HCI_IN_QUE_EMPTY2_HI 2
+#define HCI_IN_QUE_EMPTY2_SZ 1
+#define MTX_MNG_UPTHOLD_INT_MSK 0x00000008
+#define MTX_MNG_UPTHOLD_INT_I_MSK 0xfffffff7
+#define MTX_MNG_UPTHOLD_INT_SFT 3
+#define MTX_MNG_UPTHOLD_INT_HI 3
+#define MTX_MNG_UPTHOLD_INT_SZ 1
+#define EDCA0_UPTHOLD_INT_MSK 0x00000010
+#define EDCA0_UPTHOLD_INT_I_MSK 0xffffffef
+#define EDCA0_UPTHOLD_INT_SFT 4
+#define EDCA0_UPTHOLD_INT_HI 4
+#define EDCA0_UPTHOLD_INT_SZ 1
+#define EDCA1_UPTHOLD_INT_MSK 0x00000020
+#define EDCA1_UPTHOLD_INT_I_MSK 0xffffffdf
+#define EDCA1_UPTHOLD_INT_SFT 5
+#define EDCA1_UPTHOLD_INT_HI 5
+#define EDCA1_UPTHOLD_INT_SZ 1
+#define EDCA2_UPTHOLD_INT_MSK 0x00000040
+#define EDCA2_UPTHOLD_INT_I_MSK 0xffffffbf
+#define EDCA2_UPTHOLD_INT_SFT 6
+#define EDCA2_UPTHOLD_INT_HI 6
+#define EDCA2_UPTHOLD_INT_SZ 1
+#define EDCA3_UPTHOLD_INT_MSK 0x00000080
+#define EDCA3_UPTHOLD_INT_I_MSK 0xffffff7f
+#define EDCA3_UPTHOLD_INT_SFT 7
+#define EDCA3_UPTHOLD_INT_HI 7
+#define EDCA3_UPTHOLD_INT_SZ 1
+#define TX_PAGE_REMAIN2_MSK 0x0000ff00
+#define TX_PAGE_REMAIN2_I_MSK 0xffff00ff
+#define TX_PAGE_REMAIN2_SFT 8
+#define TX_PAGE_REMAIN2_HI 15
+#define TX_PAGE_REMAIN2_SZ 8
+#define TX_ID_REMAIN3_MSK 0x007f0000
+#define TX_ID_REMAIN3_I_MSK 0xff80ffff
+#define TX_ID_REMAIN3_SFT 16
+#define TX_ID_REMAIN3_HI 22
+#define TX_ID_REMAIN3_SZ 7
+#define HCI_OUTPUT_FF_CNT_0_MSK 0x00800000
+#define HCI_OUTPUT_FF_CNT_0_I_MSK 0xff7fffff
+#define HCI_OUTPUT_FF_CNT_0_SFT 23
+#define HCI_OUTPUT_FF_CNT_0_HI 23
+#define HCI_OUTPUT_FF_CNT_0_SZ 1
+#define HCI_OUTPUT_FF_CNT2_MSK 0x0f000000
+#define HCI_OUTPUT_FF_CNT2_I_MSK 0xf0ffffff
+#define HCI_OUTPUT_FF_CNT2_SFT 24
+#define HCI_OUTPUT_FF_CNT2_HI 27
+#define HCI_OUTPUT_FF_CNT2_SZ 4
+#define HCI_INPUT_FF_CNT2_MSK 0xf0000000
+#define HCI_INPUT_FF_CNT2_I_MSK 0x0fffffff
+#define HCI_INPUT_FF_CNT2_SFT 28
+#define HCI_INPUT_FF_CNT2_HI 31
+#define HCI_INPUT_FF_CNT2_SZ 4
+#define F1_BLOCK_SIZE_0_REG_MSK 0x00000fff
+#define F1_BLOCK_SIZE_0_REG_I_MSK 0xfffff000
+#define F1_BLOCK_SIZE_0_REG_SFT 0
+#define F1_BLOCK_SIZE_0_REG_HI 11
+#define F1_BLOCK_SIZE_0_REG_SZ 12
+#define START_BYTE_VALUE2_MSK 0x000000ff
+#define START_BYTE_VALUE2_I_MSK 0xffffff00
+#define START_BYTE_VALUE2_SFT 0
+#define START_BYTE_VALUE2_HI 7
+#define START_BYTE_VALUE2_SZ 8
+#define COMMAND_COUNTER_MSK 0x0000ff00
+#define COMMAND_COUNTER_I_MSK 0xffff00ff
+#define COMMAND_COUNTER_SFT 8
+#define COMMAND_COUNTER_HI 15
+#define COMMAND_COUNTER_SZ 8
+#define CMD_LOG_PART1_MSK 0xffff0000
+#define CMD_LOG_PART1_I_MSK 0x0000ffff
+#define CMD_LOG_PART1_SFT 16
+#define CMD_LOG_PART1_HI 31
+#define CMD_LOG_PART1_SZ 16
+#define CMD_LOG_PART2_MSK 0x00ffffff
+#define CMD_LOG_PART2_I_MSK 0xff000000
+#define CMD_LOG_PART2_SFT 0
+#define CMD_LOG_PART2_HI 23
+#define CMD_LOG_PART2_SZ 24
+#define END_BYTE_VALUE2_MSK 0xff000000
+#define END_BYTE_VALUE2_I_MSK 0x00ffffff
+#define END_BYTE_VALUE2_SFT 24
+#define END_BYTE_VALUE2_HI 31
+#define END_BYTE_VALUE2_SZ 8
+#define RX_PACKET_LENGTH3_MSK 0x0000ffff
+#define RX_PACKET_LENGTH3_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH3_SFT 0
+#define RX_PACKET_LENGTH3_HI 15
+#define RX_PACKET_LENGTH3_SZ 16
+#define RX_INT3_MSK 0x00010000
+#define RX_INT3_I_MSK 0xfffeffff
+#define RX_INT3_SFT 16
+#define RX_INT3_HI 16
+#define RX_INT3_SZ 1
+#define TX_ID_REMAIN2_MSK 0x00fe0000
+#define TX_ID_REMAIN2_I_MSK 0xff01ffff
+#define TX_ID_REMAIN2_SFT 17
+#define TX_ID_REMAIN2_HI 23
+#define TX_ID_REMAIN2_SZ 7
+#define TX_PAGE_REMAIN3_MSK 0xff000000
+#define TX_PAGE_REMAIN3_I_MSK 0x00ffffff
+#define TX_PAGE_REMAIN3_SFT 24
+#define TX_PAGE_REMAIN3_HI 31
+#define TX_PAGE_REMAIN3_SZ 8
+#define CCCR_00H_REG_MSK 0x000000ff
+#define CCCR_00H_REG_I_MSK 0xffffff00
+#define CCCR_00H_REG_SFT 0
+#define CCCR_00H_REG_HI 7
+#define CCCR_00H_REG_SZ 8
+#define CCCR_02H_REG_MSK 0x00ff0000
+#define CCCR_02H_REG_I_MSK 0xff00ffff
+#define CCCR_02H_REG_SFT 16
+#define CCCR_02H_REG_HI 23
+#define CCCR_02H_REG_SZ 8
+#define CCCR_03H_REG_MSK 0xff000000
+#define CCCR_03H_REG_I_MSK 0x00ffffff
+#define CCCR_03H_REG_SFT 24
+#define CCCR_03H_REG_HI 31
+#define CCCR_03H_REG_SZ 8
+#define CCCR_04H_REG_MSK 0x000000ff
+#define CCCR_04H_REG_I_MSK 0xffffff00
+#define CCCR_04H_REG_SFT 0
+#define CCCR_04H_REG_HI 7
+#define CCCR_04H_REG_SZ 8
+#define CCCR_05H_REG_MSK 0x0000ff00
+#define CCCR_05H_REG_I_MSK 0xffff00ff
+#define CCCR_05H_REG_SFT 8
+#define CCCR_05H_REG_HI 15
+#define CCCR_05H_REG_SZ 8
+#define CCCR_06H_REG_MSK 0x000f0000
+#define CCCR_06H_REG_I_MSK 0xfff0ffff
+#define CCCR_06H_REG_SFT 16
+#define CCCR_06H_REG_HI 19
+#define CCCR_06H_REG_SZ 4
+#define CCCR_07H_REG_MSK 0xff000000
+#define CCCR_07H_REG_I_MSK 0x00ffffff
+#define CCCR_07H_REG_SFT 24
+#define CCCR_07H_REG_HI 31
+#define CCCR_07H_REG_SZ 8
+#define SUPPORT_DIRECT_COMMAND_SDIO_MSK 0x00000001
+#define SUPPORT_DIRECT_COMMAND_SDIO_I_MSK 0xfffffffe
+#define SUPPORT_DIRECT_COMMAND_SDIO_SFT 0
+#define SUPPORT_DIRECT_COMMAND_SDIO_HI 0
+#define SUPPORT_DIRECT_COMMAND_SDIO_SZ 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_MSK 0x00000002
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_I_MSK 0xfffffffd
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SFT 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_HI 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SZ 1
+#define SUPPORT_READ_WAIT_MSK 0x00000004
+#define SUPPORT_READ_WAIT_I_MSK 0xfffffffb
+#define SUPPORT_READ_WAIT_SFT 2
+#define SUPPORT_READ_WAIT_HI 2
+#define SUPPORT_READ_WAIT_SZ 1
+#define SUPPORT_BUS_CONTROL_MSK 0x00000008
+#define SUPPORT_BUS_CONTROL_I_MSK 0xfffffff7
+#define SUPPORT_BUS_CONTROL_SFT 3
+#define SUPPORT_BUS_CONTROL_HI 3
+#define SUPPORT_BUS_CONTROL_SZ 1
+#define SUPPORT_BLOCK_GAP_INTERRUPT_MSK 0x00000010
+#define SUPPORT_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffef
+#define SUPPORT_BLOCK_GAP_INTERRUPT_SFT 4
+#define SUPPORT_BLOCK_GAP_INTERRUPT_HI 4
+#define SUPPORT_BLOCK_GAP_INTERRUPT_SZ 1
+#define ENABLE_BLOCK_GAP_INTERRUPT_MSK 0x00000020
+#define ENABLE_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffdf
+#define ENABLE_BLOCK_GAP_INTERRUPT_SFT 5
+#define ENABLE_BLOCK_GAP_INTERRUPT_HI 5
+#define ENABLE_BLOCK_GAP_INTERRUPT_SZ 1
+#define LOW_SPEED_CARD_MSK 0x00000040
+#define LOW_SPEED_CARD_I_MSK 0xffffffbf
+#define LOW_SPEED_CARD_SFT 6
+#define LOW_SPEED_CARD_HI 6
+#define LOW_SPEED_CARD_SZ 1
+#define LOW_SPEED_CARD_4BIT_MSK 0x00000080
+#define LOW_SPEED_CARD_4BIT_I_MSK 0xffffff7f
+#define LOW_SPEED_CARD_4BIT_SFT 7
+#define LOW_SPEED_CARD_4BIT_HI 7
+#define LOW_SPEED_CARD_4BIT_SZ 1
+#define COMMON_CIS_PONTER_MSK 0x01ffff00
+#define COMMON_CIS_PONTER_I_MSK 0xfe0000ff
+#define COMMON_CIS_PONTER_SFT 8
+#define COMMON_CIS_PONTER_HI 24
+#define COMMON_CIS_PONTER_SZ 17
+#define SUPPORT_HIGH_SPEED_MSK 0x01000000
+#define SUPPORT_HIGH_SPEED_I_MSK 0xfeffffff
+#define SUPPORT_HIGH_SPEED_SFT 24
+#define SUPPORT_HIGH_SPEED_HI 24
+#define SUPPORT_HIGH_SPEED_SZ 1
+#define BSS_MSK 0x0e000000
+#define BSS_I_MSK 0xf1ffffff
+#define BSS_SFT 25
+#define BSS_HI 27
+#define BSS_SZ 3
+#define FBR_100H_REG_MSK 0x0000000f
+#define FBR_100H_REG_I_MSK 0xfffffff0
+#define FBR_100H_REG_SFT 0
+#define FBR_100H_REG_HI 3
+#define FBR_100H_REG_SZ 4
+#define CSASUPPORT_MSK 0x00000040
+#define CSASUPPORT_I_MSK 0xffffffbf
+#define CSASUPPORT_SFT 6
+#define CSASUPPORT_HI 6
+#define CSASUPPORT_SZ 1
+#define ENABLECSA_MSK 0x00000080
+#define ENABLECSA_I_MSK 0xffffff7f
+#define ENABLECSA_SFT 7
+#define ENABLECSA_HI 7
+#define ENABLECSA_SZ 1
+#define FBR_101H_REG_MSK 0x0000ff00
+#define FBR_101H_REG_I_MSK 0xffff00ff
+#define FBR_101H_REG_SFT 8
+#define FBR_101H_REG_HI 15
+#define FBR_101H_REG_SZ 8
+#define FBR_109H_REG_MSK 0x01ffff00
+#define FBR_109H_REG_I_MSK 0xfe0000ff
+#define FBR_109H_REG_SFT 8
+#define FBR_109H_REG_HI 24
+#define FBR_109H_REG_SZ 17
+#define F0_CIS_CONTENT_REG_31_0_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_31_0_SFT 0
+#define F0_CIS_CONTENT_REG_31_0_HI 31
+#define F0_CIS_CONTENT_REG_31_0_SZ 32
+#define F0_CIS_CONTENT_REG_63_32_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_63_32_SFT 0
+#define F0_CIS_CONTENT_REG_63_32_HI 31
+#define F0_CIS_CONTENT_REG_63_32_SZ 32
+#define F0_CIS_CONTENT_REG_95_64_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_95_64_SFT 0
+#define F0_CIS_CONTENT_REG_95_64_HI 31
+#define F0_CIS_CONTENT_REG_95_64_SZ 32
+#define F0_CIS_CONTENT_REG_127_96_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_127_96_SFT 0
+#define F0_CIS_CONTENT_REG_127_96_HI 31
+#define F0_CIS_CONTENT_REG_127_96_SZ 32
+#define F0_CIS_CONTENT_REG_159_128_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_159_128_SFT 0
+#define F0_CIS_CONTENT_REG_159_128_HI 31
+#define F0_CIS_CONTENT_REG_159_128_SZ 32
+#define F0_CIS_CONTENT_REG_191_160_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_191_160_SFT 0
+#define F0_CIS_CONTENT_REG_191_160_HI 31
+#define F0_CIS_CONTENT_REG_191_160_SZ 32
+#define F0_CIS_CONTENT_REG_223_192_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_223_192_SFT 0
+#define F0_CIS_CONTENT_REG_223_192_HI 31
+#define F0_CIS_CONTENT_REG_223_192_SZ 32
+#define F0_CIS_CONTENT_REG_255_224_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_255_224_SFT 0
+#define F0_CIS_CONTENT_REG_255_224_HI 31
+#define F0_CIS_CONTENT_REG_255_224_SZ 32
+#define F0_CIS_CONTENT_REG_287_256_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_287_256_SFT 0
+#define F0_CIS_CONTENT_REG_287_256_HI 31
+#define F0_CIS_CONTENT_REG_287_256_SZ 32
+#define F0_CIS_CONTENT_REG_319_288_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_319_288_SFT 0
+#define F0_CIS_CONTENT_REG_319_288_HI 31
+#define F0_CIS_CONTENT_REG_319_288_SZ 32
+#define F0_CIS_CONTENT_REG_351_320_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_351_320_SFT 0
+#define F0_CIS_CONTENT_REG_351_320_HI 31
+#define F0_CIS_CONTENT_REG_351_320_SZ 32
+#define F0_CIS_CONTENT_REG_383_352_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_383_352_SFT 0
+#define F0_CIS_CONTENT_REG_383_352_HI 31
+#define F0_CIS_CONTENT_REG_383_352_SZ 32
+#define F0_CIS_CONTENT_REG_415_384_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_415_384_SFT 0
+#define F0_CIS_CONTENT_REG_415_384_HI 31
+#define F0_CIS_CONTENT_REG_415_384_SZ 32
+#define F0_CIS_CONTENT_REG_447_416_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_447_416_SFT 0
+#define F0_CIS_CONTENT_REG_447_416_HI 31
+#define F0_CIS_CONTENT_REG_447_416_SZ 32
+#define F0_CIS_CONTENT_REG_479_448_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_479_448_SFT 0
+#define F0_CIS_CONTENT_REG_479_448_HI 31
+#define F0_CIS_CONTENT_REG_479_448_SZ 32
+#define F0_CIS_CONTENT_REG_511_480_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_511_480_SFT 0
+#define F0_CIS_CONTENT_REG_511_480_HI 31
+#define F0_CIS_CONTENT_REG_511_480_SZ 32
+#define F1_CIS_CONTENT_REG_31_0_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_31_0_SFT 0
+#define F1_CIS_CONTENT_REG_31_0_HI 31
+#define F1_CIS_CONTENT_REG_31_0_SZ 32
+#define F1_CIS_CONTENT_REG_63_32_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_63_32_SFT 0
+#define F1_CIS_CONTENT_REG_63_32_HI 31
+#define F1_CIS_CONTENT_REG_63_32_SZ 32
+#define F1_CIS_CONTENT_REG_95_64_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_95_64_SFT 0
+#define F1_CIS_CONTENT_REG_95_64_HI 31
+#define F1_CIS_CONTENT_REG_95_64_SZ 32
+#define F1_CIS_CONTENT_REG_127_96_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_127_96_SFT 0
+#define F1_CIS_CONTENT_REG_127_96_HI 31
+#define F1_CIS_CONTENT_REG_127_96_SZ 32
+#define F1_CIS_CONTENT_REG_159_128_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_159_128_SFT 0
+#define F1_CIS_CONTENT_REG_159_128_HI 31
+#define F1_CIS_CONTENT_REG_159_128_SZ 32
+#define F1_CIS_CONTENT_REG_191_160_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_191_160_SFT 0
+#define F1_CIS_CONTENT_REG_191_160_HI 31
+#define F1_CIS_CONTENT_REG_191_160_SZ 32
+#define F1_CIS_CONTENT_REG_223_192_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_223_192_SFT 0
+#define F1_CIS_CONTENT_REG_223_192_HI 31
+#define F1_CIS_CONTENT_REG_223_192_SZ 32
+#define F1_CIS_CONTENT_REG_255_224_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_255_224_SFT 0
+#define F1_CIS_CONTENT_REG_255_224_HI 31
+#define F1_CIS_CONTENT_REG_255_224_SZ 32
+#define F1_CIS_CONTENT_REG_287_256_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_287_256_SFT 0
+#define F1_CIS_CONTENT_REG_287_256_HI 31
+#define F1_CIS_CONTENT_REG_287_256_SZ 32
+#define F1_CIS_CONTENT_REG_319_288_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_319_288_SFT 0
+#define F1_CIS_CONTENT_REG_319_288_HI 31
+#define F1_CIS_CONTENT_REG_319_288_SZ 32
+#define F1_CIS_CONTENT_REG_351_320_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_351_320_SFT 0
+#define F1_CIS_CONTENT_REG_351_320_HI 31
+#define F1_CIS_CONTENT_REG_351_320_SZ 32
+#define F1_CIS_CONTENT_REG_383_352_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_383_352_SFT 0
+#define F1_CIS_CONTENT_REG_383_352_HI 31
+#define F1_CIS_CONTENT_REG_383_352_SZ 32
+#define F1_CIS_CONTENT_REG_415_384_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_415_384_SFT 0
+#define F1_CIS_CONTENT_REG_415_384_HI 31
+#define F1_CIS_CONTENT_REG_415_384_SZ 32
+#define F1_CIS_CONTENT_REG_447_416_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_447_416_SFT 0
+#define F1_CIS_CONTENT_REG_447_416_HI 31
+#define F1_CIS_CONTENT_REG_447_416_SZ 32
+#define F1_CIS_CONTENT_REG_479_448_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_479_448_SFT 0
+#define F1_CIS_CONTENT_REG_479_448_HI 31
+#define F1_CIS_CONTENT_REG_479_448_SZ 32
+#define F1_CIS_CONTENT_REG_511_480_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_511_480_SFT 0
+#define F1_CIS_CONTENT_REG_511_480_HI 31
+#define F1_CIS_CONTENT_REG_511_480_SZ 32
+#define SPI_MODE_MSK 0xffffffff
+#define SPI_MODE_I_MSK 0x00000000
+#define SPI_MODE_SFT 0
+#define SPI_MODE_HI 31
+#define SPI_MODE_SZ 32
+#define RX_QUOTA_MSK 0x0000ffff
+#define RX_QUOTA_I_MSK 0xffff0000
+#define RX_QUOTA_SFT 0
+#define RX_QUOTA_HI 15
+#define RX_QUOTA_SZ 16
+#define CONDI_NUM_MSK 0x000000ff
+#define CONDI_NUM_I_MSK 0xffffff00
+#define CONDI_NUM_SFT 0
+#define CONDI_NUM_HI 7
+#define CONDI_NUM_SZ 8
+#define HOST_PATH_MSK 0x00000001
+#define HOST_PATH_I_MSK 0xfffffffe
+#define HOST_PATH_SFT 0
+#define HOST_PATH_HI 0
+#define HOST_PATH_SZ 1
+#define TX_SEG_MSK 0xffffffff
+#define TX_SEG_I_MSK 0x00000000
+#define TX_SEG_SFT 0
+#define TX_SEG_HI 31
+#define TX_SEG_SZ 32
+#define BRST_MODE_MSK 0x00000001
+#define BRST_MODE_I_MSK 0xfffffffe
+#define BRST_MODE_SFT 0
+#define BRST_MODE_HI 0
+#define BRST_MODE_SZ 1
+#define CLK_WIDTH_MSK 0x0000ffff
+#define CLK_WIDTH_I_MSK 0xffff0000
+#define CLK_WIDTH_SFT 0
+#define CLK_WIDTH_HI 15
+#define CLK_WIDTH_SZ 16
+#define CSN_INTER_MSK 0xffff0000
+#define CSN_INTER_I_MSK 0x0000ffff
+#define CSN_INTER_SFT 16
+#define CSN_INTER_HI 31
+#define CSN_INTER_SZ 16
+#define BACK_DLY_MSK 0x0000ffff
+#define BACK_DLY_I_MSK 0xffff0000
+#define BACK_DLY_SFT 0
+#define BACK_DLY_HI 15
+#define BACK_DLY_SZ 16
+#define FRONT_DLY_MSK 0xffff0000
+#define FRONT_DLY_I_MSK 0x0000ffff
+#define FRONT_DLY_SFT 16
+#define FRONT_DLY_HI 31
+#define FRONT_DLY_SZ 16
+#define RX_FIFO_FAIL_MSK 0x00000002
+#define RX_FIFO_FAIL_I_MSK 0xfffffffd
+#define RX_FIFO_FAIL_SFT 1
+#define RX_FIFO_FAIL_HI 1
+#define RX_FIFO_FAIL_SZ 1
+#define RX_HOST_FAIL_MSK 0x00000004
+#define RX_HOST_FAIL_I_MSK 0xfffffffb
+#define RX_HOST_FAIL_SFT 2
+#define RX_HOST_FAIL_HI 2
+#define RX_HOST_FAIL_SZ 1
+#define TX_FIFO_FAIL_MSK 0x00000008
+#define TX_FIFO_FAIL_I_MSK 0xfffffff7
+#define TX_FIFO_FAIL_SFT 3
+#define TX_FIFO_FAIL_HI 3
+#define TX_FIFO_FAIL_SZ 1
+#define TX_HOST_FAIL_MSK 0x00000010
+#define TX_HOST_FAIL_I_MSK 0xffffffef
+#define TX_HOST_FAIL_SFT 4
+#define TX_HOST_FAIL_HI 4
+#define TX_HOST_FAIL_SZ 1
+#define SPI_DOUBLE_ALLOC_MSK 0x00000020
+#define SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
+#define SPI_DOUBLE_ALLOC_SFT 5
+#define SPI_DOUBLE_ALLOC_HI 5
+#define SPI_DOUBLE_ALLOC_SZ 1
+#define SPI_TX_NO_ALLOC_MSK 0x00000040
+#define SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
+#define SPI_TX_NO_ALLOC_SFT 6
+#define SPI_TX_NO_ALLOC_HI 6
+#define SPI_TX_NO_ALLOC_SZ 1
+#define RDATA_RDY_MSK 0x00000080
+#define RDATA_RDY_I_MSK 0xffffff7f
+#define RDATA_RDY_SFT 7
+#define RDATA_RDY_HI 7
+#define RDATA_RDY_SZ 1
+#define SPI_ALLOC_STATUS_MSK 0x00000100
+#define SPI_ALLOC_STATUS_I_MSK 0xfffffeff
+#define SPI_ALLOC_STATUS_SFT 8
+#define SPI_ALLOC_STATUS_HI 8
+#define SPI_ALLOC_STATUS_SZ 1
+#define SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
+#define SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
+#define SPI_DBG_WR_FIFO_FULL_SFT 9
+#define SPI_DBG_WR_FIFO_FULL_HI 9
+#define SPI_DBG_WR_FIFO_FULL_SZ 1
+#define RX_LEN_MSK 0xffff0000
+#define RX_LEN_I_MSK 0x0000ffff
+#define RX_LEN_SFT 16
+#define RX_LEN_HI 31
+#define RX_LEN_SZ 16
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
+#define SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
+#define SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
+#define SPI_HOST_TX_ALLOC_PKBUF_SFT 8
+#define SPI_HOST_TX_ALLOC_PKBUF_HI 8
+#define SPI_HOST_TX_ALLOC_PKBUF_SZ 1
+#define SPI_TX_ALLOC_SIZE_MSK 0x000000ff
+#define SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
+#define SPI_TX_ALLOC_SIZE_SFT 0
+#define SPI_TX_ALLOC_SIZE_HI 7
+#define SPI_TX_ALLOC_SIZE_SZ 8
+#define RD_DAT_CNT_MSK 0x0000ffff
+#define RD_DAT_CNT_I_MSK 0xffff0000
+#define RD_DAT_CNT_SFT 0
+#define RD_DAT_CNT_HI 15
+#define RD_DAT_CNT_SZ 16
+#define RD_STS_CNT_MSK 0xffff0000
+#define RD_STS_CNT_I_MSK 0x0000ffff
+#define RD_STS_CNT_SFT 16
+#define RD_STS_CNT_HI 31
+#define RD_STS_CNT_SZ 16
+#define JUDGE_CNT_MSK 0x0000ffff
+#define JUDGE_CNT_I_MSK 0xffff0000
+#define JUDGE_CNT_SFT 0
+#define JUDGE_CNT_HI 15
+#define JUDGE_CNT_SZ 16
+#define RD_STS_CNT_CLR_MSK 0x00010000
+#define RD_STS_CNT_CLR_I_MSK 0xfffeffff
+#define RD_STS_CNT_CLR_SFT 16
+#define RD_STS_CNT_CLR_HI 16
+#define RD_STS_CNT_CLR_SZ 1
+#define RD_DAT_CNT_CLR_MSK 0x00020000
+#define RD_DAT_CNT_CLR_I_MSK 0xfffdffff
+#define RD_DAT_CNT_CLR_SFT 17
+#define RD_DAT_CNT_CLR_HI 17
+#define RD_DAT_CNT_CLR_SZ 1
+#define JUDGE_CNT_CLR_MSK 0x00040000
+#define JUDGE_CNT_CLR_I_MSK 0xfffbffff
+#define JUDGE_CNT_CLR_SFT 18
+#define JUDGE_CNT_CLR_HI 18
+#define JUDGE_CNT_CLR_SZ 1
+#define TX_DONE_CNT_MSK 0x0000ffff
+#define TX_DONE_CNT_I_MSK 0xffff0000
+#define TX_DONE_CNT_SFT 0
+#define TX_DONE_CNT_HI 15
+#define TX_DONE_CNT_SZ 16
+#define TX_DISCARD_CNT_MSK 0xffff0000
+#define TX_DISCARD_CNT_I_MSK 0x0000ffff
+#define TX_DISCARD_CNT_SFT 16
+#define TX_DISCARD_CNT_HI 31
+#define TX_DISCARD_CNT_SZ 16
+#define TX_SET_CNT_MSK 0x0000ffff
+#define TX_SET_CNT_I_MSK 0xffff0000
+#define TX_SET_CNT_SFT 0
+#define TX_SET_CNT_HI 15
+#define TX_SET_CNT_SZ 16
+#define TX_DISCARD_CNT_CLR_MSK 0x00010000
+#define TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
+#define TX_DISCARD_CNT_CLR_SFT 16
+#define TX_DISCARD_CNT_CLR_HI 16
+#define TX_DISCARD_CNT_CLR_SZ 1
+#define TX_DONE_CNT_CLR_MSK 0x00020000
+#define TX_DONE_CNT_CLR_I_MSK 0xfffdffff
+#define TX_DONE_CNT_CLR_SFT 17
+#define TX_DONE_CNT_CLR_HI 17
+#define TX_DONE_CNT_CLR_SZ 1
+#define TX_SET_CNT_CLR_MSK 0x00040000
+#define TX_SET_CNT_CLR_I_MSK 0xfffbffff
+#define TX_SET_CNT_CLR_SFT 18
+#define TX_SET_CNT_CLR_HI 18
+#define TX_SET_CNT_CLR_SZ 1
+#define DAT_MODE_OFF_MSK 0x00080000
+#define DAT_MODE_OFF_I_MSK 0xfff7ffff
+#define DAT_MODE_OFF_SFT 19
+#define DAT_MODE_OFF_HI 19
+#define DAT_MODE_OFF_SZ 1
+#define TX_FIFO_RESIDUE_MSK 0x00700000
+#define TX_FIFO_RESIDUE_I_MSK 0xff8fffff
+#define TX_FIFO_RESIDUE_SFT 20
+#define TX_FIFO_RESIDUE_HI 22
+#define TX_FIFO_RESIDUE_SZ 3
+#define RX_FIFO_RESIDUE_MSK 0x07000000
+#define RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
+#define RX_FIFO_RESIDUE_SFT 24
+#define RX_FIFO_RESIDUE_HI 26
+#define RX_FIFO_RESIDUE_SZ 3
+#define RX_RDY_MSK 0x00000001
+#define RX_RDY_I_MSK 0xfffffffe
+#define RX_RDY_SFT 0
+#define RX_RDY_HI 0
+#define RX_RDY_SZ 1
+#define SDIO_SYS_INT_MSK 0x00000004
+#define SDIO_SYS_INT_I_MSK 0xfffffffb
+#define SDIO_SYS_INT_SFT 2
+#define SDIO_SYS_INT_HI 2
+#define SDIO_SYS_INT_SZ 1
+#define EDCA0_LOWTHOLD_INT_MSK 0x00000008
+#define EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define EDCA0_LOWTHOLD_INT_SFT 3
+#define EDCA0_LOWTHOLD_INT_HI 3
+#define EDCA0_LOWTHOLD_INT_SZ 1
+#define EDCA1_LOWTHOLD_INT_MSK 0x00000010
+#define EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
+#define EDCA1_LOWTHOLD_INT_SFT 4
+#define EDCA1_LOWTHOLD_INT_HI 4
+#define EDCA1_LOWTHOLD_INT_SZ 1
+#define EDCA2_LOWTHOLD_INT_MSK 0x00000020
+#define EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define EDCA2_LOWTHOLD_INT_SFT 5
+#define EDCA2_LOWTHOLD_INT_HI 5
+#define EDCA2_LOWTHOLD_INT_SZ 1
+#define EDCA3_LOWTHOLD_INT_MSK 0x00000040
+#define EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define EDCA3_LOWTHOLD_INT_SFT 6
+#define EDCA3_LOWTHOLD_INT_HI 6
+#define EDCA3_LOWTHOLD_INT_SZ 1
+#define TX_LIMIT_INT_IN_MSK 0x00000080
+#define TX_LIMIT_INT_IN_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_IN_SFT 7
+#define TX_LIMIT_INT_IN_HI 7
+#define TX_LIMIT_INT_IN_SZ 1
+#define SPI_FN1_MSK 0x00007f00
+#define SPI_FN1_I_MSK 0xffff80ff
+#define SPI_FN1_SFT 8
+#define SPI_FN1_HI 14
+#define SPI_FN1_SZ 7
+#define SPI_CLK_EN_INT_MSK 0x00008000
+#define SPI_CLK_EN_INT_I_MSK 0xffff7fff
+#define SPI_CLK_EN_INT_SFT 15
+#define SPI_CLK_EN_INT_HI 15
+#define SPI_CLK_EN_INT_SZ 1
+#define SPI_HOST_MASK_MSK 0x00ff0000
+#define SPI_HOST_MASK_I_MSK 0xff00ffff
+#define SPI_HOST_MASK_SFT 16
+#define SPI_HOST_MASK_HI 23
+#define SPI_HOST_MASK_SZ 8
+#define I2CM_INT_WDONE_MSK 0x00000001
+#define I2CM_INT_WDONE_I_MSK 0xfffffffe
+#define I2CM_INT_WDONE_SFT 0
+#define I2CM_INT_WDONE_HI 0
+#define I2CM_INT_WDONE_SZ 1
+#define I2CM_INT_RDONE_MSK 0x00000002
+#define I2CM_INT_RDONE_I_MSK 0xfffffffd
+#define I2CM_INT_RDONE_SFT 1
+#define I2CM_INT_RDONE_HI 1
+#define I2CM_INT_RDONE_SZ 1
+#define I2CM_IDLE_MSK 0x00000004
+#define I2CM_IDLE_I_MSK 0xfffffffb
+#define I2CM_IDLE_SFT 2
+#define I2CM_IDLE_HI 2
+#define I2CM_IDLE_SZ 1
+#define I2CM_INT_MISMATCH_MSK 0x00000008
+#define I2CM_INT_MISMATCH_I_MSK 0xfffffff7
+#define I2CM_INT_MISMATCH_SFT 3
+#define I2CM_INT_MISMATCH_HI 3
+#define I2CM_INT_MISMATCH_SZ 1
+#define I2CM_PSCL_MSK 0x00003ff0
+#define I2CM_PSCL_I_MSK 0xffffc00f
+#define I2CM_PSCL_SFT 4
+#define I2CM_PSCL_HI 13
+#define I2CM_PSCL_SZ 10
+#define I2CM_MANUAL_MODE_MSK 0x00010000
+#define I2CM_MANUAL_MODE_I_MSK 0xfffeffff
+#define I2CM_MANUAL_MODE_SFT 16
+#define I2CM_MANUAL_MODE_HI 16
+#define I2CM_MANUAL_MODE_SZ 1
+#define I2CM_INT_WDATA_NEED_MSK 0x00020000
+#define I2CM_INT_WDATA_NEED_I_MSK 0xfffdffff
+#define I2CM_INT_WDATA_NEED_SFT 17
+#define I2CM_INT_WDATA_NEED_HI 17
+#define I2CM_INT_WDATA_NEED_SZ 1
+#define I2CM_INT_RDATA_NEED_MSK 0x00040000
+#define I2CM_INT_RDATA_NEED_I_MSK 0xfffbffff
+#define I2CM_INT_RDATA_NEED_SFT 18
+#define I2CM_INT_RDATA_NEED_HI 18
+#define I2CM_INT_RDATA_NEED_SZ 1
+#define I2CM_DEV_A_MSK 0x000003ff
+#define I2CM_DEV_A_I_MSK 0xfffffc00
+#define I2CM_DEV_A_SFT 0
+#define I2CM_DEV_A_HI 9
+#define I2CM_DEV_A_SZ 10
+#define I2CM_DEV_A10B_MSK 0x00004000
+#define I2CM_DEV_A10B_I_MSK 0xffffbfff
+#define I2CM_DEV_A10B_SFT 14
+#define I2CM_DEV_A10B_HI 14
+#define I2CM_DEV_A10B_SZ 1
+#define I2CM_RX_MSK 0x00008000
+#define I2CM_RX_I_MSK 0xffff7fff
+#define I2CM_RX_SFT 15
+#define I2CM_RX_HI 15
+#define I2CM_RX_SZ 1
+#define I2CM_LEN_MSK 0x0000ffff
+#define I2CM_LEN_I_MSK 0xffff0000
+#define I2CM_LEN_SFT 0
+#define I2CM_LEN_HI 15
+#define I2CM_LEN_SZ 16
+#define I2CM_T_LEFT_MSK 0x00070000
+#define I2CM_T_LEFT_I_MSK 0xfff8ffff
+#define I2CM_T_LEFT_SFT 16
+#define I2CM_T_LEFT_HI 18
+#define I2CM_T_LEFT_SZ 3
+#define I2CM_R_GET_MSK 0x07000000
+#define I2CM_R_GET_I_MSK 0xf8ffffff
+#define I2CM_R_GET_SFT 24
+#define I2CM_R_GET_HI 26
+#define I2CM_R_GET_SZ 3
+#define I2CM_WDAT_MSK 0xffffffff
+#define I2CM_WDAT_I_MSK 0x00000000
+#define I2CM_WDAT_SFT 0
+#define I2CM_WDAT_HI 31
+#define I2CM_WDAT_SZ 32
+#define I2CM_RDAT_MSK 0xffffffff
+#define I2CM_RDAT_I_MSK 0x00000000
+#define I2CM_RDAT_SFT 0
+#define I2CM_RDAT_HI 31
+#define I2CM_RDAT_SZ 32
+#define I2CM_SR_LEN_MSK 0x0000ffff
+#define I2CM_SR_LEN_I_MSK 0xffff0000
+#define I2CM_SR_LEN_SFT 0
+#define I2CM_SR_LEN_HI 15
+#define I2CM_SR_LEN_SZ 16
+#define I2CM_SR_RX_MSK 0x00010000
+#define I2CM_SR_RX_I_MSK 0xfffeffff
+#define I2CM_SR_RX_SFT 16
+#define I2CM_SR_RX_HI 16
+#define I2CM_SR_RX_SZ 1
+#define I2CM_REPEAT_START_MSK 0x00020000
+#define I2CM_REPEAT_START_I_MSK 0xfffdffff
+#define I2CM_REPEAT_START_SFT 17
+#define I2CM_REPEAT_START_HI 17
+#define I2CM_REPEAT_START_SZ 1
+#define UART_DATA_MSK 0x000000ff
+#define UART_DATA_I_MSK 0xffffff00
+#define UART_DATA_SFT 0
+#define UART_DATA_HI 7
+#define UART_DATA_SZ 8
+#define DATA_RDY_IE_MSK 0x00000001
+#define DATA_RDY_IE_I_MSK 0xfffffffe
+#define DATA_RDY_IE_SFT 0
+#define DATA_RDY_IE_HI 0
+#define DATA_RDY_IE_SZ 1
+#define THR_EMPTY_IE_MSK 0x00000002
+#define THR_EMPTY_IE_I_MSK 0xfffffffd
+#define THR_EMPTY_IE_SFT 1
+#define THR_EMPTY_IE_HI 1
+#define THR_EMPTY_IE_SZ 1
+#define RX_LINESTS_IE_MSK 0x00000004
+#define RX_LINESTS_IE_I_MSK 0xfffffffb
+#define RX_LINESTS_IE_SFT 2
+#define RX_LINESTS_IE_HI 2
+#define RX_LINESTS_IE_SZ 1
+#define MDM_STS_IE_MSK 0x00000008
+#define MDM_STS_IE_I_MSK 0xfffffff7
+#define MDM_STS_IE_SFT 3
+#define MDM_STS_IE_HI 3
+#define MDM_STS_IE_SZ 1
+#define DMA_RXEND_IE_MSK 0x00000040
+#define DMA_RXEND_IE_I_MSK 0xffffffbf
+#define DMA_RXEND_IE_SFT 6
+#define DMA_RXEND_IE_HI 6
+#define DMA_RXEND_IE_SZ 1
+#define DMA_TXEND_IE_MSK 0x00000080
+#define DMA_TXEND_IE_I_MSK 0xffffff7f
+#define DMA_TXEND_IE_SFT 7
+#define DMA_TXEND_IE_HI 7
+#define DMA_TXEND_IE_SZ 1
+#define FIFO_EN_MSK 0x00000001
+#define FIFO_EN_I_MSK 0xfffffffe
+#define FIFO_EN_SFT 0
+#define FIFO_EN_HI 0
+#define FIFO_EN_SZ 1
+#define RXFIFO_RST_MSK 0x00000002
+#define RXFIFO_RST_I_MSK 0xfffffffd
+#define RXFIFO_RST_SFT 1
+#define RXFIFO_RST_HI 1
+#define RXFIFO_RST_SZ 1
+#define TXFIFO_RST_MSK 0x00000004
+#define TXFIFO_RST_I_MSK 0xfffffffb
+#define TXFIFO_RST_SFT 2
+#define TXFIFO_RST_HI 2
+#define TXFIFO_RST_SZ 1
+#define DMA_MODE_MSK 0x00000008
+#define DMA_MODE_I_MSK 0xfffffff7
+#define DMA_MODE_SFT 3
+#define DMA_MODE_HI 3
+#define DMA_MODE_SZ 1
+#define EN_AUTO_RTS_MSK 0x00000010
+#define EN_AUTO_RTS_I_MSK 0xffffffef
+#define EN_AUTO_RTS_SFT 4
+#define EN_AUTO_RTS_HI 4
+#define EN_AUTO_RTS_SZ 1
+#define EN_AUTO_CTS_MSK 0x00000020
+#define EN_AUTO_CTS_I_MSK 0xffffffdf
+#define EN_AUTO_CTS_SFT 5
+#define EN_AUTO_CTS_HI 5
+#define EN_AUTO_CTS_SZ 1
+#define RXFIFO_TRGLVL_MSK 0x000000c0
+#define RXFIFO_TRGLVL_I_MSK 0xffffff3f
+#define RXFIFO_TRGLVL_SFT 6
+#define RXFIFO_TRGLVL_HI 7
+#define RXFIFO_TRGLVL_SZ 2
+#define WORD_LEN_MSK 0x00000003
+#define WORD_LEN_I_MSK 0xfffffffc
+#define WORD_LEN_SFT 0
+#define WORD_LEN_HI 1
+#define WORD_LEN_SZ 2
+#define STOP_BIT_MSK 0x00000004
+#define STOP_BIT_I_MSK 0xfffffffb
+#define STOP_BIT_SFT 2
+#define STOP_BIT_HI 2
+#define STOP_BIT_SZ 1
+#define PARITY_EN_MSK 0x00000008
+#define PARITY_EN_I_MSK 0xfffffff7
+#define PARITY_EN_SFT 3
+#define PARITY_EN_HI 3
+#define PARITY_EN_SZ 1
+#define EVEN_PARITY_MSK 0x00000010
+#define EVEN_PARITY_I_MSK 0xffffffef
+#define EVEN_PARITY_SFT 4
+#define EVEN_PARITY_HI 4
+#define EVEN_PARITY_SZ 1
+#define FORCE_PARITY_MSK 0x00000020
+#define FORCE_PARITY_I_MSK 0xffffffdf
+#define FORCE_PARITY_SFT 5
+#define FORCE_PARITY_HI 5
+#define FORCE_PARITY_SZ 1
+#define SET_BREAK_MSK 0x00000040
+#define SET_BREAK_I_MSK 0xffffffbf
+#define SET_BREAK_SFT 6
+#define SET_BREAK_HI 6
+#define SET_BREAK_SZ 1
+#define DLAB_MSK 0x00000080
+#define DLAB_I_MSK 0xffffff7f
+#define DLAB_SFT 7
+#define DLAB_HI 7
+#define DLAB_SZ 1
+#define DTR_MSK 0x00000001
+#define DTR_I_MSK 0xfffffffe
+#define DTR_SFT 0
+#define DTR_HI 0
+#define DTR_SZ 1
+#define RTS_MSK 0x00000002
+#define RTS_I_MSK 0xfffffffd
+#define RTS_SFT 1
+#define RTS_HI 1
+#define RTS_SZ 1
+#define OUT_1_MSK 0x00000004
+#define OUT_1_I_MSK 0xfffffffb
+#define OUT_1_SFT 2
+#define OUT_1_HI 2
+#define OUT_1_SZ 1
+#define OUT_2_MSK 0x00000008
+#define OUT_2_I_MSK 0xfffffff7
+#define OUT_2_SFT 3
+#define OUT_2_HI 3
+#define OUT_2_SZ 1
+#define LOOP_BACK_MSK 0x00000010
+#define LOOP_BACK_I_MSK 0xffffffef
+#define LOOP_BACK_SFT 4
+#define LOOP_BACK_HI 4
+#define LOOP_BACK_SZ 1
+#define DATA_RDY_MSK 0x00000001
+#define DATA_RDY_I_MSK 0xfffffffe
+#define DATA_RDY_SFT 0
+#define DATA_RDY_HI 0
+#define DATA_RDY_SZ 1
+#define OVERRUN_ERR_MSK 0x00000002
+#define OVERRUN_ERR_I_MSK 0xfffffffd
+#define OVERRUN_ERR_SFT 1
+#define OVERRUN_ERR_HI 1
+#define OVERRUN_ERR_SZ 1
+#define PARITY_ERR_MSK 0x00000004
+#define PARITY_ERR_I_MSK 0xfffffffb
+#define PARITY_ERR_SFT 2
+#define PARITY_ERR_HI 2
+#define PARITY_ERR_SZ 1
+#define FRAMING_ERR_MSK 0x00000008
+#define FRAMING_ERR_I_MSK 0xfffffff7
+#define FRAMING_ERR_SFT 3
+#define FRAMING_ERR_HI 3
+#define FRAMING_ERR_SZ 1
+#define BREAK_INT_MSK 0x00000010
+#define BREAK_INT_I_MSK 0xffffffef
+#define BREAK_INT_SFT 4
+#define BREAK_INT_HI 4
+#define BREAK_INT_SZ 1
+#define THR_EMPTY_MSK 0x00000020
+#define THR_EMPTY_I_MSK 0xffffffdf
+#define THR_EMPTY_SFT 5
+#define THR_EMPTY_HI 5
+#define THR_EMPTY_SZ 1
+#define TX_EMPTY_MSK 0x00000040
+#define TX_EMPTY_I_MSK 0xffffffbf
+#define TX_EMPTY_SFT 6
+#define TX_EMPTY_HI 6
+#define TX_EMPTY_SZ 1
+#define FIFODATA_ERR_MSK 0x00000080
+#define FIFODATA_ERR_I_MSK 0xffffff7f
+#define FIFODATA_ERR_SFT 7
+#define FIFODATA_ERR_HI 7
+#define FIFODATA_ERR_SZ 1
+#define DELTA_CTS_MSK 0x00000001
+#define DELTA_CTS_I_MSK 0xfffffffe
+#define DELTA_CTS_SFT 0
+#define DELTA_CTS_HI 0
+#define DELTA_CTS_SZ 1
+#define DELTA_DSR_MSK 0x00000002
+#define DELTA_DSR_I_MSK 0xfffffffd
+#define DELTA_DSR_SFT 1
+#define DELTA_DSR_HI 1
+#define DELTA_DSR_SZ 1
+#define TRAILEDGE_RI_MSK 0x00000004
+#define TRAILEDGE_RI_I_MSK 0xfffffffb
+#define TRAILEDGE_RI_SFT 2
+#define TRAILEDGE_RI_HI 2
+#define TRAILEDGE_RI_SZ 1
+#define DELTA_CD_MSK 0x00000008
+#define DELTA_CD_I_MSK 0xfffffff7
+#define DELTA_CD_SFT 3
+#define DELTA_CD_HI 3
+#define DELTA_CD_SZ 1
+#define CTS_MSK 0x00000010
+#define CTS_I_MSK 0xffffffef
+#define CTS_SFT 4
+#define CTS_HI 4
+#define CTS_SZ 1
+#define DSR_MSK 0x00000020
+#define DSR_I_MSK 0xffffffdf
+#define DSR_SFT 5
+#define DSR_HI 5
+#define DSR_SZ 1
+#define RI_MSK 0x00000040
+#define RI_I_MSK 0xffffffbf
+#define RI_SFT 6
+#define RI_HI 6
+#define RI_SZ 1
+#define CD_MSK 0x00000080
+#define CD_I_MSK 0xffffff7f
+#define CD_SFT 7
+#define CD_HI 7
+#define CD_SZ 1
+#define BRDC_DIV_MSK 0x0000ffff
+#define BRDC_DIV_I_MSK 0xffff0000
+#define BRDC_DIV_SFT 0
+#define BRDC_DIV_HI 15
+#define BRDC_DIV_SZ 16
+#define RTHR_L_MSK 0x0000000f
+#define RTHR_L_I_MSK 0xfffffff0
+#define RTHR_L_SFT 0
+#define RTHR_L_HI 3
+#define RTHR_L_SZ 4
+#define RTHR_H_MSK 0x000000f0
+#define RTHR_H_I_MSK 0xffffff0f
+#define RTHR_H_SFT 4
+#define RTHR_H_HI 7
+#define RTHR_H_SZ 4
+#define INT_IDCODE_MSK 0x0000000f
+#define INT_IDCODE_I_MSK 0xfffffff0
+#define INT_IDCODE_SFT 0
+#define INT_IDCODE_HI 3
+#define INT_IDCODE_SZ 4
+#define FIFOS_ENABLED_MSK 0x000000c0
+#define FIFOS_ENABLED_I_MSK 0xffffff3f
+#define FIFOS_ENABLED_SFT 6
+#define FIFOS_ENABLED_HI 7
+#define FIFOS_ENABLED_SZ 2
+#define DAT_UART_DATA_MSK 0x000000ff
+#define DAT_UART_DATA_I_MSK 0xffffff00
+#define DAT_UART_DATA_SFT 0
+#define DAT_UART_DATA_HI 7
+#define DAT_UART_DATA_SZ 8
+#define DAT_DATA_RDY_IE_MSK 0x00000001
+#define DAT_DATA_RDY_IE_I_MSK 0xfffffffe
+#define DAT_DATA_RDY_IE_SFT 0
+#define DAT_DATA_RDY_IE_HI 0
+#define DAT_DATA_RDY_IE_SZ 1
+#define DAT_THR_EMPTY_IE_MSK 0x00000002
+#define DAT_THR_EMPTY_IE_I_MSK 0xfffffffd
+#define DAT_THR_EMPTY_IE_SFT 1
+#define DAT_THR_EMPTY_IE_HI 1
+#define DAT_THR_EMPTY_IE_SZ 1
+#define DAT_RX_LINESTS_IE_MSK 0x00000004
+#define DAT_RX_LINESTS_IE_I_MSK 0xfffffffb
+#define DAT_RX_LINESTS_IE_SFT 2
+#define DAT_RX_LINESTS_IE_HI 2
+#define DAT_RX_LINESTS_IE_SZ 1
+#define DAT_MDM_STS_IE_MSK 0x00000008
+#define DAT_MDM_STS_IE_I_MSK 0xfffffff7
+#define DAT_MDM_STS_IE_SFT 3
+#define DAT_MDM_STS_IE_HI 3
+#define DAT_MDM_STS_IE_SZ 1
+#define DAT_DMA_RXEND_IE_MSK 0x00000040
+#define DAT_DMA_RXEND_IE_I_MSK 0xffffffbf
+#define DAT_DMA_RXEND_IE_SFT 6
+#define DAT_DMA_RXEND_IE_HI 6
+#define DAT_DMA_RXEND_IE_SZ 1
+#define DAT_DMA_TXEND_IE_MSK 0x00000080
+#define DAT_DMA_TXEND_IE_I_MSK 0xffffff7f
+#define DAT_DMA_TXEND_IE_SFT 7
+#define DAT_DMA_TXEND_IE_HI 7
+#define DAT_DMA_TXEND_IE_SZ 1
+#define DAT_FIFO_EN_MSK 0x00000001
+#define DAT_FIFO_EN_I_MSK 0xfffffffe
+#define DAT_FIFO_EN_SFT 0
+#define DAT_FIFO_EN_HI 0
+#define DAT_FIFO_EN_SZ 1
+#define DAT_RXFIFO_RST_MSK 0x00000002
+#define DAT_RXFIFO_RST_I_MSK 0xfffffffd
+#define DAT_RXFIFO_RST_SFT 1
+#define DAT_RXFIFO_RST_HI 1
+#define DAT_RXFIFO_RST_SZ 1
+#define DAT_TXFIFO_RST_MSK 0x00000004
+#define DAT_TXFIFO_RST_I_MSK 0xfffffffb
+#define DAT_TXFIFO_RST_SFT 2
+#define DAT_TXFIFO_RST_HI 2
+#define DAT_TXFIFO_RST_SZ 1
+#define DAT_DMA_MODE_MSK 0x00000008
+#define DAT_DMA_MODE_I_MSK 0xfffffff7
+#define DAT_DMA_MODE_SFT 3
+#define DAT_DMA_MODE_HI 3
+#define DAT_DMA_MODE_SZ 1
+#define DAT_EN_AUTO_RTS_MSK 0x00000010
+#define DAT_EN_AUTO_RTS_I_MSK 0xffffffef
+#define DAT_EN_AUTO_RTS_SFT 4
+#define DAT_EN_AUTO_RTS_HI 4
+#define DAT_EN_AUTO_RTS_SZ 1
+#define DAT_EN_AUTO_CTS_MSK 0x00000020
+#define DAT_EN_AUTO_CTS_I_MSK 0xffffffdf
+#define DAT_EN_AUTO_CTS_SFT 5
+#define DAT_EN_AUTO_CTS_HI 5
+#define DAT_EN_AUTO_CTS_SZ 1
+#define DAT_RXFIFO_TRGLVL_MSK 0x000000c0
+#define DAT_RXFIFO_TRGLVL_I_MSK 0xffffff3f
+#define DAT_RXFIFO_TRGLVL_SFT 6
+#define DAT_RXFIFO_TRGLVL_HI 7
+#define DAT_RXFIFO_TRGLVL_SZ 2
+#define DAT_WORD_LEN_MSK 0x00000003
+#define DAT_WORD_LEN_I_MSK 0xfffffffc
+#define DAT_WORD_LEN_SFT 0
+#define DAT_WORD_LEN_HI 1
+#define DAT_WORD_LEN_SZ 2
+#define DAT_STOP_BIT_MSK 0x00000004
+#define DAT_STOP_BIT_I_MSK 0xfffffffb
+#define DAT_STOP_BIT_SFT 2
+#define DAT_STOP_BIT_HI 2
+#define DAT_STOP_BIT_SZ 1
+#define DAT_PARITY_EN_MSK 0x00000008
+#define DAT_PARITY_EN_I_MSK 0xfffffff7
+#define DAT_PARITY_EN_SFT 3
+#define DAT_PARITY_EN_HI 3
+#define DAT_PARITY_EN_SZ 1
+#define DAT_EVEN_PARITY_MSK 0x00000010
+#define DAT_EVEN_PARITY_I_MSK 0xffffffef
+#define DAT_EVEN_PARITY_SFT 4
+#define DAT_EVEN_PARITY_HI 4
+#define DAT_EVEN_PARITY_SZ 1
+#define DAT_FORCE_PARITY_MSK 0x00000020
+#define DAT_FORCE_PARITY_I_MSK 0xffffffdf
+#define DAT_FORCE_PARITY_SFT 5
+#define DAT_FORCE_PARITY_HI 5
+#define DAT_FORCE_PARITY_SZ 1
+#define DAT_SET_BREAK_MSK 0x00000040
+#define DAT_SET_BREAK_I_MSK 0xffffffbf
+#define DAT_SET_BREAK_SFT 6
+#define DAT_SET_BREAK_HI 6
+#define DAT_SET_BREAK_SZ 1
+#define DAT_DLAB_MSK 0x00000080
+#define DAT_DLAB_I_MSK 0xffffff7f
+#define DAT_DLAB_SFT 7
+#define DAT_DLAB_HI 7
+#define DAT_DLAB_SZ 1
+#define DAT_DTR_MSK 0x00000001
+#define DAT_DTR_I_MSK 0xfffffffe
+#define DAT_DTR_SFT 0
+#define DAT_DTR_HI 0
+#define DAT_DTR_SZ 1
+#define DAT_RTS_MSK 0x00000002
+#define DAT_RTS_I_MSK 0xfffffffd
+#define DAT_RTS_SFT 1
+#define DAT_RTS_HI 1
+#define DAT_RTS_SZ 1
+#define DAT_OUT_1_MSK 0x00000004
+#define DAT_OUT_1_I_MSK 0xfffffffb
+#define DAT_OUT_1_SFT 2
+#define DAT_OUT_1_HI 2
+#define DAT_OUT_1_SZ 1
+#define DAT_OUT_2_MSK 0x00000008
+#define DAT_OUT_2_I_MSK 0xfffffff7
+#define DAT_OUT_2_SFT 3
+#define DAT_OUT_2_HI 3
+#define DAT_OUT_2_SZ 1
+#define DAT_LOOP_BACK_MSK 0x00000010
+#define DAT_LOOP_BACK_I_MSK 0xffffffef
+#define DAT_LOOP_BACK_SFT 4
+#define DAT_LOOP_BACK_HI 4
+#define DAT_LOOP_BACK_SZ 1
+#define DAT_DATA_RDY_MSK 0x00000001
+#define DAT_DATA_RDY_I_MSK 0xfffffffe
+#define DAT_DATA_RDY_SFT 0
+#define DAT_DATA_RDY_HI 0
+#define DAT_DATA_RDY_SZ 1
+#define DAT_OVERRUN_ERR_MSK 0x00000002
+#define DAT_OVERRUN_ERR_I_MSK 0xfffffffd
+#define DAT_OVERRUN_ERR_SFT 1
+#define DAT_OVERRUN_ERR_HI 1
+#define DAT_OVERRUN_ERR_SZ 1
+#define DAT_PARITY_ERR_MSK 0x00000004
+#define DAT_PARITY_ERR_I_MSK 0xfffffffb
+#define DAT_PARITY_ERR_SFT 2
+#define DAT_PARITY_ERR_HI 2
+#define DAT_PARITY_ERR_SZ 1
+#define DAT_FRAMING_ERR_MSK 0x00000008
+#define DAT_FRAMING_ERR_I_MSK 0xfffffff7
+#define DAT_FRAMING_ERR_SFT 3
+#define DAT_FRAMING_ERR_HI 3
+#define DAT_FRAMING_ERR_SZ 1
+#define DAT_BREAK_INT_MSK 0x00000010
+#define DAT_BREAK_INT_I_MSK 0xffffffef
+#define DAT_BREAK_INT_SFT 4
+#define DAT_BREAK_INT_HI 4
+#define DAT_BREAK_INT_SZ 1
+#define DAT_THR_EMPTY_MSK 0x00000020
+#define DAT_THR_EMPTY_I_MSK 0xffffffdf
+#define DAT_THR_EMPTY_SFT 5
+#define DAT_THR_EMPTY_HI 5
+#define DAT_THR_EMPTY_SZ 1
+#define DAT_TX_EMPTY_MSK 0x00000040
+#define DAT_TX_EMPTY_I_MSK 0xffffffbf
+#define DAT_TX_EMPTY_SFT 6
+#define DAT_TX_EMPTY_HI 6
+#define DAT_TX_EMPTY_SZ 1
+#define DAT_FIFODATA_ERR_MSK 0x00000080
+#define DAT_FIFODATA_ERR_I_MSK 0xffffff7f
+#define DAT_FIFODATA_ERR_SFT 7
+#define DAT_FIFODATA_ERR_HI 7
+#define DAT_FIFODATA_ERR_SZ 1
+#define DAT_DELTA_CTS_MSK 0x00000001
+#define DAT_DELTA_CTS_I_MSK 0xfffffffe
+#define DAT_DELTA_CTS_SFT 0
+#define DAT_DELTA_CTS_HI 0
+#define DAT_DELTA_CTS_SZ 1
+#define DAT_DELTA_DSR_MSK 0x00000002
+#define DAT_DELTA_DSR_I_MSK 0xfffffffd
+#define DAT_DELTA_DSR_SFT 1
+#define DAT_DELTA_DSR_HI 1
+#define DAT_DELTA_DSR_SZ 1
+#define DAT_TRAILEDGE_RI_MSK 0x00000004
+#define DAT_TRAILEDGE_RI_I_MSK 0xfffffffb
+#define DAT_TRAILEDGE_RI_SFT 2
+#define DAT_TRAILEDGE_RI_HI 2
+#define DAT_TRAILEDGE_RI_SZ 1
+#define DAT_DELTA_CD_MSK 0x00000008
+#define DAT_DELTA_CD_I_MSK 0xfffffff7
+#define DAT_DELTA_CD_SFT 3
+#define DAT_DELTA_CD_HI 3
+#define DAT_DELTA_CD_SZ 1
+#define DAT_CTS_MSK 0x00000010
+#define DAT_CTS_I_MSK 0xffffffef
+#define DAT_CTS_SFT 4
+#define DAT_CTS_HI 4
+#define DAT_CTS_SZ 1
+#define DAT_DSR_MSK 0x00000020
+#define DAT_DSR_I_MSK 0xffffffdf
+#define DAT_DSR_SFT 5
+#define DAT_DSR_HI 5
+#define DAT_DSR_SZ 1
+#define DAT_RI_MSK 0x00000040
+#define DAT_RI_I_MSK 0xffffffbf
+#define DAT_RI_SFT 6
+#define DAT_RI_HI 6
+#define DAT_RI_SZ 1
+#define DAT_CD_MSK 0x00000080
+#define DAT_CD_I_MSK 0xffffff7f
+#define DAT_CD_SFT 7
+#define DAT_CD_HI 7
+#define DAT_CD_SZ 1
+#define DAT_BRDC_DIV_MSK 0x0000ffff
+#define DAT_BRDC_DIV_I_MSK 0xffff0000
+#define DAT_BRDC_DIV_SFT 0
+#define DAT_BRDC_DIV_HI 15
+#define DAT_BRDC_DIV_SZ 16
+#define DAT_RTHR_L_MSK 0x0000000f
+#define DAT_RTHR_L_I_MSK 0xfffffff0
+#define DAT_RTHR_L_SFT 0
+#define DAT_RTHR_L_HI 3
+#define DAT_RTHR_L_SZ 4
+#define DAT_RTHR_H_MSK 0x000000f0
+#define DAT_RTHR_H_I_MSK 0xffffff0f
+#define DAT_RTHR_H_SFT 4
+#define DAT_RTHR_H_HI 7
+#define DAT_RTHR_H_SZ 4
+#define DAT_INT_IDCODE_MSK 0x0000000f
+#define DAT_INT_IDCODE_I_MSK 0xfffffff0
+#define DAT_INT_IDCODE_SFT 0
+#define DAT_INT_IDCODE_HI 3
+#define DAT_INT_IDCODE_SZ 4
+#define DAT_FIFOS_ENABLED_MSK 0x000000c0
+#define DAT_FIFOS_ENABLED_I_MSK 0xffffff3f
+#define DAT_FIFOS_ENABLED_SFT 6
+#define DAT_FIFOS_ENABLED_HI 7
+#define DAT_FIFOS_ENABLED_SZ 2
+#define MASK_TOP_MSK 0xffffffff
+#define MASK_TOP_I_MSK 0x00000000
+#define MASK_TOP_SFT 0
+#define MASK_TOP_HI 31
+#define MASK_TOP_SZ 32
+#define INT_MODE_MSK 0xffffffff
+#define INT_MODE_I_MSK 0x00000000
+#define INT_MODE_SFT 0
+#define INT_MODE_HI 31
+#define INT_MODE_SZ 32
+#define IRQ_PHY_0_MSK 0x00000001
+#define IRQ_PHY_0_I_MSK 0xfffffffe
+#define IRQ_PHY_0_SFT 0
+#define IRQ_PHY_0_HI 0
+#define IRQ_PHY_0_SZ 1
+#define IRQ_PHY_1_MSK 0x00000002
+#define IRQ_PHY_1_I_MSK 0xfffffffd
+#define IRQ_PHY_1_SFT 1
+#define IRQ_PHY_1_HI 1
+#define IRQ_PHY_1_SZ 1
+#define IRQ_SDIO_MSK 0x00000004
+#define IRQ_SDIO_I_MSK 0xfffffffb
+#define IRQ_SDIO_SFT 2
+#define IRQ_SDIO_HI 2
+#define IRQ_SDIO_SZ 1
+#define IRQ_BEACON_DONE_MSK 0x00000008
+#define IRQ_BEACON_DONE_I_MSK 0xfffffff7
+#define IRQ_BEACON_DONE_SFT 3
+#define IRQ_BEACON_DONE_HI 3
+#define IRQ_BEACON_DONE_SZ 1
+#define IRQ_BEACON_MSK 0x00000010
+#define IRQ_BEACON_I_MSK 0xffffffef
+#define IRQ_BEACON_SFT 4
+#define IRQ_BEACON_HI 4
+#define IRQ_BEACON_SZ 1
+#define IRQ_PRE_BEACON_MSK 0x00000020
+#define IRQ_PRE_BEACON_I_MSK 0xffffffdf
+#define IRQ_PRE_BEACON_SFT 5
+#define IRQ_PRE_BEACON_HI 5
+#define IRQ_PRE_BEACON_SZ 1
+#define IRQ_EDCA0_TX_DONE_MSK 0x00000040
+#define IRQ_EDCA0_TX_DONE_I_MSK 0xffffffbf
+#define IRQ_EDCA0_TX_DONE_SFT 6
+#define IRQ_EDCA0_TX_DONE_HI 6
+#define IRQ_EDCA0_TX_DONE_SZ 1
+#define IRQ_EDCA1_TX_DONE_MSK 0x00000080
+#define IRQ_EDCA1_TX_DONE_I_MSK 0xffffff7f
+#define IRQ_EDCA1_TX_DONE_SFT 7
+#define IRQ_EDCA1_TX_DONE_HI 7
+#define IRQ_EDCA1_TX_DONE_SZ 1
+#define IRQ_EDCA2_TX_DONE_MSK 0x00000100
+#define IRQ_EDCA2_TX_DONE_I_MSK 0xfffffeff
+#define IRQ_EDCA2_TX_DONE_SFT 8
+#define IRQ_EDCA2_TX_DONE_HI 8
+#define IRQ_EDCA2_TX_DONE_SZ 1
+#define IRQ_EDCA3_TX_DONE_MSK 0x00000200
+#define IRQ_EDCA3_TX_DONE_I_MSK 0xfffffdff
+#define IRQ_EDCA3_TX_DONE_SFT 9
+#define IRQ_EDCA3_TX_DONE_HI 9
+#define IRQ_EDCA3_TX_DONE_SZ 1
+#define IRQ_EDCA4_TX_DONE_MSK 0x00000400
+#define IRQ_EDCA4_TX_DONE_I_MSK 0xfffffbff
+#define IRQ_EDCA4_TX_DONE_SFT 10
+#define IRQ_EDCA4_TX_DONE_HI 10
+#define IRQ_EDCA4_TX_DONE_SZ 1
+#define IRQ_BEACON_DTIM_MSK 0x00001000
+#define IRQ_BEACON_DTIM_I_MSK 0xffffefff
+#define IRQ_BEACON_DTIM_SFT 12
+#define IRQ_BEACON_DTIM_HI 12
+#define IRQ_BEACON_DTIM_SZ 1
+#define IRQ_EDCA0_LOWTHOLD_INT_MSK 0x00002000
+#define IRQ_EDCA0_LOWTHOLD_INT_I_MSK 0xffffdfff
+#define IRQ_EDCA0_LOWTHOLD_INT_SFT 13
+#define IRQ_EDCA0_LOWTHOLD_INT_HI 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA1_LOWTHOLD_INT_MSK 0x00004000
+#define IRQ_EDCA1_LOWTHOLD_INT_I_MSK 0xffffbfff
+#define IRQ_EDCA1_LOWTHOLD_INT_SFT 14
+#define IRQ_EDCA1_LOWTHOLD_INT_HI 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA2_LOWTHOLD_INT_MSK 0x00008000
+#define IRQ_EDCA2_LOWTHOLD_INT_I_MSK 0xffff7fff
+#define IRQ_EDCA2_LOWTHOLD_INT_SFT 15
+#define IRQ_EDCA2_LOWTHOLD_INT_HI 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA3_LOWTHOLD_INT_MSK 0x00010000
+#define IRQ_EDCA3_LOWTHOLD_INT_I_MSK 0xfffeffff
+#define IRQ_EDCA3_LOWTHOLD_INT_SFT 16
+#define IRQ_EDCA3_LOWTHOLD_INT_HI 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SZ 1
+#define IRQ_FENCE_HIT_INT_MSK 0x00020000
+#define IRQ_FENCE_HIT_INT_I_MSK 0xfffdffff
+#define IRQ_FENCE_HIT_INT_SFT 17
+#define IRQ_FENCE_HIT_INT_HI 17
+#define IRQ_FENCE_HIT_INT_SZ 1
+#define IRQ_ILL_ADDR_INT_MSK 0x00040000
+#define IRQ_ILL_ADDR_INT_I_MSK 0xfffbffff
+#define IRQ_ILL_ADDR_INT_SFT 18
+#define IRQ_ILL_ADDR_INT_HI 18
+#define IRQ_ILL_ADDR_INT_SZ 1
+#define IRQ_MBOX_MSK 0x00080000
+#define IRQ_MBOX_I_MSK 0xfff7ffff
+#define IRQ_MBOX_SFT 19
+#define IRQ_MBOX_HI 19
+#define IRQ_MBOX_SZ 1
+#define IRQ_US_TIMER0_MSK 0x00100000
+#define IRQ_US_TIMER0_I_MSK 0xffefffff
+#define IRQ_US_TIMER0_SFT 20
+#define IRQ_US_TIMER0_HI 20
+#define IRQ_US_TIMER0_SZ 1
+#define IRQ_US_TIMER1_MSK 0x00200000
+#define IRQ_US_TIMER1_I_MSK 0xffdfffff
+#define IRQ_US_TIMER1_SFT 21
+#define IRQ_US_TIMER1_HI 21
+#define IRQ_US_TIMER1_SZ 1
+#define IRQ_US_TIMER2_MSK 0x00400000
+#define IRQ_US_TIMER2_I_MSK 0xffbfffff
+#define IRQ_US_TIMER2_SFT 22
+#define IRQ_US_TIMER2_HI 22
+#define IRQ_US_TIMER2_SZ 1
+#define IRQ_US_TIMER3_MSK 0x00800000
+#define IRQ_US_TIMER3_I_MSK 0xff7fffff
+#define IRQ_US_TIMER3_SFT 23
+#define IRQ_US_TIMER3_HI 23
+#define IRQ_US_TIMER3_SZ 1
+#define IRQ_MS_TIMER0_MSK 0x01000000
+#define IRQ_MS_TIMER0_I_MSK 0xfeffffff
+#define IRQ_MS_TIMER0_SFT 24
+#define IRQ_MS_TIMER0_HI 24
+#define IRQ_MS_TIMER0_SZ 1
+#define IRQ_MS_TIMER1_MSK 0x02000000
+#define IRQ_MS_TIMER1_I_MSK 0xfdffffff
+#define IRQ_MS_TIMER1_SFT 25
+#define IRQ_MS_TIMER1_HI 25
+#define IRQ_MS_TIMER1_SZ 1
+#define IRQ_MS_TIMER2_MSK 0x04000000
+#define IRQ_MS_TIMER2_I_MSK 0xfbffffff
+#define IRQ_MS_TIMER2_SFT 26
+#define IRQ_MS_TIMER2_HI 26
+#define IRQ_MS_TIMER2_SZ 1
+#define IRQ_MS_TIMER3_MSK 0x08000000
+#define IRQ_MS_TIMER3_I_MSK 0xf7ffffff
+#define IRQ_MS_TIMER3_SFT 27
+#define IRQ_MS_TIMER3_HI 27
+#define IRQ_MS_TIMER3_SZ 1
+#define IRQ_TX_LIMIT_INT_MSK 0x10000000
+#define IRQ_TX_LIMIT_INT_I_MSK 0xefffffff
+#define IRQ_TX_LIMIT_INT_SFT 28
+#define IRQ_TX_LIMIT_INT_HI 28
+#define IRQ_TX_LIMIT_INT_SZ 1
+#define IRQ_DMA0_MSK 0x20000000
+#define IRQ_DMA0_I_MSK 0xdfffffff
+#define IRQ_DMA0_SFT 29
+#define IRQ_DMA0_HI 29
+#define IRQ_DMA0_SZ 1
+#define IRQ_CO_DMA_MSK 0x40000000
+#define IRQ_CO_DMA_I_MSK 0xbfffffff
+#define IRQ_CO_DMA_SFT 30
+#define IRQ_CO_DMA_HI 30
+#define IRQ_CO_DMA_SZ 1
+#define IRQ_PERI_GROUP_MSK 0x80000000
+#define IRQ_PERI_GROUP_I_MSK 0x7fffffff
+#define IRQ_PERI_GROUP_SFT 31
+#define IRQ_PERI_GROUP_HI 31
+#define IRQ_PERI_GROUP_SZ 1
+#define FIQ_STATUS_MSK 0xffffffff
+#define FIQ_STATUS_I_MSK 0x00000000
+#define FIQ_STATUS_SFT 0
+#define FIQ_STATUS_HI 31
+#define FIQ_STATUS_SZ 32
+#define IRQ_RAW_MSK 0xffffffff
+#define IRQ_RAW_I_MSK 0x00000000
+#define IRQ_RAW_SFT 0
+#define IRQ_RAW_HI 31
+#define IRQ_RAW_SZ 32
+#define FIQ_RAW_MSK 0xffffffff
+#define FIQ_RAW_I_MSK 0x00000000
+#define FIQ_RAW_SFT 0
+#define FIQ_RAW_HI 31
+#define FIQ_RAW_SZ 32
+#define INT_PERI_MASK_MSK 0xffffffff
+#define INT_PERI_MASK_I_MSK 0x00000000
+#define INT_PERI_MASK_SFT 0
+#define INT_PERI_MASK_HI 31
+#define INT_PERI_MASK_SZ 32
+#define PERI_RTC_MSK 0x00000001
+#define PERI_RTC_I_MSK 0xfffffffe
+#define PERI_RTC_SFT 0
+#define PERI_RTC_HI 0
+#define PERI_RTC_SZ 1
+#define IRQ_UART0_TX_MSK 0x00000002
+#define IRQ_UART0_TX_I_MSK 0xfffffffd
+#define IRQ_UART0_TX_SFT 1
+#define IRQ_UART0_TX_HI 1
+#define IRQ_UART0_TX_SZ 1
+#define IRQ_UART0_RX_MSK 0x00000004
+#define IRQ_UART0_RX_I_MSK 0xfffffffb
+#define IRQ_UART0_RX_SFT 2
+#define IRQ_UART0_RX_HI 2
+#define IRQ_UART0_RX_SZ 1
+#define PERI_GPI_2_MSK 0x00000008
+#define PERI_GPI_2_I_MSK 0xfffffff7
+#define PERI_GPI_2_SFT 3
+#define PERI_GPI_2_HI 3
+#define PERI_GPI_2_SZ 1
+#define IRQ_SPI_IPC_MSK 0x00000010
+#define IRQ_SPI_IPC_I_MSK 0xffffffef
+#define IRQ_SPI_IPC_SFT 4
+#define IRQ_SPI_IPC_HI 4
+#define IRQ_SPI_IPC_SZ 1
+#define PERI_GPI_1_0_MSK 0x00000060
+#define PERI_GPI_1_0_I_MSK 0xffffff9f
+#define PERI_GPI_1_0_SFT 5
+#define PERI_GPI_1_0_HI 6
+#define PERI_GPI_1_0_SZ 2
+#define SCRT_INT_1_MSK 0x00000080
+#define SCRT_INT_1_I_MSK 0xffffff7f
+#define SCRT_INT_1_SFT 7
+#define SCRT_INT_1_HI 7
+#define SCRT_INT_1_SZ 1
+#define MMU_ALC_ERR_MSK 0x00000100
+#define MMU_ALC_ERR_I_MSK 0xfffffeff
+#define MMU_ALC_ERR_SFT 8
+#define MMU_ALC_ERR_HI 8
+#define MMU_ALC_ERR_SZ 1
+#define MMU_RLS_ERR_MSK 0x00000200
+#define MMU_RLS_ERR_I_MSK 0xfffffdff
+#define MMU_RLS_ERR_SFT 9
+#define MMU_RLS_ERR_HI 9
+#define MMU_RLS_ERR_SZ 1
+#define ID_MNG_INT_1_MSK 0x00000400
+#define ID_MNG_INT_1_I_MSK 0xfffffbff
+#define ID_MNG_INT_1_SFT 10
+#define ID_MNG_INT_1_HI 10
+#define ID_MNG_INT_1_SZ 1
+#define MBOX_INT_1_MSK 0x00000800
+#define MBOX_INT_1_I_MSK 0xfffff7ff
+#define MBOX_INT_1_SFT 11
+#define MBOX_INT_1_HI 11
+#define MBOX_INT_1_SZ 1
+#define MBOX_INT_2_MSK 0x00001000
+#define MBOX_INT_2_I_MSK 0xffffefff
+#define MBOX_INT_2_SFT 12
+#define MBOX_INT_2_HI 12
+#define MBOX_INT_2_SZ 1
+#define MBOX_INT_3_MSK 0x00002000
+#define MBOX_INT_3_I_MSK 0xffffdfff
+#define MBOX_INT_3_SFT 13
+#define MBOX_INT_3_HI 13
+#define MBOX_INT_3_SZ 1
+#define HCI_INT_1_MSK 0x00004000
+#define HCI_INT_1_I_MSK 0xffffbfff
+#define HCI_INT_1_SFT 14
+#define HCI_INT_1_HI 14
+#define HCI_INT_1_SZ 1
+#define UART_RX_TIMEOUT_MSK 0x00008000
+#define UART_RX_TIMEOUT_I_MSK 0xffff7fff
+#define UART_RX_TIMEOUT_SFT 15
+#define UART_RX_TIMEOUT_HI 15
+#define UART_RX_TIMEOUT_SZ 1
+#define UART_MULTI_IRQ_MSK 0x00010000
+#define UART_MULTI_IRQ_I_MSK 0xfffeffff
+#define UART_MULTI_IRQ_SFT 16
+#define UART_MULTI_IRQ_HI 16
+#define UART_MULTI_IRQ_SZ 1
+#define ID_MNG_INT_2_MSK 0x00020000
+#define ID_MNG_INT_2_I_MSK 0xfffdffff
+#define ID_MNG_INT_2_SFT 17
+#define ID_MNG_INT_2_HI 17
+#define ID_MNG_INT_2_SZ 1
+#define DMN_NOHIT_INT_MSK 0x00040000
+#define DMN_NOHIT_INT_I_MSK 0xfffbffff
+#define DMN_NOHIT_INT_SFT 18
+#define DMN_NOHIT_INT_HI 18
+#define DMN_NOHIT_INT_SZ 1
+#define ID_THOLD_RX_MSK 0x00080000
+#define ID_THOLD_RX_I_MSK 0xfff7ffff
+#define ID_THOLD_RX_SFT 19
+#define ID_THOLD_RX_HI 19
+#define ID_THOLD_RX_SZ 1
+#define ID_THOLD_TX_MSK 0x00100000
+#define ID_THOLD_TX_I_MSK 0xffefffff
+#define ID_THOLD_TX_SFT 20
+#define ID_THOLD_TX_HI 20
+#define ID_THOLD_TX_SZ 1
+#define ID_DOUBLE_RLS_MSK 0x00200000
+#define ID_DOUBLE_RLS_I_MSK 0xffdfffff
+#define ID_DOUBLE_RLS_SFT 21
+#define ID_DOUBLE_RLS_HI 21
+#define ID_DOUBLE_RLS_SZ 1
+#define RX_ID_LEN_THOLD_MSK 0x00400000
+#define RX_ID_LEN_THOLD_I_MSK 0xffbfffff
+#define RX_ID_LEN_THOLD_SFT 22
+#define RX_ID_LEN_THOLD_HI 22
+#define RX_ID_LEN_THOLD_SZ 1
+#define TX_ID_LEN_THOLD_MSK 0x00800000
+#define TX_ID_LEN_THOLD_I_MSK 0xff7fffff
+#define TX_ID_LEN_THOLD_SFT 23
+#define TX_ID_LEN_THOLD_HI 23
+#define TX_ID_LEN_THOLD_SZ 1
+#define ALL_ID_LEN_THOLD_MSK 0x01000000
+#define ALL_ID_LEN_THOLD_I_MSK 0xfeffffff
+#define ALL_ID_LEN_THOLD_SFT 24
+#define ALL_ID_LEN_THOLD_HI 24
+#define ALL_ID_LEN_THOLD_SZ 1
+#define DMN_MCU_INT_MSK 0x02000000
+#define DMN_MCU_INT_I_MSK 0xfdffffff
+#define DMN_MCU_INT_SFT 25
+#define DMN_MCU_INT_HI 25
+#define DMN_MCU_INT_SZ 1
+#define IRQ_DAT_UART_TX_MSK 0x04000000
+#define IRQ_DAT_UART_TX_I_MSK 0xfbffffff
+#define IRQ_DAT_UART_TX_SFT 26
+#define IRQ_DAT_UART_TX_HI 26
+#define IRQ_DAT_UART_TX_SZ 1
+#define IRQ_DAT_UART_RX_MSK 0x08000000
+#define IRQ_DAT_UART_RX_I_MSK 0xf7ffffff
+#define IRQ_DAT_UART_RX_SFT 27
+#define IRQ_DAT_UART_RX_HI 27
+#define IRQ_DAT_UART_RX_SZ 1
+#define DAT_UART_RX_TIMEOUT_MSK 0x10000000
+#define DAT_UART_RX_TIMEOUT_I_MSK 0xefffffff
+#define DAT_UART_RX_TIMEOUT_SFT 28
+#define DAT_UART_RX_TIMEOUT_HI 28
+#define DAT_UART_RX_TIMEOUT_SZ 1
+#define DAT_UART_MULTI_IRQ_MSK 0x20000000
+#define DAT_UART_MULTI_IRQ_I_MSK 0xdfffffff
+#define DAT_UART_MULTI_IRQ_SFT 29
+#define DAT_UART_MULTI_IRQ_HI 29
+#define DAT_UART_MULTI_IRQ_SZ 1
+#define ALR_ABT_NOCHG_INT_IRQ_MSK 0x40000000
+#define ALR_ABT_NOCHG_INT_IRQ_I_MSK 0xbfffffff
+#define ALR_ABT_NOCHG_INT_IRQ_SFT 30
+#define ALR_ABT_NOCHG_INT_IRQ_HI 30
+#define ALR_ABT_NOCHG_INT_IRQ_SZ 1
+#define TBLNEQ_MNGPKT_INT_IRQ_MSK 0x80000000
+#define TBLNEQ_MNGPKT_INT_IRQ_I_MSK 0x7fffffff
+#define TBLNEQ_MNGPKT_INT_IRQ_SFT 31
+#define TBLNEQ_MNGPKT_INT_IRQ_HI 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SZ 1
+#define INTR_PERI_RAW_MSK 0xffffffff
+#define INTR_PERI_RAW_I_MSK 0x00000000
+#define INTR_PERI_RAW_SFT 0
+#define INTR_PERI_RAW_HI 31
+#define INTR_PERI_RAW_SZ 32
+#define INTR_GPI00_CFG_MSK 0x00000003
+#define INTR_GPI00_CFG_I_MSK 0xfffffffc
+#define INTR_GPI00_CFG_SFT 0
+#define INTR_GPI00_CFG_HI 1
+#define INTR_GPI00_CFG_SZ 2
+#define INTR_GPI01_CFG_MSK 0x0000000c
+#define INTR_GPI01_CFG_I_MSK 0xfffffff3
+#define INTR_GPI01_CFG_SFT 2
+#define INTR_GPI01_CFG_HI 3
+#define INTR_GPI01_CFG_SZ 2
+#define SYS_RST_INT_MSK 0x00000001
+#define SYS_RST_INT_I_MSK 0xfffffffe
+#define SYS_RST_INT_SFT 0
+#define SYS_RST_INT_HI 0
+#define SYS_RST_INT_SZ 1
+#define SPI_IPC_ADDR_MSK 0xffffffff
+#define SPI_IPC_ADDR_I_MSK 0x00000000
+#define SPI_IPC_ADDR_SFT 0
+#define SPI_IPC_ADDR_HI 31
+#define SPI_IPC_ADDR_SZ 32
+#define SD_MASK_TOP_MSK 0xffffffff
+#define SD_MASK_TOP_I_MSK 0x00000000
+#define SD_MASK_TOP_SFT 0
+#define SD_MASK_TOP_HI 31
+#define SD_MASK_TOP_SZ 32
+#define IRQ_PHY_0_SD_MSK 0x00000001
+#define IRQ_PHY_0_SD_I_MSK 0xfffffffe
+#define IRQ_PHY_0_SD_SFT 0
+#define IRQ_PHY_0_SD_HI 0
+#define IRQ_PHY_0_SD_SZ 1
+#define IRQ_PHY_1_SD_MSK 0x00000002
+#define IRQ_PHY_1_SD_I_MSK 0xfffffffd
+#define IRQ_PHY_1_SD_SFT 1
+#define IRQ_PHY_1_SD_HI 1
+#define IRQ_PHY_1_SD_SZ 1
+#define IRQ_SDIO_SD_MSK 0x00000004
+#define IRQ_SDIO_SD_I_MSK 0xfffffffb
+#define IRQ_SDIO_SD_SFT 2
+#define IRQ_SDIO_SD_HI 2
+#define IRQ_SDIO_SD_SZ 1
+#define IRQ_BEACON_DONE_SD_MSK 0x00000008
+#define IRQ_BEACON_DONE_SD_I_MSK 0xfffffff7
+#define IRQ_BEACON_DONE_SD_SFT 3
+#define IRQ_BEACON_DONE_SD_HI 3
+#define IRQ_BEACON_DONE_SD_SZ 1
+#define IRQ_BEACON_SD_MSK 0x00000010
+#define IRQ_BEACON_SD_I_MSK 0xffffffef
+#define IRQ_BEACON_SD_SFT 4
+#define IRQ_BEACON_SD_HI 4
+#define IRQ_BEACON_SD_SZ 1
+#define IRQ_PRE_BEACON_SD_MSK 0x00000020
+#define IRQ_PRE_BEACON_SD_I_MSK 0xffffffdf
+#define IRQ_PRE_BEACON_SD_SFT 5
+#define IRQ_PRE_BEACON_SD_HI 5
+#define IRQ_PRE_BEACON_SD_SZ 1
+#define IRQ_EDCA0_TX_DONE_SD_MSK 0x00000040
+#define IRQ_EDCA0_TX_DONE_SD_I_MSK 0xffffffbf
+#define IRQ_EDCA0_TX_DONE_SD_SFT 6
+#define IRQ_EDCA0_TX_DONE_SD_HI 6
+#define IRQ_EDCA0_TX_DONE_SD_SZ 1
+#define IRQ_EDCA1_TX_DONE_SD_MSK 0x00000080
+#define IRQ_EDCA1_TX_DONE_SD_I_MSK 0xffffff7f
+#define IRQ_EDCA1_TX_DONE_SD_SFT 7
+#define IRQ_EDCA1_TX_DONE_SD_HI 7
+#define IRQ_EDCA1_TX_DONE_SD_SZ 1
+#define IRQ_EDCA2_TX_DONE_SD_MSK 0x00000100
+#define IRQ_EDCA2_TX_DONE_SD_I_MSK 0xfffffeff
+#define IRQ_EDCA2_TX_DONE_SD_SFT 8
+#define IRQ_EDCA2_TX_DONE_SD_HI 8
+#define IRQ_EDCA2_TX_DONE_SD_SZ 1
+#define IRQ_EDCA3_TX_DONE_SD_MSK 0x00000200
+#define IRQ_EDCA3_TX_DONE_SD_I_MSK 0xfffffdff
+#define IRQ_EDCA3_TX_DONE_SD_SFT 9
+#define IRQ_EDCA3_TX_DONE_SD_HI 9
+#define IRQ_EDCA3_TX_DONE_SD_SZ 1
+#define IRQ_EDCA4_TX_DONE_SD_MSK 0x00000400
+#define IRQ_EDCA4_TX_DONE_SD_I_MSK 0xfffffbff
+#define IRQ_EDCA4_TX_DONE_SD_SFT 10
+#define IRQ_EDCA4_TX_DONE_SD_HI 10
+#define IRQ_EDCA4_TX_DONE_SD_SZ 1
+#define IRQ_BEACON_DTIM_SD_MSK 0x00001000
+#define IRQ_BEACON_DTIM_SD_I_MSK 0xffffefff
+#define IRQ_BEACON_DTIM_SD_SFT 12
+#define IRQ_BEACON_DTIM_SD_HI 12
+#define IRQ_BEACON_DTIM_SD_SZ 1
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_MSK 0x00002000
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_I_MSK 0xffffdfff
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_SFT 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_HI 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_MSK 0x00004000
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_I_MSK 0xffffbfff
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_SFT 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_HI 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_MSK 0x00008000
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_I_MSK 0xffff7fff
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_SFT 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_HI 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_MSK 0x00010000
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_I_MSK 0xfffeffff
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_SFT 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_HI 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_FENCE_HIT_INT_SD_MSK 0x00020000
+#define IRQ_FENCE_HIT_INT_SD_I_MSK 0xfffdffff
+#define IRQ_FENCE_HIT_INT_SD_SFT 17
+#define IRQ_FENCE_HIT_INT_SD_HI 17
+#define IRQ_FENCE_HIT_INT_SD_SZ 1
+#define IRQ_ILL_ADDR_INT_SD_MSK 0x00040000
+#define IRQ_ILL_ADDR_INT_SD_I_MSK 0xfffbffff
+#define IRQ_ILL_ADDR_INT_SD_SFT 18
+#define IRQ_ILL_ADDR_INT_SD_HI 18
+#define IRQ_ILL_ADDR_INT_SD_SZ 1
+#define IRQ_MBOX_SD_MSK 0x00080000
+#define IRQ_MBOX_SD_I_MSK 0xfff7ffff
+#define IRQ_MBOX_SD_SFT 19
+#define IRQ_MBOX_SD_HI 19
+#define IRQ_MBOX_SD_SZ 1
+#define IRQ_US_TIMER0_SD_MSK 0x00100000
+#define IRQ_US_TIMER0_SD_I_MSK 0xffefffff
+#define IRQ_US_TIMER0_SD_SFT 20
+#define IRQ_US_TIMER0_SD_HI 20
+#define IRQ_US_TIMER0_SD_SZ 1
+#define IRQ_US_TIMER1_SD_MSK 0x00200000
+#define IRQ_US_TIMER1_SD_I_MSK 0xffdfffff
+#define IRQ_US_TIMER1_SD_SFT 21
+#define IRQ_US_TIMER1_SD_HI 21
+#define IRQ_US_TIMER1_SD_SZ 1
+#define IRQ_US_TIMER2_SD_MSK 0x00400000
+#define IRQ_US_TIMER2_SD_I_MSK 0xffbfffff
+#define IRQ_US_TIMER2_SD_SFT 22
+#define IRQ_US_TIMER2_SD_HI 22
+#define IRQ_US_TIMER2_SD_SZ 1
+#define IRQ_US_TIMER3_SD_MSK 0x00800000
+#define IRQ_US_TIMER3_SD_I_MSK 0xff7fffff
+#define IRQ_US_TIMER3_SD_SFT 23
+#define IRQ_US_TIMER3_SD_HI 23
+#define IRQ_US_TIMER3_SD_SZ 1
+#define IRQ_MS_TIMER0_SD_MSK 0x01000000
+#define IRQ_MS_TIMER0_SD_I_MSK 0xfeffffff
+#define IRQ_MS_TIMER0_SD_SFT 24
+#define IRQ_MS_TIMER0_SD_HI 24
+#define IRQ_MS_TIMER0_SD_SZ 1
+#define IRQ_MS_TIMER1_SD_MSK 0x02000000
+#define IRQ_MS_TIMER1_SD_I_MSK 0xfdffffff
+#define IRQ_MS_TIMER1_SD_SFT 25
+#define IRQ_MS_TIMER1_SD_HI 25
+#define IRQ_MS_TIMER1_SD_SZ 1
+#define IRQ_MS_TIMER2_SD_MSK 0x04000000
+#define IRQ_MS_TIMER2_SD_I_MSK 0xfbffffff
+#define IRQ_MS_TIMER2_SD_SFT 26
+#define IRQ_MS_TIMER2_SD_HI 26
+#define IRQ_MS_TIMER2_SD_SZ 1
+#define IRQ_MS_TIMER3_SD_MSK 0x08000000
+#define IRQ_MS_TIMER3_SD_I_MSK 0xf7ffffff
+#define IRQ_MS_TIMER3_SD_SFT 27
+#define IRQ_MS_TIMER3_SD_HI 27
+#define IRQ_MS_TIMER3_SD_SZ 1
+#define IRQ_TX_LIMIT_INT_SD_MSK 0x10000000
+#define IRQ_TX_LIMIT_INT_SD_I_MSK 0xefffffff
+#define IRQ_TX_LIMIT_INT_SD_SFT 28
+#define IRQ_TX_LIMIT_INT_SD_HI 28
+#define IRQ_TX_LIMIT_INT_SD_SZ 1
+#define IRQ_DMA0_SD_MSK 0x20000000
+#define IRQ_DMA0_SD_I_MSK 0xdfffffff
+#define IRQ_DMA0_SD_SFT 29
+#define IRQ_DMA0_SD_HI 29
+#define IRQ_DMA0_SD_SZ 1
+#define IRQ_CO_DMA_SD_MSK 0x40000000
+#define IRQ_CO_DMA_SD_I_MSK 0xbfffffff
+#define IRQ_CO_DMA_SD_SFT 30
+#define IRQ_CO_DMA_SD_HI 30
+#define IRQ_CO_DMA_SD_SZ 1
+#define IRQ_PERI_GROUP_SD_MSK 0x80000000
+#define IRQ_PERI_GROUP_SD_I_MSK 0x7fffffff
+#define IRQ_PERI_GROUP_SD_SFT 31
+#define IRQ_PERI_GROUP_SD_HI 31
+#define IRQ_PERI_GROUP_SD_SZ 1
+#define INT_PERI_MASK_SD_MSK 0xffffffff
+#define INT_PERI_MASK_SD_I_MSK 0x00000000
+#define INT_PERI_MASK_SD_SFT 0
+#define INT_PERI_MASK_SD_HI 31
+#define INT_PERI_MASK_SD_SZ 32
+#define PERI_RTC_SD_MSK 0x00000001
+#define PERI_RTC_SD_I_MSK 0xfffffffe
+#define PERI_RTC_SD_SFT 0
+#define PERI_RTC_SD_HI 0
+#define PERI_RTC_SD_SZ 1
+#define IRQ_UART0_TX_SD_MSK 0x00000002
+#define IRQ_UART0_TX_SD_I_MSK 0xfffffffd
+#define IRQ_UART0_TX_SD_SFT 1
+#define IRQ_UART0_TX_SD_HI 1
+#define IRQ_UART0_TX_SD_SZ 1
+#define IRQ_UART0_RX_SD_MSK 0x00000004
+#define IRQ_UART0_RX_SD_I_MSK 0xfffffffb
+#define IRQ_UART0_RX_SD_SFT 2
+#define IRQ_UART0_RX_SD_HI 2
+#define IRQ_UART0_RX_SD_SZ 1
+#define PERI_GPI_SD_2_MSK 0x00000008
+#define PERI_GPI_SD_2_I_MSK 0xfffffff7
+#define PERI_GPI_SD_2_SFT 3
+#define PERI_GPI_SD_2_HI 3
+#define PERI_GPI_SD_2_SZ 1
+#define IRQ_SPI_IPC_SD_MSK 0x00000010
+#define IRQ_SPI_IPC_SD_I_MSK 0xffffffef
+#define IRQ_SPI_IPC_SD_SFT 4
+#define IRQ_SPI_IPC_SD_HI 4
+#define IRQ_SPI_IPC_SD_SZ 1
+#define PERI_GPI_SD_1_0_MSK 0x00000060
+#define PERI_GPI_SD_1_0_I_MSK 0xffffff9f
+#define PERI_GPI_SD_1_0_SFT 5
+#define PERI_GPI_SD_1_0_HI 6
+#define PERI_GPI_SD_1_0_SZ 2
+#define SCRT_INT_1_SD_MSK 0x00000080
+#define SCRT_INT_1_SD_I_MSK 0xffffff7f
+#define SCRT_INT_1_SD_SFT 7
+#define SCRT_INT_1_SD_HI 7
+#define SCRT_INT_1_SD_SZ 1
+#define MMU_ALC_ERR_SD_MSK 0x00000100
+#define MMU_ALC_ERR_SD_I_MSK 0xfffffeff
+#define MMU_ALC_ERR_SD_SFT 8
+#define MMU_ALC_ERR_SD_HI 8
+#define MMU_ALC_ERR_SD_SZ 1
+#define MMU_RLS_ERR_SD_MSK 0x00000200
+#define MMU_RLS_ERR_SD_I_MSK 0xfffffdff
+#define MMU_RLS_ERR_SD_SFT 9
+#define MMU_RLS_ERR_SD_HI 9
+#define MMU_RLS_ERR_SD_SZ 1
+#define ID_MNG_INT_1_SD_MSK 0x00000400
+#define ID_MNG_INT_1_SD_I_MSK 0xfffffbff
+#define ID_MNG_INT_1_SD_SFT 10
+#define ID_MNG_INT_1_SD_HI 10
+#define ID_MNG_INT_1_SD_SZ 1
+#define MBOX_INT_1_SD_MSK 0x00000800
+#define MBOX_INT_1_SD_I_MSK 0xfffff7ff
+#define MBOX_INT_1_SD_SFT 11
+#define MBOX_INT_1_SD_HI 11
+#define MBOX_INT_1_SD_SZ 1
+#define MBOX_INT_2_SD_MSK 0x00001000
+#define MBOX_INT_2_SD_I_MSK 0xffffefff
+#define MBOX_INT_2_SD_SFT 12
+#define MBOX_INT_2_SD_HI 12
+#define MBOX_INT_2_SD_SZ 1
+#define MBOX_INT_3_SD_MSK 0x00002000
+#define MBOX_INT_3_SD_I_MSK 0xffffdfff
+#define MBOX_INT_3_SD_SFT 13
+#define MBOX_INT_3_SD_HI 13
+#define MBOX_INT_3_SD_SZ 1
+#define HCI_INT_1_SD_MSK 0x00004000
+#define HCI_INT_1_SD_I_MSK 0xffffbfff
+#define HCI_INT_1_SD_SFT 14
+#define HCI_INT_1_SD_HI 14
+#define HCI_INT_1_SD_SZ 1
+#define UART_RX_TIMEOUT_SD_MSK 0x00008000
+#define UART_RX_TIMEOUT_SD_I_MSK 0xffff7fff
+#define UART_RX_TIMEOUT_SD_SFT 15
+#define UART_RX_TIMEOUT_SD_HI 15
+#define UART_RX_TIMEOUT_SD_SZ 1
+#define UART_MULTI_IRQ_SD_MSK 0x00010000
+#define UART_MULTI_IRQ_SD_I_MSK 0xfffeffff
+#define UART_MULTI_IRQ_SD_SFT 16
+#define UART_MULTI_IRQ_SD_HI 16
+#define UART_MULTI_IRQ_SD_SZ 1
+#define ID_MNG_INT_2_SD_MSK 0x00020000
+#define ID_MNG_INT_2_SD_I_MSK 0xfffdffff
+#define ID_MNG_INT_2_SD_SFT 17
+#define ID_MNG_INT_2_SD_HI 17
+#define ID_MNG_INT_2_SD_SZ 1
+#define DMN_NOHIT_INT_SD_MSK 0x00040000
+#define DMN_NOHIT_INT_SD_I_MSK 0xfffbffff
+#define DMN_NOHIT_INT_SD_SFT 18
+#define DMN_NOHIT_INT_SD_HI 18
+#define DMN_NOHIT_INT_SD_SZ 1
+#define ID_THOLD_RX_SD_MSK 0x00080000
+#define ID_THOLD_RX_SD_I_MSK 0xfff7ffff
+#define ID_THOLD_RX_SD_SFT 19
+#define ID_THOLD_RX_SD_HI 19
+#define ID_THOLD_RX_SD_SZ 1
+#define ID_THOLD_TX_SD_MSK 0x00100000
+#define ID_THOLD_TX_SD_I_MSK 0xffefffff
+#define ID_THOLD_TX_SD_SFT 20
+#define ID_THOLD_TX_SD_HI 20
+#define ID_THOLD_TX_SD_SZ 1
+#define ID_DOUBLE_RLS_SD_MSK 0x00200000
+#define ID_DOUBLE_RLS_SD_I_MSK 0xffdfffff
+#define ID_DOUBLE_RLS_SD_SFT 21
+#define ID_DOUBLE_RLS_SD_HI 21
+#define ID_DOUBLE_RLS_SD_SZ 1
+#define RX_ID_LEN_THOLD_SD_MSK 0x00400000
+#define RX_ID_LEN_THOLD_SD_I_MSK 0xffbfffff
+#define RX_ID_LEN_THOLD_SD_SFT 22
+#define RX_ID_LEN_THOLD_SD_HI 22
+#define RX_ID_LEN_THOLD_SD_SZ 1
+#define TX_ID_LEN_THOLD_SD_MSK 0x00800000
+#define TX_ID_LEN_THOLD_SD_I_MSK 0xff7fffff
+#define TX_ID_LEN_THOLD_SD_SFT 23
+#define TX_ID_LEN_THOLD_SD_HI 23
+#define TX_ID_LEN_THOLD_SD_SZ 1
+#define ALL_ID_LEN_THOLD_SD_MSK 0x01000000
+#define ALL_ID_LEN_THOLD_SD_I_MSK 0xfeffffff
+#define ALL_ID_LEN_THOLD_SD_SFT 24
+#define ALL_ID_LEN_THOLD_SD_HI 24
+#define ALL_ID_LEN_THOLD_SD_SZ 1
+#define DMN_MCU_INT_SD_MSK 0x02000000
+#define DMN_MCU_INT_SD_I_MSK 0xfdffffff
+#define DMN_MCU_INT_SD_SFT 25
+#define DMN_MCU_INT_SD_HI 25
+#define DMN_MCU_INT_SD_SZ 1
+#define IRQ_DAT_UART_TX_SD_MSK 0x04000000
+#define IRQ_DAT_UART_TX_SD_I_MSK 0xfbffffff
+#define IRQ_DAT_UART_TX_SD_SFT 26
+#define IRQ_DAT_UART_TX_SD_HI 26
+#define IRQ_DAT_UART_TX_SD_SZ 1
+#define IRQ_DAT_UART_RX_SD_MSK 0x08000000
+#define IRQ_DAT_UART_RX_SD_I_MSK 0xf7ffffff
+#define IRQ_DAT_UART_RX_SD_SFT 27
+#define IRQ_DAT_UART_RX_SD_HI 27
+#define IRQ_DAT_UART_RX_SD_SZ 1
+#define DAT_UART_RX_TIMEOUT_SD_MSK 0x10000000
+#define DAT_UART_RX_TIMEOUT_SD_I_MSK 0xefffffff
+#define DAT_UART_RX_TIMEOUT_SD_SFT 28
+#define DAT_UART_RX_TIMEOUT_SD_HI 28
+#define DAT_UART_RX_TIMEOUT_SD_SZ 1
+#define DAT_UART_MULTI_IRQ_SD_MSK 0x20000000
+#define DAT_UART_MULTI_IRQ_SD_I_MSK 0xdfffffff
+#define DAT_UART_MULTI_IRQ_SD_SFT 29
+#define DAT_UART_MULTI_IRQ_SD_HI 29
+#define DAT_UART_MULTI_IRQ_SD_SZ 1
+#define ALR_ABT_NOCHG_INT_IRQ_SD_MSK 0x40000000
+#define ALR_ABT_NOCHG_INT_IRQ_SD_I_MSK 0xbfffffff
+#define ALR_ABT_NOCHG_INT_IRQ_SD_SFT 30
+#define ALR_ABT_NOCHG_INT_IRQ_SD_HI 30
+#define ALR_ABT_NOCHG_INT_IRQ_SD_SZ 1
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_MSK 0x80000000
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_I_MSK 0x7fffffff
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_SFT 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_HI 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_SZ 1
+#define DBG_SPI_MODE_MSK 0xffffffff
+#define DBG_SPI_MODE_I_MSK 0x00000000
+#define DBG_SPI_MODE_SFT 0
+#define DBG_SPI_MODE_HI 31
+#define DBG_SPI_MODE_SZ 32
+#define DBG_RX_QUOTA_MSK 0x0000ffff
+#define DBG_RX_QUOTA_I_MSK 0xffff0000
+#define DBG_RX_QUOTA_SFT 0
+#define DBG_RX_QUOTA_HI 15
+#define DBG_RX_QUOTA_SZ 16
+#define DBG_CONDI_NUM_MSK 0x000000ff
+#define DBG_CONDI_NUM_I_MSK 0xffffff00
+#define DBG_CONDI_NUM_SFT 0
+#define DBG_CONDI_NUM_HI 7
+#define DBG_CONDI_NUM_SZ 8
+#define DBG_HOST_PATH_MSK 0x00000001
+#define DBG_HOST_PATH_I_MSK 0xfffffffe
+#define DBG_HOST_PATH_SFT 0
+#define DBG_HOST_PATH_HI 0
+#define DBG_HOST_PATH_SZ 1
+#define DBG_TX_SEG_MSK 0xffffffff
+#define DBG_TX_SEG_I_MSK 0x00000000
+#define DBG_TX_SEG_SFT 0
+#define DBG_TX_SEG_HI 31
+#define DBG_TX_SEG_SZ 32
+#define DBG_BRST_MODE_MSK 0x00000001
+#define DBG_BRST_MODE_I_MSK 0xfffffffe
+#define DBG_BRST_MODE_SFT 0
+#define DBG_BRST_MODE_HI 0
+#define DBG_BRST_MODE_SZ 1
+#define DBG_CLK_WIDTH_MSK 0x0000ffff
+#define DBG_CLK_WIDTH_I_MSK 0xffff0000
+#define DBG_CLK_WIDTH_SFT 0
+#define DBG_CLK_WIDTH_HI 15
+#define DBG_CLK_WIDTH_SZ 16
+#define DBG_CSN_INTER_MSK 0xffff0000
+#define DBG_CSN_INTER_I_MSK 0x0000ffff
+#define DBG_CSN_INTER_SFT 16
+#define DBG_CSN_INTER_HI 31
+#define DBG_CSN_INTER_SZ 16
+#define DBG_BACK_DLY_MSK 0x0000ffff
+#define DBG_BACK_DLY_I_MSK 0xffff0000
+#define DBG_BACK_DLY_SFT 0
+#define DBG_BACK_DLY_HI 15
+#define DBG_BACK_DLY_SZ 16
+#define DBG_FRONT_DLY_MSK 0xffff0000
+#define DBG_FRONT_DLY_I_MSK 0x0000ffff
+#define DBG_FRONT_DLY_SFT 16
+#define DBG_FRONT_DLY_HI 31
+#define DBG_FRONT_DLY_SZ 16
+#define DBG_RX_FIFO_FAIL_MSK 0x00000002
+#define DBG_RX_FIFO_FAIL_I_MSK 0xfffffffd
+#define DBG_RX_FIFO_FAIL_SFT 1
+#define DBG_RX_FIFO_FAIL_HI 1
+#define DBG_RX_FIFO_FAIL_SZ 1
+#define DBG_RX_HOST_FAIL_MSK 0x00000004
+#define DBG_RX_HOST_FAIL_I_MSK 0xfffffffb
+#define DBG_RX_HOST_FAIL_SFT 2
+#define DBG_RX_HOST_FAIL_HI 2
+#define DBG_RX_HOST_FAIL_SZ 1
+#define DBG_TX_FIFO_FAIL_MSK 0x00000008
+#define DBG_TX_FIFO_FAIL_I_MSK 0xfffffff7
+#define DBG_TX_FIFO_FAIL_SFT 3
+#define DBG_TX_FIFO_FAIL_HI 3
+#define DBG_TX_FIFO_FAIL_SZ 1
+#define DBG_TX_HOST_FAIL_MSK 0x00000010
+#define DBG_TX_HOST_FAIL_I_MSK 0xffffffef
+#define DBG_TX_HOST_FAIL_SFT 4
+#define DBG_TX_HOST_FAIL_HI 4
+#define DBG_TX_HOST_FAIL_SZ 1
+#define DBG_SPI_DOUBLE_ALLOC_MSK 0x00000020
+#define DBG_SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
+#define DBG_SPI_DOUBLE_ALLOC_SFT 5
+#define DBG_SPI_DOUBLE_ALLOC_HI 5
+#define DBG_SPI_DOUBLE_ALLOC_SZ 1
+#define DBG_SPI_TX_NO_ALLOC_MSK 0x00000040
+#define DBG_SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
+#define DBG_SPI_TX_NO_ALLOC_SFT 6
+#define DBG_SPI_TX_NO_ALLOC_HI 6
+#define DBG_SPI_TX_NO_ALLOC_SZ 1
+#define DBG_RDATA_RDY_MSK 0x00000080
+#define DBG_RDATA_RDY_I_MSK 0xffffff7f
+#define DBG_RDATA_RDY_SFT 7
+#define DBG_RDATA_RDY_HI 7
+#define DBG_RDATA_RDY_SZ 1
+#define DBG_SPI_ALLOC_STATUS_MSK 0x00000100
+#define DBG_SPI_ALLOC_STATUS_I_MSK 0xfffffeff
+#define DBG_SPI_ALLOC_STATUS_SFT 8
+#define DBG_SPI_ALLOC_STATUS_HI 8
+#define DBG_SPI_ALLOC_STATUS_SZ 1
+#define DBG_SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
+#define DBG_SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
+#define DBG_SPI_DBG_WR_FIFO_FULL_SFT 9
+#define DBG_SPI_DBG_WR_FIFO_FULL_HI 9
+#define DBG_SPI_DBG_WR_FIFO_FULL_SZ 1
+#define DBG_RX_LEN_MSK 0xffff0000
+#define DBG_RX_LEN_I_MSK 0x0000ffff
+#define DBG_RX_LEN_SFT 16
+#define DBG_RX_LEN_HI 31
+#define DBG_RX_LEN_SZ 16
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SFT 8
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_HI 8
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SZ 1
+#define DBG_SPI_TX_ALLOC_SIZE_MSK 0x000000ff
+#define DBG_SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
+#define DBG_SPI_TX_ALLOC_SIZE_SFT 0
+#define DBG_SPI_TX_ALLOC_SIZE_HI 7
+#define DBG_SPI_TX_ALLOC_SIZE_SZ 8
+#define DBG_RD_DAT_CNT_MSK 0x0000ffff
+#define DBG_RD_DAT_CNT_I_MSK 0xffff0000
+#define DBG_RD_DAT_CNT_SFT 0
+#define DBG_RD_DAT_CNT_HI 15
+#define DBG_RD_DAT_CNT_SZ 16
+#define DBG_RD_STS_CNT_MSK 0xffff0000
+#define DBG_RD_STS_CNT_I_MSK 0x0000ffff
+#define DBG_RD_STS_CNT_SFT 16
+#define DBG_RD_STS_CNT_HI 31
+#define DBG_RD_STS_CNT_SZ 16
+#define DBG_JUDGE_CNT_MSK 0x0000ffff
+#define DBG_JUDGE_CNT_I_MSK 0xffff0000
+#define DBG_JUDGE_CNT_SFT 0
+#define DBG_JUDGE_CNT_HI 15
+#define DBG_JUDGE_CNT_SZ 16
+#define DBG_RD_STS_CNT_CLR_MSK 0x00010000
+#define DBG_RD_STS_CNT_CLR_I_MSK 0xfffeffff
+#define DBG_RD_STS_CNT_CLR_SFT 16
+#define DBG_RD_STS_CNT_CLR_HI 16
+#define DBG_RD_STS_CNT_CLR_SZ 1
+#define DBG_RD_DAT_CNT_CLR_MSK 0x00020000
+#define DBG_RD_DAT_CNT_CLR_I_MSK 0xfffdffff
+#define DBG_RD_DAT_CNT_CLR_SFT 17
+#define DBG_RD_DAT_CNT_CLR_HI 17
+#define DBG_RD_DAT_CNT_CLR_SZ 1
+#define DBG_JUDGE_CNT_CLR_MSK 0x00040000
+#define DBG_JUDGE_CNT_CLR_I_MSK 0xfffbffff
+#define DBG_JUDGE_CNT_CLR_SFT 18
+#define DBG_JUDGE_CNT_CLR_HI 18
+#define DBG_JUDGE_CNT_CLR_SZ 1
+#define DBG_TX_DONE_CNT_MSK 0x0000ffff
+#define DBG_TX_DONE_CNT_I_MSK 0xffff0000
+#define DBG_TX_DONE_CNT_SFT 0
+#define DBG_TX_DONE_CNT_HI 15
+#define DBG_TX_DONE_CNT_SZ 16
+#define DBG_TX_DISCARD_CNT_MSK 0xffff0000
+#define DBG_TX_DISCARD_CNT_I_MSK 0x0000ffff
+#define DBG_TX_DISCARD_CNT_SFT 16
+#define DBG_TX_DISCARD_CNT_HI 31
+#define DBG_TX_DISCARD_CNT_SZ 16
+#define DBG_TX_SET_CNT_MSK 0x0000ffff
+#define DBG_TX_SET_CNT_I_MSK 0xffff0000
+#define DBG_TX_SET_CNT_SFT 0
+#define DBG_TX_SET_CNT_HI 15
+#define DBG_TX_SET_CNT_SZ 16
+#define DBG_TX_DISCARD_CNT_CLR_MSK 0x00010000
+#define DBG_TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
+#define DBG_TX_DISCARD_CNT_CLR_SFT 16
+#define DBG_TX_DISCARD_CNT_CLR_HI 16
+#define DBG_TX_DISCARD_CNT_CLR_SZ 1
+#define DBG_TX_DONE_CNT_CLR_MSK 0x00020000
+#define DBG_TX_DONE_CNT_CLR_I_MSK 0xfffdffff
+#define DBG_TX_DONE_CNT_CLR_SFT 17
+#define DBG_TX_DONE_CNT_CLR_HI 17
+#define DBG_TX_DONE_CNT_CLR_SZ 1
+#define DBG_TX_SET_CNT_CLR_MSK 0x00040000
+#define DBG_TX_SET_CNT_CLR_I_MSK 0xfffbffff
+#define DBG_TX_SET_CNT_CLR_SFT 18
+#define DBG_TX_SET_CNT_CLR_HI 18
+#define DBG_TX_SET_CNT_CLR_SZ 1
+#define DBG_DAT_MODE_OFF_MSK 0x00080000
+#define DBG_DAT_MODE_OFF_I_MSK 0xfff7ffff
+#define DBG_DAT_MODE_OFF_SFT 19
+#define DBG_DAT_MODE_OFF_HI 19
+#define DBG_DAT_MODE_OFF_SZ 1
+#define DBG_TX_FIFO_RESIDUE_MSK 0x00700000
+#define DBG_TX_FIFO_RESIDUE_I_MSK 0xff8fffff
+#define DBG_TX_FIFO_RESIDUE_SFT 20
+#define DBG_TX_FIFO_RESIDUE_HI 22
+#define DBG_TX_FIFO_RESIDUE_SZ 3
+#define DBG_RX_FIFO_RESIDUE_MSK 0x07000000
+#define DBG_RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
+#define DBG_RX_FIFO_RESIDUE_SFT 24
+#define DBG_RX_FIFO_RESIDUE_HI 26
+#define DBG_RX_FIFO_RESIDUE_SZ 3
+#define DBG_RX_RDY_MSK 0x00000001
+#define DBG_RX_RDY_I_MSK 0xfffffffe
+#define DBG_RX_RDY_SFT 0
+#define DBG_RX_RDY_HI 0
+#define DBG_RX_RDY_SZ 1
+#define DBG_SDIO_SYS_INT_MSK 0x00000004
+#define DBG_SDIO_SYS_INT_I_MSK 0xfffffffb
+#define DBG_SDIO_SYS_INT_SFT 2
+#define DBG_SDIO_SYS_INT_HI 2
+#define DBG_SDIO_SYS_INT_SZ 1
+#define DBG_EDCA0_LOWTHOLD_INT_MSK 0x00000008
+#define DBG_EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define DBG_EDCA0_LOWTHOLD_INT_SFT 3
+#define DBG_EDCA0_LOWTHOLD_INT_HI 3
+#define DBG_EDCA0_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA1_LOWTHOLD_INT_MSK 0x00000010
+#define DBG_EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
+#define DBG_EDCA1_LOWTHOLD_INT_SFT 4
+#define DBG_EDCA1_LOWTHOLD_INT_HI 4
+#define DBG_EDCA1_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA2_LOWTHOLD_INT_MSK 0x00000020
+#define DBG_EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define DBG_EDCA2_LOWTHOLD_INT_SFT 5
+#define DBG_EDCA2_LOWTHOLD_INT_HI 5
+#define DBG_EDCA2_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA3_LOWTHOLD_INT_MSK 0x00000040
+#define DBG_EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define DBG_EDCA3_LOWTHOLD_INT_SFT 6
+#define DBG_EDCA3_LOWTHOLD_INT_HI 6
+#define DBG_EDCA3_LOWTHOLD_INT_SZ 1
+#define DBG_TX_LIMIT_INT_IN_MSK 0x00000080
+#define DBG_TX_LIMIT_INT_IN_I_MSK 0xffffff7f
+#define DBG_TX_LIMIT_INT_IN_SFT 7
+#define DBG_TX_LIMIT_INT_IN_HI 7
+#define DBG_TX_LIMIT_INT_IN_SZ 1
+#define DBG_SPI_FN1_MSK 0x00007f00
+#define DBG_SPI_FN1_I_MSK 0xffff80ff
+#define DBG_SPI_FN1_SFT 8
+#define DBG_SPI_FN1_HI 14
+#define DBG_SPI_FN1_SZ 7
+#define DBG_SPI_CLK_EN_INT_MSK 0x00008000
+#define DBG_SPI_CLK_EN_INT_I_MSK 0xffff7fff
+#define DBG_SPI_CLK_EN_INT_SFT 15
+#define DBG_SPI_CLK_EN_INT_HI 15
+#define DBG_SPI_CLK_EN_INT_SZ 1
+#define DBG_SPI_HOST_MASK_MSK 0x00ff0000
+#define DBG_SPI_HOST_MASK_I_MSK 0xff00ffff
+#define DBG_SPI_HOST_MASK_SFT 16
+#define DBG_SPI_HOST_MASK_HI 23
+#define DBG_SPI_HOST_MASK_SZ 8
+#define BOOT_ADDR_MSK 0x00ffffff
+#define BOOT_ADDR_I_MSK 0xff000000
+#define BOOT_ADDR_SFT 0
+#define BOOT_ADDR_HI 23
+#define BOOT_ADDR_SZ 24
+#define CHECK_SUM_FAIL_MSK 0x80000000
+#define CHECK_SUM_FAIL_I_MSK 0x7fffffff
+#define CHECK_SUM_FAIL_SFT 31
+#define CHECK_SUM_FAIL_HI 31
+#define CHECK_SUM_FAIL_SZ 1
+#define VERIFY_DATA_MSK 0xffffffff
+#define VERIFY_DATA_I_MSK 0x00000000
+#define VERIFY_DATA_SFT 0
+#define VERIFY_DATA_HI 31
+#define VERIFY_DATA_SZ 32
+#define FLASH_ADDR_MSK 0x00ffffff
+#define FLASH_ADDR_I_MSK 0xff000000
+#define FLASH_ADDR_SFT 0
+#define FLASH_ADDR_HI 23
+#define FLASH_ADDR_SZ 24
+#define FLASH_CMD_CLR_MSK 0x10000000
+#define FLASH_CMD_CLR_I_MSK 0xefffffff
+#define FLASH_CMD_CLR_SFT 28
+#define FLASH_CMD_CLR_HI 28
+#define FLASH_CMD_CLR_SZ 1
+#define FLASH_DMA_CLR_MSK 0x20000000
+#define FLASH_DMA_CLR_I_MSK 0xdfffffff
+#define FLASH_DMA_CLR_SFT 29
+#define FLASH_DMA_CLR_HI 29
+#define FLASH_DMA_CLR_SZ 1
+#define DMA_EN_MSK 0x40000000
+#define DMA_EN_I_MSK 0xbfffffff
+#define DMA_EN_SFT 30
+#define DMA_EN_HI 30
+#define DMA_EN_SZ 1
+#define DMA_BUSY_MSK 0x80000000
+#define DMA_BUSY_I_MSK 0x7fffffff
+#define DMA_BUSY_SFT 31
+#define DMA_BUSY_HI 31
+#define DMA_BUSY_SZ 1
+#define SRAM_ADDR_MSK 0xffffffff
+#define SRAM_ADDR_I_MSK 0x00000000
+#define SRAM_ADDR_SFT 0
+#define SRAM_ADDR_HI 31
+#define SRAM_ADDR_SZ 32
+#define FLASH_DMA_LEN_MSK 0xffffffff
+#define FLASH_DMA_LEN_I_MSK 0x00000000
+#define FLASH_DMA_LEN_SFT 0
+#define FLASH_DMA_LEN_HI 31
+#define FLASH_DMA_LEN_SZ 32
+#define FLASH_FRONT_DLY_MSK 0x0000ffff
+#define FLASH_FRONT_DLY_I_MSK 0xffff0000
+#define FLASH_FRONT_DLY_SFT 0
+#define FLASH_FRONT_DLY_HI 15
+#define FLASH_FRONT_DLY_SZ 16
+#define FLASH_BACK_DLY_MSK 0xffff0000
+#define FLASH_BACK_DLY_I_MSK 0x0000ffff
+#define FLASH_BACK_DLY_SFT 16
+#define FLASH_BACK_DLY_HI 31
+#define FLASH_BACK_DLY_SZ 16
+#define FLASH_CLK_WIDTH_MSK 0x0000ffff
+#define FLASH_CLK_WIDTH_I_MSK 0xffff0000
+#define FLASH_CLK_WIDTH_SFT 0
+#define FLASH_CLK_WIDTH_HI 15
+#define FLASH_CLK_WIDTH_SZ 16
+#define SPI_BUSY_MSK 0x00010000
+#define SPI_BUSY_I_MSK 0xfffeffff
+#define SPI_BUSY_SFT 16
+#define SPI_BUSY_HI 16
+#define SPI_BUSY_SZ 1
+#define FLS_REMAP_MSK 0x00020000
+#define FLS_REMAP_I_MSK 0xfffdffff
+#define FLS_REMAP_SFT 17
+#define FLS_REMAP_HI 17
+#define FLS_REMAP_SZ 1
+#define PBUS_SWP_MSK 0x00040000
+#define PBUS_SWP_I_MSK 0xfffbffff
+#define PBUS_SWP_SFT 18
+#define PBUS_SWP_HI 18
+#define PBUS_SWP_SZ 1
+#define BIT_MODE1_MSK 0x00080000
+#define BIT_MODE1_I_MSK 0xfff7ffff
+#define BIT_MODE1_SFT 19
+#define BIT_MODE1_HI 19
+#define BIT_MODE1_SZ 1
+#define BIT_MODE2_MSK 0x00100000
+#define BIT_MODE2_I_MSK 0xffefffff
+#define BIT_MODE2_SFT 20
+#define BIT_MODE2_HI 20
+#define BIT_MODE2_SZ 1
+#define BIT_MODE4_MSK 0x00200000
+#define BIT_MODE4_I_MSK 0xffdfffff
+#define BIT_MODE4_SFT 21
+#define BIT_MODE4_HI 21
+#define BIT_MODE4_SZ 1
+#define BOOT_CHECK_SUM_MSK 0xffffffff
+#define BOOT_CHECK_SUM_I_MSK 0x00000000
+#define BOOT_CHECK_SUM_SFT 0
+#define BOOT_CHECK_SUM_HI 31
+#define BOOT_CHECK_SUM_SZ 32
+#define CHECK_SUM_TAG_MSK 0xffffffff
+#define CHECK_SUM_TAG_I_MSK 0x00000000
+#define CHECK_SUM_TAG_SFT 0
+#define CHECK_SUM_TAG_HI 31
+#define CHECK_SUM_TAG_SZ 32
+#define CMD_LEN_MSK 0x0000ffff
+#define CMD_LEN_I_MSK 0xffff0000
+#define CMD_LEN_SFT 0
+#define CMD_LEN_HI 15
+#define CMD_LEN_SZ 16
+#define CMD_ADDR_MSK 0xffffffff
+#define CMD_ADDR_I_MSK 0x00000000
+#define CMD_ADDR_SFT 0
+#define CMD_ADDR_HI 31
+#define CMD_ADDR_SZ 32
+#define DMA_ADR_SRC_MSK 0xffffffff
+#define DMA_ADR_SRC_I_MSK 0x00000000
+#define DMA_ADR_SRC_SFT 0
+#define DMA_ADR_SRC_HI 31
+#define DMA_ADR_SRC_SZ 32
+#define DMA_ADR_DST_MSK 0xffffffff
+#define DMA_ADR_DST_I_MSK 0x00000000
+#define DMA_ADR_DST_SFT 0
+#define DMA_ADR_DST_HI 31
+#define DMA_ADR_DST_SZ 32
+#define DMA_SRC_SIZE_MSK 0x00000007
+#define DMA_SRC_SIZE_I_MSK 0xfffffff8
+#define DMA_SRC_SIZE_SFT 0
+#define DMA_SRC_SIZE_HI 2
+#define DMA_SRC_SIZE_SZ 3
+#define DMA_SRC_INC_MSK 0x00000008
+#define DMA_SRC_INC_I_MSK 0xfffffff7
+#define DMA_SRC_INC_SFT 3
+#define DMA_SRC_INC_HI 3
+#define DMA_SRC_INC_SZ 1
+#define DMA_DST_SIZE_MSK 0x00000070
+#define DMA_DST_SIZE_I_MSK 0xffffff8f
+#define DMA_DST_SIZE_SFT 4
+#define DMA_DST_SIZE_HI 6
+#define DMA_DST_SIZE_SZ 3
+#define DMA_DST_INC_MSK 0x00000080
+#define DMA_DST_INC_I_MSK 0xffffff7f
+#define DMA_DST_INC_SFT 7
+#define DMA_DST_INC_HI 7
+#define DMA_DST_INC_SZ 1
+#define DMA_FAST_FILL_MSK 0x00000100
+#define DMA_FAST_FILL_I_MSK 0xfffffeff
+#define DMA_FAST_FILL_SFT 8
+#define DMA_FAST_FILL_HI 8
+#define DMA_FAST_FILL_SZ 1
+#define DMA_SDIO_KICK_MSK 0x00001000
+#define DMA_SDIO_KICK_I_MSK 0xffffefff
+#define DMA_SDIO_KICK_SFT 12
+#define DMA_SDIO_KICK_HI 12
+#define DMA_SDIO_KICK_SZ 1
+#define DMA_BADR_EN_MSK 0x00002000
+#define DMA_BADR_EN_I_MSK 0xffffdfff
+#define DMA_BADR_EN_SFT 13
+#define DMA_BADR_EN_HI 13
+#define DMA_BADR_EN_SZ 1
+#define DMA_LEN_MSK 0xffff0000
+#define DMA_LEN_I_MSK 0x0000ffff
+#define DMA_LEN_SFT 16
+#define DMA_LEN_HI 31
+#define DMA_LEN_SZ 16
+#define DMA_INT_MASK_MSK 0x00000001
+#define DMA_INT_MASK_I_MSK 0xfffffffe
+#define DMA_INT_MASK_SFT 0
+#define DMA_INT_MASK_HI 0
+#define DMA_INT_MASK_SZ 1
+#define DMA_STS_MSK 0x00000100
+#define DMA_STS_I_MSK 0xfffffeff
+#define DMA_STS_SFT 8
+#define DMA_STS_HI 8
+#define DMA_STS_SZ 1
+#define DMA_FINISH_MSK 0x80000000
+#define DMA_FINISH_I_MSK 0x7fffffff
+#define DMA_FINISH_SFT 31
+#define DMA_FINISH_HI 31
+#define DMA_FINISH_SZ 1
+#define DMA_CONST_MSK 0xffffffff
+#define DMA_CONST_I_MSK 0x00000000
+#define DMA_CONST_SFT 0
+#define DMA_CONST_HI 31
+#define DMA_CONST_SZ 32
+#define SLEEP_WAKE_CNT_MSK 0x00ffffff
+#define SLEEP_WAKE_CNT_I_MSK 0xff000000
+#define SLEEP_WAKE_CNT_SFT 0
+#define SLEEP_WAKE_CNT_HI 23
+#define SLEEP_WAKE_CNT_SZ 24
+#define RG_DLDO_LEVEL_MSK 0x07000000
+#define RG_DLDO_LEVEL_I_MSK 0xf8ffffff
+#define RG_DLDO_LEVEL_SFT 24
+#define RG_DLDO_LEVEL_HI 26
+#define RG_DLDO_LEVEL_SZ 3
+#define RG_DLDO_BOOST_IQ_MSK 0x08000000
+#define RG_DLDO_BOOST_IQ_I_MSK 0xf7ffffff
+#define RG_DLDO_BOOST_IQ_SFT 27
+#define RG_DLDO_BOOST_IQ_HI 27
+#define RG_DLDO_BOOST_IQ_SZ 1
+#define RG_BUCK_LEVEL_MSK 0x70000000
+#define RG_BUCK_LEVEL_I_MSK 0x8fffffff
+#define RG_BUCK_LEVEL_SFT 28
+#define RG_BUCK_LEVEL_HI 30
+#define RG_BUCK_LEVEL_SZ 3
+#define RG_BUCK_VREF_SEL_MSK 0x80000000
+#define RG_BUCK_VREF_SEL_I_MSK 0x7fffffff
+#define RG_BUCK_VREF_SEL_SFT 31
+#define RG_BUCK_VREF_SEL_HI 31
+#define RG_BUCK_VREF_SEL_SZ 1
+#define RG_RTC_OSC_RES_SW_MANUAL_MSK 0x000003ff
+#define RG_RTC_OSC_RES_SW_MANUAL_I_MSK 0xfffffc00
+#define RG_RTC_OSC_RES_SW_MANUAL_SFT 0
+#define RG_RTC_OSC_RES_SW_MANUAL_HI 9
+#define RG_RTC_OSC_RES_SW_MANUAL_SZ 10
+#define RG_RTC_OSC_RES_SW_MSK 0x03ff0000
+#define RG_RTC_OSC_RES_SW_I_MSK 0xfc00ffff
+#define RG_RTC_OSC_RES_SW_SFT 16
+#define RG_RTC_OSC_RES_SW_HI 25
+#define RG_RTC_OSC_RES_SW_SZ 10
+#define RTC_OSC_CAL_RES_RDY_MSK 0x80000000
+#define RTC_OSC_CAL_RES_RDY_I_MSK 0x7fffffff
+#define RTC_OSC_CAL_RES_RDY_SFT 31
+#define RTC_OSC_CAL_RES_RDY_HI 31
+#define RTC_OSC_CAL_RES_RDY_SZ 1
+#define RG_DCDC_MODE_MSK 0x00000001
+#define RG_DCDC_MODE_I_MSK 0xfffffffe
+#define RG_DCDC_MODE_SFT 0
+#define RG_DCDC_MODE_HI 0
+#define RG_DCDC_MODE_SZ 1
+#define RG_BUCK_EN_PSM_MSK 0x00000010
+#define RG_BUCK_EN_PSM_I_MSK 0xffffffef
+#define RG_BUCK_EN_PSM_SFT 4
+#define RG_BUCK_EN_PSM_HI 4
+#define RG_BUCK_EN_PSM_SZ 1
+#define RG_BUCK_PSM_VTH_MSK 0x00000100
+#define RG_BUCK_PSM_VTH_I_MSK 0xfffffeff
+#define RG_BUCK_PSM_VTH_SFT 8
+#define RG_BUCK_PSM_VTH_HI 8
+#define RG_BUCK_PSM_VTH_SZ 1
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_MSK 0x00001000
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_I_MSK 0xffffefff
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_SFT 12
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_HI 12
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_SZ 1
+#define RG_RTC_RDY_DEGLITCH_TIMER_MSK 0x00006000
+#define RG_RTC_RDY_DEGLITCH_TIMER_I_MSK 0xffff9fff
+#define RG_RTC_RDY_DEGLITCH_TIMER_SFT 13
+#define RG_RTC_RDY_DEGLITCH_TIMER_HI 14
+#define RG_RTC_RDY_DEGLITCH_TIMER_SZ 2
+#define RTC_CAL_ENA_MSK 0x00010000
+#define RTC_CAL_ENA_I_MSK 0xfffeffff
+#define RTC_CAL_ENA_SFT 16
+#define RTC_CAL_ENA_HI 16
+#define RTC_CAL_ENA_SZ 1
+#define PMU_WAKE_TRIG_EVENT_MSK 0x00000003
+#define PMU_WAKE_TRIG_EVENT_I_MSK 0xfffffffc
+#define PMU_WAKE_TRIG_EVENT_SFT 0
+#define PMU_WAKE_TRIG_EVENT_HI 1
+#define PMU_WAKE_TRIG_EVENT_SZ 2
+#define DIGI_TOP_POR_MASK_MSK 0x00000010
+#define DIGI_TOP_POR_MASK_I_MSK 0xffffffef
+#define DIGI_TOP_POR_MASK_SFT 4
+#define DIGI_TOP_POR_MASK_HI 4
+#define DIGI_TOP_POR_MASK_SZ 1
+#define PMU_ENTER_SLEEP_MODE_MSK 0x00000100
+#define PMU_ENTER_SLEEP_MODE_I_MSK 0xfffffeff
+#define PMU_ENTER_SLEEP_MODE_SFT 8
+#define PMU_ENTER_SLEEP_MODE_HI 8
+#define PMU_ENTER_SLEEP_MODE_SZ 1
+#define RG_RTC_DUMMIES_MSK 0xffff0000
+#define RG_RTC_DUMMIES_I_MSK 0x0000ffff
+#define RG_RTC_DUMMIES_SFT 16
+#define RG_RTC_DUMMIES_HI 31
+#define RG_RTC_DUMMIES_SZ 16
+#define RTC_EN_MSK 0x00000001
+#define RTC_EN_I_MSK 0xfffffffe
+#define RTC_EN_SFT 0
+#define RTC_EN_HI 0
+#define RTC_EN_SZ 1
+#define RTC_SRC_MSK 0x00000002
+#define RTC_SRC_I_MSK 0xfffffffd
+#define RTC_SRC_SFT 1
+#define RTC_SRC_HI 1
+#define RTC_SRC_SZ 1
+#define RTC_TICK_CNT_MSK 0x7fff0000
+#define RTC_TICK_CNT_I_MSK 0x8000ffff
+#define RTC_TICK_CNT_SFT 16
+#define RTC_TICK_CNT_HI 30
+#define RTC_TICK_CNT_SZ 15
+#define RTC_INT_SEC_MASK_MSK 0x00000001
+#define RTC_INT_SEC_MASK_I_MSK 0xfffffffe
+#define RTC_INT_SEC_MASK_SFT 0
+#define RTC_INT_SEC_MASK_HI 0
+#define RTC_INT_SEC_MASK_SZ 1
+#define RTC_INT_ALARM_MASK_MSK 0x00000002
+#define RTC_INT_ALARM_MASK_I_MSK 0xfffffffd
+#define RTC_INT_ALARM_MASK_SFT 1
+#define RTC_INT_ALARM_MASK_HI 1
+#define RTC_INT_ALARM_MASK_SZ 1
+#define RTC_INT_SEC_MSK 0x00010000
+#define RTC_INT_SEC_I_MSK 0xfffeffff
+#define RTC_INT_SEC_SFT 16
+#define RTC_INT_SEC_HI 16
+#define RTC_INT_SEC_SZ 1
+#define RTC_INT_ALARM_MSK 0x00020000
+#define RTC_INT_ALARM_I_MSK 0xfffdffff
+#define RTC_INT_ALARM_SFT 17
+#define RTC_INT_ALARM_HI 17
+#define RTC_INT_ALARM_SZ 1
+#define RTC_SEC_START_CNT_MSK 0xffffffff
+#define RTC_SEC_START_CNT_I_MSK 0x00000000
+#define RTC_SEC_START_CNT_SFT 0
+#define RTC_SEC_START_CNT_HI 31
+#define RTC_SEC_START_CNT_SZ 32
+#define RTC_SEC_CNT_MSK 0xffffffff
+#define RTC_SEC_CNT_I_MSK 0x00000000
+#define RTC_SEC_CNT_SFT 0
+#define RTC_SEC_CNT_HI 31
+#define RTC_SEC_CNT_SZ 32
+#define RTC_SEC_ALARM_VALUE_MSK 0xffffffff
+#define RTC_SEC_ALARM_VALUE_I_MSK 0x00000000
+#define RTC_SEC_ALARM_VALUE_SFT 0
+#define RTC_SEC_ALARM_VALUE_HI 31
+#define RTC_SEC_ALARM_VALUE_SZ 32
+#define D2_DMA_ADR_SRC_MSK 0xffffffff
+#define D2_DMA_ADR_SRC_I_MSK 0x00000000
+#define D2_DMA_ADR_SRC_SFT 0
+#define D2_DMA_ADR_SRC_HI 31
+#define D2_DMA_ADR_SRC_SZ 32
+#define D2_DMA_ADR_DST_MSK 0xffffffff
+#define D2_DMA_ADR_DST_I_MSK 0x00000000
+#define D2_DMA_ADR_DST_SFT 0
+#define D2_DMA_ADR_DST_HI 31
+#define D2_DMA_ADR_DST_SZ 32
+#define D2_DMA_SRC_SIZE_MSK 0x00000007
+#define D2_DMA_SRC_SIZE_I_MSK 0xfffffff8
+#define D2_DMA_SRC_SIZE_SFT 0
+#define D2_DMA_SRC_SIZE_HI 2
+#define D2_DMA_SRC_SIZE_SZ 3
+#define D2_DMA_SRC_INC_MSK 0x00000008
+#define D2_DMA_SRC_INC_I_MSK 0xfffffff7
+#define D2_DMA_SRC_INC_SFT 3
+#define D2_DMA_SRC_INC_HI 3
+#define D2_DMA_SRC_INC_SZ 1
+#define D2_DMA_DST_SIZE_MSK 0x00000070
+#define D2_DMA_DST_SIZE_I_MSK 0xffffff8f
+#define D2_DMA_DST_SIZE_SFT 4
+#define D2_DMA_DST_SIZE_HI 6
+#define D2_DMA_DST_SIZE_SZ 3
+#define D2_DMA_DST_INC_MSK 0x00000080
+#define D2_DMA_DST_INC_I_MSK 0xffffff7f
+#define D2_DMA_DST_INC_SFT 7
+#define D2_DMA_DST_INC_HI 7
+#define D2_DMA_DST_INC_SZ 1
+#define D2_DMA_FAST_FILL_MSK 0x00000100
+#define D2_DMA_FAST_FILL_I_MSK 0xfffffeff
+#define D2_DMA_FAST_FILL_SFT 8
+#define D2_DMA_FAST_FILL_HI 8
+#define D2_DMA_FAST_FILL_SZ 1
+#define D2_DMA_SDIO_KICK_MSK 0x00001000
+#define D2_DMA_SDIO_KICK_I_MSK 0xffffefff
+#define D2_DMA_SDIO_KICK_SFT 12
+#define D2_DMA_SDIO_KICK_HI 12
+#define D2_DMA_SDIO_KICK_SZ 1
+#define D2_DMA_BADR_EN_MSK 0x00002000
+#define D2_DMA_BADR_EN_I_MSK 0xffffdfff
+#define D2_DMA_BADR_EN_SFT 13
+#define D2_DMA_BADR_EN_HI 13
+#define D2_DMA_BADR_EN_SZ 1
+#define D2_DMA_LEN_MSK 0xffff0000
+#define D2_DMA_LEN_I_MSK 0x0000ffff
+#define D2_DMA_LEN_SFT 16
+#define D2_DMA_LEN_HI 31
+#define D2_DMA_LEN_SZ 16
+#define D2_DMA_INT_MASK_MSK 0x00000001
+#define D2_DMA_INT_MASK_I_MSK 0xfffffffe
+#define D2_DMA_INT_MASK_SFT 0
+#define D2_DMA_INT_MASK_HI 0
+#define D2_DMA_INT_MASK_SZ 1
+#define D2_DMA_STS_MSK 0x00000100
+#define D2_DMA_STS_I_MSK 0xfffffeff
+#define D2_DMA_STS_SFT 8
+#define D2_DMA_STS_HI 8
+#define D2_DMA_STS_SZ 1
+#define D2_DMA_FINISH_MSK 0x80000000
+#define D2_DMA_FINISH_I_MSK 0x7fffffff
+#define D2_DMA_FINISH_SFT 31
+#define D2_DMA_FINISH_HI 31
+#define D2_DMA_FINISH_SZ 1
+#define D2_DMA_CONST_MSK 0xffffffff
+#define D2_DMA_CONST_I_MSK 0x00000000
+#define D2_DMA_CONST_SFT 0
+#define D2_DMA_CONST_HI 31
+#define D2_DMA_CONST_SZ 32
+#define TRAP_UNKNOWN_TYPE_MSK 0x00000001
+#define TRAP_UNKNOWN_TYPE_I_MSK 0xfffffffe
+#define TRAP_UNKNOWN_TYPE_SFT 0
+#define TRAP_UNKNOWN_TYPE_HI 0
+#define TRAP_UNKNOWN_TYPE_SZ 1
+#define TX_ON_DEMAND_ENA_MSK 0x00000002
+#define TX_ON_DEMAND_ENA_I_MSK 0xfffffffd
+#define TX_ON_DEMAND_ENA_SFT 1
+#define TX_ON_DEMAND_ENA_HI 1
+#define TX_ON_DEMAND_ENA_SZ 1
+#define RX_2_HOST_MSK 0x00000004
+#define RX_2_HOST_I_MSK 0xfffffffb
+#define RX_2_HOST_SFT 2
+#define RX_2_HOST_HI 2
+#define RX_2_HOST_SZ 1
+#define AUTO_SEQNO_MSK 0x00000008
+#define AUTO_SEQNO_I_MSK 0xfffffff7
+#define AUTO_SEQNO_SFT 3
+#define AUTO_SEQNO_HI 3
+#define AUTO_SEQNO_SZ 1
+#define BYPASSS_TX_PARSER_ENCAP_MSK 0x00000010
+#define BYPASSS_TX_PARSER_ENCAP_I_MSK 0xffffffef
+#define BYPASSS_TX_PARSER_ENCAP_SFT 4
+#define BYPASSS_TX_PARSER_ENCAP_HI 4
+#define BYPASSS_TX_PARSER_ENCAP_SZ 1
+#define HDR_STRIP_MSK 0x00000020
+#define HDR_STRIP_I_MSK 0xffffffdf
+#define HDR_STRIP_SFT 5
+#define HDR_STRIP_HI 5
+#define HDR_STRIP_SZ 1
+#define ERP_PROTECT_MSK 0x000000c0
+#define ERP_PROTECT_I_MSK 0xffffff3f
+#define ERP_PROTECT_SFT 6
+#define ERP_PROTECT_HI 7
+#define ERP_PROTECT_SZ 2
+#define PRO_VER_MSK 0x00000300
+#define PRO_VER_I_MSK 0xfffffcff
+#define PRO_VER_SFT 8
+#define PRO_VER_HI 9
+#define PRO_VER_SZ 2
+#define TXQ_ID0_MSK 0x00007000
+#define TXQ_ID0_I_MSK 0xffff8fff
+#define TXQ_ID0_SFT 12
+#define TXQ_ID0_HI 14
+#define TXQ_ID0_SZ 3
+#define TXQ_ID1_MSK 0x00070000
+#define TXQ_ID1_I_MSK 0xfff8ffff
+#define TXQ_ID1_SFT 16
+#define TXQ_ID1_HI 18
+#define TXQ_ID1_SZ 3
+#define TX_ETHER_TRAP_EN_MSK 0x00100000
+#define TX_ETHER_TRAP_EN_I_MSK 0xffefffff
+#define TX_ETHER_TRAP_EN_SFT 20
+#define TX_ETHER_TRAP_EN_HI 20
+#define TX_ETHER_TRAP_EN_SZ 1
+#define RX_ETHER_TRAP_EN_MSK 0x00200000
+#define RX_ETHER_TRAP_EN_I_MSK 0xffdfffff
+#define RX_ETHER_TRAP_EN_SFT 21
+#define RX_ETHER_TRAP_EN_HI 21
+#define RX_ETHER_TRAP_EN_SZ 1
+#define RX_NULL_TRAP_EN_MSK 0x00400000
+#define RX_NULL_TRAP_EN_I_MSK 0xffbfffff
+#define RX_NULL_TRAP_EN_SFT 22
+#define RX_NULL_TRAP_EN_HI 22
+#define RX_NULL_TRAP_EN_SZ 1
+#define RX_GET_TX_QUEUE_EN_MSK 0x02000000
+#define RX_GET_TX_QUEUE_EN_I_MSK 0xfdffffff
+#define RX_GET_TX_QUEUE_EN_SFT 25
+#define RX_GET_TX_QUEUE_EN_HI 25
+#define RX_GET_TX_QUEUE_EN_SZ 1
+#define HCI_INQ_SEL_MSK 0x04000000
+#define HCI_INQ_SEL_I_MSK 0xfbffffff
+#define HCI_INQ_SEL_SFT 26
+#define HCI_INQ_SEL_HI 26
+#define HCI_INQ_SEL_SZ 1
+#define TRX_DEBUG_CNT_ENA_MSK 0x10000000
+#define TRX_DEBUG_CNT_ENA_I_MSK 0xefffffff
+#define TRX_DEBUG_CNT_ENA_SFT 28
+#define TRX_DEBUG_CNT_ENA_HI 28
+#define TRX_DEBUG_CNT_ENA_SZ 1
+#define WAKE_SOON_WITH_SCK_MSK 0x00000001
+#define WAKE_SOON_WITH_SCK_I_MSK 0xfffffffe
+#define WAKE_SOON_WITH_SCK_SFT 0
+#define WAKE_SOON_WITH_SCK_HI 0
+#define WAKE_SOON_WITH_SCK_SZ 1
+#define TX_FLOW_CTRL_MSK 0x0000ffff
+#define TX_FLOW_CTRL_I_MSK 0xffff0000
+#define TX_FLOW_CTRL_SFT 0
+#define TX_FLOW_CTRL_HI 15
+#define TX_FLOW_CTRL_SZ 16
+#define TX_FLOW_MGMT_MSK 0xffff0000
+#define TX_FLOW_MGMT_I_MSK 0x0000ffff
+#define TX_FLOW_MGMT_SFT 16
+#define TX_FLOW_MGMT_HI 31
+#define TX_FLOW_MGMT_SZ 16
+#define TX_FLOW_DATA_MSK 0xffffffff
+#define TX_FLOW_DATA_I_MSK 0x00000000
+#define TX_FLOW_DATA_SFT 0
+#define TX_FLOW_DATA_HI 31
+#define TX_FLOW_DATA_SZ 32
+#define DOT11RTSTHRESHOLD_MSK 0xffff0000
+#define DOT11RTSTHRESHOLD_I_MSK 0x0000ffff
+#define DOT11RTSTHRESHOLD_SFT 16
+#define DOT11RTSTHRESHOLD_HI 31
+#define DOT11RTSTHRESHOLD_SZ 16
+#define TXF_ID_MSK 0x0000003f
+#define TXF_ID_I_MSK 0xffffffc0
+#define TXF_ID_SFT 0
+#define TXF_ID_HI 5
+#define TXF_ID_SZ 6
+#define SEQ_CTRL_MSK 0x0000ffff
+#define SEQ_CTRL_I_MSK 0xffff0000
+#define SEQ_CTRL_SFT 0
+#define SEQ_CTRL_HI 15
+#define SEQ_CTRL_SZ 16
+#define TX_PBOFFSET_MSK 0x000000ff
+#define TX_PBOFFSET_I_MSK 0xffffff00
+#define TX_PBOFFSET_SFT 0
+#define TX_PBOFFSET_HI 7
+#define TX_PBOFFSET_SZ 8
+#define TX_INFO_SIZE_MSK 0x0000ff00
+#define TX_INFO_SIZE_I_MSK 0xffff00ff
+#define TX_INFO_SIZE_SFT 8
+#define TX_INFO_SIZE_HI 15
+#define TX_INFO_SIZE_SZ 8
+#define RX_INFO_SIZE_MSK 0x00ff0000
+#define RX_INFO_SIZE_I_MSK 0xff00ffff
+#define RX_INFO_SIZE_SFT 16
+#define RX_INFO_SIZE_HI 23
+#define RX_INFO_SIZE_SZ 8
+#define RX_LAST_PHY_SIZE_MSK 0xff000000
+#define RX_LAST_PHY_SIZE_I_MSK 0x00ffffff
+#define RX_LAST_PHY_SIZE_SFT 24
+#define RX_LAST_PHY_SIZE_HI 31
+#define RX_LAST_PHY_SIZE_SZ 8
+#define TX_INFO_CLEAR_SIZE_MSK 0x0000003f
+#define TX_INFO_CLEAR_SIZE_I_MSK 0xffffffc0
+#define TX_INFO_CLEAR_SIZE_SFT 0
+#define TX_INFO_CLEAR_SIZE_HI 5
+#define TX_INFO_CLEAR_SIZE_SZ 6
+#define TX_INFO_CLEAR_ENABLE_MSK 0x00000100
+#define TX_INFO_CLEAR_ENABLE_I_MSK 0xfffffeff
+#define TX_INFO_CLEAR_ENABLE_SFT 8
+#define TX_INFO_CLEAR_ENABLE_HI 8
+#define TX_INFO_CLEAR_ENABLE_SZ 1
+#define TXTRAP_ETHTYPE1_MSK 0x0000ffff
+#define TXTRAP_ETHTYPE1_I_MSK 0xffff0000
+#define TXTRAP_ETHTYPE1_SFT 0
+#define TXTRAP_ETHTYPE1_HI 15
+#define TXTRAP_ETHTYPE1_SZ 16
+#define TXTRAP_ETHTYPE0_MSK 0xffff0000
+#define TXTRAP_ETHTYPE0_I_MSK 0x0000ffff
+#define TXTRAP_ETHTYPE0_SFT 16
+#define TXTRAP_ETHTYPE0_HI 31
+#define TXTRAP_ETHTYPE0_SZ 16
+#define RXTRAP_ETHTYPE1_MSK 0x0000ffff
+#define RXTRAP_ETHTYPE1_I_MSK 0xffff0000
+#define RXTRAP_ETHTYPE1_SFT 0
+#define RXTRAP_ETHTYPE1_HI 15
+#define RXTRAP_ETHTYPE1_SZ 16
+#define RXTRAP_ETHTYPE0_MSK 0xffff0000
+#define RXTRAP_ETHTYPE0_I_MSK 0x0000ffff
+#define RXTRAP_ETHTYPE0_SFT 16
+#define RXTRAP_ETHTYPE0_HI 31
+#define RXTRAP_ETHTYPE0_SZ 16
+#define TX_PKT_COUNTER_MSK 0xffffffff
+#define TX_PKT_COUNTER_I_MSK 0x00000000
+#define TX_PKT_COUNTER_SFT 0
+#define TX_PKT_COUNTER_HI 31
+#define TX_PKT_COUNTER_SZ 32
+#define RX_PKT_COUNTER_MSK 0xffffffff
+#define RX_PKT_COUNTER_I_MSK 0x00000000
+#define RX_PKT_COUNTER_SFT 0
+#define RX_PKT_COUNTER_HI 31
+#define RX_PKT_COUNTER_SZ 32
+#define HOST_CMD_COUNTER_MSK 0x000000ff
+#define HOST_CMD_COUNTER_I_MSK 0xffffff00
+#define HOST_CMD_COUNTER_SFT 0
+#define HOST_CMD_COUNTER_HI 7
+#define HOST_CMD_COUNTER_SZ 8
+#define HOST_EVENT_COUNTER_MSK 0x000000ff
+#define HOST_EVENT_COUNTER_I_MSK 0xffffff00
+#define HOST_EVENT_COUNTER_SFT 0
+#define HOST_EVENT_COUNTER_HI 7
+#define HOST_EVENT_COUNTER_SZ 8
+#define TX_PKT_DROP_COUNTER_MSK 0x000000ff
+#define TX_PKT_DROP_COUNTER_I_MSK 0xffffff00
+#define TX_PKT_DROP_COUNTER_SFT 0
+#define TX_PKT_DROP_COUNTER_HI 7
+#define TX_PKT_DROP_COUNTER_SZ 8
+#define RX_PKT_DROP_COUNTER_MSK 0x000000ff
+#define RX_PKT_DROP_COUNTER_I_MSK 0xffffff00
+#define RX_PKT_DROP_COUNTER_SFT 0
+#define RX_PKT_DROP_COUNTER_HI 7
+#define RX_PKT_DROP_COUNTER_SZ 8
+#define TX_PKT_TRAP_COUNTER_MSK 0x000000ff
+#define TX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
+#define TX_PKT_TRAP_COUNTER_SFT 0
+#define TX_PKT_TRAP_COUNTER_HI 7
+#define TX_PKT_TRAP_COUNTER_SZ 8
+#define RX_PKT_TRAP_COUNTER_MSK 0x000000ff
+#define RX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
+#define RX_PKT_TRAP_COUNTER_SFT 0
+#define RX_PKT_TRAP_COUNTER_HI 7
+#define RX_PKT_TRAP_COUNTER_SZ 8
+#define HOST_TX_FAIL_COUNTER_MSK 0x000000ff
+#define HOST_TX_FAIL_COUNTER_I_MSK 0xffffff00
+#define HOST_TX_FAIL_COUNTER_SFT 0
+#define HOST_TX_FAIL_COUNTER_HI 7
+#define HOST_TX_FAIL_COUNTER_SZ 8
+#define HOST_RX_FAIL_COUNTER_MSK 0x000000ff
+#define HOST_RX_FAIL_COUNTER_I_MSK 0xffffff00
+#define HOST_RX_FAIL_COUNTER_SFT 0
+#define HOST_RX_FAIL_COUNTER_HI 7
+#define HOST_RX_FAIL_COUNTER_SZ 8
+#define HCI_STATE_MONITOR_MSK 0xffffffff
+#define HCI_STATE_MONITOR_I_MSK 0x00000000
+#define HCI_STATE_MONITOR_SFT 0
+#define HCI_STATE_MONITOR_HI 31
+#define HCI_STATE_MONITOR_SZ 32
+#define HCI_ST_TIMEOUT_MONITOR_MSK 0xffffffff
+#define HCI_ST_TIMEOUT_MONITOR_I_MSK 0x00000000
+#define HCI_ST_TIMEOUT_MONITOR_SFT 0
+#define HCI_ST_TIMEOUT_MONITOR_HI 31
+#define HCI_ST_TIMEOUT_MONITOR_SZ 32
+#define TX_ON_DEMAND_LENGTH_MSK 0xffffffff
+#define TX_ON_DEMAND_LENGTH_I_MSK 0x00000000
+#define TX_ON_DEMAND_LENGTH_SFT 0
+#define TX_ON_DEMAND_LENGTH_HI 31
+#define TX_ON_DEMAND_LENGTH_SZ 32
+#define HCI_MONITOR_REG1_MSK 0xffffffff
+#define HCI_MONITOR_REG1_I_MSK 0x00000000
+#define HCI_MONITOR_REG1_SFT 0
+#define HCI_MONITOR_REG1_HI 31
+#define HCI_MONITOR_REG1_SZ 32
+#define HCI_MONITOR_REG2_MSK 0xffffffff
+#define HCI_MONITOR_REG2_I_MSK 0x00000000
+#define HCI_MONITOR_REG2_SFT 0
+#define HCI_MONITOR_REG2_HI 31
+#define HCI_MONITOR_REG2_SZ 32
+#define HCI_TX_ALLOC_TIME_31_0_MSK 0xffffffff
+#define HCI_TX_ALLOC_TIME_31_0_I_MSK 0x00000000
+#define HCI_TX_ALLOC_TIME_31_0_SFT 0
+#define HCI_TX_ALLOC_TIME_31_0_HI 31
+#define HCI_TX_ALLOC_TIME_31_0_SZ 32
+#define HCI_TX_ALLOC_TIME_47_32_MSK 0x0000ffff
+#define HCI_TX_ALLOC_TIME_47_32_I_MSK 0xffff0000
+#define HCI_TX_ALLOC_TIME_47_32_SFT 0
+#define HCI_TX_ALLOC_TIME_47_32_HI 15
+#define HCI_TX_ALLOC_TIME_47_32_SZ 16
+#define HCI_MB_MAX_CNT_MSK 0x00ff0000
+#define HCI_MB_MAX_CNT_I_MSK 0xff00ffff
+#define HCI_MB_MAX_CNT_SFT 16
+#define HCI_MB_MAX_CNT_HI 23
+#define HCI_MB_MAX_CNT_SZ 8
+#define HCI_TX_ALLOC_CNT_31_0_MSK 0xffffffff
+#define HCI_TX_ALLOC_CNT_31_0_I_MSK 0x00000000
+#define HCI_TX_ALLOC_CNT_31_0_SFT 0
+#define HCI_TX_ALLOC_CNT_31_0_HI 31
+#define HCI_TX_ALLOC_CNT_31_0_SZ 32
+#define HCI_TX_ALLOC_CNT_47_32_MSK 0x0000ffff
+#define HCI_TX_ALLOC_CNT_47_32_I_MSK 0xffff0000
+#define HCI_TX_ALLOC_CNT_47_32_SFT 0
+#define HCI_TX_ALLOC_CNT_47_32_HI 15
+#define HCI_TX_ALLOC_CNT_47_32_SZ 16
+#define HCI_PROC_CNT_MSK 0x00ff0000
+#define HCI_PROC_CNT_I_MSK 0xff00ffff
+#define HCI_PROC_CNT_SFT 16
+#define HCI_PROC_CNT_HI 23
+#define HCI_PROC_CNT_SZ 8
+#define SDIO_TRANS_CNT_MSK 0xff000000
+#define SDIO_TRANS_CNT_I_MSK 0x00ffffff
+#define SDIO_TRANS_CNT_SFT 24
+#define SDIO_TRANS_CNT_HI 31
+#define SDIO_TRANS_CNT_SZ 8
+#define SDIO_TX_INVALID_CNT_31_0_MSK 0xffffffff
+#define SDIO_TX_INVALID_CNT_31_0_I_MSK 0x00000000
+#define SDIO_TX_INVALID_CNT_31_0_SFT 0
+#define SDIO_TX_INVALID_CNT_31_0_HI 31
+#define SDIO_TX_INVALID_CNT_31_0_SZ 32
+#define SDIO_TX_INVALID_CNT_47_32_MSK 0x0000ffff
+#define SDIO_TX_INVALID_CNT_47_32_I_MSK 0xffff0000
+#define SDIO_TX_INVALID_CNT_47_32_SFT 0
+#define SDIO_TX_INVALID_CNT_47_32_HI 15
+#define SDIO_TX_INVALID_CNT_47_32_SZ 16
+#define CS_START_ADDR_MSK 0x0000ffff
+#define CS_START_ADDR_I_MSK 0xffff0000
+#define CS_START_ADDR_SFT 0
+#define CS_START_ADDR_HI 15
+#define CS_START_ADDR_SZ 16
+#define CS_PKT_ID_MSK 0x007f0000
+#define CS_PKT_ID_I_MSK 0xff80ffff
+#define CS_PKT_ID_SFT 16
+#define CS_PKT_ID_HI 22
+#define CS_PKT_ID_SZ 7
+#define ADD_LEN_MSK 0x0000ffff
+#define ADD_LEN_I_MSK 0xffff0000
+#define ADD_LEN_SFT 0
+#define ADD_LEN_HI 15
+#define ADD_LEN_SZ 16
+#define CS_ADDER_EN_MSK 0x00000001
+#define CS_ADDER_EN_I_MSK 0xfffffffe
+#define CS_ADDER_EN_SFT 0
+#define CS_ADDER_EN_HI 0
+#define CS_ADDER_EN_SZ 1
+#define PSEUDO_MSK 0x00000002
+#define PSEUDO_I_MSK 0xfffffffd
+#define PSEUDO_SFT 1
+#define PSEUDO_HI 1
+#define PSEUDO_SZ 1
+#define CALCULATE_MSK 0xffffffff
+#define CALCULATE_I_MSK 0x00000000
+#define CALCULATE_SFT 0
+#define CALCULATE_HI 31
+#define CALCULATE_SZ 32
+#define L4_LEN_MSK 0x0000ffff
+#define L4_LEN_I_MSK 0xffff0000
+#define L4_LEN_SFT 0
+#define L4_LEN_HI 15
+#define L4_LEN_SZ 16
+#define L4_PROTOL_MSK 0x00ff0000
+#define L4_PROTOL_I_MSK 0xff00ffff
+#define L4_PROTOL_SFT 16
+#define L4_PROTOL_HI 23
+#define L4_PROTOL_SZ 8
+#define CHECK_SUM_MSK 0x0000ffff
+#define CHECK_SUM_I_MSK 0xffff0000
+#define CHECK_SUM_SFT 0
+#define CHECK_SUM_HI 15
+#define CHECK_SUM_SZ 16
+#define RAND_EN_MSK 0x00000001
+#define RAND_EN_I_MSK 0xfffffffe
+#define RAND_EN_SFT 0
+#define RAND_EN_HI 0
+#define RAND_EN_SZ 1
+#define RAND_NUM_MSK 0xffffffff
+#define RAND_NUM_I_MSK 0x00000000
+#define RAND_NUM_SFT 0
+#define RAND_NUM_HI 31
+#define RAND_NUM_SZ 32
+#define MUL_OP1_MSK 0xffffffff
+#define MUL_OP1_I_MSK 0x00000000
+#define MUL_OP1_SFT 0
+#define MUL_OP1_HI 31
+#define MUL_OP1_SZ 32
+#define MUL_OP2_MSK 0xffffffff
+#define MUL_OP2_I_MSK 0x00000000
+#define MUL_OP2_SFT 0
+#define MUL_OP2_HI 31
+#define MUL_OP2_SZ 32
+#define MUL_ANS0_MSK 0xffffffff
+#define MUL_ANS0_I_MSK 0x00000000
+#define MUL_ANS0_SFT 0
+#define MUL_ANS0_HI 31
+#define MUL_ANS0_SZ 32
+#define MUL_ANS1_MSK 0xffffffff
+#define MUL_ANS1_I_MSK 0x00000000
+#define MUL_ANS1_SFT 0
+#define MUL_ANS1_HI 31
+#define MUL_ANS1_SZ 32
+#define RD_ADDR_MSK 0x0000ffff
+#define RD_ADDR_I_MSK 0xffff0000
+#define RD_ADDR_SFT 0
+#define RD_ADDR_HI 15
+#define RD_ADDR_SZ 16
+#define RD_ID_MSK 0x007f0000
+#define RD_ID_I_MSK 0xff80ffff
+#define RD_ID_SFT 16
+#define RD_ID_HI 22
+#define RD_ID_SZ 7
+#define WR_ADDR_MSK 0x0000ffff
+#define WR_ADDR_I_MSK 0xffff0000
+#define WR_ADDR_SFT 0
+#define WR_ADDR_HI 15
+#define WR_ADDR_SZ 16
+#define WR_ID_MSK 0x007f0000
+#define WR_ID_I_MSK 0xff80ffff
+#define WR_ID_SFT 16
+#define WR_ID_HI 22
+#define WR_ID_SZ 7
+#define LEN_MSK 0x0000ffff
+#define LEN_I_MSK 0xffff0000
+#define LEN_SFT 0
+#define LEN_HI 15
+#define LEN_SZ 16
+#define CLR_MSK 0x00000001
+#define CLR_I_MSK 0xfffffffe
+#define CLR_SFT 0
+#define CLR_HI 0
+#define CLR_SZ 1
+#define PHY_MODE_MSK 0x00000003
+#define PHY_MODE_I_MSK 0xfffffffc
+#define PHY_MODE_SFT 0
+#define PHY_MODE_HI 1
+#define PHY_MODE_SZ 2
+#define SHRT_PREAM_MSK 0x00000004
+#define SHRT_PREAM_I_MSK 0xfffffffb
+#define SHRT_PREAM_SFT 2
+#define SHRT_PREAM_HI 2
+#define SHRT_PREAM_SZ 1
+#define SHRT_GI_MSK 0x00000008
+#define SHRT_GI_I_MSK 0xfffffff7
+#define SHRT_GI_SFT 3
+#define SHRT_GI_HI 3
+#define SHRT_GI_SZ 1
+#define DATA_RATE_MSK 0x000007f0
+#define DATA_RATE_I_MSK 0xfffff80f
+#define DATA_RATE_SFT 4
+#define DATA_RATE_HI 10
+#define DATA_RATE_SZ 7
+#define MCS_MSK 0x00007000
+#define MCS_I_MSK 0xffff8fff
+#define MCS_SFT 12
+#define MCS_HI 14
+#define MCS_SZ 3
+#define FRAME_LEN_MSK 0xffff0000
+#define FRAME_LEN_I_MSK 0x0000ffff
+#define FRAME_LEN_SFT 16
+#define FRAME_LEN_HI 31
+#define FRAME_LEN_SZ 16
+#define DURATION_MSK 0x0000ffff
+#define DURATION_I_MSK 0xffff0000
+#define DURATION_SFT 0
+#define DURATION_HI 15
+#define DURATION_SZ 16
+#define SHA_DST_ADDR_MSK 0xffffffff
+#define SHA_DST_ADDR_I_MSK 0x00000000
+#define SHA_DST_ADDR_SFT 0
+#define SHA_DST_ADDR_HI 31
+#define SHA_DST_ADDR_SZ 32
+#define SHA_SRC_ADDR_MSK 0xffffffff
+#define SHA_SRC_ADDR_I_MSK 0x00000000
+#define SHA_SRC_ADDR_SFT 0
+#define SHA_SRC_ADDR_HI 31
+#define SHA_SRC_ADDR_SZ 32
+#define SHA_BUSY_MSK 0x00000001
+#define SHA_BUSY_I_MSK 0xfffffffe
+#define SHA_BUSY_SFT 0
+#define SHA_BUSY_HI 0
+#define SHA_BUSY_SZ 1
+#define SHA_ENDIAN_MSK 0x00000002
+#define SHA_ENDIAN_I_MSK 0xfffffffd
+#define SHA_ENDIAN_SFT 1
+#define SHA_ENDIAN_HI 1
+#define SHA_ENDIAN_SZ 1
+#define EFS_CLKFREQ_MSK 0x00000fff
+#define EFS_CLKFREQ_I_MSK 0xfffff000
+#define EFS_CLKFREQ_SFT 0
+#define EFS_CLKFREQ_HI 11
+#define EFS_CLKFREQ_SZ 12
+#define LOW_ACTIVE_MSK 0x00010000
+#define LOW_ACTIVE_I_MSK 0xfffeffff
+#define LOW_ACTIVE_SFT 16
+#define LOW_ACTIVE_HI 16
+#define LOW_ACTIVE_SZ 1
+#define EFS_CLKFREQ_RD_MSK 0x0ff00000
+#define EFS_CLKFREQ_RD_I_MSK 0xf00fffff
+#define EFS_CLKFREQ_RD_SFT 20
+#define EFS_CLKFREQ_RD_HI 27
+#define EFS_CLKFREQ_RD_SZ 8
+#define EFS_PRE_RD_MSK 0xf0000000
+#define EFS_PRE_RD_I_MSK 0x0fffffff
+#define EFS_PRE_RD_SFT 28
+#define EFS_PRE_RD_HI 31
+#define EFS_PRE_RD_SZ 4
+#define EFS_LDO_ON_MSK 0x0000ffff
+#define EFS_LDO_ON_I_MSK 0xffff0000
+#define EFS_LDO_ON_SFT 0
+#define EFS_LDO_ON_HI 15
+#define EFS_LDO_ON_SZ 16
+#define EFS_LDO_OFF_MSK 0xffff0000
+#define EFS_LDO_OFF_I_MSK 0x0000ffff
+#define EFS_LDO_OFF_SFT 16
+#define EFS_LDO_OFF_HI 31
+#define EFS_LDO_OFF_SZ 16
+#define EFS_RDATA_0_MSK 0xffffffff
+#define EFS_RDATA_0_I_MSK 0x00000000
+#define EFS_RDATA_0_SFT 0
+#define EFS_RDATA_0_HI 31
+#define EFS_RDATA_0_SZ 32
+#define EFS_WDATA_0_MSK 0xffffffff
+#define EFS_WDATA_0_I_MSK 0x00000000
+#define EFS_WDATA_0_SFT 0
+#define EFS_WDATA_0_HI 31
+#define EFS_WDATA_0_SZ 32
+#define EFS_RDATA_1_MSK 0xffffffff
+#define EFS_RDATA_1_I_MSK 0x00000000
+#define EFS_RDATA_1_SFT 0
+#define EFS_RDATA_1_HI 31
+#define EFS_RDATA_1_SZ 32
+#define EFS_WDATA_1_MSK 0xffffffff
+#define EFS_WDATA_1_I_MSK 0x00000000
+#define EFS_WDATA_1_SFT 0
+#define EFS_WDATA_1_HI 31
+#define EFS_WDATA_1_SZ 32
+#define EFS_RDATA_2_MSK 0xffffffff
+#define EFS_RDATA_2_I_MSK 0x00000000
+#define EFS_RDATA_2_SFT 0
+#define EFS_RDATA_2_HI 31
+#define EFS_RDATA_2_SZ 32
+#define EFS_WDATA_2_MSK 0xffffffff
+#define EFS_WDATA_2_I_MSK 0x00000000
+#define EFS_WDATA_2_SFT 0
+#define EFS_WDATA_2_HI 31
+#define EFS_WDATA_2_SZ 32
+#define EFS_RDATA_3_MSK 0xffffffff
+#define EFS_RDATA_3_I_MSK 0x00000000
+#define EFS_RDATA_3_SFT 0
+#define EFS_RDATA_3_HI 31
+#define EFS_RDATA_3_SZ 32
+#define EFS_WDATA_3_MSK 0xffffffff
+#define EFS_WDATA_3_I_MSK 0x00000000
+#define EFS_WDATA_3_SFT 0
+#define EFS_WDATA_3_HI 31
+#define EFS_WDATA_3_SZ 32
+#define EFS_RDATA_4_MSK 0xffffffff
+#define EFS_RDATA_4_I_MSK 0x00000000
+#define EFS_RDATA_4_SFT 0
+#define EFS_RDATA_4_HI 31
+#define EFS_RDATA_4_SZ 32
+#define EFS_WDATA_4_MSK 0xffffffff
+#define EFS_WDATA_4_I_MSK 0x00000000
+#define EFS_WDATA_4_SFT 0
+#define EFS_WDATA_4_HI 31
+#define EFS_WDATA_4_SZ 32
+#define EFS_RDATA_5_MSK 0xffffffff
+#define EFS_RDATA_5_I_MSK 0x00000000
+#define EFS_RDATA_5_SFT 0
+#define EFS_RDATA_5_HI 31
+#define EFS_RDATA_5_SZ 32
+#define EFS_WDATA_5_MSK 0xffffffff
+#define EFS_WDATA_5_I_MSK 0x00000000
+#define EFS_WDATA_5_SFT 0
+#define EFS_WDATA_5_HI 31
+#define EFS_WDATA_5_SZ 32
+#define EFS_RDATA_6_MSK 0xffffffff
+#define EFS_RDATA_6_I_MSK 0x00000000
+#define EFS_RDATA_6_SFT 0
+#define EFS_RDATA_6_HI 31
+#define EFS_RDATA_6_SZ 32
+#define EFS_WDATA_6_MSK 0xffffffff
+#define EFS_WDATA_6_I_MSK 0x00000000
+#define EFS_WDATA_6_SFT 0
+#define EFS_WDATA_6_HI 31
+#define EFS_WDATA_6_SZ 32
+#define EFS_RDATA_7_MSK 0xffffffff
+#define EFS_RDATA_7_I_MSK 0x00000000
+#define EFS_RDATA_7_SFT 0
+#define EFS_RDATA_7_HI 31
+#define EFS_RDATA_7_SZ 32
+#define EFS_WDATA_7_MSK 0xffffffff
+#define EFS_WDATA_7_I_MSK 0x00000000
+#define EFS_WDATA_7_SFT 0
+#define EFS_WDATA_7_HI 31
+#define EFS_WDATA_7_SZ 32
+#define EFS_SPI_RD0_EN_MSK 0x00000001
+#define EFS_SPI_RD0_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD0_EN_SFT 0
+#define EFS_SPI_RD0_EN_HI 0
+#define EFS_SPI_RD0_EN_SZ 1
+#define EFS_SPI_RD1_EN_MSK 0x00000001
+#define EFS_SPI_RD1_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD1_EN_SFT 0
+#define EFS_SPI_RD1_EN_HI 0
+#define EFS_SPI_RD1_EN_SZ 1
+#define EFS_SPI_RD2_EN_MSK 0x00000001
+#define EFS_SPI_RD2_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD2_EN_SFT 0
+#define EFS_SPI_RD2_EN_HI 0
+#define EFS_SPI_RD2_EN_SZ 1
+#define EFS_SPI_RD3_EN_MSK 0x00000001
+#define EFS_SPI_RD3_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD3_EN_SFT 0
+#define EFS_SPI_RD3_EN_HI 0
+#define EFS_SPI_RD3_EN_SZ 1
+#define EFS_SPI_RD4_EN_MSK 0x00000001
+#define EFS_SPI_RD4_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD4_EN_SFT 0
+#define EFS_SPI_RD4_EN_HI 0
+#define EFS_SPI_RD4_EN_SZ 1
+#define EFS_SPI_RD5_EN_MSK 0x00000001
+#define EFS_SPI_RD5_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD5_EN_SFT 0
+#define EFS_SPI_RD5_EN_HI 0
+#define EFS_SPI_RD5_EN_SZ 1
+#define EFS_SPI_RD6_EN_MSK 0x00000001
+#define EFS_SPI_RD6_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD6_EN_SFT 0
+#define EFS_SPI_RD6_EN_HI 0
+#define EFS_SPI_RD6_EN_SZ 1
+#define EFS_SPI_RD7_EN_MSK 0x00000001
+#define EFS_SPI_RD7_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD7_EN_SFT 0
+#define EFS_SPI_RD7_EN_HI 0
+#define EFS_SPI_RD7_EN_SZ 1
+#define EFS_SPI_RBUSY_MSK 0x00000001
+#define EFS_SPI_RBUSY_I_MSK 0xfffffffe
+#define EFS_SPI_RBUSY_SFT 0
+#define EFS_SPI_RBUSY_HI 0
+#define EFS_SPI_RBUSY_SZ 1
+#define EFS_SPI_RDATA_0_MSK 0xffffffff
+#define EFS_SPI_RDATA_0_I_MSK 0x00000000
+#define EFS_SPI_RDATA_0_SFT 0
+#define EFS_SPI_RDATA_0_HI 31
+#define EFS_SPI_RDATA_0_SZ 32
+#define EFS_SPI_RDATA_1_MSK 0xffffffff
+#define EFS_SPI_RDATA_1_I_MSK 0x00000000
+#define EFS_SPI_RDATA_1_SFT 0
+#define EFS_SPI_RDATA_1_HI 31
+#define EFS_SPI_RDATA_1_SZ 32
+#define EFS_SPI_RDATA_2_MSK 0xffffffff
+#define EFS_SPI_RDATA_2_I_MSK 0x00000000
+#define EFS_SPI_RDATA_2_SFT 0
+#define EFS_SPI_RDATA_2_HI 31
+#define EFS_SPI_RDATA_2_SZ 32
+#define EFS_SPI_RDATA_3_MSK 0xffffffff
+#define EFS_SPI_RDATA_3_I_MSK 0x00000000
+#define EFS_SPI_RDATA_3_SFT 0
+#define EFS_SPI_RDATA_3_HI 31
+#define EFS_SPI_RDATA_3_SZ 32
+#define EFS_SPI_RDATA_4_MSK 0xffffffff
+#define EFS_SPI_RDATA_4_I_MSK 0x00000000
+#define EFS_SPI_RDATA_4_SFT 0
+#define EFS_SPI_RDATA_4_HI 31
+#define EFS_SPI_RDATA_4_SZ 32
+#define EFS_SPI_RDATA_5_MSK 0xffffffff
+#define EFS_SPI_RDATA_5_I_MSK 0x00000000
+#define EFS_SPI_RDATA_5_SFT 0
+#define EFS_SPI_RDATA_5_HI 31
+#define EFS_SPI_RDATA_5_SZ 32
+#define EFS_SPI_RDATA_6_MSK 0xffffffff
+#define EFS_SPI_RDATA_6_I_MSK 0x00000000
+#define EFS_SPI_RDATA_6_SFT 0
+#define EFS_SPI_RDATA_6_HI 31
+#define EFS_SPI_RDATA_6_SZ 32
+#define EFS_SPI_RDATA_7_MSK 0xffffffff
+#define EFS_SPI_RDATA_7_I_MSK 0x00000000
+#define EFS_SPI_RDATA_7_SFT 0
+#define EFS_SPI_RDATA_7_HI 31
+#define EFS_SPI_RDATA_7_SZ 32
+#define GET_RK_MSK 0x00000001
+#define GET_RK_I_MSK 0xfffffffe
+#define GET_RK_SFT 0
+#define GET_RK_HI 0
+#define GET_RK_SZ 1
+#define FORCE_GET_RK_MSK 0x00000002
+#define FORCE_GET_RK_I_MSK 0xfffffffd
+#define FORCE_GET_RK_SFT 1
+#define FORCE_GET_RK_HI 1
+#define FORCE_GET_RK_SZ 1
+#define SMS4_DESCRY_EN_MSK 0x00000010
+#define SMS4_DESCRY_EN_I_MSK 0xffffffef
+#define SMS4_DESCRY_EN_SFT 4
+#define SMS4_DESCRY_EN_HI 4
+#define SMS4_DESCRY_EN_SZ 1
+#define DEC_DOUT_MSB_MSK 0x00000001
+#define DEC_DOUT_MSB_I_MSK 0xfffffffe
+#define DEC_DOUT_MSB_SFT 0
+#define DEC_DOUT_MSB_HI 0
+#define DEC_DOUT_MSB_SZ 1
+#define DEC_DIN_MSB_MSK 0x00000002
+#define DEC_DIN_MSB_I_MSK 0xfffffffd
+#define DEC_DIN_MSB_SFT 1
+#define DEC_DIN_MSB_HI 1
+#define DEC_DIN_MSB_SZ 1
+#define ENC_DOUT_MSB_MSK 0x00000004
+#define ENC_DOUT_MSB_I_MSK 0xfffffffb
+#define ENC_DOUT_MSB_SFT 2
+#define ENC_DOUT_MSB_HI 2
+#define ENC_DOUT_MSB_SZ 1
+#define ENC_DIN_MSB_MSK 0x00000008
+#define ENC_DIN_MSB_I_MSK 0xfffffff7
+#define ENC_DIN_MSB_SFT 3
+#define ENC_DIN_MSB_HI 3
+#define ENC_DIN_MSB_SZ 1
+#define KEY_DIN_MSB_MSK 0x00000010
+#define KEY_DIN_MSB_I_MSK 0xffffffef
+#define KEY_DIN_MSB_SFT 4
+#define KEY_DIN_MSB_HI 4
+#define KEY_DIN_MSB_SZ 1
+#define SMS4_CBC_EN_MSK 0x00000001
+#define SMS4_CBC_EN_I_MSK 0xfffffffe
+#define SMS4_CBC_EN_SFT 0
+#define SMS4_CBC_EN_HI 0
+#define SMS4_CBC_EN_SZ 1
+#define SMS4_CFB_EN_MSK 0x00000002
+#define SMS4_CFB_EN_I_MSK 0xfffffffd
+#define SMS4_CFB_EN_SFT 1
+#define SMS4_CFB_EN_HI 1
+#define SMS4_CFB_EN_SZ 1
+#define SMS4_OFB_EN_MSK 0x00000004
+#define SMS4_OFB_EN_I_MSK 0xfffffffb
+#define SMS4_OFB_EN_SFT 2
+#define SMS4_OFB_EN_HI 2
+#define SMS4_OFB_EN_SZ 1
+#define SMS4_START_TRIG_MSK 0x00000001
+#define SMS4_START_TRIG_I_MSK 0xfffffffe
+#define SMS4_START_TRIG_SFT 0
+#define SMS4_START_TRIG_HI 0
+#define SMS4_START_TRIG_SZ 1
+#define SMS4_BUSY_MSK 0x00000001
+#define SMS4_BUSY_I_MSK 0xfffffffe
+#define SMS4_BUSY_SFT 0
+#define SMS4_BUSY_HI 0
+#define SMS4_BUSY_SZ 1
+#define SMS4_DONE_MSK 0x00000001
+#define SMS4_DONE_I_MSK 0xfffffffe
+#define SMS4_DONE_SFT 0
+#define SMS4_DONE_HI 0
+#define SMS4_DONE_SZ 1
+#define SMS4_DATAIN_0_MSK 0xffffffff
+#define SMS4_DATAIN_0_I_MSK 0x00000000
+#define SMS4_DATAIN_0_SFT 0
+#define SMS4_DATAIN_0_HI 31
+#define SMS4_DATAIN_0_SZ 32
+#define SMS4_DATAIN_1_MSK 0xffffffff
+#define SMS4_DATAIN_1_I_MSK 0x00000000
+#define SMS4_DATAIN_1_SFT 0
+#define SMS4_DATAIN_1_HI 31
+#define SMS4_DATAIN_1_SZ 32
+#define SMS4_DATAIN_2_MSK 0xffffffff
+#define SMS4_DATAIN_2_I_MSK 0x00000000
+#define SMS4_DATAIN_2_SFT 0
+#define SMS4_DATAIN_2_HI 31
+#define SMS4_DATAIN_2_SZ 32
+#define SMS4_DATAIN_3_MSK 0xffffffff
+#define SMS4_DATAIN_3_I_MSK 0x00000000
+#define SMS4_DATAIN_3_SFT 0
+#define SMS4_DATAIN_3_HI 31
+#define SMS4_DATAIN_3_SZ 32
+#define SMS4_DATAOUT_0_MSK 0xffffffff
+#define SMS4_DATAOUT_0_I_MSK 0x00000000
+#define SMS4_DATAOUT_0_SFT 0
+#define SMS4_DATAOUT_0_HI 31
+#define SMS4_DATAOUT_0_SZ 32
+#define SMS4_DATAOUT_1_MSK 0xffffffff
+#define SMS4_DATAOUT_1_I_MSK 0x00000000
+#define SMS4_DATAOUT_1_SFT 0
+#define SMS4_DATAOUT_1_HI 31
+#define SMS4_DATAOUT_1_SZ 32
+#define SMS4_DATAOUT_2_MSK 0xffffffff
+#define SMS4_DATAOUT_2_I_MSK 0x00000000
+#define SMS4_DATAOUT_2_SFT 0
+#define SMS4_DATAOUT_2_HI 31
+#define SMS4_DATAOUT_2_SZ 32
+#define SMS4_DATAOUT_3_MSK 0xffffffff
+#define SMS4_DATAOUT_3_I_MSK 0x00000000
+#define SMS4_DATAOUT_3_SFT 0
+#define SMS4_DATAOUT_3_HI 31
+#define SMS4_DATAOUT_3_SZ 32
+#define SMS4_KEY_0_MSK 0xffffffff
+#define SMS4_KEY_0_I_MSK 0x00000000
+#define SMS4_KEY_0_SFT 0
+#define SMS4_KEY_0_HI 31
+#define SMS4_KEY_0_SZ 32
+#define SMS4_KEY_1_MSK 0xffffffff
+#define SMS4_KEY_1_I_MSK 0x00000000
+#define SMS4_KEY_1_SFT 0
+#define SMS4_KEY_1_HI 31
+#define SMS4_KEY_1_SZ 32
+#define SMS4_KEY_2_MSK 0xffffffff
+#define SMS4_KEY_2_I_MSK 0x00000000
+#define SMS4_KEY_2_SFT 0
+#define SMS4_KEY_2_HI 31
+#define SMS4_KEY_2_SZ 32
+#define SMS4_KEY_3_MSK 0xffffffff
+#define SMS4_KEY_3_I_MSK 0x00000000
+#define SMS4_KEY_3_SFT 0
+#define SMS4_KEY_3_HI 31
+#define SMS4_KEY_3_SZ 32
+#define SMS4_MODE_IV0_MSK 0xffffffff
+#define SMS4_MODE_IV0_I_MSK 0x00000000
+#define SMS4_MODE_IV0_SFT 0
+#define SMS4_MODE_IV0_HI 31
+#define SMS4_MODE_IV0_SZ 32
+#define SMS4_MODE_IV1_MSK 0xffffffff
+#define SMS4_MODE_IV1_I_MSK 0x00000000
+#define SMS4_MODE_IV1_SFT 0
+#define SMS4_MODE_IV1_HI 31
+#define SMS4_MODE_IV1_SZ 32
+#define SMS4_MODE_IV2_MSK 0xffffffff
+#define SMS4_MODE_IV2_I_MSK 0x00000000
+#define SMS4_MODE_IV2_SFT 0
+#define SMS4_MODE_IV2_HI 31
+#define SMS4_MODE_IV2_SZ 32
+#define SMS4_MODE_IV3_MSK 0xffffffff
+#define SMS4_MODE_IV3_I_MSK 0x00000000
+#define SMS4_MODE_IV3_SFT 0
+#define SMS4_MODE_IV3_HI 31
+#define SMS4_MODE_IV3_SZ 32
+#define SMS4_OFB_ENC0_MSK 0xffffffff
+#define SMS4_OFB_ENC0_I_MSK 0x00000000
+#define SMS4_OFB_ENC0_SFT 0
+#define SMS4_OFB_ENC0_HI 31
+#define SMS4_OFB_ENC0_SZ 32
+#define SMS4_OFB_ENC1_MSK 0xffffffff
+#define SMS4_OFB_ENC1_I_MSK 0x00000000
+#define SMS4_OFB_ENC1_SFT 0
+#define SMS4_OFB_ENC1_HI 31
+#define SMS4_OFB_ENC1_SZ 32
+#define SMS4_OFB_ENC2_MSK 0xffffffff
+#define SMS4_OFB_ENC2_I_MSK 0x00000000
+#define SMS4_OFB_ENC2_SFT 0
+#define SMS4_OFB_ENC2_HI 31
+#define SMS4_OFB_ENC2_SZ 32
+#define SMS4_OFB_ENC3_MSK 0xffffffff
+#define SMS4_OFB_ENC3_I_MSK 0x00000000
+#define SMS4_OFB_ENC3_SFT 0
+#define SMS4_OFB_ENC3_HI 31
+#define SMS4_OFB_ENC3_SZ 32
+#define MRX_MCAST_TB0_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB0_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB0_31_0_SFT 0
+#define MRX_MCAST_TB0_31_0_HI 31
+#define MRX_MCAST_TB0_31_0_SZ 32
+#define MRX_MCAST_TB0_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB0_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB0_47_32_SFT 0
+#define MRX_MCAST_TB0_47_32_HI 15
+#define MRX_MCAST_TB0_47_32_SZ 16
+#define MRX_MCAST_MASK0_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK0_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK0_31_0_SFT 0
+#define MRX_MCAST_MASK0_31_0_HI 31
+#define MRX_MCAST_MASK0_31_0_SZ 32
+#define MRX_MCAST_MASK0_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK0_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK0_47_32_SFT 0
+#define MRX_MCAST_MASK0_47_32_HI 15
+#define MRX_MCAST_MASK0_47_32_SZ 16
+#define MRX_MCAST_CTRL_0_MSK 0x00000003
+#define MRX_MCAST_CTRL_0_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_0_SFT 0
+#define MRX_MCAST_CTRL_0_HI 1
+#define MRX_MCAST_CTRL_0_SZ 2
+#define MRX_MCAST_TB1_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB1_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB1_31_0_SFT 0
+#define MRX_MCAST_TB1_31_0_HI 31
+#define MRX_MCAST_TB1_31_0_SZ 32
+#define MRX_MCAST_TB1_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB1_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB1_47_32_SFT 0
+#define MRX_MCAST_TB1_47_32_HI 15
+#define MRX_MCAST_TB1_47_32_SZ 16
+#define MRX_MCAST_MASK1_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK1_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK1_31_0_SFT 0
+#define MRX_MCAST_MASK1_31_0_HI 31
+#define MRX_MCAST_MASK1_31_0_SZ 32
+#define MRX_MCAST_MASK1_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK1_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK1_47_32_SFT 0
+#define MRX_MCAST_MASK1_47_32_HI 15
+#define MRX_MCAST_MASK1_47_32_SZ 16
+#define MRX_MCAST_CTRL_1_MSK 0x00000003
+#define MRX_MCAST_CTRL_1_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_1_SFT 0
+#define MRX_MCAST_CTRL_1_HI 1
+#define MRX_MCAST_CTRL_1_SZ 2
+#define MRX_MCAST_TB2_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB2_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB2_31_0_SFT 0
+#define MRX_MCAST_TB2_31_0_HI 31
+#define MRX_MCAST_TB2_31_0_SZ 32
+#define MRX_MCAST_TB2_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB2_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB2_47_32_SFT 0
+#define MRX_MCAST_TB2_47_32_HI 15
+#define MRX_MCAST_TB2_47_32_SZ 16
+#define MRX_MCAST_MASK2_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK2_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK2_31_0_SFT 0
+#define MRX_MCAST_MASK2_31_0_HI 31
+#define MRX_MCAST_MASK2_31_0_SZ 32
+#define MRX_MCAST_MASK2_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK2_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK2_47_32_SFT 0
+#define MRX_MCAST_MASK2_47_32_HI 15
+#define MRX_MCAST_MASK2_47_32_SZ 16
+#define MRX_MCAST_CTRL_2_MSK 0x00000003
+#define MRX_MCAST_CTRL_2_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_2_SFT 0
+#define MRX_MCAST_CTRL_2_HI 1
+#define MRX_MCAST_CTRL_2_SZ 2
+#define MRX_MCAST_TB3_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB3_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB3_31_0_SFT 0
+#define MRX_MCAST_TB3_31_0_HI 31
+#define MRX_MCAST_TB3_31_0_SZ 32
+#define MRX_MCAST_TB3_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB3_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB3_47_32_SFT 0
+#define MRX_MCAST_TB3_47_32_HI 15
+#define MRX_MCAST_TB3_47_32_SZ 16
+#define MRX_MCAST_MASK3_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK3_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK3_31_0_SFT 0
+#define MRX_MCAST_MASK3_31_0_HI 31
+#define MRX_MCAST_MASK3_31_0_SZ 32
+#define MRX_MCAST_MASK3_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK3_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK3_47_32_SFT 0
+#define MRX_MCAST_MASK3_47_32_HI 15
+#define MRX_MCAST_MASK3_47_32_SZ 16
+#define MRX_MCAST_CTRL_3_MSK 0x00000003
+#define MRX_MCAST_CTRL_3_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_3_SFT 0
+#define MRX_MCAST_CTRL_3_HI 1
+#define MRX_MCAST_CTRL_3_SZ 2
+#define MRX_PHY_INFO_MSK 0xffffffff
+#define MRX_PHY_INFO_I_MSK 0x00000000
+#define MRX_PHY_INFO_SFT 0
+#define MRX_PHY_INFO_HI 31
+#define MRX_PHY_INFO_SZ 32
+#define DBG_BA_TYPE_MSK 0x0000003f
+#define DBG_BA_TYPE_I_MSK 0xffffffc0
+#define DBG_BA_TYPE_SFT 0
+#define DBG_BA_TYPE_HI 5
+#define DBG_BA_TYPE_SZ 6
+#define DBG_BA_SEQ_MSK 0x000fff00
+#define DBG_BA_SEQ_I_MSK 0xfff000ff
+#define DBG_BA_SEQ_SFT 8
+#define DBG_BA_SEQ_HI 19
+#define DBG_BA_SEQ_SZ 12
+#define MRX_FLT_TB0_MSK 0x00007fff
+#define MRX_FLT_TB0_I_MSK 0xffff8000
+#define MRX_FLT_TB0_SFT 0
+#define MRX_FLT_TB0_HI 14
+#define MRX_FLT_TB0_SZ 15
+#define MRX_FLT_TB1_MSK 0x00007fff
+#define MRX_FLT_TB1_I_MSK 0xffff8000
+#define MRX_FLT_TB1_SFT 0
+#define MRX_FLT_TB1_HI 14
+#define MRX_FLT_TB1_SZ 15
+#define MRX_FLT_TB2_MSK 0x00007fff
+#define MRX_FLT_TB2_I_MSK 0xffff8000
+#define MRX_FLT_TB2_SFT 0
+#define MRX_FLT_TB2_HI 14
+#define MRX_FLT_TB2_SZ 15
+#define MRX_FLT_TB3_MSK 0x00007fff
+#define MRX_FLT_TB3_I_MSK 0xffff8000
+#define MRX_FLT_TB3_SFT 0
+#define MRX_FLT_TB3_HI 14
+#define MRX_FLT_TB3_SZ 15
+#define MRX_FLT_TB4_MSK 0x00007fff
+#define MRX_FLT_TB4_I_MSK 0xffff8000
+#define MRX_FLT_TB4_SFT 0
+#define MRX_FLT_TB4_HI 14
+#define MRX_FLT_TB4_SZ 15
+#define MRX_FLT_TB5_MSK 0x00007fff
+#define MRX_FLT_TB5_I_MSK 0xffff8000
+#define MRX_FLT_TB5_SFT 0
+#define MRX_FLT_TB5_HI 14
+#define MRX_FLT_TB5_SZ 15
+#define MRX_FLT_TB6_MSK 0x00007fff
+#define MRX_FLT_TB6_I_MSK 0xffff8000
+#define MRX_FLT_TB6_SFT 0
+#define MRX_FLT_TB6_HI 14
+#define MRX_FLT_TB6_SZ 15
+#define MRX_FLT_TB7_MSK 0x00007fff
+#define MRX_FLT_TB7_I_MSK 0xffff8000
+#define MRX_FLT_TB7_SFT 0
+#define MRX_FLT_TB7_HI 14
+#define MRX_FLT_TB7_SZ 15
+#define MRX_FLT_TB8_MSK 0x00007fff
+#define MRX_FLT_TB8_I_MSK 0xffff8000
+#define MRX_FLT_TB8_SFT 0
+#define MRX_FLT_TB8_HI 14
+#define MRX_FLT_TB8_SZ 15
+#define MRX_FLT_TB9_MSK 0x00007fff
+#define MRX_FLT_TB9_I_MSK 0xffff8000
+#define MRX_FLT_TB9_SFT 0
+#define MRX_FLT_TB9_HI 14
+#define MRX_FLT_TB9_SZ 15
+#define MRX_FLT_TB10_MSK 0x00007fff
+#define MRX_FLT_TB10_I_MSK 0xffff8000
+#define MRX_FLT_TB10_SFT 0
+#define MRX_FLT_TB10_HI 14
+#define MRX_FLT_TB10_SZ 15
+#define MRX_FLT_TB11_MSK 0x00007fff
+#define MRX_FLT_TB11_I_MSK 0xffff8000
+#define MRX_FLT_TB11_SFT 0
+#define MRX_FLT_TB11_HI 14
+#define MRX_FLT_TB11_SZ 15
+#define MRX_FLT_TB12_MSK 0x00007fff
+#define MRX_FLT_TB12_I_MSK 0xffff8000
+#define MRX_FLT_TB12_SFT 0
+#define MRX_FLT_TB12_HI 14
+#define MRX_FLT_TB12_SZ 15
+#define MRX_FLT_TB13_MSK 0x00007fff
+#define MRX_FLT_TB13_I_MSK 0xffff8000
+#define MRX_FLT_TB13_SFT 0
+#define MRX_FLT_TB13_HI 14
+#define MRX_FLT_TB13_SZ 15
+#define MRX_FLT_TB14_MSK 0x00007fff
+#define MRX_FLT_TB14_I_MSK 0xffff8000
+#define MRX_FLT_TB14_SFT 0
+#define MRX_FLT_TB14_HI 14
+#define MRX_FLT_TB14_SZ 15
+#define MRX_FLT_TB15_MSK 0x00007fff
+#define MRX_FLT_TB15_I_MSK 0xffff8000
+#define MRX_FLT_TB15_SFT 0
+#define MRX_FLT_TB15_HI 14
+#define MRX_FLT_TB15_SZ 15
+#define MRX_FLT_EN0_MSK 0x0000ffff
+#define MRX_FLT_EN0_I_MSK 0xffff0000
+#define MRX_FLT_EN0_SFT 0
+#define MRX_FLT_EN0_HI 15
+#define MRX_FLT_EN0_SZ 16
+#define MRX_FLT_EN1_MSK 0x0000ffff
+#define MRX_FLT_EN1_I_MSK 0xffff0000
+#define MRX_FLT_EN1_SFT 0
+#define MRX_FLT_EN1_HI 15
+#define MRX_FLT_EN1_SZ 16
+#define MRX_FLT_EN2_MSK 0x0000ffff
+#define MRX_FLT_EN2_I_MSK 0xffff0000
+#define MRX_FLT_EN2_SFT 0
+#define MRX_FLT_EN2_HI 15
+#define MRX_FLT_EN2_SZ 16
+#define MRX_FLT_EN3_MSK 0x0000ffff
+#define MRX_FLT_EN3_I_MSK 0xffff0000
+#define MRX_FLT_EN3_SFT 0
+#define MRX_FLT_EN3_HI 15
+#define MRX_FLT_EN3_SZ 16
+#define MRX_FLT_EN4_MSK 0x0000ffff
+#define MRX_FLT_EN4_I_MSK 0xffff0000
+#define MRX_FLT_EN4_SFT 0
+#define MRX_FLT_EN4_HI 15
+#define MRX_FLT_EN4_SZ 16
+#define MRX_FLT_EN5_MSK 0x0000ffff
+#define MRX_FLT_EN5_I_MSK 0xffff0000
+#define MRX_FLT_EN5_SFT 0
+#define MRX_FLT_EN5_HI 15
+#define MRX_FLT_EN5_SZ 16
+#define MRX_FLT_EN6_MSK 0x0000ffff
+#define MRX_FLT_EN6_I_MSK 0xffff0000
+#define MRX_FLT_EN6_SFT 0
+#define MRX_FLT_EN6_HI 15
+#define MRX_FLT_EN6_SZ 16
+#define MRX_FLT_EN7_MSK 0x0000ffff
+#define MRX_FLT_EN7_I_MSK 0xffff0000
+#define MRX_FLT_EN7_SFT 0
+#define MRX_FLT_EN7_HI 15
+#define MRX_FLT_EN7_SZ 16
+#define MRX_FLT_EN8_MSK 0x0000ffff
+#define MRX_FLT_EN8_I_MSK 0xffff0000
+#define MRX_FLT_EN8_SFT 0
+#define MRX_FLT_EN8_HI 15
+#define MRX_FLT_EN8_SZ 16
+#define MRX_LEN_FLT_MSK 0x0000ffff
+#define MRX_LEN_FLT_I_MSK 0xffff0000
+#define MRX_LEN_FLT_SFT 0
+#define MRX_LEN_FLT_HI 15
+#define MRX_LEN_FLT_SZ 16
+#define RX_FLOW_DATA_MSK 0xffffffff
+#define RX_FLOW_DATA_I_MSK 0x00000000
+#define RX_FLOW_DATA_SFT 0
+#define RX_FLOW_DATA_HI 31
+#define RX_FLOW_DATA_SZ 32
+#define RX_FLOW_MNG_MSK 0x0000ffff
+#define RX_FLOW_MNG_I_MSK 0xffff0000
+#define RX_FLOW_MNG_SFT 0
+#define RX_FLOW_MNG_HI 15
+#define RX_FLOW_MNG_SZ 16
+#define RX_FLOW_CTRL_MSK 0x0000ffff
+#define RX_FLOW_CTRL_I_MSK 0xffff0000
+#define RX_FLOW_CTRL_SFT 0
+#define RX_FLOW_CTRL_HI 15
+#define RX_FLOW_CTRL_SZ 16
+#define MRX_STP_EN_MSK 0x00000001
+#define MRX_STP_EN_I_MSK 0xfffffffe
+#define MRX_STP_EN_SFT 0
+#define MRX_STP_EN_HI 0
+#define MRX_STP_EN_SZ 1
+#define MRX_STP_OFST_MSK 0x0000ff00
+#define MRX_STP_OFST_I_MSK 0xffff00ff
+#define MRX_STP_OFST_SFT 8
+#define MRX_STP_OFST_HI 15
+#define MRX_STP_OFST_SZ 8
+#define DBG_FF_FULL_MSK 0x0000ffff
+#define DBG_FF_FULL_I_MSK 0xffff0000
+#define DBG_FF_FULL_SFT 0
+#define DBG_FF_FULL_HI 15
+#define DBG_FF_FULL_SZ 16
+#define DBG_FF_FULL_CLR_MSK 0x80000000
+#define DBG_FF_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_FF_FULL_CLR_SFT 31
+#define DBG_FF_FULL_CLR_HI 31
+#define DBG_FF_FULL_CLR_SZ 1
+#define DBG_WFF_FULL_MSK 0x0000ffff
+#define DBG_WFF_FULL_I_MSK 0xffff0000
+#define DBG_WFF_FULL_SFT 0
+#define DBG_WFF_FULL_HI 15
+#define DBG_WFF_FULL_SZ 16
+#define DBG_WFF_FULL_CLR_MSK 0x80000000
+#define DBG_WFF_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_WFF_FULL_CLR_SFT 31
+#define DBG_WFF_FULL_CLR_HI 31
+#define DBG_WFF_FULL_CLR_SZ 1
+#define DBG_MB_FULL_MSK 0x0000ffff
+#define DBG_MB_FULL_I_MSK 0xffff0000
+#define DBG_MB_FULL_SFT 0
+#define DBG_MB_FULL_HI 15
+#define DBG_MB_FULL_SZ 16
+#define DBG_MB_FULL_CLR_MSK 0x80000000
+#define DBG_MB_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_MB_FULL_CLR_SFT 31
+#define DBG_MB_FULL_CLR_HI 31
+#define DBG_MB_FULL_CLR_SZ 1
+#define BA_CTRL_MSK 0x00000003
+#define BA_CTRL_I_MSK 0xfffffffc
+#define BA_CTRL_SFT 0
+#define BA_CTRL_HI 1
+#define BA_CTRL_SZ 2
+#define BA_DBG_EN_MSK 0x00000004
+#define BA_DBG_EN_I_MSK 0xfffffffb
+#define BA_DBG_EN_SFT 2
+#define BA_DBG_EN_HI 2
+#define BA_DBG_EN_SZ 1
+#define BA_AGRE_EN_MSK 0x00000008
+#define BA_AGRE_EN_I_MSK 0xfffffff7
+#define BA_AGRE_EN_SFT 3
+#define BA_AGRE_EN_HI 3
+#define BA_AGRE_EN_SZ 1
+#define BA_TA_31_0_MSK 0xffffffff
+#define BA_TA_31_0_I_MSK 0x00000000
+#define BA_TA_31_0_SFT 0
+#define BA_TA_31_0_HI 31
+#define BA_TA_31_0_SZ 32
+#define BA_TA_47_32_MSK 0x0000ffff
+#define BA_TA_47_32_I_MSK 0xffff0000
+#define BA_TA_47_32_SFT 0
+#define BA_TA_47_32_HI 15
+#define BA_TA_47_32_SZ 16
+#define BA_TID_MSK 0x0000000f
+#define BA_TID_I_MSK 0xfffffff0
+#define BA_TID_SFT 0
+#define BA_TID_HI 3
+#define BA_TID_SZ 4
+#define BA_ST_SEQ_MSK 0x00000fff
+#define BA_ST_SEQ_I_MSK 0xfffff000
+#define BA_ST_SEQ_SFT 0
+#define BA_ST_SEQ_HI 11
+#define BA_ST_SEQ_SZ 12
+#define BA_SB0_MSK 0xffffffff
+#define BA_SB0_I_MSK 0x00000000
+#define BA_SB0_SFT 0
+#define BA_SB0_HI 31
+#define BA_SB0_SZ 32
+#define BA_SB1_MSK 0xffffffff
+#define BA_SB1_I_MSK 0x00000000
+#define BA_SB1_SFT 0
+#define BA_SB1_HI 31
+#define BA_SB1_SZ 32
+#define MRX_WD_MSK 0x0001ffff
+#define MRX_WD_I_MSK 0xfffe0000
+#define MRX_WD_SFT 0
+#define MRX_WD_HI 16
+#define MRX_WD_SZ 17
+#define ACK_GEN_EN_MSK 0x00000001
+#define ACK_GEN_EN_I_MSK 0xfffffffe
+#define ACK_GEN_EN_SFT 0
+#define ACK_GEN_EN_HI 0
+#define ACK_GEN_EN_SZ 1
+#define BA_GEN_EN_MSK 0x00000002
+#define BA_GEN_EN_I_MSK 0xfffffffd
+#define BA_GEN_EN_SFT 1
+#define BA_GEN_EN_HI 1
+#define BA_GEN_EN_SZ 1
+#define ACK_GEN_DUR_MSK 0x0000ffff
+#define ACK_GEN_DUR_I_MSK 0xffff0000
+#define ACK_GEN_DUR_SFT 0
+#define ACK_GEN_DUR_HI 15
+#define ACK_GEN_DUR_SZ 16
+#define ACK_GEN_INFO_MSK 0x003f0000
+#define ACK_GEN_INFO_I_MSK 0xffc0ffff
+#define ACK_GEN_INFO_SFT 16
+#define ACK_GEN_INFO_HI 21
+#define ACK_GEN_INFO_SZ 6
+#define ACK_GEN_RA_31_0_MSK 0xffffffff
+#define ACK_GEN_RA_31_0_I_MSK 0x00000000
+#define ACK_GEN_RA_31_0_SFT 0
+#define ACK_GEN_RA_31_0_HI 31
+#define ACK_GEN_RA_31_0_SZ 32
+#define ACK_GEN_RA_47_32_MSK 0x0000ffff
+#define ACK_GEN_RA_47_32_I_MSK 0xffff0000
+#define ACK_GEN_RA_47_32_SFT 0
+#define ACK_GEN_RA_47_32_HI 15
+#define ACK_GEN_RA_47_32_SZ 16
+#define MIB_LEN_FAIL_MSK 0x0000ffff
+#define MIB_LEN_FAIL_I_MSK 0xffff0000
+#define MIB_LEN_FAIL_SFT 0
+#define MIB_LEN_FAIL_HI 15
+#define MIB_LEN_FAIL_SZ 16
+#define TRAP_HW_ID_MSK 0x0000000f
+#define TRAP_HW_ID_I_MSK 0xfffffff0
+#define TRAP_HW_ID_SFT 0
+#define TRAP_HW_ID_HI 3
+#define TRAP_HW_ID_SZ 4
+#define ID_IN_USE_MSK 0x000000ff
+#define ID_IN_USE_I_MSK 0xffffff00
+#define ID_IN_USE_SFT 0
+#define ID_IN_USE_HI 7
+#define ID_IN_USE_SZ 8
+#define MRX_ERR_MSK 0xffffffff
+#define MRX_ERR_I_MSK 0x00000000
+#define MRX_ERR_SFT 0
+#define MRX_ERR_HI 31
+#define MRX_ERR_SZ 32
+#define W0_T0_SEQ_MSK 0x0000ffff
+#define W0_T0_SEQ_I_MSK 0xffff0000
+#define W0_T0_SEQ_SFT 0
+#define W0_T0_SEQ_HI 15
+#define W0_T0_SEQ_SZ 16
+#define W0_T1_SEQ_MSK 0x0000ffff
+#define W0_T1_SEQ_I_MSK 0xffff0000
+#define W0_T1_SEQ_SFT 0
+#define W0_T1_SEQ_HI 15
+#define W0_T1_SEQ_SZ 16
+#define W0_T2_SEQ_MSK 0x0000ffff
+#define W0_T2_SEQ_I_MSK 0xffff0000
+#define W0_T2_SEQ_SFT 0
+#define W0_T2_SEQ_HI 15
+#define W0_T2_SEQ_SZ 16
+#define W0_T3_SEQ_MSK 0x0000ffff
+#define W0_T3_SEQ_I_MSK 0xffff0000
+#define W0_T3_SEQ_SFT 0
+#define W0_T3_SEQ_HI 15
+#define W0_T3_SEQ_SZ 16
+#define W0_T4_SEQ_MSK 0x0000ffff
+#define W0_T4_SEQ_I_MSK 0xffff0000
+#define W0_T4_SEQ_SFT 0
+#define W0_T4_SEQ_HI 15
+#define W0_T4_SEQ_SZ 16
+#define W0_T5_SEQ_MSK 0x0000ffff
+#define W0_T5_SEQ_I_MSK 0xffff0000
+#define W0_T5_SEQ_SFT 0
+#define W0_T5_SEQ_HI 15
+#define W0_T5_SEQ_SZ 16
+#define W0_T6_SEQ_MSK 0x0000ffff
+#define W0_T6_SEQ_I_MSK 0xffff0000
+#define W0_T6_SEQ_SFT 0
+#define W0_T6_SEQ_HI 15
+#define W0_T6_SEQ_SZ 16
+#define W0_T7_SEQ_MSK 0x0000ffff
+#define W0_T7_SEQ_I_MSK 0xffff0000
+#define W0_T7_SEQ_SFT 0
+#define W0_T7_SEQ_HI 15
+#define W0_T7_SEQ_SZ 16
+#define W1_T0_SEQ_MSK 0x0000ffff
+#define W1_T0_SEQ_I_MSK 0xffff0000
+#define W1_T0_SEQ_SFT 0
+#define W1_T0_SEQ_HI 15
+#define W1_T0_SEQ_SZ 16
+#define W1_T1_SEQ_MSK 0x0000ffff
+#define W1_T1_SEQ_I_MSK 0xffff0000
+#define W1_T1_SEQ_SFT 0
+#define W1_T1_SEQ_HI 15
+#define W1_T1_SEQ_SZ 16
+#define W1_T2_SEQ_MSK 0x0000ffff
+#define W1_T2_SEQ_I_MSK 0xffff0000
+#define W1_T2_SEQ_SFT 0
+#define W1_T2_SEQ_HI 15
+#define W1_T2_SEQ_SZ 16
+#define W1_T3_SEQ_MSK 0x0000ffff
+#define W1_T3_SEQ_I_MSK 0xffff0000
+#define W1_T3_SEQ_SFT 0
+#define W1_T3_SEQ_HI 15
+#define W1_T3_SEQ_SZ 16
+#define W1_T4_SEQ_MSK 0x0000ffff
+#define W1_T4_SEQ_I_MSK 0xffff0000
+#define W1_T4_SEQ_SFT 0
+#define W1_T4_SEQ_HI 15
+#define W1_T4_SEQ_SZ 16
+#define W1_T5_SEQ_MSK 0x0000ffff
+#define W1_T5_SEQ_I_MSK 0xffff0000
+#define W1_T5_SEQ_SFT 0
+#define W1_T5_SEQ_HI 15
+#define W1_T5_SEQ_SZ 16
+#define W1_T6_SEQ_MSK 0x0000ffff
+#define W1_T6_SEQ_I_MSK 0xffff0000
+#define W1_T6_SEQ_SFT 0
+#define W1_T6_SEQ_HI 15
+#define W1_T6_SEQ_SZ 16
+#define W1_T7_SEQ_MSK 0x0000ffff
+#define W1_T7_SEQ_I_MSK 0xffff0000
+#define W1_T7_SEQ_SFT 0
+#define W1_T7_SEQ_HI 15
+#define W1_T7_SEQ_SZ 16
+#define ADDR1A_SEL_MSK 0x00000003
+#define ADDR1A_SEL_I_MSK 0xfffffffc
+#define ADDR1A_SEL_SFT 0
+#define ADDR1A_SEL_HI 1
+#define ADDR1A_SEL_SZ 2
+#define ADDR2A_SEL_MSK 0x0000000c
+#define ADDR2A_SEL_I_MSK 0xfffffff3
+#define ADDR2A_SEL_SFT 2
+#define ADDR2A_SEL_HI 3
+#define ADDR2A_SEL_SZ 2
+#define ADDR3A_SEL_MSK 0x00000030
+#define ADDR3A_SEL_I_MSK 0xffffffcf
+#define ADDR3A_SEL_SFT 4
+#define ADDR3A_SEL_HI 5
+#define ADDR3A_SEL_SZ 2
+#define ADDR1B_SEL_MSK 0x000000c0
+#define ADDR1B_SEL_I_MSK 0xffffff3f
+#define ADDR1B_SEL_SFT 6
+#define ADDR1B_SEL_HI 7
+#define ADDR1B_SEL_SZ 2
+#define ADDR2B_SEL_MSK 0x00000300
+#define ADDR2B_SEL_I_MSK 0xfffffcff
+#define ADDR2B_SEL_SFT 8
+#define ADDR2B_SEL_HI 9
+#define ADDR2B_SEL_SZ 2
+#define ADDR3B_SEL_MSK 0x00000c00
+#define ADDR3B_SEL_I_MSK 0xfffff3ff
+#define ADDR3B_SEL_SFT 10
+#define ADDR3B_SEL_HI 11
+#define ADDR3B_SEL_SZ 2
+#define ADDR3C_SEL_MSK 0x00003000
+#define ADDR3C_SEL_I_MSK 0xffffcfff
+#define ADDR3C_SEL_SFT 12
+#define ADDR3C_SEL_HI 13
+#define ADDR3C_SEL_SZ 2
+#define FRM_CTRL_MSK 0x0000003f
+#define FRM_CTRL_I_MSK 0xffffffc0
+#define FRM_CTRL_SFT 0
+#define FRM_CTRL_HI 5
+#define FRM_CTRL_SZ 6
+#define CSR_PHY_INFO_MSK 0x00007fff
+#define CSR_PHY_INFO_I_MSK 0xffff8000
+#define CSR_PHY_INFO_SFT 0
+#define CSR_PHY_INFO_HI 14
+#define CSR_PHY_INFO_SZ 15
+#define AMPDU_SIG_MSK 0x000000ff
+#define AMPDU_SIG_I_MSK 0xffffff00
+#define AMPDU_SIG_SFT 0
+#define AMPDU_SIG_HI 7
+#define AMPDU_SIG_SZ 8
+#define MIB_AMPDU_MSK 0xffffffff
+#define MIB_AMPDU_I_MSK 0x00000000
+#define MIB_AMPDU_SFT 0
+#define MIB_AMPDU_HI 31
+#define MIB_AMPDU_SZ 32
+#define LEN_FLT_MSK 0x0000ffff
+#define LEN_FLT_I_MSK 0xffff0000
+#define LEN_FLT_SFT 0
+#define LEN_FLT_HI 15
+#define LEN_FLT_SZ 16
+#define MIB_DELIMITER_MSK 0x0000ffff
+#define MIB_DELIMITER_I_MSK 0xffff0000
+#define MIB_DELIMITER_SFT 0
+#define MIB_DELIMITER_HI 15
+#define MIB_DELIMITER_SZ 16
+#define MTX_INT_Q0_Q_EMPTY_MSK 0x00010000
+#define MTX_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
+#define MTX_INT_Q0_Q_EMPTY_SFT 16
+#define MTX_INT_Q0_Q_EMPTY_HI 16
+#define MTX_INT_Q0_Q_EMPTY_SZ 1
+#define MTX_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
+#define MTX_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
+#define MTX_INT_Q0_TXOP_RUNOUT_SFT 17
+#define MTX_INT_Q0_TXOP_RUNOUT_HI 17
+#define MTX_INT_Q0_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q1_Q_EMPTY_MSK 0x00040000
+#define MTX_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
+#define MTX_INT_Q1_Q_EMPTY_SFT 18
+#define MTX_INT_Q1_Q_EMPTY_HI 18
+#define MTX_INT_Q1_Q_EMPTY_SZ 1
+#define MTX_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
+#define MTX_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
+#define MTX_INT_Q1_TXOP_RUNOUT_SFT 19
+#define MTX_INT_Q1_TXOP_RUNOUT_HI 19
+#define MTX_INT_Q1_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q2_Q_EMPTY_MSK 0x00100000
+#define MTX_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
+#define MTX_INT_Q2_Q_EMPTY_SFT 20
+#define MTX_INT_Q2_Q_EMPTY_HI 20
+#define MTX_INT_Q2_Q_EMPTY_SZ 1
+#define MTX_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
+#define MTX_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
+#define MTX_INT_Q2_TXOP_RUNOUT_SFT 21
+#define MTX_INT_Q2_TXOP_RUNOUT_HI 21
+#define MTX_INT_Q2_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q3_Q_EMPTY_MSK 0x00400000
+#define MTX_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
+#define MTX_INT_Q3_Q_EMPTY_SFT 22
+#define MTX_INT_Q3_Q_EMPTY_HI 22
+#define MTX_INT_Q3_Q_EMPTY_SZ 1
+#define MTX_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
+#define MTX_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
+#define MTX_INT_Q3_TXOP_RUNOUT_SFT 23
+#define MTX_INT_Q3_TXOP_RUNOUT_HI 23
+#define MTX_INT_Q3_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q4_Q_EMPTY_MSK 0x01000000
+#define MTX_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
+#define MTX_INT_Q4_Q_EMPTY_SFT 24
+#define MTX_INT_Q4_Q_EMPTY_HI 24
+#define MTX_INT_Q4_Q_EMPTY_SZ 1
+#define MTX_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
+#define MTX_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
+#define MTX_INT_Q4_TXOP_RUNOUT_SFT 25
+#define MTX_INT_Q4_TXOP_RUNOUT_HI 25
+#define MTX_INT_Q4_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q0_Q_EMPTY_MSK 0x00010000
+#define MTX_EN_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
+#define MTX_EN_INT_Q0_Q_EMPTY_SFT 16
+#define MTX_EN_INT_Q0_Q_EMPTY_HI 16
+#define MTX_EN_INT_Q0_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_SFT 17
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_HI 17
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q1_Q_EMPTY_MSK 0x00040000
+#define MTX_EN_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
+#define MTX_EN_INT_Q1_Q_EMPTY_SFT 18
+#define MTX_EN_INT_Q1_Q_EMPTY_HI 18
+#define MTX_EN_INT_Q1_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_SFT 19
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_HI 19
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q2_Q_EMPTY_MSK 0x00100000
+#define MTX_EN_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
+#define MTX_EN_INT_Q2_Q_EMPTY_SFT 20
+#define MTX_EN_INT_Q2_Q_EMPTY_HI 20
+#define MTX_EN_INT_Q2_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_SFT 21
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_HI 21
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q3_Q_EMPTY_MSK 0x00400000
+#define MTX_EN_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
+#define MTX_EN_INT_Q3_Q_EMPTY_SFT 22
+#define MTX_EN_INT_Q3_Q_EMPTY_HI 22
+#define MTX_EN_INT_Q3_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_SFT 23
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_HI 23
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q4_Q_EMPTY_MSK 0x01000000
+#define MTX_EN_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
+#define MTX_EN_INT_Q4_Q_EMPTY_SFT 24
+#define MTX_EN_INT_Q4_Q_EMPTY_HI 24
+#define MTX_EN_INT_Q4_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_SFT 25
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_HI 25
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_SZ 1
+#define MTX_MTX2PHY_SLOW_MSK 0x00000001
+#define MTX_MTX2PHY_SLOW_I_MSK 0xfffffffe
+#define MTX_MTX2PHY_SLOW_SFT 0
+#define MTX_MTX2PHY_SLOW_HI 0
+#define MTX_MTX2PHY_SLOW_SZ 1
+#define MTX_M2M_SLOW_PRD_MSK 0x0000000e
+#define MTX_M2M_SLOW_PRD_I_MSK 0xfffffff1
+#define MTX_M2M_SLOW_PRD_SFT 1
+#define MTX_M2M_SLOW_PRD_HI 3
+#define MTX_M2M_SLOW_PRD_SZ 3
+#define MTX_AMPDU_CRC_AUTO_MSK 0x00000020
+#define MTX_AMPDU_CRC_AUTO_I_MSK 0xffffffdf
+#define MTX_AMPDU_CRC_AUTO_SFT 5
+#define MTX_AMPDU_CRC_AUTO_HI 5
+#define MTX_AMPDU_CRC_AUTO_SZ 1
+#define MTX_FAST_RSP_MODE_MSK 0x00000040
+#define MTX_FAST_RSP_MODE_I_MSK 0xffffffbf
+#define MTX_FAST_RSP_MODE_SFT 6
+#define MTX_FAST_RSP_MODE_HI 6
+#define MTX_FAST_RSP_MODE_SZ 1
+#define MTX_RAW_DATA_MODE_MSK 0x00000080
+#define MTX_RAW_DATA_MODE_I_MSK 0xffffff7f
+#define MTX_RAW_DATA_MODE_SFT 7
+#define MTX_RAW_DATA_MODE_HI 7
+#define MTX_RAW_DATA_MODE_SZ 1
+#define MTX_ACK_DUR0_MSK 0x00000100
+#define MTX_ACK_DUR0_I_MSK 0xfffffeff
+#define MTX_ACK_DUR0_SFT 8
+#define MTX_ACK_DUR0_HI 8
+#define MTX_ACK_DUR0_SZ 1
+#define MTX_TSF_AUTO_BCN_MSK 0x00000400
+#define MTX_TSF_AUTO_BCN_I_MSK 0xfffffbff
+#define MTX_TSF_AUTO_BCN_SFT 10
+#define MTX_TSF_AUTO_BCN_HI 10
+#define MTX_TSF_AUTO_BCN_SZ 1
+#define MTX_TSF_AUTO_MISC_MSK 0x00000800
+#define MTX_TSF_AUTO_MISC_I_MSK 0xfffff7ff
+#define MTX_TSF_AUTO_MISC_SFT 11
+#define MTX_TSF_AUTO_MISC_HI 11
+#define MTX_TSF_AUTO_MISC_SZ 1
+#define MTX_FORCE_CS_IDLE_MSK 0x00001000
+#define MTX_FORCE_CS_IDLE_I_MSK 0xffffefff
+#define MTX_FORCE_CS_IDLE_SFT 12
+#define MTX_FORCE_CS_IDLE_HI 12
+#define MTX_FORCE_CS_IDLE_SZ 1
+#define MTX_FORCE_BKF_RXEN0_MSK 0x00002000
+#define MTX_FORCE_BKF_RXEN0_I_MSK 0xffffdfff
+#define MTX_FORCE_BKF_RXEN0_SFT 13
+#define MTX_FORCE_BKF_RXEN0_HI 13
+#define MTX_FORCE_BKF_RXEN0_SZ 1
+#define MTX_FORCE_DMA_RXEN0_MSK 0x00004000
+#define MTX_FORCE_DMA_RXEN0_I_MSK 0xffffbfff
+#define MTX_FORCE_DMA_RXEN0_SFT 14
+#define MTX_FORCE_DMA_RXEN0_HI 14
+#define MTX_FORCE_DMA_RXEN0_SZ 1
+#define MTX_FORCE_RXEN0_MSK 0x00008000
+#define MTX_FORCE_RXEN0_I_MSK 0xffff7fff
+#define MTX_FORCE_RXEN0_SFT 15
+#define MTX_FORCE_RXEN0_HI 15
+#define MTX_FORCE_RXEN0_SZ 1
+#define MTX_HALT_Q_MB_MSK 0x003f0000
+#define MTX_HALT_Q_MB_I_MSK 0xffc0ffff
+#define MTX_HALT_Q_MB_SFT 16
+#define MTX_HALT_Q_MB_HI 21
+#define MTX_HALT_Q_MB_SZ 6
+#define MTX_CTS_SET_DIF_MSK 0x00400000
+#define MTX_CTS_SET_DIF_I_MSK 0xffbfffff
+#define MTX_CTS_SET_DIF_SFT 22
+#define MTX_CTS_SET_DIF_HI 22
+#define MTX_CTS_SET_DIF_SZ 1
+#define MTX_AMPDU_SET_DIF_MSK 0x00800000
+#define MTX_AMPDU_SET_DIF_I_MSK 0xff7fffff
+#define MTX_AMPDU_SET_DIF_SFT 23
+#define MTX_AMPDU_SET_DIF_HI 23
+#define MTX_AMPDU_SET_DIF_SZ 1
+#define MTX_EDCCA_TOUT_MSK 0x000003ff
+#define MTX_EDCCA_TOUT_I_MSK 0xfffffc00
+#define MTX_EDCCA_TOUT_SFT 0
+#define MTX_EDCCA_TOUT_HI 9
+#define MTX_EDCCA_TOUT_SZ 10
+#define MTX_INT_BCN_MSK 0x00000002
+#define MTX_INT_BCN_I_MSK 0xfffffffd
+#define MTX_INT_BCN_SFT 1
+#define MTX_INT_BCN_HI 1
+#define MTX_INT_BCN_SZ 1
+#define MTX_INT_DTIM_MSK 0x00000008
+#define MTX_INT_DTIM_I_MSK 0xfffffff7
+#define MTX_INT_DTIM_SFT 3
+#define MTX_INT_DTIM_HI 3
+#define MTX_INT_DTIM_SZ 1
+#define MTX_EN_INT_BCN_MSK 0x00000002
+#define MTX_EN_INT_BCN_I_MSK 0xfffffffd
+#define MTX_EN_INT_BCN_SFT 1
+#define MTX_EN_INT_BCN_HI 1
+#define MTX_EN_INT_BCN_SZ 1
+#define MTX_EN_INT_DTIM_MSK 0x00000008
+#define MTX_EN_INT_DTIM_I_MSK 0xfffffff7
+#define MTX_EN_INT_DTIM_SFT 3
+#define MTX_EN_INT_DTIM_HI 3
+#define MTX_EN_INT_DTIM_SZ 1
+#define MTX_BCN_TIMER_EN_MSK 0x00000001
+#define MTX_BCN_TIMER_EN_I_MSK 0xfffffffe
+#define MTX_BCN_TIMER_EN_SFT 0
+#define MTX_BCN_TIMER_EN_HI 0
+#define MTX_BCN_TIMER_EN_SZ 1
+#define MTX_TIME_STAMP_AUTO_FILL_MSK 0x00000002
+#define MTX_TIME_STAMP_AUTO_FILL_I_MSK 0xfffffffd
+#define MTX_TIME_STAMP_AUTO_FILL_SFT 1
+#define MTX_TIME_STAMP_AUTO_FILL_HI 1
+#define MTX_TIME_STAMP_AUTO_FILL_SZ 1
+#define MTX_TSF_TIMER_EN_MSK 0x00000020
+#define MTX_TSF_TIMER_EN_I_MSK 0xffffffdf
+#define MTX_TSF_TIMER_EN_SFT 5
+#define MTX_TSF_TIMER_EN_HI 5
+#define MTX_TSF_TIMER_EN_SZ 1
+#define MTX_HALT_MNG_UNTIL_DTIM_MSK 0x00000040
+#define MTX_HALT_MNG_UNTIL_DTIM_I_MSK 0xffffffbf
+#define MTX_HALT_MNG_UNTIL_DTIM_SFT 6
+#define MTX_HALT_MNG_UNTIL_DTIM_HI 6
+#define MTX_HALT_MNG_UNTIL_DTIM_SZ 1
+#define MTX_INT_DTIM_NUM_MSK 0x0000ff00
+#define MTX_INT_DTIM_NUM_I_MSK 0xffff00ff
+#define MTX_INT_DTIM_NUM_SFT 8
+#define MTX_INT_DTIM_NUM_HI 15
+#define MTX_INT_DTIM_NUM_SZ 8
+#define MTX_AUTO_FLUSH_Q4_MSK 0x00010000
+#define MTX_AUTO_FLUSH_Q4_I_MSK 0xfffeffff
+#define MTX_AUTO_FLUSH_Q4_SFT 16
+#define MTX_AUTO_FLUSH_Q4_HI 16
+#define MTX_AUTO_FLUSH_Q4_SZ 1
+#define MTX_BCN_PKTID_CH_LOCK_MSK 0x00000001
+#define MTX_BCN_PKTID_CH_LOCK_I_MSK 0xfffffffe
+#define MTX_BCN_PKTID_CH_LOCK_SFT 0
+#define MTX_BCN_PKTID_CH_LOCK_HI 0
+#define MTX_BCN_PKTID_CH_LOCK_SZ 1
+#define MTX_BCN_CFG_VLD_MSK 0x00000006
+#define MTX_BCN_CFG_VLD_I_MSK 0xfffffff9
+#define MTX_BCN_CFG_VLD_SFT 1
+#define MTX_BCN_CFG_VLD_HI 2
+#define MTX_BCN_CFG_VLD_SZ 2
+#define MTX_AUTO_BCN_ONGOING_MSK 0x00000008
+#define MTX_AUTO_BCN_ONGOING_I_MSK 0xfffffff7
+#define MTX_AUTO_BCN_ONGOING_SFT 3
+#define MTX_AUTO_BCN_ONGOING_HI 3
+#define MTX_AUTO_BCN_ONGOING_SZ 1
+#define MTX_BCN_TIMER_MSK 0xffff0000
+#define MTX_BCN_TIMER_I_MSK 0x0000ffff
+#define MTX_BCN_TIMER_SFT 16
+#define MTX_BCN_TIMER_HI 31
+#define MTX_BCN_TIMER_SZ 16
+#define MTX_BCN_PERIOD_MSK 0x0000ffff
+#define MTX_BCN_PERIOD_I_MSK 0xffff0000
+#define MTX_BCN_PERIOD_SFT 0
+#define MTX_BCN_PERIOD_HI 15
+#define MTX_BCN_PERIOD_SZ 16
+#define MTX_DTIM_NUM_MSK 0xff000000
+#define MTX_DTIM_NUM_I_MSK 0x00ffffff
+#define MTX_DTIM_NUM_SFT 24
+#define MTX_DTIM_NUM_HI 31
+#define MTX_DTIM_NUM_SZ 8
+#define MTX_BCN_TSF_L_MSK 0xffffffff
+#define MTX_BCN_TSF_L_I_MSK 0x00000000
+#define MTX_BCN_TSF_L_SFT 0
+#define MTX_BCN_TSF_L_HI 31
+#define MTX_BCN_TSF_L_SZ 32
+#define MTX_BCN_TSF_U_MSK 0xffffffff
+#define MTX_BCN_TSF_U_I_MSK 0x00000000
+#define MTX_BCN_TSF_U_SFT 0
+#define MTX_BCN_TSF_U_HI 31
+#define MTX_BCN_TSF_U_SZ 32
+#define MTX_BCN_PKT_ID0_MSK 0x0000007f
+#define MTX_BCN_PKT_ID0_I_MSK 0xffffff80
+#define MTX_BCN_PKT_ID0_SFT 0
+#define MTX_BCN_PKT_ID0_HI 6
+#define MTX_BCN_PKT_ID0_SZ 7
+#define MTX_DTIM_OFST0_MSK 0x03ff0000
+#define MTX_DTIM_OFST0_I_MSK 0xfc00ffff
+#define MTX_DTIM_OFST0_SFT 16
+#define MTX_DTIM_OFST0_HI 25
+#define MTX_DTIM_OFST0_SZ 10
+#define MTX_BCN_PKT_ID1_MSK 0x0000007f
+#define MTX_BCN_PKT_ID1_I_MSK 0xffffff80
+#define MTX_BCN_PKT_ID1_SFT 0
+#define MTX_BCN_PKT_ID1_HI 6
+#define MTX_BCN_PKT_ID1_SZ 7
+#define MTX_DTIM_OFST1_MSK 0x03ff0000
+#define MTX_DTIM_OFST1_I_MSK 0xfc00ffff
+#define MTX_DTIM_OFST1_SFT 16
+#define MTX_DTIM_OFST1_HI 25
+#define MTX_DTIM_OFST1_SZ 10
+#define MTX_CCA_MSK 0x00000001
+#define MTX_CCA_I_MSK 0xfffffffe
+#define MTX_CCA_SFT 0
+#define MTX_CCA_HI 0
+#define MTX_CCA_SZ 1
+#define MRX_CCA_MSK 0x00000002
+#define MRX_CCA_I_MSK 0xfffffffd
+#define MRX_CCA_SFT 1
+#define MRX_CCA_HI 1
+#define MRX_CCA_SZ 1
+#define MTX_DMA_FSM_MSK 0x0000001c
+#define MTX_DMA_FSM_I_MSK 0xffffffe3
+#define MTX_DMA_FSM_SFT 2
+#define MTX_DMA_FSM_HI 4
+#define MTX_DMA_FSM_SZ 3
+#define CH_ST_FSM_MSK 0x000000e0
+#define CH_ST_FSM_I_MSK 0xffffff1f
+#define CH_ST_FSM_SFT 5
+#define CH_ST_FSM_HI 7
+#define CH_ST_FSM_SZ 3
+#define MTX_GNT_LOCK_MSK 0x00000100
+#define MTX_GNT_LOCK_I_MSK 0xfffffeff
+#define MTX_GNT_LOCK_SFT 8
+#define MTX_GNT_LOCK_HI 8
+#define MTX_GNT_LOCK_SZ 1
+#define MTX_DMA_REQ_MSK 0x00000200
+#define MTX_DMA_REQ_I_MSK 0xfffffdff
+#define MTX_DMA_REQ_SFT 9
+#define MTX_DMA_REQ_HI 9
+#define MTX_DMA_REQ_SZ 1
+#define MTX_Q_REQ_MSK 0x00000400
+#define MTX_Q_REQ_I_MSK 0xfffffbff
+#define MTX_Q_REQ_SFT 10
+#define MTX_Q_REQ_HI 10
+#define MTX_Q_REQ_SZ 1
+#define MTX_TX_EN_MSK 0x00000800
+#define MTX_TX_EN_I_MSK 0xfffff7ff
+#define MTX_TX_EN_SFT 11
+#define MTX_TX_EN_HI 11
+#define MTX_TX_EN_SZ 1
+#define MRX_RX_EN_MSK 0x00001000
+#define MRX_RX_EN_I_MSK 0xffffefff
+#define MRX_RX_EN_SFT 12
+#define MRX_RX_EN_HI 12
+#define MRX_RX_EN_SZ 1
+#define DBG_PRTC_PRD_MSK 0x00002000
+#define DBG_PRTC_PRD_I_MSK 0xffffdfff
+#define DBG_PRTC_PRD_SFT 13
+#define DBG_PRTC_PRD_HI 13
+#define DBG_PRTC_PRD_SZ 1
+#define DBG_DMA_RDY_MSK 0x00004000
+#define DBG_DMA_RDY_I_MSK 0xffffbfff
+#define DBG_DMA_RDY_SFT 14
+#define DBG_DMA_RDY_HI 14
+#define DBG_DMA_RDY_SZ 1
+#define DBG_WAIT_RSP_MSK 0x00008000
+#define DBG_WAIT_RSP_I_MSK 0xffff7fff
+#define DBG_WAIT_RSP_SFT 15
+#define DBG_WAIT_RSP_HI 15
+#define DBG_WAIT_RSP_SZ 1
+#define DBG_CFRM_BUSY_MSK 0x00010000
+#define DBG_CFRM_BUSY_I_MSK 0xfffeffff
+#define DBG_CFRM_BUSY_SFT 16
+#define DBG_CFRM_BUSY_HI 16
+#define DBG_CFRM_BUSY_SZ 1
+#define DBG_RST_MSK 0x00000001
+#define DBG_RST_I_MSK 0xfffffffe
+#define DBG_RST_SFT 0
+#define DBG_RST_HI 0
+#define DBG_RST_SZ 1
+#define DBG_MODE_MSK 0x00000002
+#define DBG_MODE_I_MSK 0xfffffffd
+#define DBG_MODE_SFT 1
+#define DBG_MODE_HI 1
+#define DBG_MODE_SZ 1
+#define MB_REQ_DUR_MSK 0x0000ffff
+#define MB_REQ_DUR_I_MSK 0xffff0000
+#define MB_REQ_DUR_SFT 0
+#define MB_REQ_DUR_HI 15
+#define MB_REQ_DUR_SZ 16
+#define RX_EN_DUR_MSK 0xffff0000
+#define RX_EN_DUR_I_MSK 0x0000ffff
+#define RX_EN_DUR_SFT 16
+#define RX_EN_DUR_HI 31
+#define RX_EN_DUR_SZ 16
+#define RX_CS_DUR_MSK 0x0000ffff
+#define RX_CS_DUR_I_MSK 0xffff0000
+#define RX_CS_DUR_SFT 0
+#define RX_CS_DUR_HI 15
+#define RX_CS_DUR_SZ 16
+#define TX_CCA_DUR_MSK 0xffff0000
+#define TX_CCA_DUR_I_MSK 0x0000ffff
+#define TX_CCA_DUR_SFT 16
+#define TX_CCA_DUR_HI 31
+#define TX_CCA_DUR_SZ 16
+#define Q_REQ_DUR_MSK 0x0000ffff
+#define Q_REQ_DUR_I_MSK 0xffff0000
+#define Q_REQ_DUR_SFT 0
+#define Q_REQ_DUR_HI 15
+#define Q_REQ_DUR_SZ 16
+#define CH_STA0_DUR_MSK 0xffff0000
+#define CH_STA0_DUR_I_MSK 0x0000ffff
+#define CH_STA0_DUR_SFT 16
+#define CH_STA0_DUR_HI 31
+#define CH_STA0_DUR_SZ 16
+#define MTX_DUR_RSP_TOUT_B_MSK 0x000000ff
+#define MTX_DUR_RSP_TOUT_B_I_MSK 0xffffff00
+#define MTX_DUR_RSP_TOUT_B_SFT 0
+#define MTX_DUR_RSP_TOUT_B_HI 7
+#define MTX_DUR_RSP_TOUT_B_SZ 8
+#define MTX_DUR_RSP_TOUT_G_MSK 0x0000ff00
+#define MTX_DUR_RSP_TOUT_G_I_MSK 0xffff00ff
+#define MTX_DUR_RSP_TOUT_G_SFT 8
+#define MTX_DUR_RSP_TOUT_G_HI 15
+#define MTX_DUR_RSP_TOUT_G_SZ 8
+#define MTX_DUR_RSP_SIFS_MSK 0x000000ff
+#define MTX_DUR_RSP_SIFS_I_MSK 0xffffff00
+#define MTX_DUR_RSP_SIFS_SFT 0
+#define MTX_DUR_RSP_SIFS_HI 7
+#define MTX_DUR_RSP_SIFS_SZ 8
+#define MTX_DUR_BURST_SIFS_MSK 0x0000ff00
+#define MTX_DUR_BURST_SIFS_I_MSK 0xffff00ff
+#define MTX_DUR_BURST_SIFS_SFT 8
+#define MTX_DUR_BURST_SIFS_HI 15
+#define MTX_DUR_BURST_SIFS_SZ 8
+#define MTX_DUR_SLOT_MSK 0x003f0000
+#define MTX_DUR_SLOT_I_MSK 0xffc0ffff
+#define MTX_DUR_SLOT_SFT 16
+#define MTX_DUR_SLOT_HI 21
+#define MTX_DUR_SLOT_SZ 6
+#define MTX_DUR_RSP_EIFS_MSK 0xffc00000
+#define MTX_DUR_RSP_EIFS_I_MSK 0x003fffff
+#define MTX_DUR_RSP_EIFS_SFT 22
+#define MTX_DUR_RSP_EIFS_HI 31
+#define MTX_DUR_RSP_EIFS_SZ 10
+#define MTX_DUR_RSP_SIFS_G_MSK 0x000000ff
+#define MTX_DUR_RSP_SIFS_G_I_MSK 0xffffff00
+#define MTX_DUR_RSP_SIFS_G_SFT 0
+#define MTX_DUR_RSP_SIFS_G_HI 7
+#define MTX_DUR_RSP_SIFS_G_SZ 8
+#define MTX_DUR_BURST_SIFS_G_MSK 0x0000ff00
+#define MTX_DUR_BURST_SIFS_G_I_MSK 0xffff00ff
+#define MTX_DUR_BURST_SIFS_G_SFT 8
+#define MTX_DUR_BURST_SIFS_G_HI 15
+#define MTX_DUR_BURST_SIFS_G_SZ 8
+#define MTX_DUR_SLOT_G_MSK 0x003f0000
+#define MTX_DUR_SLOT_G_I_MSK 0xffc0ffff
+#define MTX_DUR_SLOT_G_SFT 16
+#define MTX_DUR_SLOT_G_HI 21
+#define MTX_DUR_SLOT_G_SZ 6
+#define MTX_DUR_RSP_EIFS_G_MSK 0xffc00000
+#define MTX_DUR_RSP_EIFS_G_I_MSK 0x003fffff
+#define MTX_DUR_RSP_EIFS_G_SFT 22
+#define MTX_DUR_RSP_EIFS_G_HI 31
+#define MTX_DUR_RSP_EIFS_G_SZ 10
+#define CH_STA1_DUR_MSK 0x0000ffff
+#define CH_STA1_DUR_I_MSK 0xffff0000
+#define CH_STA1_DUR_SFT 0
+#define CH_STA1_DUR_HI 15
+#define CH_STA1_DUR_SZ 16
+#define CH_STA2_DUR_MSK 0xffff0000
+#define CH_STA2_DUR_I_MSK 0x0000ffff
+#define CH_STA2_DUR_SFT 16
+#define CH_STA2_DUR_HI 31
+#define CH_STA2_DUR_SZ 16
+#define MTX_NAV_MSK 0x0000ffff
+#define MTX_NAV_I_MSK 0xffff0000
+#define MTX_NAV_SFT 0
+#define MTX_NAV_HI 15
+#define MTX_NAV_SZ 16
+#define MTX_MIB_CNT0_MSK 0x3fffffff
+#define MTX_MIB_CNT0_I_MSK 0xc0000000
+#define MTX_MIB_CNT0_SFT 0
+#define MTX_MIB_CNT0_HI 29
+#define MTX_MIB_CNT0_SZ 30
+#define MTX_MIB_EN0_MSK 0x40000000
+#define MTX_MIB_EN0_I_MSK 0xbfffffff
+#define MTX_MIB_EN0_SFT 30
+#define MTX_MIB_EN0_HI 30
+#define MTX_MIB_EN0_SZ 1
+#define MTX_MIB_CNT1_MSK 0x3fffffff
+#define MTX_MIB_CNT1_I_MSK 0xc0000000
+#define MTX_MIB_CNT1_SFT 0
+#define MTX_MIB_CNT1_HI 29
+#define MTX_MIB_CNT1_SZ 30
+#define MTX_MIB_EN1_MSK 0x40000000
+#define MTX_MIB_EN1_I_MSK 0xbfffffff
+#define MTX_MIB_EN1_SFT 30
+#define MTX_MIB_EN1_HI 30
+#define MTX_MIB_EN1_SZ 1
+#define CH_STA3_DUR_MSK 0x0000ffff
+#define CH_STA3_DUR_I_MSK 0xffff0000
+#define CH_STA3_DUR_SFT 0
+#define CH_STA3_DUR_HI 15
+#define CH_STA3_DUR_SZ 16
+#define CH_STA4_DUR_MSK 0xffff0000
+#define CH_STA4_DUR_I_MSK 0x0000ffff
+#define CH_STA4_DUR_SFT 16
+#define CH_STA4_DUR_HI 31
+#define CH_STA4_DUR_SZ 16
+#define TXQ0_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ0_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ0_MTX_Q_PRE_LD_SFT 1
+#define TXQ0_MTX_Q_PRE_LD_HI 1
+#define TXQ0_MTX_Q_PRE_LD_SZ 1
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ0_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ0_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ0_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ0_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ0_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ0_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ0_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ0_MTX_Q_RND_MODE_SFT 6
+#define TXQ0_MTX_Q_RND_MODE_HI 7
+#define TXQ0_MTX_Q_RND_MODE_SZ 2
+#define TXQ0_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ0_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ0_MTX_Q_AIFSN_SFT 0
+#define TXQ0_MTX_Q_AIFSN_HI 3
+#define TXQ0_MTX_Q_AIFSN_SZ 4
+#define TXQ0_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ0_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ0_MTX_Q_ECWMIN_SFT 8
+#define TXQ0_MTX_Q_ECWMIN_HI 11
+#define TXQ0_MTX_Q_ECWMIN_SZ 4
+#define TXQ0_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ0_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ0_MTX_Q_ECWMAX_SFT 12
+#define TXQ0_MTX_Q_ECWMAX_HI 15
+#define TXQ0_MTX_Q_ECWMAX_SZ 4
+#define TXQ0_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ0_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ0_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ0_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ0_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_BKF_CNT_SFT 0
+#define TXQ0_MTX_Q_BKF_CNT_HI 15
+#define TXQ0_MTX_Q_BKF_CNT_SZ 16
+#define TXQ0_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ0_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ0_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ0_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ0_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ0_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ0_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ0_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ0_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ0_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ0_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ0_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ0_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ0_MTX_Q_ID_MAP_L_HI 31
+#define TXQ0_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ0_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ0_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ0_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ0_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ0_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ0_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ1_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ1_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ1_MTX_Q_PRE_LD_SFT 1
+#define TXQ1_MTX_Q_PRE_LD_HI 1
+#define TXQ1_MTX_Q_PRE_LD_SZ 1
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ1_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ1_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ1_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ1_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ1_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ1_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ1_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ1_MTX_Q_RND_MODE_SFT 6
+#define TXQ1_MTX_Q_RND_MODE_HI 7
+#define TXQ1_MTX_Q_RND_MODE_SZ 2
+#define TXQ1_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ1_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ1_MTX_Q_AIFSN_SFT 0
+#define TXQ1_MTX_Q_AIFSN_HI 3
+#define TXQ1_MTX_Q_AIFSN_SZ 4
+#define TXQ1_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ1_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ1_MTX_Q_ECWMIN_SFT 8
+#define TXQ1_MTX_Q_ECWMIN_HI 11
+#define TXQ1_MTX_Q_ECWMIN_SZ 4
+#define TXQ1_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ1_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ1_MTX_Q_ECWMAX_SFT 12
+#define TXQ1_MTX_Q_ECWMAX_HI 15
+#define TXQ1_MTX_Q_ECWMAX_SZ 4
+#define TXQ1_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ1_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ1_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ1_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ1_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_BKF_CNT_SFT 0
+#define TXQ1_MTX_Q_BKF_CNT_HI 15
+#define TXQ1_MTX_Q_BKF_CNT_SZ 16
+#define TXQ1_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ1_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ1_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ1_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ1_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ1_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ1_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ1_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ1_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ1_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ1_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ1_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ1_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ1_MTX_Q_ID_MAP_L_HI 31
+#define TXQ1_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ1_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ1_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ1_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ1_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ1_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ1_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ2_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ2_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ2_MTX_Q_PRE_LD_SFT 1
+#define TXQ2_MTX_Q_PRE_LD_HI 1
+#define TXQ2_MTX_Q_PRE_LD_SZ 1
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ2_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ2_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ2_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ2_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ2_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ2_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ2_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ2_MTX_Q_RND_MODE_SFT 6
+#define TXQ2_MTX_Q_RND_MODE_HI 7
+#define TXQ2_MTX_Q_RND_MODE_SZ 2
+#define TXQ2_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ2_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ2_MTX_Q_AIFSN_SFT 0
+#define TXQ2_MTX_Q_AIFSN_HI 3
+#define TXQ2_MTX_Q_AIFSN_SZ 4
+#define TXQ2_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ2_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ2_MTX_Q_ECWMIN_SFT 8
+#define TXQ2_MTX_Q_ECWMIN_HI 11
+#define TXQ2_MTX_Q_ECWMIN_SZ 4
+#define TXQ2_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ2_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ2_MTX_Q_ECWMAX_SFT 12
+#define TXQ2_MTX_Q_ECWMAX_HI 15
+#define TXQ2_MTX_Q_ECWMAX_SZ 4
+#define TXQ2_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ2_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ2_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ2_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ2_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_BKF_CNT_SFT 0
+#define TXQ2_MTX_Q_BKF_CNT_HI 15
+#define TXQ2_MTX_Q_BKF_CNT_SZ 16
+#define TXQ2_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ2_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ2_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ2_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ2_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ2_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ2_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ2_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ2_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ2_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ2_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ2_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ2_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ2_MTX_Q_ID_MAP_L_HI 31
+#define TXQ2_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ2_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ2_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ2_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ2_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ2_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ2_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ3_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ3_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ3_MTX_Q_PRE_LD_SFT 1
+#define TXQ3_MTX_Q_PRE_LD_HI 1
+#define TXQ3_MTX_Q_PRE_LD_SZ 1
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ3_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ3_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ3_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ3_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ3_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ3_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ3_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ3_MTX_Q_RND_MODE_SFT 6
+#define TXQ3_MTX_Q_RND_MODE_HI 7
+#define TXQ3_MTX_Q_RND_MODE_SZ 2
+#define TXQ3_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ3_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ3_MTX_Q_AIFSN_SFT 0
+#define TXQ3_MTX_Q_AIFSN_HI 3
+#define TXQ3_MTX_Q_AIFSN_SZ 4
+#define TXQ3_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ3_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ3_MTX_Q_ECWMIN_SFT 8
+#define TXQ3_MTX_Q_ECWMIN_HI 11
+#define TXQ3_MTX_Q_ECWMIN_SZ 4
+#define TXQ3_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ3_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ3_MTX_Q_ECWMAX_SFT 12
+#define TXQ3_MTX_Q_ECWMAX_HI 15
+#define TXQ3_MTX_Q_ECWMAX_SZ 4
+#define TXQ3_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ3_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ3_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ3_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ3_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_BKF_CNT_SFT 0
+#define TXQ3_MTX_Q_BKF_CNT_HI 15
+#define TXQ3_MTX_Q_BKF_CNT_SZ 16
+#define TXQ3_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ3_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ3_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ3_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ3_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ3_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ3_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ3_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ3_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ3_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ3_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ3_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ3_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ3_MTX_Q_ID_MAP_L_HI 31
+#define TXQ3_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ3_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ3_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ3_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ3_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ3_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ3_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ4_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ4_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ4_MTX_Q_PRE_LD_SFT 1
+#define TXQ4_MTX_Q_PRE_LD_HI 1
+#define TXQ4_MTX_Q_PRE_LD_SZ 1
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ4_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ4_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ4_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ4_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ4_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ4_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ4_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ4_MTX_Q_RND_MODE_SFT 6
+#define TXQ4_MTX_Q_RND_MODE_HI 7
+#define TXQ4_MTX_Q_RND_MODE_SZ 2
+#define TXQ4_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ4_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ4_MTX_Q_AIFSN_SFT 0
+#define TXQ4_MTX_Q_AIFSN_HI 3
+#define TXQ4_MTX_Q_AIFSN_SZ 4
+#define TXQ4_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ4_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ4_MTX_Q_ECWMIN_SFT 8
+#define TXQ4_MTX_Q_ECWMIN_HI 11
+#define TXQ4_MTX_Q_ECWMIN_SZ 4
+#define TXQ4_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ4_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ4_MTX_Q_ECWMAX_SFT 12
+#define TXQ4_MTX_Q_ECWMAX_HI 15
+#define TXQ4_MTX_Q_ECWMAX_SZ 4
+#define TXQ4_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ4_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ4_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ4_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ4_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_BKF_CNT_SFT 0
+#define TXQ4_MTX_Q_BKF_CNT_HI 15
+#define TXQ4_MTX_Q_BKF_CNT_SZ 16
+#define TXQ4_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ4_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ4_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ4_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ4_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ4_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ4_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ4_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ4_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ4_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ4_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ4_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ4_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ4_MTX_Q_ID_MAP_L_HI 31
+#define TXQ4_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ4_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ4_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ4_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ4_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ4_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ4_MTX_Q_TXOP_OV_THD_SZ 16
+#define VALID0_MSK 0x00000001
+#define VALID0_I_MSK 0xfffffffe
+#define VALID0_SFT 0
+#define VALID0_HI 0
+#define VALID0_SZ 1
+#define PEER_QOS_EN0_MSK 0x00000002
+#define PEER_QOS_EN0_I_MSK 0xfffffffd
+#define PEER_QOS_EN0_SFT 1
+#define PEER_QOS_EN0_HI 1
+#define PEER_QOS_EN0_SZ 1
+#define PEER_OP_MODE0_MSK 0x0000000c
+#define PEER_OP_MODE0_I_MSK 0xfffffff3
+#define PEER_OP_MODE0_SFT 2
+#define PEER_OP_MODE0_HI 3
+#define PEER_OP_MODE0_SZ 2
+#define PEER_HT_MODE0_MSK 0x00000030
+#define PEER_HT_MODE0_I_MSK 0xffffffcf
+#define PEER_HT_MODE0_SFT 4
+#define PEER_HT_MODE0_HI 5
+#define PEER_HT_MODE0_SZ 2
+#define PEER_MAC0_31_0_MSK 0xffffffff
+#define PEER_MAC0_31_0_I_MSK 0x00000000
+#define PEER_MAC0_31_0_SFT 0
+#define PEER_MAC0_31_0_HI 31
+#define PEER_MAC0_31_0_SZ 32
+#define PEER_MAC0_47_32_MSK 0x0000ffff
+#define PEER_MAC0_47_32_I_MSK 0xffff0000
+#define PEER_MAC0_47_32_SFT 0
+#define PEER_MAC0_47_32_HI 15
+#define PEER_MAC0_47_32_SZ 16
+#define TX_ACK_POLICY_0_0_MSK 0x00000003
+#define TX_ACK_POLICY_0_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_0_SFT 0
+#define TX_ACK_POLICY_0_0_HI 1
+#define TX_ACK_POLICY_0_0_SZ 2
+#define TX_SEQ_CTRL_0_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_0_SFT 0
+#define TX_SEQ_CTRL_0_0_HI 11
+#define TX_SEQ_CTRL_0_0_SZ 12
+#define TX_ACK_POLICY_0_1_MSK 0x00000003
+#define TX_ACK_POLICY_0_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_1_SFT 0
+#define TX_ACK_POLICY_0_1_HI 1
+#define TX_ACK_POLICY_0_1_SZ 2
+#define TX_SEQ_CTRL_0_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_1_SFT 0
+#define TX_SEQ_CTRL_0_1_HI 11
+#define TX_SEQ_CTRL_0_1_SZ 12
+#define TX_ACK_POLICY_0_2_MSK 0x00000003
+#define TX_ACK_POLICY_0_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_2_SFT 0
+#define TX_ACK_POLICY_0_2_HI 1
+#define TX_ACK_POLICY_0_2_SZ 2
+#define TX_SEQ_CTRL_0_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_2_SFT 0
+#define TX_SEQ_CTRL_0_2_HI 11
+#define TX_SEQ_CTRL_0_2_SZ 12
+#define TX_ACK_POLICY_0_3_MSK 0x00000003
+#define TX_ACK_POLICY_0_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_3_SFT 0
+#define TX_ACK_POLICY_0_3_HI 1
+#define TX_ACK_POLICY_0_3_SZ 2
+#define TX_SEQ_CTRL_0_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_3_SFT 0
+#define TX_SEQ_CTRL_0_3_HI 11
+#define TX_SEQ_CTRL_0_3_SZ 12
+#define TX_ACK_POLICY_0_4_MSK 0x00000003
+#define TX_ACK_POLICY_0_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_4_SFT 0
+#define TX_ACK_POLICY_0_4_HI 1
+#define TX_ACK_POLICY_0_4_SZ 2
+#define TX_SEQ_CTRL_0_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_4_SFT 0
+#define TX_SEQ_CTRL_0_4_HI 11
+#define TX_SEQ_CTRL_0_4_SZ 12
+#define TX_ACK_POLICY_0_5_MSK 0x00000003
+#define TX_ACK_POLICY_0_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_5_SFT 0
+#define TX_ACK_POLICY_0_5_HI 1
+#define TX_ACK_POLICY_0_5_SZ 2
+#define TX_SEQ_CTRL_0_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_5_SFT 0
+#define TX_SEQ_CTRL_0_5_HI 11
+#define TX_SEQ_CTRL_0_5_SZ 12
+#define TX_ACK_POLICY_0_6_MSK 0x00000003
+#define TX_ACK_POLICY_0_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_6_SFT 0
+#define TX_ACK_POLICY_0_6_HI 1
+#define TX_ACK_POLICY_0_6_SZ 2
+#define TX_SEQ_CTRL_0_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_6_SFT 0
+#define TX_SEQ_CTRL_0_6_HI 11
+#define TX_SEQ_CTRL_0_6_SZ 12
+#define TX_ACK_POLICY_0_7_MSK 0x00000003
+#define TX_ACK_POLICY_0_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_7_SFT 0
+#define TX_ACK_POLICY_0_7_HI 1
+#define TX_ACK_POLICY_0_7_SZ 2
+#define TX_SEQ_CTRL_0_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_7_SFT 0
+#define TX_SEQ_CTRL_0_7_HI 11
+#define TX_SEQ_CTRL_0_7_SZ 12
+#define VALID1_MSK 0x00000001
+#define VALID1_I_MSK 0xfffffffe
+#define VALID1_SFT 0
+#define VALID1_HI 0
+#define VALID1_SZ 1
+#define PEER_QOS_EN1_MSK 0x00000002
+#define PEER_QOS_EN1_I_MSK 0xfffffffd
+#define PEER_QOS_EN1_SFT 1
+#define PEER_QOS_EN1_HI 1
+#define PEER_QOS_EN1_SZ 1
+#define PEER_OP_MODE1_MSK 0x0000000c
+#define PEER_OP_MODE1_I_MSK 0xfffffff3
+#define PEER_OP_MODE1_SFT 2
+#define PEER_OP_MODE1_HI 3
+#define PEER_OP_MODE1_SZ 2
+#define PEER_HT_MODE1_MSK 0x00000030
+#define PEER_HT_MODE1_I_MSK 0xffffffcf
+#define PEER_HT_MODE1_SFT 4
+#define PEER_HT_MODE1_HI 5
+#define PEER_HT_MODE1_SZ 2
+#define PEER_MAC1_31_0_MSK 0xffffffff
+#define PEER_MAC1_31_0_I_MSK 0x00000000
+#define PEER_MAC1_31_0_SFT 0
+#define PEER_MAC1_31_0_HI 31
+#define PEER_MAC1_31_0_SZ 32
+#define PEER_MAC1_47_32_MSK 0x0000ffff
+#define PEER_MAC1_47_32_I_MSK 0xffff0000
+#define PEER_MAC1_47_32_SFT 0
+#define PEER_MAC1_47_32_HI 15
+#define PEER_MAC1_47_32_SZ 16
+#define TX_ACK_POLICY_1_0_MSK 0x00000003
+#define TX_ACK_POLICY_1_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_0_SFT 0
+#define TX_ACK_POLICY_1_0_HI 1
+#define TX_ACK_POLICY_1_0_SZ 2
+#define TX_SEQ_CTRL_1_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_0_SFT 0
+#define TX_SEQ_CTRL_1_0_HI 11
+#define TX_SEQ_CTRL_1_0_SZ 12
+#define TX_ACK_POLICY_1_1_MSK 0x00000003
+#define TX_ACK_POLICY_1_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_1_SFT 0
+#define TX_ACK_POLICY_1_1_HI 1
+#define TX_ACK_POLICY_1_1_SZ 2
+#define TX_SEQ_CTRL_1_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_1_SFT 0
+#define TX_SEQ_CTRL_1_1_HI 11
+#define TX_SEQ_CTRL_1_1_SZ 12
+#define TX_ACK_POLICY_1_2_MSK 0x00000003
+#define TX_ACK_POLICY_1_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_2_SFT 0
+#define TX_ACK_POLICY_1_2_HI 1
+#define TX_ACK_POLICY_1_2_SZ 2
+#define TX_SEQ_CTRL_1_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_2_SFT 0
+#define TX_SEQ_CTRL_1_2_HI 11
+#define TX_SEQ_CTRL_1_2_SZ 12
+#define TX_ACK_POLICY_1_3_MSK 0x00000003
+#define TX_ACK_POLICY_1_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_3_SFT 0
+#define TX_ACK_POLICY_1_3_HI 1
+#define TX_ACK_POLICY_1_3_SZ 2
+#define TX_SEQ_CTRL_1_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_3_SFT 0
+#define TX_SEQ_CTRL_1_3_HI 11
+#define TX_SEQ_CTRL_1_3_SZ 12
+#define TX_ACK_POLICY_1_4_MSK 0x00000003
+#define TX_ACK_POLICY_1_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_4_SFT 0
+#define TX_ACK_POLICY_1_4_HI 1
+#define TX_ACK_POLICY_1_4_SZ 2
+#define TX_SEQ_CTRL_1_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_4_SFT 0
+#define TX_SEQ_CTRL_1_4_HI 11
+#define TX_SEQ_CTRL_1_4_SZ 12
+#define TX_ACK_POLICY_1_5_MSK 0x00000003
+#define TX_ACK_POLICY_1_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_5_SFT 0
+#define TX_ACK_POLICY_1_5_HI 1
+#define TX_ACK_POLICY_1_5_SZ 2
+#define TX_SEQ_CTRL_1_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_5_SFT 0
+#define TX_SEQ_CTRL_1_5_HI 11
+#define TX_SEQ_CTRL_1_5_SZ 12
+#define TX_ACK_POLICY_1_6_MSK 0x00000003
+#define TX_ACK_POLICY_1_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_6_SFT 0
+#define TX_ACK_POLICY_1_6_HI 1
+#define TX_ACK_POLICY_1_6_SZ 2
+#define TX_SEQ_CTRL_1_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_6_SFT 0
+#define TX_SEQ_CTRL_1_6_HI 11
+#define TX_SEQ_CTRL_1_6_SZ 12
+#define TX_ACK_POLICY_1_7_MSK 0x00000003
+#define TX_ACK_POLICY_1_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_7_SFT 0
+#define TX_ACK_POLICY_1_7_HI 1
+#define TX_ACK_POLICY_1_7_SZ 2
+#define TX_SEQ_CTRL_1_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_7_SFT 0
+#define TX_SEQ_CTRL_1_7_HI 11
+#define TX_SEQ_CTRL_1_7_SZ 12
+#define INFO0_MSK 0xffffffff
+#define INFO0_I_MSK 0x00000000
+#define INFO0_SFT 0
+#define INFO0_HI 31
+#define INFO0_SZ 32
+#define INFO1_MSK 0xffffffff
+#define INFO1_I_MSK 0x00000000
+#define INFO1_SFT 0
+#define INFO1_HI 31
+#define INFO1_SZ 32
+#define INFO2_MSK 0xffffffff
+#define INFO2_I_MSK 0x00000000
+#define INFO2_SFT 0
+#define INFO2_HI 31
+#define INFO2_SZ 32
+#define INFO3_MSK 0xffffffff
+#define INFO3_I_MSK 0x00000000
+#define INFO3_SFT 0
+#define INFO3_HI 31
+#define INFO3_SZ 32
+#define INFO4_MSK 0xffffffff
+#define INFO4_I_MSK 0x00000000
+#define INFO4_SFT 0
+#define INFO4_HI 31
+#define INFO4_SZ 32
+#define INFO5_MSK 0xffffffff
+#define INFO5_I_MSK 0x00000000
+#define INFO5_SFT 0
+#define INFO5_HI 31
+#define INFO5_SZ 32
+#define INFO6_MSK 0xffffffff
+#define INFO6_I_MSK 0x00000000
+#define INFO6_SFT 0
+#define INFO6_HI 31
+#define INFO6_SZ 32
+#define INFO7_MSK 0xffffffff
+#define INFO7_I_MSK 0x00000000
+#define INFO7_SFT 0
+#define INFO7_HI 31
+#define INFO7_SZ 32
+#define INFO8_MSK 0xffffffff
+#define INFO8_I_MSK 0x00000000
+#define INFO8_SFT 0
+#define INFO8_HI 31
+#define INFO8_SZ 32
+#define INFO9_MSK 0xffffffff
+#define INFO9_I_MSK 0x00000000
+#define INFO9_SFT 0
+#define INFO9_HI 31
+#define INFO9_SZ 32
+#define INFO10_MSK 0xffffffff
+#define INFO10_I_MSK 0x00000000
+#define INFO10_SFT 0
+#define INFO10_HI 31
+#define INFO10_SZ 32
+#define INFO11_MSK 0xffffffff
+#define INFO11_I_MSK 0x00000000
+#define INFO11_SFT 0
+#define INFO11_HI 31
+#define INFO11_SZ 32
+#define INFO12_MSK 0xffffffff
+#define INFO12_I_MSK 0x00000000
+#define INFO12_SFT 0
+#define INFO12_HI 31
+#define INFO12_SZ 32
+#define INFO13_MSK 0xffffffff
+#define INFO13_I_MSK 0x00000000
+#define INFO13_SFT 0
+#define INFO13_HI 31
+#define INFO13_SZ 32
+#define INFO14_MSK 0xffffffff
+#define INFO14_I_MSK 0x00000000
+#define INFO14_SFT 0
+#define INFO14_HI 31
+#define INFO14_SZ 32
+#define INFO15_MSK 0xffffffff
+#define INFO15_I_MSK 0x00000000
+#define INFO15_SFT 0
+#define INFO15_HI 31
+#define INFO15_SZ 32
+#define INFO16_MSK 0xffffffff
+#define INFO16_I_MSK 0x00000000
+#define INFO16_SFT 0
+#define INFO16_HI 31
+#define INFO16_SZ 32
+#define INFO17_MSK 0xffffffff
+#define INFO17_I_MSK 0x00000000
+#define INFO17_SFT 0
+#define INFO17_HI 31
+#define INFO17_SZ 32
+#define INFO18_MSK 0xffffffff
+#define INFO18_I_MSK 0x00000000
+#define INFO18_SFT 0
+#define INFO18_HI 31
+#define INFO18_SZ 32
+#define INFO19_MSK 0xffffffff
+#define INFO19_I_MSK 0x00000000
+#define INFO19_SFT 0
+#define INFO19_HI 31
+#define INFO19_SZ 32
+#define INFO20_MSK 0xffffffff
+#define INFO20_I_MSK 0x00000000
+#define INFO20_SFT 0
+#define INFO20_HI 31
+#define INFO20_SZ 32
+#define INFO21_MSK 0xffffffff
+#define INFO21_I_MSK 0x00000000
+#define INFO21_SFT 0
+#define INFO21_HI 31
+#define INFO21_SZ 32
+#define INFO22_MSK 0xffffffff
+#define INFO22_I_MSK 0x00000000
+#define INFO22_SFT 0
+#define INFO22_HI 31
+#define INFO22_SZ 32
+#define INFO23_MSK 0xffffffff
+#define INFO23_I_MSK 0x00000000
+#define INFO23_SFT 0
+#define INFO23_HI 31
+#define INFO23_SZ 32
+#define INFO24_MSK 0xffffffff
+#define INFO24_I_MSK 0x00000000
+#define INFO24_SFT 0
+#define INFO24_HI 31
+#define INFO24_SZ 32
+#define INFO25_MSK 0xffffffff
+#define INFO25_I_MSK 0x00000000
+#define INFO25_SFT 0
+#define INFO25_HI 31
+#define INFO25_SZ 32
+#define INFO26_MSK 0xffffffff
+#define INFO26_I_MSK 0x00000000
+#define INFO26_SFT 0
+#define INFO26_HI 31
+#define INFO26_SZ 32
+#define INFO27_MSK 0xffffffff
+#define INFO27_I_MSK 0x00000000
+#define INFO27_SFT 0
+#define INFO27_HI 31
+#define INFO27_SZ 32
+#define INFO28_MSK 0xffffffff
+#define INFO28_I_MSK 0x00000000
+#define INFO28_SFT 0
+#define INFO28_HI 31
+#define INFO28_SZ 32
+#define INFO29_MSK 0xffffffff
+#define INFO29_I_MSK 0x00000000
+#define INFO29_SFT 0
+#define INFO29_HI 31
+#define INFO29_SZ 32
+#define INFO30_MSK 0xffffffff
+#define INFO30_I_MSK 0x00000000
+#define INFO30_SFT 0
+#define INFO30_HI 31
+#define INFO30_SZ 32
+#define INFO31_MSK 0xffffffff
+#define INFO31_I_MSK 0x00000000
+#define INFO31_SFT 0
+#define INFO31_HI 31
+#define INFO31_SZ 32
+#define INFO32_MSK 0xffffffff
+#define INFO32_I_MSK 0x00000000
+#define INFO32_SFT 0
+#define INFO32_HI 31
+#define INFO32_SZ 32
+#define INFO33_MSK 0xffffffff
+#define INFO33_I_MSK 0x00000000
+#define INFO33_SFT 0
+#define INFO33_HI 31
+#define INFO33_SZ 32
+#define INFO34_MSK 0xffffffff
+#define INFO34_I_MSK 0x00000000
+#define INFO34_SFT 0
+#define INFO34_HI 31
+#define INFO34_SZ 32
+#define INFO35_MSK 0xffffffff
+#define INFO35_I_MSK 0x00000000
+#define INFO35_SFT 0
+#define INFO35_HI 31
+#define INFO35_SZ 32
+#define INFO36_MSK 0xffffffff
+#define INFO36_I_MSK 0x00000000
+#define INFO36_SFT 0
+#define INFO36_HI 31
+#define INFO36_SZ 32
+#define INFO37_MSK 0xffffffff
+#define INFO37_I_MSK 0x00000000
+#define INFO37_SFT 0
+#define INFO37_HI 31
+#define INFO37_SZ 32
+#define INFO38_MSK 0xffffffff
+#define INFO38_I_MSK 0x00000000
+#define INFO38_SFT 0
+#define INFO38_HI 31
+#define INFO38_SZ 32
+#define INFO_MASK_MSK 0xffffffff
+#define INFO_MASK_I_MSK 0x00000000
+#define INFO_MASK_SFT 0
+#define INFO_MASK_HI 31
+#define INFO_MASK_SZ 32
+#define INFO_DEF_RATE_MSK 0x0000003f
+#define INFO_DEF_RATE_I_MSK 0xffffffc0
+#define INFO_DEF_RATE_SFT 0
+#define INFO_DEF_RATE_HI 5
+#define INFO_DEF_RATE_SZ 6
+#define INFO_MRX_OFFSET_MSK 0x000f0000
+#define INFO_MRX_OFFSET_I_MSK 0xfff0ffff
+#define INFO_MRX_OFFSET_SFT 16
+#define INFO_MRX_OFFSET_HI 19
+#define INFO_MRX_OFFSET_SZ 4
+#define BCAST_RATEUNKNOW_MSK 0x3f000000
+#define BCAST_RATEUNKNOW_I_MSK 0xc0ffffff
+#define BCAST_RATEUNKNOW_SFT 24
+#define BCAST_RATEUNKNOW_HI 29
+#define BCAST_RATEUNKNOW_SZ 6
+#define INFO_IDX_TBL_ADDR_MSK 0xffffffff
+#define INFO_IDX_TBL_ADDR_I_MSK 0x00000000
+#define INFO_IDX_TBL_ADDR_SFT 0
+#define INFO_IDX_TBL_ADDR_HI 31
+#define INFO_IDX_TBL_ADDR_SZ 32
+#define INFO_LEN_TBL_ADDR_MSK 0xffffffff
+#define INFO_LEN_TBL_ADDR_I_MSK 0x00000000
+#define INFO_LEN_TBL_ADDR_SFT 0
+#define INFO_LEN_TBL_ADDR_HI 31
+#define INFO_LEN_TBL_ADDR_SZ 32
+#define IC_TAG_31_0_MSK 0xffffffff
+#define IC_TAG_31_0_I_MSK 0x00000000
+#define IC_TAG_31_0_SFT 0
+#define IC_TAG_31_0_HI 31
+#define IC_TAG_31_0_SZ 32
+#define IC_TAG_63_32_MSK 0xffffffff
+#define IC_TAG_63_32_I_MSK 0x00000000
+#define IC_TAG_63_32_SFT 0
+#define IC_TAG_63_32_HI 31
+#define IC_TAG_63_32_SZ 32
+#define CH1_PRI_MSK 0x00000003
+#define CH1_PRI_I_MSK 0xfffffffc
+#define CH1_PRI_SFT 0
+#define CH1_PRI_HI 1
+#define CH1_PRI_SZ 2
+#define CH2_PRI_MSK 0x00000300
+#define CH2_PRI_I_MSK 0xfffffcff
+#define CH2_PRI_SFT 8
+#define CH2_PRI_HI 9
+#define CH2_PRI_SZ 2
+#define CH3_PRI_MSK 0x00030000
+#define CH3_PRI_I_MSK 0xfffcffff
+#define CH3_PRI_SFT 16
+#define CH3_PRI_HI 17
+#define CH3_PRI_SZ 2
+#define RG_MAC_LPBK_MSK 0x00000001
+#define RG_MAC_LPBK_I_MSK 0xfffffffe
+#define RG_MAC_LPBK_SFT 0
+#define RG_MAC_LPBK_HI 0
+#define RG_MAC_LPBK_SZ 1
+#define RG_MAC_M2M_MSK 0x00000002
+#define RG_MAC_M2M_I_MSK 0xfffffffd
+#define RG_MAC_M2M_SFT 1
+#define RG_MAC_M2M_HI 1
+#define RG_MAC_M2M_SZ 1
+#define RG_PHY_LPBK_MSK 0x00000004
+#define RG_PHY_LPBK_I_MSK 0xfffffffb
+#define RG_PHY_LPBK_SFT 2
+#define RG_PHY_LPBK_HI 2
+#define RG_PHY_LPBK_SZ 1
+#define RG_LPBK_RX_EN_MSK 0x00000008
+#define RG_LPBK_RX_EN_I_MSK 0xfffffff7
+#define RG_LPBK_RX_EN_SFT 3
+#define RG_LPBK_RX_EN_HI 3
+#define RG_LPBK_RX_EN_SZ 1
+#define EXT_MAC_MODE_MSK 0x00000010
+#define EXT_MAC_MODE_I_MSK 0xffffffef
+#define EXT_MAC_MODE_SFT 4
+#define EXT_MAC_MODE_HI 4
+#define EXT_MAC_MODE_SZ 1
+#define EXT_PHY_MODE_MSK 0x00000020
+#define EXT_PHY_MODE_I_MSK 0xffffffdf
+#define EXT_PHY_MODE_SFT 5
+#define EXT_PHY_MODE_HI 5
+#define EXT_PHY_MODE_SZ 1
+#define ASIC_TAG_MSK 0xff000000
+#define ASIC_TAG_I_MSK 0x00ffffff
+#define ASIC_TAG_SFT 24
+#define ASIC_TAG_HI 31
+#define ASIC_TAG_SZ 8
+#define HCI_SW_RST_MSK 0x00000001
+#define HCI_SW_RST_I_MSK 0xfffffffe
+#define HCI_SW_RST_SFT 0
+#define HCI_SW_RST_HI 0
+#define HCI_SW_RST_SZ 1
+#define CO_PROC_SW_RST_MSK 0x00000002
+#define CO_PROC_SW_RST_I_MSK 0xfffffffd
+#define CO_PROC_SW_RST_SFT 1
+#define CO_PROC_SW_RST_HI 1
+#define CO_PROC_SW_RST_SZ 1
+#define MTX_MISC_SW_RST_MSK 0x00000008
+#define MTX_MISC_SW_RST_I_MSK 0xfffffff7
+#define MTX_MISC_SW_RST_SFT 3
+#define MTX_MISC_SW_RST_HI 3
+#define MTX_MISC_SW_RST_SZ 1
+#define MTX_QUE_SW_RST_MSK 0x00000010
+#define MTX_QUE_SW_RST_I_MSK 0xffffffef
+#define MTX_QUE_SW_RST_SFT 4
+#define MTX_QUE_SW_RST_HI 4
+#define MTX_QUE_SW_RST_SZ 1
+#define MTX_CHST_SW_RST_MSK 0x00000020
+#define MTX_CHST_SW_RST_I_MSK 0xffffffdf
+#define MTX_CHST_SW_RST_SFT 5
+#define MTX_CHST_SW_RST_HI 5
+#define MTX_CHST_SW_RST_SZ 1
+#define MTX_BCN_SW_RST_MSK 0x00000040
+#define MTX_BCN_SW_RST_I_MSK 0xffffffbf
+#define MTX_BCN_SW_RST_SFT 6
+#define MTX_BCN_SW_RST_HI 6
+#define MTX_BCN_SW_RST_SZ 1
+#define MRX_SW_RST_MSK 0x00000080
+#define MRX_SW_RST_I_MSK 0xffffff7f
+#define MRX_SW_RST_SFT 7
+#define MRX_SW_RST_HI 7
+#define MRX_SW_RST_SZ 1
+#define AMPDU_SW_RST_MSK 0x00000100
+#define AMPDU_SW_RST_I_MSK 0xfffffeff
+#define AMPDU_SW_RST_SFT 8
+#define AMPDU_SW_RST_HI 8
+#define AMPDU_SW_RST_SZ 1
+#define MMU_SW_RST_MSK 0x00000200
+#define MMU_SW_RST_I_MSK 0xfffffdff
+#define MMU_SW_RST_SFT 9
+#define MMU_SW_RST_HI 9
+#define MMU_SW_RST_SZ 1
+#define ID_MNG_SW_RST_MSK 0x00000800
+#define ID_MNG_SW_RST_I_MSK 0xfffff7ff
+#define ID_MNG_SW_RST_SFT 11
+#define ID_MNG_SW_RST_HI 11
+#define ID_MNG_SW_RST_SZ 1
+#define MBOX_SW_RST_MSK 0x00001000
+#define MBOX_SW_RST_I_MSK 0xffffefff
+#define MBOX_SW_RST_SFT 12
+#define MBOX_SW_RST_HI 12
+#define MBOX_SW_RST_SZ 1
+#define SCRT_SW_RST_MSK 0x00002000
+#define SCRT_SW_RST_I_MSK 0xffffdfff
+#define SCRT_SW_RST_SFT 13
+#define SCRT_SW_RST_HI 13
+#define SCRT_SW_RST_SZ 1
+#define MIC_SW_RST_MSK 0x00004000
+#define MIC_SW_RST_I_MSK 0xffffbfff
+#define MIC_SW_RST_SFT 14
+#define MIC_SW_RST_HI 14
+#define MIC_SW_RST_SZ 1
+#define CO_PROC_ENG_RST_MSK 0x00000002
+#define CO_PROC_ENG_RST_I_MSK 0xfffffffd
+#define CO_PROC_ENG_RST_SFT 1
+#define CO_PROC_ENG_RST_HI 1
+#define CO_PROC_ENG_RST_SZ 1
+#define MTX_MISC_ENG_RST_MSK 0x00000008
+#define MTX_MISC_ENG_RST_I_MSK 0xfffffff7
+#define MTX_MISC_ENG_RST_SFT 3
+#define MTX_MISC_ENG_RST_HI 3
+#define MTX_MISC_ENG_RST_SZ 1
+#define MTX_QUE_ENG_RST_MSK 0x00000010
+#define MTX_QUE_ENG_RST_I_MSK 0xffffffef
+#define MTX_QUE_ENG_RST_SFT 4
+#define MTX_QUE_ENG_RST_HI 4
+#define MTX_QUE_ENG_RST_SZ 1
+#define MTX_CHST_ENG_RST_MSK 0x00000020
+#define MTX_CHST_ENG_RST_I_MSK 0xffffffdf
+#define MTX_CHST_ENG_RST_SFT 5
+#define MTX_CHST_ENG_RST_HI 5
+#define MTX_CHST_ENG_RST_SZ 1
+#define MTX_BCN_ENG_RST_MSK 0x00000040
+#define MTX_BCN_ENG_RST_I_MSK 0xffffffbf
+#define MTX_BCN_ENG_RST_SFT 6
+#define MTX_BCN_ENG_RST_HI 6
+#define MTX_BCN_ENG_RST_SZ 1
+#define MRX_ENG_RST_MSK 0x00000080
+#define MRX_ENG_RST_I_MSK 0xffffff7f
+#define MRX_ENG_RST_SFT 7
+#define MRX_ENG_RST_HI 7
+#define MRX_ENG_RST_SZ 1
+#define AMPDU_ENG_RST_MSK 0x00000100
+#define AMPDU_ENG_RST_I_MSK 0xfffffeff
+#define AMPDU_ENG_RST_SFT 8
+#define AMPDU_ENG_RST_HI 8
+#define AMPDU_ENG_RST_SZ 1
+#define ID_MNG_ENG_RST_MSK 0x00004000
+#define ID_MNG_ENG_RST_I_MSK 0xffffbfff
+#define ID_MNG_ENG_RST_SFT 14
+#define ID_MNG_ENG_RST_HI 14
+#define ID_MNG_ENG_RST_SZ 1
+#define MBOX_ENG_RST_MSK 0x00008000
+#define MBOX_ENG_RST_I_MSK 0xffff7fff
+#define MBOX_ENG_RST_SFT 15
+#define MBOX_ENG_RST_HI 15
+#define MBOX_ENG_RST_SZ 1
+#define SCRT_ENG_RST_MSK 0x00010000
+#define SCRT_ENG_RST_I_MSK 0xfffeffff
+#define SCRT_ENG_RST_SFT 16
+#define SCRT_ENG_RST_HI 16
+#define SCRT_ENG_RST_SZ 1
+#define MIC_ENG_RST_MSK 0x00020000
+#define MIC_ENG_RST_I_MSK 0xfffdffff
+#define MIC_ENG_RST_SFT 17
+#define MIC_ENG_RST_HI 17
+#define MIC_ENG_RST_SZ 1
+#define CO_PROC_CSR_RST_MSK 0x00000002
+#define CO_PROC_CSR_RST_I_MSK 0xfffffffd
+#define CO_PROC_CSR_RST_SFT 1
+#define CO_PROC_CSR_RST_HI 1
+#define CO_PROC_CSR_RST_SZ 1
+#define MTX_MISC_CSR_RST_MSK 0x00000008
+#define MTX_MISC_CSR_RST_I_MSK 0xfffffff7
+#define MTX_MISC_CSR_RST_SFT 3
+#define MTX_MISC_CSR_RST_HI 3
+#define MTX_MISC_CSR_RST_SZ 1
+#define MTX_QUE0_CSR_RST_MSK 0x00000010
+#define MTX_QUE0_CSR_RST_I_MSK 0xffffffef
+#define MTX_QUE0_CSR_RST_SFT 4
+#define MTX_QUE0_CSR_RST_HI 4
+#define MTX_QUE0_CSR_RST_SZ 1
+#define MTX_QUE1_CSR_RST_MSK 0x00000020
+#define MTX_QUE1_CSR_RST_I_MSK 0xffffffdf
+#define MTX_QUE1_CSR_RST_SFT 5
+#define MTX_QUE1_CSR_RST_HI 5
+#define MTX_QUE1_CSR_RST_SZ 1
+#define MTX_QUE2_CSR_RST_MSK 0x00000040
+#define MTX_QUE2_CSR_RST_I_MSK 0xffffffbf
+#define MTX_QUE2_CSR_RST_SFT 6
+#define MTX_QUE2_CSR_RST_HI 6
+#define MTX_QUE2_CSR_RST_SZ 1
+#define MTX_QUE3_CSR_RST_MSK 0x00000080
+#define MTX_QUE3_CSR_RST_I_MSK 0xffffff7f
+#define MTX_QUE3_CSR_RST_SFT 7
+#define MTX_QUE3_CSR_RST_HI 7
+#define MTX_QUE3_CSR_RST_SZ 1
+#define MTX_QUE4_CSR_RST_MSK 0x00000100
+#define MTX_QUE4_CSR_RST_I_MSK 0xfffffeff
+#define MTX_QUE4_CSR_RST_SFT 8
+#define MTX_QUE4_CSR_RST_HI 8
+#define MTX_QUE4_CSR_RST_SZ 1
+#define MTX_QUE5_CSR_RST_MSK 0x00000200
+#define MTX_QUE5_CSR_RST_I_MSK 0xfffffdff
+#define MTX_QUE5_CSR_RST_SFT 9
+#define MTX_QUE5_CSR_RST_HI 9
+#define MTX_QUE5_CSR_RST_SZ 1
+#define MRX_CSR_RST_MSK 0x00000400
+#define MRX_CSR_RST_I_MSK 0xfffffbff
+#define MRX_CSR_RST_SFT 10
+#define MRX_CSR_RST_HI 10
+#define MRX_CSR_RST_SZ 1
+#define AMPDU_CSR_RST_MSK 0x00000800
+#define AMPDU_CSR_RST_I_MSK 0xfffff7ff
+#define AMPDU_CSR_RST_SFT 11
+#define AMPDU_CSR_RST_HI 11
+#define AMPDU_CSR_RST_SZ 1
+#define SCRT_CSR_RST_MSK 0x00002000
+#define SCRT_CSR_RST_I_MSK 0xffffdfff
+#define SCRT_CSR_RST_SFT 13
+#define SCRT_CSR_RST_HI 13
+#define SCRT_CSR_RST_SZ 1
+#define ID_MNG_CSR_RST_MSK 0x00004000
+#define ID_MNG_CSR_RST_I_MSK 0xffffbfff
+#define ID_MNG_CSR_RST_SFT 14
+#define ID_MNG_CSR_RST_HI 14
+#define ID_MNG_CSR_RST_SZ 1
+#define MBOX_CSR_RST_MSK 0x00008000
+#define MBOX_CSR_RST_I_MSK 0xffff7fff
+#define MBOX_CSR_RST_SFT 15
+#define MBOX_CSR_RST_HI 15
+#define MBOX_CSR_RST_SZ 1
+#define HCI_CLK_EN_MSK 0x00000001
+#define HCI_CLK_EN_I_MSK 0xfffffffe
+#define HCI_CLK_EN_SFT 0
+#define HCI_CLK_EN_HI 0
+#define HCI_CLK_EN_SZ 1
+#define CO_PROC_CLK_EN_MSK 0x00000002
+#define CO_PROC_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_CLK_EN_SFT 1
+#define CO_PROC_CLK_EN_HI 1
+#define CO_PROC_CLK_EN_SZ 1
+#define MTX_MISC_CLK_EN_MSK 0x00000008
+#define MTX_MISC_CLK_EN_I_MSK 0xfffffff7
+#define MTX_MISC_CLK_EN_SFT 3
+#define MTX_MISC_CLK_EN_HI 3
+#define MTX_MISC_CLK_EN_SZ 1
+#define MTX_QUE_CLK_EN_MSK 0x00000010
+#define MTX_QUE_CLK_EN_I_MSK 0xffffffef
+#define MTX_QUE_CLK_EN_SFT 4
+#define MTX_QUE_CLK_EN_HI 4
+#define MTX_QUE_CLK_EN_SZ 1
+#define MRX_CLK_EN_MSK 0x00000020
+#define MRX_CLK_EN_I_MSK 0xffffffdf
+#define MRX_CLK_EN_SFT 5
+#define MRX_CLK_EN_HI 5
+#define MRX_CLK_EN_SZ 1
+#define AMPDU_CLK_EN_MSK 0x00000040
+#define AMPDU_CLK_EN_I_MSK 0xffffffbf
+#define AMPDU_CLK_EN_SFT 6
+#define AMPDU_CLK_EN_HI 6
+#define AMPDU_CLK_EN_SZ 1
+#define MMU_CLK_EN_MSK 0x00000080
+#define MMU_CLK_EN_I_MSK 0xffffff7f
+#define MMU_CLK_EN_SFT 7
+#define MMU_CLK_EN_HI 7
+#define MMU_CLK_EN_SZ 1
+#define ID_MNG_CLK_EN_MSK 0x00000200
+#define ID_MNG_CLK_EN_I_MSK 0xfffffdff
+#define ID_MNG_CLK_EN_SFT 9
+#define ID_MNG_CLK_EN_HI 9
+#define ID_MNG_CLK_EN_SZ 1
+#define MBOX_CLK_EN_MSK 0x00000400
+#define MBOX_CLK_EN_I_MSK 0xfffffbff
+#define MBOX_CLK_EN_SFT 10
+#define MBOX_CLK_EN_HI 10
+#define MBOX_CLK_EN_SZ 1
+#define SCRT_CLK_EN_MSK 0x00000800
+#define SCRT_CLK_EN_I_MSK 0xfffff7ff
+#define SCRT_CLK_EN_SFT 11
+#define SCRT_CLK_EN_HI 11
+#define SCRT_CLK_EN_SZ 1
+#define MIC_CLK_EN_MSK 0x00001000
+#define MIC_CLK_EN_I_MSK 0xffffefff
+#define MIC_CLK_EN_SFT 12
+#define MIC_CLK_EN_HI 12
+#define MIC_CLK_EN_SZ 1
+#define MIB_CLK_EN_MSK 0x00002000
+#define MIB_CLK_EN_I_MSK 0xffffdfff
+#define MIB_CLK_EN_SFT 13
+#define MIB_CLK_EN_HI 13
+#define MIB_CLK_EN_SZ 1
+#define HCI_ENG_CLK_EN_MSK 0x00000001
+#define HCI_ENG_CLK_EN_I_MSK 0xfffffffe
+#define HCI_ENG_CLK_EN_SFT 0
+#define HCI_ENG_CLK_EN_HI 0
+#define HCI_ENG_CLK_EN_SZ 1
+#define CO_PROC_ENG_CLK_EN_MSK 0x00000002
+#define CO_PROC_ENG_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_ENG_CLK_EN_SFT 1
+#define CO_PROC_ENG_CLK_EN_HI 1
+#define CO_PROC_ENG_CLK_EN_SZ 1
+#define MTX_MISC_ENG_CLK_EN_MSK 0x00000008
+#define MTX_MISC_ENG_CLK_EN_I_MSK 0xfffffff7
+#define MTX_MISC_ENG_CLK_EN_SFT 3
+#define MTX_MISC_ENG_CLK_EN_HI 3
+#define MTX_MISC_ENG_CLK_EN_SZ 1
+#define MTX_QUE_ENG_CLK_EN_MSK 0x00000010
+#define MTX_QUE_ENG_CLK_EN_I_MSK 0xffffffef
+#define MTX_QUE_ENG_CLK_EN_SFT 4
+#define MTX_QUE_ENG_CLK_EN_HI 4
+#define MTX_QUE_ENG_CLK_EN_SZ 1
+#define MRX_ENG_CLK_EN_MSK 0x00000020
+#define MRX_ENG_CLK_EN_I_MSK 0xffffffdf
+#define MRX_ENG_CLK_EN_SFT 5
+#define MRX_ENG_CLK_EN_HI 5
+#define MRX_ENG_CLK_EN_SZ 1
+#define AMPDU_ENG_CLK_EN_MSK 0x00000040
+#define AMPDU_ENG_CLK_EN_I_MSK 0xffffffbf
+#define AMPDU_ENG_CLK_EN_SFT 6
+#define AMPDU_ENG_CLK_EN_HI 6
+#define AMPDU_ENG_CLK_EN_SZ 1
+#define ID_MNG_ENG_CLK_EN_MSK 0x00001000
+#define ID_MNG_ENG_CLK_EN_I_MSK 0xffffefff
+#define ID_MNG_ENG_CLK_EN_SFT 12
+#define ID_MNG_ENG_CLK_EN_HI 12
+#define ID_MNG_ENG_CLK_EN_SZ 1
+#define MBOX_ENG_CLK_EN_MSK 0x00002000
+#define MBOX_ENG_CLK_EN_I_MSK 0xffffdfff
+#define MBOX_ENG_CLK_EN_SFT 13
+#define MBOX_ENG_CLK_EN_HI 13
+#define MBOX_ENG_CLK_EN_SZ 1
+#define SCRT_ENG_CLK_EN_MSK 0x00004000
+#define SCRT_ENG_CLK_EN_I_MSK 0xffffbfff
+#define SCRT_ENG_CLK_EN_SFT 14
+#define SCRT_ENG_CLK_EN_HI 14
+#define SCRT_ENG_CLK_EN_SZ 1
+#define MIC_ENG_CLK_EN_MSK 0x00008000
+#define MIC_ENG_CLK_EN_I_MSK 0xffff7fff
+#define MIC_ENG_CLK_EN_SFT 15
+#define MIC_ENG_CLK_EN_HI 15
+#define MIC_ENG_CLK_EN_SZ 1
+#define CO_PROC_CSR_CLK_EN_MSK 0x00000002
+#define CO_PROC_CSR_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_CSR_CLK_EN_SFT 1
+#define CO_PROC_CSR_CLK_EN_HI 1
+#define CO_PROC_CSR_CLK_EN_SZ 1
+#define MRX_CSR_CLK_EN_MSK 0x00000400
+#define MRX_CSR_CLK_EN_I_MSK 0xfffffbff
+#define MRX_CSR_CLK_EN_SFT 10
+#define MRX_CSR_CLK_EN_HI 10
+#define MRX_CSR_CLK_EN_SZ 1
+#define AMPDU_CSR_CLK_EN_MSK 0x00000800
+#define AMPDU_CSR_CLK_EN_I_MSK 0xfffff7ff
+#define AMPDU_CSR_CLK_EN_SFT 11
+#define AMPDU_CSR_CLK_EN_HI 11
+#define AMPDU_CSR_CLK_EN_SZ 1
+#define SCRT_CSR_CLK_EN_MSK 0x00002000
+#define SCRT_CSR_CLK_EN_I_MSK 0xffffdfff
+#define SCRT_CSR_CLK_EN_SFT 13
+#define SCRT_CSR_CLK_EN_HI 13
+#define SCRT_CSR_CLK_EN_SZ 1
+#define ID_MNG_CSR_CLK_EN_MSK 0x00004000
+#define ID_MNG_CSR_CLK_EN_I_MSK 0xffffbfff
+#define ID_MNG_CSR_CLK_EN_SFT 14
+#define ID_MNG_CSR_CLK_EN_HI 14
+#define ID_MNG_CSR_CLK_EN_SZ 1
+#define MBOX_CSR_CLK_EN_MSK 0x00008000
+#define MBOX_CSR_CLK_EN_I_MSK 0xffff7fff
+#define MBOX_CSR_CLK_EN_SFT 15
+#define MBOX_CSR_CLK_EN_HI 15
+#define MBOX_CSR_CLK_EN_SZ 1
+#define OP_MODE_MSK 0x00000003
+#define OP_MODE_I_MSK 0xfffffffc
+#define OP_MODE_SFT 0
+#define OP_MODE_HI 1
+#define OP_MODE_SZ 2
+#define HT_MODE_MSK 0x0000000c
+#define HT_MODE_I_MSK 0xfffffff3
+#define HT_MODE_SFT 2
+#define HT_MODE_HI 3
+#define HT_MODE_SZ 2
+#define QOS_EN_MSK 0x00000010
+#define QOS_EN_I_MSK 0xffffffef
+#define QOS_EN_SFT 4
+#define QOS_EN_HI 4
+#define QOS_EN_SZ 1
+#define PB_OFFSET_MSK 0x0000ff00
+#define PB_OFFSET_I_MSK 0xffff00ff
+#define PB_OFFSET_SFT 8
+#define PB_OFFSET_HI 15
+#define PB_OFFSET_SZ 8
+#define SNIFFER_MODE_MSK 0x00010000
+#define SNIFFER_MODE_I_MSK 0xfffeffff
+#define SNIFFER_MODE_SFT 16
+#define SNIFFER_MODE_HI 16
+#define SNIFFER_MODE_SZ 1
+#define DUP_FLT_MSK 0x00020000
+#define DUP_FLT_I_MSK 0xfffdffff
+#define DUP_FLT_SFT 17
+#define DUP_FLT_HI 17
+#define DUP_FLT_SZ 1
+#define TX_PKT_RSVD_MSK 0x001c0000
+#define TX_PKT_RSVD_I_MSK 0xffe3ffff
+#define TX_PKT_RSVD_SFT 18
+#define TX_PKT_RSVD_HI 20
+#define TX_PKT_RSVD_SZ 3
+#define AMPDU_SNIFFER_MSK 0x00200000
+#define AMPDU_SNIFFER_I_MSK 0xffdfffff
+#define AMPDU_SNIFFER_SFT 21
+#define AMPDU_SNIFFER_HI 21
+#define AMPDU_SNIFFER_SZ 1
+#define REASON_TRAP0_MSK 0xffffffff
+#define REASON_TRAP0_I_MSK 0x00000000
+#define REASON_TRAP0_SFT 0
+#define REASON_TRAP0_HI 31
+#define REASON_TRAP0_SZ 32
+#define REASON_TRAP1_MSK 0xffffffff
+#define REASON_TRAP1_I_MSK 0x00000000
+#define REASON_TRAP1_SFT 0
+#define REASON_TRAP1_HI 31
+#define REASON_TRAP1_SZ 32
+#define BSSID_31_0_MSK 0xffffffff
+#define BSSID_31_0_I_MSK 0x00000000
+#define BSSID_31_0_SFT 0
+#define BSSID_31_0_HI 31
+#define BSSID_31_0_SZ 32
+#define BSSID_47_32_MSK 0x0000ffff
+#define BSSID_47_32_I_MSK 0xffff0000
+#define BSSID_47_32_SFT 0
+#define BSSID_47_32_HI 15
+#define BSSID_47_32_SZ 16
+#define SCRT_STATE_MSK 0x0000000f
+#define SCRT_STATE_I_MSK 0xfffffff0
+#define SCRT_STATE_SFT 0
+#define SCRT_STATE_HI 3
+#define SCRT_STATE_SZ 4
+#define STA_MAC_31_0_MSK 0xffffffff
+#define STA_MAC_31_0_I_MSK 0x00000000
+#define STA_MAC_31_0_SFT 0
+#define STA_MAC_31_0_HI 31
+#define STA_MAC_31_0_SZ 32
+#define STA_MAC_47_32_MSK 0x0000ffff
+#define STA_MAC_47_32_I_MSK 0xffff0000
+#define STA_MAC_47_32_SFT 0
+#define STA_MAC_47_32_HI 15
+#define STA_MAC_47_32_SZ 16
+#define PAIR_SCRT_MSK 0x00000007
+#define PAIR_SCRT_I_MSK 0xfffffff8
+#define PAIR_SCRT_SFT 0
+#define PAIR_SCRT_HI 2
+#define PAIR_SCRT_SZ 3
+#define GRP_SCRT_MSK 0x00000038
+#define GRP_SCRT_I_MSK 0xffffffc7
+#define GRP_SCRT_SFT 3
+#define GRP_SCRT_HI 5
+#define GRP_SCRT_SZ 3
+#define SCRT_PKT_ID_MSK 0x00001fc0
+#define SCRT_PKT_ID_I_MSK 0xffffe03f
+#define SCRT_PKT_ID_SFT 6
+#define SCRT_PKT_ID_HI 12
+#define SCRT_PKT_ID_SZ 7
+#define SCRT_RPLY_IGNORE_MSK 0x00010000
+#define SCRT_RPLY_IGNORE_I_MSK 0xfffeffff
+#define SCRT_RPLY_IGNORE_SFT 16
+#define SCRT_RPLY_IGNORE_HI 16
+#define SCRT_RPLY_IGNORE_SZ 1
+#define COEXIST_EN_MSK 0x00000001
+#define COEXIST_EN_I_MSK 0xfffffffe
+#define COEXIST_EN_SFT 0
+#define COEXIST_EN_HI 0
+#define COEXIST_EN_SZ 1
+#define WIRE_MODE_MSK 0x0000000e
+#define WIRE_MODE_I_MSK 0xfffffff1
+#define WIRE_MODE_SFT 1
+#define WIRE_MODE_HI 3
+#define WIRE_MODE_SZ 3
+#define WL_RX_PRI_MSK 0x00000010
+#define WL_RX_PRI_I_MSK 0xffffffef
+#define WL_RX_PRI_SFT 4
+#define WL_RX_PRI_HI 4
+#define WL_RX_PRI_SZ 1
+#define WL_TX_PRI_MSK 0x00000020
+#define WL_TX_PRI_I_MSK 0xffffffdf
+#define WL_TX_PRI_SFT 5
+#define WL_TX_PRI_HI 5
+#define WL_TX_PRI_SZ 1
+#define GURAN_USE_EN_MSK 0x00000100
+#define GURAN_USE_EN_I_MSK 0xfffffeff
+#define GURAN_USE_EN_SFT 8
+#define GURAN_USE_EN_HI 8
+#define GURAN_USE_EN_SZ 1
+#define GURAN_USE_CTRL_MSK 0x00000200
+#define GURAN_USE_CTRL_I_MSK 0xfffffdff
+#define GURAN_USE_CTRL_SFT 9
+#define GURAN_USE_CTRL_HI 9
+#define GURAN_USE_CTRL_SZ 1
+#define BEACON_TIMEOUT_EN_MSK 0x00000400
+#define BEACON_TIMEOUT_EN_I_MSK 0xfffffbff
+#define BEACON_TIMEOUT_EN_SFT 10
+#define BEACON_TIMEOUT_EN_HI 10
+#define BEACON_TIMEOUT_EN_SZ 1
+#define WLAN_ACT_POL_MSK 0x00000800
+#define WLAN_ACT_POL_I_MSK 0xfffff7ff
+#define WLAN_ACT_POL_SFT 11
+#define WLAN_ACT_POL_HI 11
+#define WLAN_ACT_POL_SZ 1
+#define DUAL_ANT_EN_MSK 0x00001000
+#define DUAL_ANT_EN_I_MSK 0xffffefff
+#define DUAL_ANT_EN_SFT 12
+#define DUAL_ANT_EN_HI 12
+#define DUAL_ANT_EN_SZ 1
+#define TRSW_PHY_POL_MSK 0x00010000
+#define TRSW_PHY_POL_I_MSK 0xfffeffff
+#define TRSW_PHY_POL_SFT 16
+#define TRSW_PHY_POL_HI 16
+#define TRSW_PHY_POL_SZ 1
+#define WIFI_TX_SW_POL_MSK 0x00020000
+#define WIFI_TX_SW_POL_I_MSK 0xfffdffff
+#define WIFI_TX_SW_POL_SFT 17
+#define WIFI_TX_SW_POL_HI 17
+#define WIFI_TX_SW_POL_SZ 1
+#define WIFI_RX_SW_POL_MSK 0x00040000
+#define WIFI_RX_SW_POL_I_MSK 0xfffbffff
+#define WIFI_RX_SW_POL_SFT 18
+#define WIFI_RX_SW_POL_HI 18
+#define WIFI_RX_SW_POL_SZ 1
+#define BT_SW_POL_MSK 0x00080000
+#define BT_SW_POL_I_MSK 0xfff7ffff
+#define BT_SW_POL_SFT 19
+#define BT_SW_POL_HI 19
+#define BT_SW_POL_SZ 1
+#define BT_PRI_SMP_TIME_MSK 0x000000ff
+#define BT_PRI_SMP_TIME_I_MSK 0xffffff00
+#define BT_PRI_SMP_TIME_SFT 0
+#define BT_PRI_SMP_TIME_HI 7
+#define BT_PRI_SMP_TIME_SZ 8
+#define BT_STA_SMP_TIME_MSK 0x0000ff00
+#define BT_STA_SMP_TIME_I_MSK 0xffff00ff
+#define BT_STA_SMP_TIME_SFT 8
+#define BT_STA_SMP_TIME_HI 15
+#define BT_STA_SMP_TIME_SZ 8
+#define BEACON_TIMEOUT_MSK 0x00ff0000
+#define BEACON_TIMEOUT_I_MSK 0xff00ffff
+#define BEACON_TIMEOUT_SFT 16
+#define BEACON_TIMEOUT_HI 23
+#define BEACON_TIMEOUT_SZ 8
+#define WLAN_REMAIN_TIME_MSK 0xff000000
+#define WLAN_REMAIN_TIME_I_MSK 0x00ffffff
+#define WLAN_REMAIN_TIME_SFT 24
+#define WLAN_REMAIN_TIME_HI 31
+#define WLAN_REMAIN_TIME_SZ 8
+#define SW_MANUAL_EN_MSK 0x00000001
+#define SW_MANUAL_EN_I_MSK 0xfffffffe
+#define SW_MANUAL_EN_SFT 0
+#define SW_MANUAL_EN_HI 0
+#define SW_MANUAL_EN_SZ 1
+#define SW_WL_TX_MSK 0x00000002
+#define SW_WL_TX_I_MSK 0xfffffffd
+#define SW_WL_TX_SFT 1
+#define SW_WL_TX_HI 1
+#define SW_WL_TX_SZ 1
+#define SW_WL_RX_MSK 0x00000004
+#define SW_WL_RX_I_MSK 0xfffffffb
+#define SW_WL_RX_SFT 2
+#define SW_WL_RX_HI 2
+#define SW_WL_RX_SZ 1
+#define SW_BT_TRX_MSK 0x00000008
+#define SW_BT_TRX_I_MSK 0xfffffff7
+#define SW_BT_TRX_SFT 3
+#define SW_BT_TRX_HI 3
+#define SW_BT_TRX_SZ 1
+#define BT_TXBAR_MANUAL_EN_MSK 0x00000010
+#define BT_TXBAR_MANUAL_EN_I_MSK 0xffffffef
+#define BT_TXBAR_MANUAL_EN_SFT 4
+#define BT_TXBAR_MANUAL_EN_HI 4
+#define BT_TXBAR_MANUAL_EN_SZ 1
+#define BT_TXBAR_SET_MSK 0x00000020
+#define BT_TXBAR_SET_I_MSK 0xffffffdf
+#define BT_TXBAR_SET_SFT 5
+#define BT_TXBAR_SET_HI 5
+#define BT_TXBAR_SET_SZ 1
+#define BT_BUSY_MANUAL_EN_MSK 0x00000100
+#define BT_BUSY_MANUAL_EN_I_MSK 0xfffffeff
+#define BT_BUSY_MANUAL_EN_SFT 8
+#define BT_BUSY_MANUAL_EN_HI 8
+#define BT_BUSY_MANUAL_EN_SZ 1
+#define BT_BUSY_SET_MSK 0x00000200
+#define BT_BUSY_SET_I_MSK 0xfffffdff
+#define BT_BUSY_SET_SFT 9
+#define BT_BUSY_SET_HI 9
+#define BT_BUSY_SET_SZ 1
+#define G0_PKT_CLS_MIB_EN_MSK 0x00000004
+#define G0_PKT_CLS_MIB_EN_I_MSK 0xfffffffb
+#define G0_PKT_CLS_MIB_EN_SFT 2
+#define G0_PKT_CLS_MIB_EN_HI 2
+#define G0_PKT_CLS_MIB_EN_SZ 1
+#define G0_PKT_CLS_ONGOING_MSK 0x00000008
+#define G0_PKT_CLS_ONGOING_I_MSK 0xfffffff7
+#define G0_PKT_CLS_ONGOING_SFT 3
+#define G0_PKT_CLS_ONGOING_HI 3
+#define G0_PKT_CLS_ONGOING_SZ 1
+#define G1_PKT_CLS_MIB_EN_MSK 0x00000010
+#define G1_PKT_CLS_MIB_EN_I_MSK 0xffffffef
+#define G1_PKT_CLS_MIB_EN_SFT 4
+#define G1_PKT_CLS_MIB_EN_HI 4
+#define G1_PKT_CLS_MIB_EN_SZ 1
+#define G1_PKT_CLS_ONGOING_MSK 0x00000020
+#define G1_PKT_CLS_ONGOING_I_MSK 0xffffffdf
+#define G1_PKT_CLS_ONGOING_SFT 5
+#define G1_PKT_CLS_ONGOING_HI 5
+#define G1_PKT_CLS_ONGOING_SZ 1
+#define Q0_PKT_CLS_MIB_EN_MSK 0x00000040
+#define Q0_PKT_CLS_MIB_EN_I_MSK 0xffffffbf
+#define Q0_PKT_CLS_MIB_EN_SFT 6
+#define Q0_PKT_CLS_MIB_EN_HI 6
+#define Q0_PKT_CLS_MIB_EN_SZ 1
+#define Q0_PKT_CLS_ONGOING_MSK 0x00000080
+#define Q0_PKT_CLS_ONGOING_I_MSK 0xffffff7f
+#define Q0_PKT_CLS_ONGOING_SFT 7
+#define Q0_PKT_CLS_ONGOING_HI 7
+#define Q0_PKT_CLS_ONGOING_SZ 1
+#define Q1_PKT_CLS_MIB_EN_MSK 0x00000100
+#define Q1_PKT_CLS_MIB_EN_I_MSK 0xfffffeff
+#define Q1_PKT_CLS_MIB_EN_SFT 8
+#define Q1_PKT_CLS_MIB_EN_HI 8
+#define Q1_PKT_CLS_MIB_EN_SZ 1
+#define Q1_PKT_CLS_ONGOING_MSK 0x00000200
+#define Q1_PKT_CLS_ONGOING_I_MSK 0xfffffdff
+#define Q1_PKT_CLS_ONGOING_SFT 9
+#define Q1_PKT_CLS_ONGOING_HI 9
+#define Q1_PKT_CLS_ONGOING_SZ 1
+#define Q2_PKT_CLS_MIB_EN_MSK 0x00000400
+#define Q2_PKT_CLS_MIB_EN_I_MSK 0xfffffbff
+#define Q2_PKT_CLS_MIB_EN_SFT 10
+#define Q2_PKT_CLS_MIB_EN_HI 10
+#define Q2_PKT_CLS_MIB_EN_SZ 1
+#define Q2_PKT_CLS_ONGOING_MSK 0x00000800
+#define Q2_PKT_CLS_ONGOING_I_MSK 0xfffff7ff
+#define Q2_PKT_CLS_ONGOING_SFT 11
+#define Q2_PKT_CLS_ONGOING_HI 11
+#define Q2_PKT_CLS_ONGOING_SZ 1
+#define Q3_PKT_CLS_MIB_EN_MSK 0x00001000
+#define Q3_PKT_CLS_MIB_EN_I_MSK 0xffffefff
+#define Q3_PKT_CLS_MIB_EN_SFT 12
+#define Q3_PKT_CLS_MIB_EN_HI 12
+#define Q3_PKT_CLS_MIB_EN_SZ 1
+#define Q3_PKT_CLS_ONGOING_MSK 0x00002000
+#define Q3_PKT_CLS_ONGOING_I_MSK 0xffffdfff
+#define Q3_PKT_CLS_ONGOING_SFT 13
+#define Q3_PKT_CLS_ONGOING_HI 13
+#define Q3_PKT_CLS_ONGOING_SZ 1
+#define SCRT_PKT_CLS_MIB_EN_MSK 0x00004000
+#define SCRT_PKT_CLS_MIB_EN_I_MSK 0xffffbfff
+#define SCRT_PKT_CLS_MIB_EN_SFT 14
+#define SCRT_PKT_CLS_MIB_EN_HI 14
+#define SCRT_PKT_CLS_MIB_EN_SZ 1
+#define SCRT_PKT_CLS_ONGOING_MSK 0x00008000
+#define SCRT_PKT_CLS_ONGOING_I_MSK 0xffff7fff
+#define SCRT_PKT_CLS_ONGOING_SFT 15
+#define SCRT_PKT_CLS_ONGOING_HI 15
+#define SCRT_PKT_CLS_ONGOING_SZ 1
+#define MISC_PKT_CLS_MIB_EN_MSK 0x00010000
+#define MISC_PKT_CLS_MIB_EN_I_MSK 0xfffeffff
+#define MISC_PKT_CLS_MIB_EN_SFT 16
+#define MISC_PKT_CLS_MIB_EN_HI 16
+#define MISC_PKT_CLS_MIB_EN_SZ 1
+#define MISC_PKT_CLS_ONGOING_MSK 0x00020000
+#define MISC_PKT_CLS_ONGOING_I_MSK 0xfffdffff
+#define MISC_PKT_CLS_ONGOING_SFT 17
+#define MISC_PKT_CLS_ONGOING_HI 17
+#define MISC_PKT_CLS_ONGOING_SZ 1
+#define MTX_WSID0_SUCC_MSK 0x0000ffff
+#define MTX_WSID0_SUCC_I_MSK 0xffff0000
+#define MTX_WSID0_SUCC_SFT 0
+#define MTX_WSID0_SUCC_HI 15
+#define MTX_WSID0_SUCC_SZ 16
+#define MTX_WSID0_FRM_MSK 0x0000ffff
+#define MTX_WSID0_FRM_I_MSK 0xffff0000
+#define MTX_WSID0_FRM_SFT 0
+#define MTX_WSID0_FRM_HI 15
+#define MTX_WSID0_FRM_SZ 16
+#define MTX_WSID0_RETRY_MSK 0x0000ffff
+#define MTX_WSID0_RETRY_I_MSK 0xffff0000
+#define MTX_WSID0_RETRY_SFT 0
+#define MTX_WSID0_RETRY_HI 15
+#define MTX_WSID0_RETRY_SZ 16
+#define MTX_WSID0_TOTAL_MSK 0x0000ffff
+#define MTX_WSID0_TOTAL_I_MSK 0xffff0000
+#define MTX_WSID0_TOTAL_SFT 0
+#define MTX_WSID0_TOTAL_HI 15
+#define MTX_WSID0_TOTAL_SZ 16
+#define MTX_GRP_MSK 0x000fffff
+#define MTX_GRP_I_MSK 0xfff00000
+#define MTX_GRP_SFT 0
+#define MTX_GRP_HI 19
+#define MTX_GRP_SZ 20
+#define MTX_FAIL_MSK 0x0000ffff
+#define MTX_FAIL_I_MSK 0xffff0000
+#define MTX_FAIL_SFT 0
+#define MTX_FAIL_HI 15
+#define MTX_FAIL_SZ 16
+#define MTX_RETRY_MSK 0x000fffff
+#define MTX_RETRY_I_MSK 0xfff00000
+#define MTX_RETRY_SFT 0
+#define MTX_RETRY_HI 19
+#define MTX_RETRY_SZ 20
+#define MTX_MULTI_RETRY_MSK 0x000fffff
+#define MTX_MULTI_RETRY_I_MSK 0xfff00000
+#define MTX_MULTI_RETRY_SFT 0
+#define MTX_MULTI_RETRY_HI 19
+#define MTX_MULTI_RETRY_SZ 20
+#define MTX_RTS_SUCC_MSK 0x0000ffff
+#define MTX_RTS_SUCC_I_MSK 0xffff0000
+#define MTX_RTS_SUCC_SFT 0
+#define MTX_RTS_SUCC_HI 15
+#define MTX_RTS_SUCC_SZ 16
+#define MTX_RTS_FAIL_MSK 0x0000ffff
+#define MTX_RTS_FAIL_I_MSK 0xffff0000
+#define MTX_RTS_FAIL_SFT 0
+#define MTX_RTS_FAIL_HI 15
+#define MTX_RTS_FAIL_SZ 16
+#define MTX_ACK_FAIL_MSK 0x0000ffff
+#define MTX_ACK_FAIL_I_MSK 0xffff0000
+#define MTX_ACK_FAIL_SFT 0
+#define MTX_ACK_FAIL_HI 15
+#define MTX_ACK_FAIL_SZ 16
+#define MTX_FRM_MSK 0x000fffff
+#define MTX_FRM_I_MSK 0xfff00000
+#define MTX_FRM_SFT 0
+#define MTX_FRM_HI 19
+#define MTX_FRM_SZ 20
+#define MTX_ACK_TX_MSK 0x0000ffff
+#define MTX_ACK_TX_I_MSK 0xffff0000
+#define MTX_ACK_TX_SFT 0
+#define MTX_ACK_TX_HI 15
+#define MTX_ACK_TX_SZ 16
+#define MTX_CTS_TX_MSK 0x0000ffff
+#define MTX_CTS_TX_I_MSK 0xffff0000
+#define MTX_CTS_TX_SFT 0
+#define MTX_CTS_TX_HI 15
+#define MTX_CTS_TX_SZ 16
+#define MRX_DUP_MSK 0x0000ffff
+#define MRX_DUP_I_MSK 0xffff0000
+#define MRX_DUP_SFT 0
+#define MRX_DUP_HI 15
+#define MRX_DUP_SZ 16
+#define MRX_FRG_MSK 0x000fffff
+#define MRX_FRG_I_MSK 0xfff00000
+#define MRX_FRG_SFT 0
+#define MRX_FRG_HI 19
+#define MRX_FRG_SZ 20
+#define MRX_GRP_MSK 0x000fffff
+#define MRX_GRP_I_MSK 0xfff00000
+#define MRX_GRP_SFT 0
+#define MRX_GRP_HI 19
+#define MRX_GRP_SZ 20
+#define MRX_FCS_ERR_MSK 0x0000ffff
+#define MRX_FCS_ERR_I_MSK 0xffff0000
+#define MRX_FCS_ERR_SFT 0
+#define MRX_FCS_ERR_HI 15
+#define MRX_FCS_ERR_SZ 16
+#define MRX_FCS_SUC_MSK 0x0000ffff
+#define MRX_FCS_SUC_I_MSK 0xffff0000
+#define MRX_FCS_SUC_SFT 0
+#define MRX_FCS_SUC_HI 15
+#define MRX_FCS_SUC_SZ 16
+#define MRX_MISS_MSK 0x0000ffff
+#define MRX_MISS_I_MSK 0xffff0000
+#define MRX_MISS_SFT 0
+#define MRX_MISS_HI 15
+#define MRX_MISS_SZ 16
+#define MRX_ALC_FAIL_MSK 0x0000ffff
+#define MRX_ALC_FAIL_I_MSK 0xffff0000
+#define MRX_ALC_FAIL_SFT 0
+#define MRX_ALC_FAIL_HI 15
+#define MRX_ALC_FAIL_SZ 16
+#define MRX_DAT_NTF_MSK 0x0000ffff
+#define MRX_DAT_NTF_I_MSK 0xffff0000
+#define MRX_DAT_NTF_SFT 0
+#define MRX_DAT_NTF_HI 15
+#define MRX_DAT_NTF_SZ 16
+#define MRX_RTS_NTF_MSK 0x0000ffff
+#define MRX_RTS_NTF_I_MSK 0xffff0000
+#define MRX_RTS_NTF_SFT 0
+#define MRX_RTS_NTF_HI 15
+#define MRX_RTS_NTF_SZ 16
+#define MRX_CTS_NTF_MSK 0x0000ffff
+#define MRX_CTS_NTF_I_MSK 0xffff0000
+#define MRX_CTS_NTF_SFT 0
+#define MRX_CTS_NTF_HI 15
+#define MRX_CTS_NTF_SZ 16
+#define MRX_ACK_NTF_MSK 0x0000ffff
+#define MRX_ACK_NTF_I_MSK 0xffff0000
+#define MRX_ACK_NTF_SFT 0
+#define MRX_ACK_NTF_HI 15
+#define MRX_ACK_NTF_SZ 16
+#define MRX_BA_NTF_MSK 0x0000ffff
+#define MRX_BA_NTF_I_MSK 0xffff0000
+#define MRX_BA_NTF_SFT 0
+#define MRX_BA_NTF_HI 15
+#define MRX_BA_NTF_SZ 16
+#define MRX_DATA_NTF_MSK 0x0000ffff
+#define MRX_DATA_NTF_I_MSK 0xffff0000
+#define MRX_DATA_NTF_SFT 0
+#define MRX_DATA_NTF_HI 15
+#define MRX_DATA_NTF_SZ 16
+#define MRX_MNG_NTF_MSK 0x0000ffff
+#define MRX_MNG_NTF_I_MSK 0xffff0000
+#define MRX_MNG_NTF_SFT 0
+#define MRX_MNG_NTF_HI 15
+#define MRX_MNG_NTF_SZ 16
+#define MRX_DAT_CRC_NTF_MSK 0x0000ffff
+#define MRX_DAT_CRC_NTF_I_MSK 0xffff0000
+#define MRX_DAT_CRC_NTF_SFT 0
+#define MRX_DAT_CRC_NTF_HI 15
+#define MRX_DAT_CRC_NTF_SZ 16
+#define MRX_BAR_NTF_MSK 0x0000ffff
+#define MRX_BAR_NTF_I_MSK 0xffff0000
+#define MRX_BAR_NTF_SFT 0
+#define MRX_BAR_NTF_HI 15
+#define MRX_BAR_NTF_SZ 16
+#define MRX_MB_MISS_MSK 0x0000ffff
+#define MRX_MB_MISS_I_MSK 0xffff0000
+#define MRX_MB_MISS_SFT 0
+#define MRX_MB_MISS_HI 15
+#define MRX_MB_MISS_SZ 16
+#define MRX_NIDLE_MISS_MSK 0x0000ffff
+#define MRX_NIDLE_MISS_I_MSK 0xffff0000
+#define MRX_NIDLE_MISS_SFT 0
+#define MRX_NIDLE_MISS_HI 15
+#define MRX_NIDLE_MISS_SZ 16
+#define MRX_CSR_NTF_MSK 0x0000ffff
+#define MRX_CSR_NTF_I_MSK 0xffff0000
+#define MRX_CSR_NTF_SFT 0
+#define MRX_CSR_NTF_HI 15
+#define MRX_CSR_NTF_SZ 16
+#define DBG_Q0_SUCC_MSK 0x0000ffff
+#define DBG_Q0_SUCC_I_MSK 0xffff0000
+#define DBG_Q0_SUCC_SFT 0
+#define DBG_Q0_SUCC_HI 15
+#define DBG_Q0_SUCC_SZ 16
+#define DBG_Q0_FAIL_MSK 0x0000ffff
+#define DBG_Q0_FAIL_I_MSK 0xffff0000
+#define DBG_Q0_FAIL_SFT 0
+#define DBG_Q0_FAIL_HI 15
+#define DBG_Q0_FAIL_SZ 16
+#define DBG_Q0_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q0_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q0_ACK_SUCC_SFT 0
+#define DBG_Q0_ACK_SUCC_HI 15
+#define DBG_Q0_ACK_SUCC_SZ 16
+#define DBG_Q0_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q0_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q0_ACK_FAIL_SFT 0
+#define DBG_Q0_ACK_FAIL_HI 15
+#define DBG_Q0_ACK_FAIL_SZ 16
+#define DBG_Q1_SUCC_MSK 0x0000ffff
+#define DBG_Q1_SUCC_I_MSK 0xffff0000
+#define DBG_Q1_SUCC_SFT 0
+#define DBG_Q1_SUCC_HI 15
+#define DBG_Q1_SUCC_SZ 16
+#define DBG_Q1_FAIL_MSK 0x0000ffff
+#define DBG_Q1_FAIL_I_MSK 0xffff0000
+#define DBG_Q1_FAIL_SFT 0
+#define DBG_Q1_FAIL_HI 15
+#define DBG_Q1_FAIL_SZ 16
+#define DBG_Q1_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q1_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q1_ACK_SUCC_SFT 0
+#define DBG_Q1_ACK_SUCC_HI 15
+#define DBG_Q1_ACK_SUCC_SZ 16
+#define DBG_Q1_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q1_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q1_ACK_FAIL_SFT 0
+#define DBG_Q1_ACK_FAIL_HI 15
+#define DBG_Q1_ACK_FAIL_SZ 16
+#define DBG_Q2_SUCC_MSK 0x0000ffff
+#define DBG_Q2_SUCC_I_MSK 0xffff0000
+#define DBG_Q2_SUCC_SFT 0
+#define DBG_Q2_SUCC_HI 15
+#define DBG_Q2_SUCC_SZ 16
+#define DBG_Q2_FAIL_MSK 0x0000ffff
+#define DBG_Q2_FAIL_I_MSK 0xffff0000
+#define DBG_Q2_FAIL_SFT 0
+#define DBG_Q2_FAIL_HI 15
+#define DBG_Q2_FAIL_SZ 16
+#define DBG_Q2_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q2_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q2_ACK_SUCC_SFT 0
+#define DBG_Q2_ACK_SUCC_HI 15
+#define DBG_Q2_ACK_SUCC_SZ 16
+#define DBG_Q2_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q2_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q2_ACK_FAIL_SFT 0
+#define DBG_Q2_ACK_FAIL_HI 15
+#define DBG_Q2_ACK_FAIL_SZ 16
+#define DBG_Q3_SUCC_MSK 0x0000ffff
+#define DBG_Q3_SUCC_I_MSK 0xffff0000
+#define DBG_Q3_SUCC_SFT 0
+#define DBG_Q3_SUCC_HI 15
+#define DBG_Q3_SUCC_SZ 16
+#define DBG_Q3_FAIL_MSK 0x0000ffff
+#define DBG_Q3_FAIL_I_MSK 0xffff0000
+#define DBG_Q3_FAIL_SFT 0
+#define DBG_Q3_FAIL_HI 15
+#define DBG_Q3_FAIL_SZ 16
+#define DBG_Q3_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q3_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q3_ACK_SUCC_SFT 0
+#define DBG_Q3_ACK_SUCC_HI 15
+#define DBG_Q3_ACK_SUCC_SZ 16
+#define DBG_Q3_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q3_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q3_ACK_FAIL_SFT 0
+#define DBG_Q3_ACK_FAIL_HI 15
+#define DBG_Q3_ACK_FAIL_SZ 16
+#define SCRT_TKIP_CERR_MSK 0x000fffff
+#define SCRT_TKIP_CERR_I_MSK 0xfff00000
+#define SCRT_TKIP_CERR_SFT 0
+#define SCRT_TKIP_CERR_HI 19
+#define SCRT_TKIP_CERR_SZ 20
+#define SCRT_TKIP_MIC_ERR_MSK 0x000fffff
+#define SCRT_TKIP_MIC_ERR_I_MSK 0xfff00000
+#define SCRT_TKIP_MIC_ERR_SFT 0
+#define SCRT_TKIP_MIC_ERR_HI 19
+#define SCRT_TKIP_MIC_ERR_SZ 20
+#define SCRT_TKIP_RPLY_MSK 0x000fffff
+#define SCRT_TKIP_RPLY_I_MSK 0xfff00000
+#define SCRT_TKIP_RPLY_SFT 0
+#define SCRT_TKIP_RPLY_HI 19
+#define SCRT_TKIP_RPLY_SZ 20
+#define SCRT_CCMP_RPLY_MSK 0x000fffff
+#define SCRT_CCMP_RPLY_I_MSK 0xfff00000
+#define SCRT_CCMP_RPLY_SFT 0
+#define SCRT_CCMP_RPLY_HI 19
+#define SCRT_CCMP_RPLY_SZ 20
+#define SCRT_CCMP_CERR_MSK 0x000fffff
+#define SCRT_CCMP_CERR_I_MSK 0xfff00000
+#define SCRT_CCMP_CERR_SFT 0
+#define SCRT_CCMP_CERR_HI 19
+#define SCRT_CCMP_CERR_SZ 20
+#define DBG_LEN_CRC_FAIL_MSK 0x0000ffff
+#define DBG_LEN_CRC_FAIL_I_MSK 0xffff0000
+#define DBG_LEN_CRC_FAIL_SFT 0
+#define DBG_LEN_CRC_FAIL_HI 15
+#define DBG_LEN_CRC_FAIL_SZ 16
+#define DBG_LEN_ALC_FAIL_MSK 0x0000ffff
+#define DBG_LEN_ALC_FAIL_I_MSK 0xffff0000
+#define DBG_LEN_ALC_FAIL_SFT 0
+#define DBG_LEN_ALC_FAIL_HI 15
+#define DBG_LEN_ALC_FAIL_SZ 16
+#define DBG_AMPDU_PASS_MSK 0x0000ffff
+#define DBG_AMPDU_PASS_I_MSK 0xffff0000
+#define DBG_AMPDU_PASS_SFT 0
+#define DBG_AMPDU_PASS_HI 15
+#define DBG_AMPDU_PASS_SZ 16
+#define DBG_AMPDU_FAIL_MSK 0x0000ffff
+#define DBG_AMPDU_FAIL_I_MSK 0xffff0000
+#define DBG_AMPDU_FAIL_SFT 0
+#define DBG_AMPDU_FAIL_HI 15
+#define DBG_AMPDU_FAIL_SZ 16
+#define RXID_ALC_CNT_FAIL_MSK 0x0000ffff
+#define RXID_ALC_CNT_FAIL_I_MSK 0xffff0000
+#define RXID_ALC_CNT_FAIL_SFT 0
+#define RXID_ALC_CNT_FAIL_HI 15
+#define RXID_ALC_CNT_FAIL_SZ 16
+#define RXID_ALC_LEN_FAIL_MSK 0x0000ffff
+#define RXID_ALC_LEN_FAIL_I_MSK 0xffff0000
+#define RXID_ALC_LEN_FAIL_SFT 0
+#define RXID_ALC_LEN_FAIL_HI 15
+#define RXID_ALC_LEN_FAIL_SZ 16
+#define CBR_RG_EN_MANUAL_MSK 0x00000001
+#define CBR_RG_EN_MANUAL_I_MSK 0xfffffffe
+#define CBR_RG_EN_MANUAL_SFT 0
+#define CBR_RG_EN_MANUAL_HI 0
+#define CBR_RG_EN_MANUAL_SZ 1
+#define CBR_RG_TX_EN_MSK 0x00000002
+#define CBR_RG_TX_EN_I_MSK 0xfffffffd
+#define CBR_RG_TX_EN_SFT 1
+#define CBR_RG_TX_EN_HI 1
+#define CBR_RG_TX_EN_SZ 1
+#define CBR_RG_TX_PA_EN_MSK 0x00000004
+#define CBR_RG_TX_PA_EN_I_MSK 0xfffffffb
+#define CBR_RG_TX_PA_EN_SFT 2
+#define CBR_RG_TX_PA_EN_HI 2
+#define CBR_RG_TX_PA_EN_SZ 1
+#define CBR_RG_TX_DAC_EN_MSK 0x00000008
+#define CBR_RG_TX_DAC_EN_I_MSK 0xfffffff7
+#define CBR_RG_TX_DAC_EN_SFT 3
+#define CBR_RG_TX_DAC_EN_HI 3
+#define CBR_RG_TX_DAC_EN_SZ 1
+#define CBR_RG_RX_AGC_MSK 0x00000010
+#define CBR_RG_RX_AGC_I_MSK 0xffffffef
+#define CBR_RG_RX_AGC_SFT 4
+#define CBR_RG_RX_AGC_HI 4
+#define CBR_RG_RX_AGC_SZ 1
+#define CBR_RG_RX_GAIN_MANUAL_MSK 0x00000020
+#define CBR_RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
+#define CBR_RG_RX_GAIN_MANUAL_SFT 5
+#define CBR_RG_RX_GAIN_MANUAL_HI 5
+#define CBR_RG_RX_GAIN_MANUAL_SZ 1
+#define CBR_RG_RFG_MSK 0x000000c0
+#define CBR_RG_RFG_I_MSK 0xffffff3f
+#define CBR_RG_RFG_SFT 6
+#define CBR_RG_RFG_HI 7
+#define CBR_RG_RFG_SZ 2
+#define CBR_RG_PGAG_MSK 0x00000f00
+#define CBR_RG_PGAG_I_MSK 0xfffff0ff
+#define CBR_RG_PGAG_SFT 8
+#define CBR_RG_PGAG_HI 11
+#define CBR_RG_PGAG_SZ 4
+#define CBR_RG_MODE_MSK 0x00003000
+#define CBR_RG_MODE_I_MSK 0xffffcfff
+#define CBR_RG_MODE_SFT 12
+#define CBR_RG_MODE_HI 13
+#define CBR_RG_MODE_SZ 2
+#define CBR_RG_EN_TX_TRSW_MSK 0x00004000
+#define CBR_RG_EN_TX_TRSW_I_MSK 0xffffbfff
+#define CBR_RG_EN_TX_TRSW_SFT 14
+#define CBR_RG_EN_TX_TRSW_HI 14
+#define CBR_RG_EN_TX_TRSW_SZ 1
+#define CBR_RG_EN_SX_MSK 0x00008000
+#define CBR_RG_EN_SX_I_MSK 0xffff7fff
+#define CBR_RG_EN_SX_SFT 15
+#define CBR_RG_EN_SX_HI 15
+#define CBR_RG_EN_SX_SZ 1
+#define CBR_RG_EN_RX_LNA_MSK 0x00010000
+#define CBR_RG_EN_RX_LNA_I_MSK 0xfffeffff
+#define CBR_RG_EN_RX_LNA_SFT 16
+#define CBR_RG_EN_RX_LNA_HI 16
+#define CBR_RG_EN_RX_LNA_SZ 1
+#define CBR_RG_EN_RX_MIXER_MSK 0x00020000
+#define CBR_RG_EN_RX_MIXER_I_MSK 0xfffdffff
+#define CBR_RG_EN_RX_MIXER_SFT 17
+#define CBR_RG_EN_RX_MIXER_HI 17
+#define CBR_RG_EN_RX_MIXER_SZ 1
+#define CBR_RG_EN_RX_DIV2_MSK 0x00040000
+#define CBR_RG_EN_RX_DIV2_I_MSK 0xfffbffff
+#define CBR_RG_EN_RX_DIV2_SFT 18
+#define CBR_RG_EN_RX_DIV2_HI 18
+#define CBR_RG_EN_RX_DIV2_SZ 1
+#define CBR_RG_EN_RX_LOBUF_MSK 0x00080000
+#define CBR_RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
+#define CBR_RG_EN_RX_LOBUF_SFT 19
+#define CBR_RG_EN_RX_LOBUF_HI 19
+#define CBR_RG_EN_RX_LOBUF_SZ 1
+#define CBR_RG_EN_RX_TZ_MSK 0x00100000
+#define CBR_RG_EN_RX_TZ_I_MSK 0xffefffff
+#define CBR_RG_EN_RX_TZ_SFT 20
+#define CBR_RG_EN_RX_TZ_HI 20
+#define CBR_RG_EN_RX_TZ_SZ 1
+#define CBR_RG_EN_RX_FILTER_MSK 0x00200000
+#define CBR_RG_EN_RX_FILTER_I_MSK 0xffdfffff
+#define CBR_RG_EN_RX_FILTER_SFT 21
+#define CBR_RG_EN_RX_FILTER_HI 21
+#define CBR_RG_EN_RX_FILTER_SZ 1
+#define CBR_RG_EN_RX_HPF_MSK 0x00400000
+#define CBR_RG_EN_RX_HPF_I_MSK 0xffbfffff
+#define CBR_RG_EN_RX_HPF_SFT 22
+#define CBR_RG_EN_RX_HPF_HI 22
+#define CBR_RG_EN_RX_HPF_SZ 1
+#define CBR_RG_EN_RX_RSSI_MSK 0x00800000
+#define CBR_RG_EN_RX_RSSI_I_MSK 0xff7fffff
+#define CBR_RG_EN_RX_RSSI_SFT 23
+#define CBR_RG_EN_RX_RSSI_HI 23
+#define CBR_RG_EN_RX_RSSI_SZ 1
+#define CBR_RG_EN_ADC_MSK 0x01000000
+#define CBR_RG_EN_ADC_I_MSK 0xfeffffff
+#define CBR_RG_EN_ADC_SFT 24
+#define CBR_RG_EN_ADC_HI 24
+#define CBR_RG_EN_ADC_SZ 1
+#define CBR_RG_EN_TX_MOD_MSK 0x02000000
+#define CBR_RG_EN_TX_MOD_I_MSK 0xfdffffff
+#define CBR_RG_EN_TX_MOD_SFT 25
+#define CBR_RG_EN_TX_MOD_HI 25
+#define CBR_RG_EN_TX_MOD_SZ 1
+#define CBR_RG_EN_TX_DIV2_MSK 0x04000000
+#define CBR_RG_EN_TX_DIV2_I_MSK 0xfbffffff
+#define CBR_RG_EN_TX_DIV2_SFT 26
+#define CBR_RG_EN_TX_DIV2_HI 26
+#define CBR_RG_EN_TX_DIV2_SZ 1
+#define CBR_RG_EN_TX_DIV2_BUF_MSK 0x08000000
+#define CBR_RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
+#define CBR_RG_EN_TX_DIV2_BUF_SFT 27
+#define CBR_RG_EN_TX_DIV2_BUF_HI 27
+#define CBR_RG_EN_TX_DIV2_BUF_SZ 1
+#define CBR_RG_EN_TX_LOBF_MSK 0x10000000
+#define CBR_RG_EN_TX_LOBF_I_MSK 0xefffffff
+#define CBR_RG_EN_TX_LOBF_SFT 28
+#define CBR_RG_EN_TX_LOBF_HI 28
+#define CBR_RG_EN_TX_LOBF_SZ 1
+#define CBR_RG_EN_RX_LOBF_MSK 0x20000000
+#define CBR_RG_EN_RX_LOBF_I_MSK 0xdfffffff
+#define CBR_RG_EN_RX_LOBF_SFT 29
+#define CBR_RG_EN_RX_LOBF_HI 29
+#define CBR_RG_EN_RX_LOBF_SZ 1
+#define CBR_RG_SEL_DPLL_CLK_MSK 0x40000000
+#define CBR_RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
+#define CBR_RG_SEL_DPLL_CLK_SFT 30
+#define CBR_RG_SEL_DPLL_CLK_HI 30
+#define CBR_RG_SEL_DPLL_CLK_SZ 1
+#define CBR_RG_EN_TX_DPD_MSK 0x00000001
+#define CBR_RG_EN_TX_DPD_I_MSK 0xfffffffe
+#define CBR_RG_EN_TX_DPD_SFT 0
+#define CBR_RG_EN_TX_DPD_HI 0
+#define CBR_RG_EN_TX_DPD_SZ 1
+#define CBR_RG_EN_TX_TSSI_MSK 0x00000002
+#define CBR_RG_EN_TX_TSSI_I_MSK 0xfffffffd
+#define CBR_RG_EN_TX_TSSI_SFT 1
+#define CBR_RG_EN_TX_TSSI_HI 1
+#define CBR_RG_EN_TX_TSSI_SZ 1
+#define CBR_RG_EN_RX_IQCAL_MSK 0x00000004
+#define CBR_RG_EN_RX_IQCAL_I_MSK 0xfffffffb
+#define CBR_RG_EN_RX_IQCAL_SFT 2
+#define CBR_RG_EN_RX_IQCAL_HI 2
+#define CBR_RG_EN_RX_IQCAL_SZ 1
+#define CBR_RG_EN_TX_DAC_CAL_MSK 0x00000008
+#define CBR_RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
+#define CBR_RG_EN_TX_DAC_CAL_SFT 3
+#define CBR_RG_EN_TX_DAC_CAL_HI 3
+#define CBR_RG_EN_TX_DAC_CAL_SZ 1
+#define CBR_RG_EN_TX_SELF_MIXER_MSK 0x00000010
+#define CBR_RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
+#define CBR_RG_EN_TX_SELF_MIXER_SFT 4
+#define CBR_RG_EN_TX_SELF_MIXER_HI 4
+#define CBR_RG_EN_TX_SELF_MIXER_SZ 1
+#define CBR_RG_EN_TX_DAC_OUT_MSK 0x00000020
+#define CBR_RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
+#define CBR_RG_EN_TX_DAC_OUT_SFT 5
+#define CBR_RG_EN_TX_DAC_OUT_HI 5
+#define CBR_RG_EN_TX_DAC_OUT_SZ 1
+#define CBR_RG_EN_LDO_RX_FE_MSK 0x00000040
+#define CBR_RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
+#define CBR_RG_EN_LDO_RX_FE_SFT 6
+#define CBR_RG_EN_LDO_RX_FE_HI 6
+#define CBR_RG_EN_LDO_RX_FE_SZ 1
+#define CBR_RG_EN_LDO_ABB_MSK 0x00000080
+#define CBR_RG_EN_LDO_ABB_I_MSK 0xffffff7f
+#define CBR_RG_EN_LDO_ABB_SFT 7
+#define CBR_RG_EN_LDO_ABB_HI 7
+#define CBR_RG_EN_LDO_ABB_SZ 1
+#define CBR_RG_EN_LDO_AFE_MSK 0x00000100
+#define CBR_RG_EN_LDO_AFE_I_MSK 0xfffffeff
+#define CBR_RG_EN_LDO_AFE_SFT 8
+#define CBR_RG_EN_LDO_AFE_HI 8
+#define CBR_RG_EN_LDO_AFE_SZ 1
+#define CBR_RG_EN_SX_CHPLDO_MSK 0x00000200
+#define CBR_RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
+#define CBR_RG_EN_SX_CHPLDO_SFT 9
+#define CBR_RG_EN_SX_CHPLDO_HI 9
+#define CBR_RG_EN_SX_CHPLDO_SZ 1
+#define CBR_RG_EN_SX_LOBFLDO_MSK 0x00000400
+#define CBR_RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
+#define CBR_RG_EN_SX_LOBFLDO_SFT 10
+#define CBR_RG_EN_SX_LOBFLDO_HI 10
+#define CBR_RG_EN_SX_LOBFLDO_SZ 1
+#define CBR_RG_EN_IREF_RX_MSK 0x00000800
+#define CBR_RG_EN_IREF_RX_I_MSK 0xfffff7ff
+#define CBR_RG_EN_IREF_RX_SFT 11
+#define CBR_RG_EN_IREF_RX_HI 11
+#define CBR_RG_EN_IREF_RX_SZ 1
+#define CBR_RG_DCDC_MODE_MSK 0x00001000
+#define CBR_RG_DCDC_MODE_I_MSK 0xffffefff
+#define CBR_RG_DCDC_MODE_SFT 12
+#define CBR_RG_DCDC_MODE_HI 12
+#define CBR_RG_DCDC_MODE_SZ 1
+#define CBR_RG_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define CBR_RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define CBR_RG_LDO_LEVEL_RX_FE_SFT 0
+#define CBR_RG_LDO_LEVEL_RX_FE_HI 2
+#define CBR_RG_LDO_LEVEL_RX_FE_SZ 3
+#define CBR_RG_LDO_LEVEL_ABB_MSK 0x00000038
+#define CBR_RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
+#define CBR_RG_LDO_LEVEL_ABB_SFT 3
+#define CBR_RG_LDO_LEVEL_ABB_HI 5
+#define CBR_RG_LDO_LEVEL_ABB_SZ 3
+#define CBR_RG_LDO_LEVEL_AFE_MSK 0x000001c0
+#define CBR_RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
+#define CBR_RG_LDO_LEVEL_AFE_SFT 6
+#define CBR_RG_LDO_LEVEL_AFE_HI 8
+#define CBR_RG_LDO_LEVEL_AFE_SZ 3
+#define CBR_RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
+#define CBR_RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
+#define CBR_RG_SX_LDO_CHP_LEVEL_SFT 9
+#define CBR_RG_SX_LDO_CHP_LEVEL_HI 11
+#define CBR_RG_SX_LDO_CHP_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
+#define CBR_RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
+#define CBR_RG_SX_LDO_LOBF_LEVEL_SFT 12
+#define CBR_RG_SX_LDO_LOBF_LEVEL_HI 14
+#define CBR_RG_SX_LDO_LOBF_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
+#define CBR_RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
+#define CBR_RG_SX_LDO_XOSC_LEVEL_SFT 15
+#define CBR_RG_SX_LDO_XOSC_LEVEL_HI 17
+#define CBR_RG_SX_LDO_XOSC_LEVEL_SZ 3
+#define CBR_RG_DP_LDO_LEVEL_MSK 0x001c0000
+#define CBR_RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
+#define CBR_RG_DP_LDO_LEVEL_SFT 18
+#define CBR_RG_DP_LDO_LEVEL_HI 20
+#define CBR_RG_DP_LDO_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
+#define CBR_RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
+#define CBR_RG_SX_LDO_VCO_LEVEL_SFT 21
+#define CBR_RG_SX_LDO_VCO_LEVEL_HI 23
+#define CBR_RG_SX_LDO_VCO_LEVEL_SZ 3
+#define CBR_RG_TX_LDO_TX_LEVEL_MSK 0x07000000
+#define CBR_RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
+#define CBR_RG_TX_LDO_TX_LEVEL_SFT 24
+#define CBR_RG_TX_LDO_TX_LEVEL_HI 26
+#define CBR_RG_TX_LDO_TX_LEVEL_SZ 3
+#define CBR_RG_BUCK_LEVEL_MSK 0x38000000
+#define CBR_RG_BUCK_LEVEL_I_MSK 0xc7ffffff
+#define CBR_RG_BUCK_LEVEL_SFT 27
+#define CBR_RG_BUCK_LEVEL_HI 29
+#define CBR_RG_BUCK_LEVEL_SZ 3
+#define CBR_RG_EN_RX_PADSW_MSK 0x00000001
+#define CBR_RG_EN_RX_PADSW_I_MSK 0xfffffffe
+#define CBR_RG_EN_RX_PADSW_SFT 0
+#define CBR_RG_EN_RX_PADSW_HI 0
+#define CBR_RG_EN_RX_PADSW_SZ 1
+#define CBR_RG_EN_RX_TESTNODE_MSK 0x00000002
+#define CBR_RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
+#define CBR_RG_EN_RX_TESTNODE_SFT 1
+#define CBR_RG_EN_RX_TESTNODE_HI 1
+#define CBR_RG_EN_RX_TESTNODE_SZ 1
+#define CBR_RG_RX_ABBCFIX_MSK 0x00000004
+#define CBR_RG_RX_ABBCFIX_I_MSK 0xfffffffb
+#define CBR_RG_RX_ABBCFIX_SFT 2
+#define CBR_RG_RX_ABBCFIX_HI 2
+#define CBR_RG_RX_ABBCFIX_SZ 1
+#define CBR_RG_RX_ABBCTUNE_MSK 0x000001f8
+#define CBR_RG_RX_ABBCTUNE_I_MSK 0xfffffe07
+#define CBR_RG_RX_ABBCTUNE_SFT 3
+#define CBR_RG_RX_ABBCTUNE_HI 8
+#define CBR_RG_RX_ABBCTUNE_SZ 6
+#define CBR_RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
+#define CBR_RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
+#define CBR_RG_RX_ABBOUT_TRI_STATE_SFT 9
+#define CBR_RG_RX_ABBOUT_TRI_STATE_HI 9
+#define CBR_RG_RX_ABBOUT_TRI_STATE_SZ 1
+#define CBR_RG_RX_ABB_N_MODE_MSK 0x00000400
+#define CBR_RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
+#define CBR_RG_RX_ABB_N_MODE_SFT 10
+#define CBR_RG_RX_ABB_N_MODE_HI 10
+#define CBR_RG_RX_ABB_N_MODE_SZ 1
+#define CBR_RG_RX_EN_LOOPA_MSK 0x00000800
+#define CBR_RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
+#define CBR_RG_RX_EN_LOOPA_SFT 11
+#define CBR_RG_RX_EN_LOOPA_HI 11
+#define CBR_RG_RX_EN_LOOPA_SZ 1
+#define CBR_RG_RX_FILTERI1ST_MSK 0x00003000
+#define CBR_RG_RX_FILTERI1ST_I_MSK 0xffffcfff
+#define CBR_RG_RX_FILTERI1ST_SFT 12
+#define CBR_RG_RX_FILTERI1ST_HI 13
+#define CBR_RG_RX_FILTERI1ST_SZ 2
+#define CBR_RG_RX_FILTERI2ND_MSK 0x0000c000
+#define CBR_RG_RX_FILTERI2ND_I_MSK 0xffff3fff
+#define CBR_RG_RX_FILTERI2ND_SFT 14
+#define CBR_RG_RX_FILTERI2ND_HI 15
+#define CBR_RG_RX_FILTERI2ND_SZ 2
+#define CBR_RG_RX_FILTERI3RD_MSK 0x00030000
+#define CBR_RG_RX_FILTERI3RD_I_MSK 0xfffcffff
+#define CBR_RG_RX_FILTERI3RD_SFT 16
+#define CBR_RG_RX_FILTERI3RD_HI 17
+#define CBR_RG_RX_FILTERI3RD_SZ 2
+#define CBR_RG_RX_FILTERI_COURSE_MSK 0x000c0000
+#define CBR_RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
+#define CBR_RG_RX_FILTERI_COURSE_SFT 18
+#define CBR_RG_RX_FILTERI_COURSE_HI 19
+#define CBR_RG_RX_FILTERI_COURSE_SZ 2
+#define CBR_RG_RX_FILTERVCM_MSK 0x00300000
+#define CBR_RG_RX_FILTERVCM_I_MSK 0xffcfffff
+#define CBR_RG_RX_FILTERVCM_SFT 20
+#define CBR_RG_RX_FILTERVCM_HI 21
+#define CBR_RG_RX_FILTERVCM_SZ 2
+#define CBR_RG_RX_HPF3M_MSK 0x00400000
+#define CBR_RG_RX_HPF3M_I_MSK 0xffbfffff
+#define CBR_RG_RX_HPF3M_SFT 22
+#define CBR_RG_RX_HPF3M_HI 22
+#define CBR_RG_RX_HPF3M_SZ 1
+#define CBR_RG_RX_HPF300K_MSK 0x00800000
+#define CBR_RG_RX_HPF300K_I_MSK 0xff7fffff
+#define CBR_RG_RX_HPF300K_SFT 23
+#define CBR_RG_RX_HPF300K_HI 23
+#define CBR_RG_RX_HPF300K_SZ 1
+#define CBR_RG_RX_HPFI_MSK 0x03000000
+#define CBR_RG_RX_HPFI_I_MSK 0xfcffffff
+#define CBR_RG_RX_HPFI_SFT 24
+#define CBR_RG_RX_HPFI_HI 25
+#define CBR_RG_RX_HPFI_SZ 2
+#define CBR_RG_RX_HPF_FINALCORNER_MSK 0x0c000000
+#define CBR_RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
+#define CBR_RG_RX_HPF_FINALCORNER_SFT 26
+#define CBR_RG_RX_HPF_FINALCORNER_HI 27
+#define CBR_RG_RX_HPF_FINALCORNER_SZ 2
+#define CBR_RG_RX_HPF_SETTLE1_C_MSK 0x30000000
+#define CBR_RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
+#define CBR_RG_RX_HPF_SETTLE1_C_SFT 28
+#define CBR_RG_RX_HPF_SETTLE1_C_HI 29
+#define CBR_RG_RX_HPF_SETTLE1_C_SZ 2
+#define CBR_RG_RX_HPF_SETTLE1_R_MSK 0x00000003
+#define CBR_RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
+#define CBR_RG_RX_HPF_SETTLE1_R_SFT 0
+#define CBR_RG_RX_HPF_SETTLE1_R_HI 1
+#define CBR_RG_RX_HPF_SETTLE1_R_SZ 2
+#define CBR_RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
+#define CBR_RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
+#define CBR_RG_RX_HPF_SETTLE2_C_SFT 2
+#define CBR_RG_RX_HPF_SETTLE2_C_HI 3
+#define CBR_RG_RX_HPF_SETTLE2_C_SZ 2
+#define CBR_RG_RX_HPF_SETTLE2_R_MSK 0x00000030
+#define CBR_RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
+#define CBR_RG_RX_HPF_SETTLE2_R_SFT 4
+#define CBR_RG_RX_HPF_SETTLE2_R_HI 5
+#define CBR_RG_RX_HPF_SETTLE2_R_SZ 2
+#define CBR_RG_RX_HPF_VCMCON2_MSK 0x000000c0
+#define CBR_RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
+#define CBR_RG_RX_HPF_VCMCON2_SFT 6
+#define CBR_RG_RX_HPF_VCMCON2_HI 7
+#define CBR_RG_RX_HPF_VCMCON2_SZ 2
+#define CBR_RG_RX_HPF_VCMCON_MSK 0x00000300
+#define CBR_RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
+#define CBR_RG_RX_HPF_VCMCON_SFT 8
+#define CBR_RG_RX_HPF_VCMCON_HI 9
+#define CBR_RG_RX_HPF_VCMCON_SZ 2
+#define CBR_RG_RX_OUTVCM_MSK 0x00000c00
+#define CBR_RG_RX_OUTVCM_I_MSK 0xfffff3ff
+#define CBR_RG_RX_OUTVCM_SFT 10
+#define CBR_RG_RX_OUTVCM_HI 11
+#define CBR_RG_RX_OUTVCM_SZ 2
+#define CBR_RG_RX_TZI_MSK 0x00003000
+#define CBR_RG_RX_TZI_I_MSK 0xffffcfff
+#define CBR_RG_RX_TZI_SFT 12
+#define CBR_RG_RX_TZI_HI 13
+#define CBR_RG_RX_TZI_SZ 2
+#define CBR_RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
+#define CBR_RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
+#define CBR_RG_RX_TZ_OUT_TRISTATE_SFT 14
+#define CBR_RG_RX_TZ_OUT_TRISTATE_HI 14
+#define CBR_RG_RX_TZ_OUT_TRISTATE_SZ 1
+#define CBR_RG_RX_TZ_VCM_MSK 0x00018000
+#define CBR_RG_RX_TZ_VCM_I_MSK 0xfffe7fff
+#define CBR_RG_RX_TZ_VCM_SFT 15
+#define CBR_RG_RX_TZ_VCM_HI 16
+#define CBR_RG_RX_TZ_VCM_SZ 2
+#define CBR_RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
+#define CBR_RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
+#define CBR_RG_EN_RX_RSSI_TESTNODE_SFT 17
+#define CBR_RG_EN_RX_RSSI_TESTNODE_HI 19
+#define CBR_RG_EN_RX_RSSI_TESTNODE_SZ 3
+#define CBR_RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
+#define CBR_RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
+#define CBR_RG_RX_ADCRSSI_CLKSEL_SFT 20
+#define CBR_RG_RX_ADCRSSI_CLKSEL_HI 20
+#define CBR_RG_RX_ADCRSSI_CLKSEL_SZ 1
+#define CBR_RG_RX_ADCRSSI_VCM_MSK 0x00600000
+#define CBR_RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
+#define CBR_RG_RX_ADCRSSI_VCM_SFT 21
+#define CBR_RG_RX_ADCRSSI_VCM_HI 22
+#define CBR_RG_RX_ADCRSSI_VCM_SZ 2
+#define CBR_RG_RX_REC_LPFCORNER_MSK 0x01800000
+#define CBR_RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
+#define CBR_RG_RX_REC_LPFCORNER_SFT 23
+#define CBR_RG_RX_REC_LPFCORNER_HI 24
+#define CBR_RG_RX_REC_LPFCORNER_SZ 2
+#define CBR_RG_RSSI_CLOCK_GATING_MSK 0x02000000
+#define CBR_RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
+#define CBR_RG_RSSI_CLOCK_GATING_SFT 25
+#define CBR_RG_RSSI_CLOCK_GATING_HI 25
+#define CBR_RG_RSSI_CLOCK_GATING_SZ 1
+#define CBR_RG_TXPGA_CAPSW_MSK 0x00000003
+#define CBR_RG_TXPGA_CAPSW_I_MSK 0xfffffffc
+#define CBR_RG_TXPGA_CAPSW_SFT 0
+#define CBR_RG_TXPGA_CAPSW_HI 1
+#define CBR_RG_TXPGA_CAPSW_SZ 2
+#define CBR_RG_TXPGA_MAIN_MSK 0x000000fc
+#define CBR_RG_TXPGA_MAIN_I_MSK 0xffffff03
+#define CBR_RG_TXPGA_MAIN_SFT 2
+#define CBR_RG_TXPGA_MAIN_HI 7
+#define CBR_RG_TXPGA_MAIN_SZ 6
+#define CBR_RG_TXPGA_STEER_MSK 0x00003f00
+#define CBR_RG_TXPGA_STEER_I_MSK 0xffffc0ff
+#define CBR_RG_TXPGA_STEER_SFT 8
+#define CBR_RG_TXPGA_STEER_HI 13
+#define CBR_RG_TXPGA_STEER_SZ 6
+#define CBR_RG_TXMOD_GMCELL_MSK 0x0000c000
+#define CBR_RG_TXMOD_GMCELL_I_MSK 0xffff3fff
+#define CBR_RG_TXMOD_GMCELL_SFT 14
+#define CBR_RG_TXMOD_GMCELL_HI 15
+#define CBR_RG_TXMOD_GMCELL_SZ 2
+#define CBR_RG_TXLPF_GMCELL_MSK 0x00030000
+#define CBR_RG_TXLPF_GMCELL_I_MSK 0xfffcffff
+#define CBR_RG_TXLPF_GMCELL_SFT 16
+#define CBR_RG_TXLPF_GMCELL_HI 17
+#define CBR_RG_TXLPF_GMCELL_SZ 2
+#define CBR_RG_PACELL_EN_MSK 0x001c0000
+#define CBR_RG_PACELL_EN_I_MSK 0xffe3ffff
+#define CBR_RG_PACELL_EN_SFT 18
+#define CBR_RG_PACELL_EN_HI 20
+#define CBR_RG_PACELL_EN_SZ 3
+#define CBR_RG_PABIAS_CTRL_MSK 0x01e00000
+#define CBR_RG_PABIAS_CTRL_I_MSK 0xfe1fffff
+#define CBR_RG_PABIAS_CTRL_SFT 21
+#define CBR_RG_PABIAS_CTRL_HI 24
+#define CBR_RG_PABIAS_CTRL_SZ 4
+#define CBR_RG_PABIAS_AB_MSK 0x02000000
+#define CBR_RG_PABIAS_AB_I_MSK 0xfdffffff
+#define CBR_RG_PABIAS_AB_SFT 25
+#define CBR_RG_PABIAS_AB_HI 25
+#define CBR_RG_PABIAS_AB_SZ 1
+#define CBR_RG_TX_DIV_VSET_MSK 0x0c000000
+#define CBR_RG_TX_DIV_VSET_I_MSK 0xf3ffffff
+#define CBR_RG_TX_DIV_VSET_SFT 26
+#define CBR_RG_TX_DIV_VSET_HI 27
+#define CBR_RG_TX_DIV_VSET_SZ 2
+#define CBR_RG_TX_LOBUF_VSET_MSK 0x30000000
+#define CBR_RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
+#define CBR_RG_TX_LOBUF_VSET_SFT 28
+#define CBR_RG_TX_LOBUF_VSET_HI 29
+#define CBR_RG_TX_LOBUF_VSET_SZ 2
+#define CBR_RG_RX_SQDC_MSK 0x00000007
+#define CBR_RG_RX_SQDC_I_MSK 0xfffffff8
+#define CBR_RG_RX_SQDC_SFT 0
+#define CBR_RG_RX_SQDC_HI 2
+#define CBR_RG_RX_SQDC_SZ 3
+#define CBR_RG_RX_DIV2_CORE_MSK 0x00000018
+#define CBR_RG_RX_DIV2_CORE_I_MSK 0xffffffe7
+#define CBR_RG_RX_DIV2_CORE_SFT 3
+#define CBR_RG_RX_DIV2_CORE_HI 4
+#define CBR_RG_RX_DIV2_CORE_SZ 2
+#define CBR_RG_RX_LOBUF_MSK 0x00000060
+#define CBR_RG_RX_LOBUF_I_MSK 0xffffff9f
+#define CBR_RG_RX_LOBUF_SFT 5
+#define CBR_RG_RX_LOBUF_HI 6
+#define CBR_RG_RX_LOBUF_SZ 2
+#define CBR_RG_TX_DPDGM_BIAS_MSK 0x00000780
+#define CBR_RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
+#define CBR_RG_TX_DPDGM_BIAS_SFT 7
+#define CBR_RG_TX_DPDGM_BIAS_HI 10
+#define CBR_RG_TX_DPDGM_BIAS_SZ 4
+#define CBR_RG_TX_DPD_DIV_MSK 0x00007800
+#define CBR_RG_TX_DPD_DIV_I_MSK 0xffff87ff
+#define CBR_RG_TX_DPD_DIV_SFT 11
+#define CBR_RG_TX_DPD_DIV_HI 14
+#define CBR_RG_TX_DPD_DIV_SZ 4
+#define CBR_RG_TX_TSSI_BIAS_MSK 0x00038000
+#define CBR_RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
+#define CBR_RG_TX_TSSI_BIAS_SFT 15
+#define CBR_RG_TX_TSSI_BIAS_HI 17
+#define CBR_RG_TX_TSSI_BIAS_SZ 3
+#define CBR_RG_TX_TSSI_DIV_MSK 0x001c0000
+#define CBR_RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
+#define CBR_RG_TX_TSSI_DIV_SFT 18
+#define CBR_RG_TX_TSSI_DIV_HI 20
+#define CBR_RG_TX_TSSI_DIV_SZ 3
+#define CBR_RG_TX_TSSI_TESTMODE_MSK 0x00200000
+#define CBR_RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
+#define CBR_RG_TX_TSSI_TESTMODE_SFT 21
+#define CBR_RG_TX_TSSI_TESTMODE_HI 21
+#define CBR_RG_TX_TSSI_TESTMODE_SZ 1
+#define CBR_RG_TX_TSSI_TEST_MSK 0x00c00000
+#define CBR_RG_TX_TSSI_TEST_I_MSK 0xff3fffff
+#define CBR_RG_TX_TSSI_TEST_SFT 22
+#define CBR_RG_TX_TSSI_TEST_HI 23
+#define CBR_RG_TX_TSSI_TEST_SZ 2
+#define CBR_RG_RX_HG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_HG_LNA_GC_SFT 0
+#define CBR_RG_RX_HG_LNA_GC_HI 1
+#define CBR_RG_RX_HG_LNA_GC_SZ 2
+#define CBR_RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_HG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_HG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_HG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_HG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_HG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_HG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_HG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_HG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_HG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_HG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_HG_TZ_GC_SFT 14
+#define CBR_RG_RX_HG_TZ_GC_HI 15
+#define CBR_RG_RX_HG_TZ_GC_SZ 2
+#define CBR_RG_RX_HG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_HG_TZ_CAP_SFT 16
+#define CBR_RG_RX_HG_TZ_CAP_HI 18
+#define CBR_RG_RX_HG_TZ_CAP_SZ 3
+#define CBR_RG_RX_MG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_MG_LNA_GC_SFT 0
+#define CBR_RG_RX_MG_LNA_GC_HI 1
+#define CBR_RG_RX_MG_LNA_GC_SZ 2
+#define CBR_RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_MG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_MG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_MG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_MG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_MG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_MG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_MG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_MG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_MG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_MG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_MG_TZ_GC_SFT 14
+#define CBR_RG_RX_MG_TZ_GC_HI 15
+#define CBR_RG_RX_MG_TZ_GC_SZ 2
+#define CBR_RG_RX_MG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_MG_TZ_CAP_SFT 16
+#define CBR_RG_RX_MG_TZ_CAP_HI 18
+#define CBR_RG_RX_MG_TZ_CAP_SZ 3
+#define CBR_RG_RX_LG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_LG_LNA_GC_SFT 0
+#define CBR_RG_RX_LG_LNA_GC_HI 1
+#define CBR_RG_RX_LG_LNA_GC_SZ 2
+#define CBR_RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_LG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_LG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_LG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_LG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_LG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_LG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_LG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_LG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_LG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_LG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_LG_TZ_GC_SFT 14
+#define CBR_RG_RX_LG_TZ_GC_HI 15
+#define CBR_RG_RX_LG_TZ_GC_SZ 2
+#define CBR_RG_RX_LG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_LG_TZ_CAP_SFT 16
+#define CBR_RG_RX_LG_TZ_CAP_HI 18
+#define CBR_RG_RX_LG_TZ_CAP_SZ 3
+#define CBR_RG_RX_ULG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_ULG_LNA_GC_SFT 0
+#define CBR_RG_RX_ULG_LNA_GC_HI 1
+#define CBR_RG_RX_ULG_LNA_GC_SZ 2
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_ULG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_ULG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_ULG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_ULG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_ULG_TZ_GC_SFT 14
+#define CBR_RG_RX_ULG_TZ_GC_HI 15
+#define CBR_RG_RX_ULG_TZ_GC_SZ 2
+#define CBR_RG_RX_ULG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_ULG_TZ_CAP_SFT 16
+#define CBR_RG_RX_ULG_TZ_CAP_HI 18
+#define CBR_RG_RX_ULG_TZ_CAP_SZ 3
+#define CBR_RG_HPF1_FAST_SET_X_MSK 0x00000001
+#define CBR_RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
+#define CBR_RG_HPF1_FAST_SET_X_SFT 0
+#define CBR_RG_HPF1_FAST_SET_X_HI 0
+#define CBR_RG_HPF1_FAST_SET_X_SZ 1
+#define CBR_RG_HPF1_FAST_SET_Y_MSK 0x00000002
+#define CBR_RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
+#define CBR_RG_HPF1_FAST_SET_Y_SFT 1
+#define CBR_RG_HPF1_FAST_SET_Y_HI 1
+#define CBR_RG_HPF1_FAST_SET_Y_SZ 1
+#define CBR_RG_HPF1_FAST_SET_Z_MSK 0x00000004
+#define CBR_RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
+#define CBR_RG_HPF1_FAST_SET_Z_SFT 2
+#define CBR_RG_HPF1_FAST_SET_Z_HI 2
+#define CBR_RG_HPF1_FAST_SET_Z_SZ 1
+#define CBR_RG_HPF_T1A_MSK 0x00000018
+#define CBR_RG_HPF_T1A_I_MSK 0xffffffe7
+#define CBR_RG_HPF_T1A_SFT 3
+#define CBR_RG_HPF_T1A_HI 4
+#define CBR_RG_HPF_T1A_SZ 2
+#define CBR_RG_HPF_T1B_MSK 0x00000060
+#define CBR_RG_HPF_T1B_I_MSK 0xffffff9f
+#define CBR_RG_HPF_T1B_SFT 5
+#define CBR_RG_HPF_T1B_HI 6
+#define CBR_RG_HPF_T1B_SZ 2
+#define CBR_RG_HPF_T1C_MSK 0x00000180
+#define CBR_RG_HPF_T1C_I_MSK 0xfffffe7f
+#define CBR_RG_HPF_T1C_SFT 7
+#define CBR_RG_HPF_T1C_HI 8
+#define CBR_RG_HPF_T1C_SZ 2
+#define CBR_RG_RX_LNA_TRI_SEL_MSK 0x00000600
+#define CBR_RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
+#define CBR_RG_RX_LNA_TRI_SEL_SFT 9
+#define CBR_RG_RX_LNA_TRI_SEL_HI 10
+#define CBR_RG_RX_LNA_TRI_SEL_SZ 2
+#define CBR_RG_RX_LNA_SETTLE_MSK 0x00001800
+#define CBR_RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
+#define CBR_RG_RX_LNA_SETTLE_SFT 11
+#define CBR_RG_RX_LNA_SETTLE_HI 12
+#define CBR_RG_RX_LNA_SETTLE_SZ 2
+#define CBR_RG_ADC_CLKSEL_MSK 0x00000001
+#define CBR_RG_ADC_CLKSEL_I_MSK 0xfffffffe
+#define CBR_RG_ADC_CLKSEL_SFT 0
+#define CBR_RG_ADC_CLKSEL_HI 0
+#define CBR_RG_ADC_CLKSEL_SZ 1
+#define CBR_RG_ADC_DIBIAS_MSK 0x00000006
+#define CBR_RG_ADC_DIBIAS_I_MSK 0xfffffff9
+#define CBR_RG_ADC_DIBIAS_SFT 1
+#define CBR_RG_ADC_DIBIAS_HI 2
+#define CBR_RG_ADC_DIBIAS_SZ 2
+#define CBR_RG_ADC_DIVR_MSK 0x00000008
+#define CBR_RG_ADC_DIVR_I_MSK 0xfffffff7
+#define CBR_RG_ADC_DIVR_SFT 3
+#define CBR_RG_ADC_DIVR_HI 3
+#define CBR_RG_ADC_DIVR_SZ 1
+#define CBR_RG_ADC_DVCMI_MSK 0x00000030
+#define CBR_RG_ADC_DVCMI_I_MSK 0xffffffcf
+#define CBR_RG_ADC_DVCMI_SFT 4
+#define CBR_RG_ADC_DVCMI_HI 5
+#define CBR_RG_ADC_DVCMI_SZ 2
+#define CBR_RG_ADC_SAMSEL_MSK 0x000003c0
+#define CBR_RG_ADC_SAMSEL_I_MSK 0xfffffc3f
+#define CBR_RG_ADC_SAMSEL_SFT 6
+#define CBR_RG_ADC_SAMSEL_HI 9
+#define CBR_RG_ADC_SAMSEL_SZ 4
+#define CBR_RG_ADC_STNBY_MSK 0x00000400
+#define CBR_RG_ADC_STNBY_I_MSK 0xfffffbff
+#define CBR_RG_ADC_STNBY_SFT 10
+#define CBR_RG_ADC_STNBY_HI 10
+#define CBR_RG_ADC_STNBY_SZ 1
+#define CBR_RG_ADC_TESTMODE_MSK 0x00000800
+#define CBR_RG_ADC_TESTMODE_I_MSK 0xfffff7ff
+#define CBR_RG_ADC_TESTMODE_SFT 11
+#define CBR_RG_ADC_TESTMODE_HI 11
+#define CBR_RG_ADC_TESTMODE_SZ 1
+#define CBR_RG_ADC_TSEL_MSK 0x0000f000
+#define CBR_RG_ADC_TSEL_I_MSK 0xffff0fff
+#define CBR_RG_ADC_TSEL_SFT 12
+#define CBR_RG_ADC_TSEL_HI 15
+#define CBR_RG_ADC_TSEL_SZ 4
+#define CBR_RG_ADC_VRSEL_MSK 0x00030000
+#define CBR_RG_ADC_VRSEL_I_MSK 0xfffcffff
+#define CBR_RG_ADC_VRSEL_SFT 16
+#define CBR_RG_ADC_VRSEL_HI 17
+#define CBR_RG_ADC_VRSEL_SZ 2
+#define CBR_RG_DICMP_MSK 0x000c0000
+#define CBR_RG_DICMP_I_MSK 0xfff3ffff
+#define CBR_RG_DICMP_SFT 18
+#define CBR_RG_DICMP_HI 19
+#define CBR_RG_DICMP_SZ 2
+#define CBR_RG_DIOP_MSK 0x00300000
+#define CBR_RG_DIOP_I_MSK 0xffcfffff
+#define CBR_RG_DIOP_SFT 20
+#define CBR_RG_DIOP_HI 21
+#define CBR_RG_DIOP_SZ 2
+#define CBR_RG_DACI1ST_MSK 0x00000003
+#define CBR_RG_DACI1ST_I_MSK 0xfffffffc
+#define CBR_RG_DACI1ST_SFT 0
+#define CBR_RG_DACI1ST_HI 1
+#define CBR_RG_DACI1ST_SZ 2
+#define CBR_RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
+#define CBR_RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
+#define CBR_RG_TX_DACLPF_ICOURSE_SFT 2
+#define CBR_RG_TX_DACLPF_ICOURSE_HI 3
+#define CBR_RG_TX_DACLPF_ICOURSE_SZ 2
+#define CBR_RG_TX_DACLPF_IFINE_MSK 0x00000030
+#define CBR_RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define CBR_RG_TX_DACLPF_IFINE_SFT 4
+#define CBR_RG_TX_DACLPF_IFINE_HI 5
+#define CBR_RG_TX_DACLPF_IFINE_SZ 2
+#define CBR_RG_TX_DACLPF_VCM_MSK 0x000000c0
+#define CBR_RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define CBR_RG_TX_DACLPF_VCM_SFT 6
+#define CBR_RG_TX_DACLPF_VCM_HI 7
+#define CBR_RG_TX_DACLPF_VCM_SZ 2
+#define CBR_RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
+#define CBR_RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
+#define CBR_RG_TX_DAC_CKEDGE_SEL_SFT 8
+#define CBR_RG_TX_DAC_CKEDGE_SEL_HI 8
+#define CBR_RG_TX_DAC_CKEDGE_SEL_SZ 1
+#define CBR_RG_TX_DAC_IBIAS_MSK 0x00000600
+#define CBR_RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
+#define CBR_RG_TX_DAC_IBIAS_SFT 9
+#define CBR_RG_TX_DAC_IBIAS_HI 10
+#define CBR_RG_TX_DAC_IBIAS_SZ 2
+#define CBR_RG_TX_DAC_OS_MSK 0x00003800
+#define CBR_RG_TX_DAC_OS_I_MSK 0xffffc7ff
+#define CBR_RG_TX_DAC_OS_SFT 11
+#define CBR_RG_TX_DAC_OS_HI 13
+#define CBR_RG_TX_DAC_OS_SZ 3
+#define CBR_RG_TX_DAC_RCAL_MSK 0x0000c000
+#define CBR_RG_TX_DAC_RCAL_I_MSK 0xffff3fff
+#define CBR_RG_TX_DAC_RCAL_SFT 14
+#define CBR_RG_TX_DAC_RCAL_HI 15
+#define CBR_RG_TX_DAC_RCAL_SZ 2
+#define CBR_RG_TX_DAC_TSEL_MSK 0x000f0000
+#define CBR_RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
+#define CBR_RG_TX_DAC_TSEL_SFT 16
+#define CBR_RG_TX_DAC_TSEL_HI 19
+#define CBR_RG_TX_DAC_TSEL_SZ 4
+#define CBR_RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
+#define CBR_RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
+#define CBR_RG_TX_EN_VOLTAGE_IN_SFT 20
+#define CBR_RG_TX_EN_VOLTAGE_IN_HI 20
+#define CBR_RG_TX_EN_VOLTAGE_IN_SZ 1
+#define CBR_RG_TXLPF_BYPASS_MSK 0x00200000
+#define CBR_RG_TXLPF_BYPASS_I_MSK 0xffdfffff
+#define CBR_RG_TXLPF_BYPASS_SFT 21
+#define CBR_RG_TXLPF_BYPASS_HI 21
+#define CBR_RG_TXLPF_BYPASS_SZ 1
+#define CBR_RG_TXLPF_BOOSTI_MSK 0x00400000
+#define CBR_RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
+#define CBR_RG_TXLPF_BOOSTI_SFT 22
+#define CBR_RG_TXLPF_BOOSTI_HI 22
+#define CBR_RG_TXLPF_BOOSTI_SZ 1
+#define CBR_RG_EN_SX_R3_MSK 0x00000001
+#define CBR_RG_EN_SX_R3_I_MSK 0xfffffffe
+#define CBR_RG_EN_SX_R3_SFT 0
+#define CBR_RG_EN_SX_R3_HI 0
+#define CBR_RG_EN_SX_R3_SZ 1
+#define CBR_RG_EN_SX_CH_MSK 0x00000002
+#define CBR_RG_EN_SX_CH_I_MSK 0xfffffffd
+#define CBR_RG_EN_SX_CH_SFT 1
+#define CBR_RG_EN_SX_CH_HI 1
+#define CBR_RG_EN_SX_CH_SZ 1
+#define CBR_RG_EN_SX_CHP_MSK 0x00000004
+#define CBR_RG_EN_SX_CHP_I_MSK 0xfffffffb
+#define CBR_RG_EN_SX_CHP_SFT 2
+#define CBR_RG_EN_SX_CHP_HI 2
+#define CBR_RG_EN_SX_CHP_SZ 1
+#define CBR_RG_EN_SX_DIVCK_MSK 0x00000008
+#define CBR_RG_EN_SX_DIVCK_I_MSK 0xfffffff7
+#define CBR_RG_EN_SX_DIVCK_SFT 3
+#define CBR_RG_EN_SX_DIVCK_HI 3
+#define CBR_RG_EN_SX_DIVCK_SZ 1
+#define CBR_RG_EN_SX_VCOBF_MSK 0x00000010
+#define CBR_RG_EN_SX_VCOBF_I_MSK 0xffffffef
+#define CBR_RG_EN_SX_VCOBF_SFT 4
+#define CBR_RG_EN_SX_VCOBF_HI 4
+#define CBR_RG_EN_SX_VCOBF_SZ 1
+#define CBR_RG_EN_SX_VCO_MSK 0x00000020
+#define CBR_RG_EN_SX_VCO_I_MSK 0xffffffdf
+#define CBR_RG_EN_SX_VCO_SFT 5
+#define CBR_RG_EN_SX_VCO_HI 5
+#define CBR_RG_EN_SX_VCO_SZ 1
+#define CBR_RG_EN_SX_MOD_MSK 0x00000040
+#define CBR_RG_EN_SX_MOD_I_MSK 0xffffffbf
+#define CBR_RG_EN_SX_MOD_SFT 6
+#define CBR_RG_EN_SX_MOD_HI 6
+#define CBR_RG_EN_SX_MOD_SZ 1
+#define CBR_RG_EN_SX_LCK_MSK 0x00000080
+#define CBR_RG_EN_SX_LCK_I_MSK 0xffffff7f
+#define CBR_RG_EN_SX_LCK_SFT 7
+#define CBR_RG_EN_SX_LCK_HI 7
+#define CBR_RG_EN_SX_LCK_SZ 1
+#define CBR_RG_EN_SX_DITHER_MSK 0x00000100
+#define CBR_RG_EN_SX_DITHER_I_MSK 0xfffffeff
+#define CBR_RG_EN_SX_DITHER_SFT 8
+#define CBR_RG_EN_SX_DITHER_HI 8
+#define CBR_RG_EN_SX_DITHER_SZ 1
+#define CBR_RG_EN_SX_DELCAL_MSK 0x00000200
+#define CBR_RG_EN_SX_DELCAL_I_MSK 0xfffffdff
+#define CBR_RG_EN_SX_DELCAL_SFT 9
+#define CBR_RG_EN_SX_DELCAL_HI 9
+#define CBR_RG_EN_SX_DELCAL_SZ 1
+#define CBR_RG_EN_SX_PC_BYPASS_MSK 0x00000400
+#define CBR_RG_EN_SX_PC_BYPASS_I_MSK 0xfffffbff
+#define CBR_RG_EN_SX_PC_BYPASS_SFT 10
+#define CBR_RG_EN_SX_PC_BYPASS_HI 10
+#define CBR_RG_EN_SX_PC_BYPASS_SZ 1
+#define CBR_RG_EN_SX_VT_MON_MSK 0x00000800
+#define CBR_RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
+#define CBR_RG_EN_SX_VT_MON_SFT 11
+#define CBR_RG_EN_SX_VT_MON_HI 11
+#define CBR_RG_EN_SX_VT_MON_SZ 1
+#define CBR_RG_EN_SX_VT_MON_DG_MSK 0x00001000
+#define CBR_RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
+#define CBR_RG_EN_SX_VT_MON_DG_SFT 12
+#define CBR_RG_EN_SX_VT_MON_DG_HI 12
+#define CBR_RG_EN_SX_VT_MON_DG_SZ 1
+#define CBR_RG_EN_SX_DIV_MSK 0x00002000
+#define CBR_RG_EN_SX_DIV_I_MSK 0xffffdfff
+#define CBR_RG_EN_SX_DIV_SFT 13
+#define CBR_RG_EN_SX_DIV_HI 13
+#define CBR_RG_EN_SX_DIV_SZ 1
+#define CBR_RG_EN_SX_LPF_MSK 0x00004000
+#define CBR_RG_EN_SX_LPF_I_MSK 0xffffbfff
+#define CBR_RG_EN_SX_LPF_SFT 14
+#define CBR_RG_EN_SX_LPF_HI 14
+#define CBR_RG_EN_SX_LPF_SZ 1
+#define CBR_RG_SX_RFCTRL_F_MSK 0x00ffffff
+#define CBR_RG_SX_RFCTRL_F_I_MSK 0xff000000
+#define CBR_RG_SX_RFCTRL_F_SFT 0
+#define CBR_RG_SX_RFCTRL_F_HI 23
+#define CBR_RG_SX_RFCTRL_F_SZ 24
+#define CBR_RG_SX_SEL_CP_MSK 0x0f000000
+#define CBR_RG_SX_SEL_CP_I_MSK 0xf0ffffff
+#define CBR_RG_SX_SEL_CP_SFT 24
+#define CBR_RG_SX_SEL_CP_HI 27
+#define CBR_RG_SX_SEL_CP_SZ 4
+#define CBR_RG_SX_SEL_CS_MSK 0xf0000000
+#define CBR_RG_SX_SEL_CS_I_MSK 0x0fffffff
+#define CBR_RG_SX_SEL_CS_SFT 28
+#define CBR_RG_SX_SEL_CS_HI 31
+#define CBR_RG_SX_SEL_CS_SZ 4
+#define CBR_RG_SX_RFCTRL_CH_MSK 0x000007ff
+#define CBR_RG_SX_RFCTRL_CH_I_MSK 0xfffff800
+#define CBR_RG_SX_RFCTRL_CH_SFT 0
+#define CBR_RG_SX_RFCTRL_CH_HI 10
+#define CBR_RG_SX_RFCTRL_CH_SZ 11
+#define CBR_RG_SX_SEL_C3_MSK 0x00007800
+#define CBR_RG_SX_SEL_C3_I_MSK 0xffff87ff
+#define CBR_RG_SX_SEL_C3_SFT 11
+#define CBR_RG_SX_SEL_C3_HI 14
+#define CBR_RG_SX_SEL_C3_SZ 4
+#define CBR_RG_SX_SEL_RS_MSK 0x000f8000
+#define CBR_RG_SX_SEL_RS_I_MSK 0xfff07fff
+#define CBR_RG_SX_SEL_RS_SFT 15
+#define CBR_RG_SX_SEL_RS_HI 19
+#define CBR_RG_SX_SEL_RS_SZ 5
+#define CBR_RG_SX_SEL_R3_MSK 0x01f00000
+#define CBR_RG_SX_SEL_R3_I_MSK 0xfe0fffff
+#define CBR_RG_SX_SEL_R3_SFT 20
+#define CBR_RG_SX_SEL_R3_HI 24
+#define CBR_RG_SX_SEL_R3_SZ 5
+#define CBR_RG_SX_SEL_ICHP_MSK 0x0000001f
+#define CBR_RG_SX_SEL_ICHP_I_MSK 0xffffffe0
+#define CBR_RG_SX_SEL_ICHP_SFT 0
+#define CBR_RG_SX_SEL_ICHP_HI 4
+#define CBR_RG_SX_SEL_ICHP_SZ 5
+#define CBR_RG_SX_SEL_PCHP_MSK 0x000003e0
+#define CBR_RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
+#define CBR_RG_SX_SEL_PCHP_SFT 5
+#define CBR_RG_SX_SEL_PCHP_HI 9
+#define CBR_RG_SX_SEL_PCHP_SZ 5
+#define CBR_RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
+#define CBR_RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
+#define CBR_RG_SX_SEL_CHP_REGOP_SFT 10
+#define CBR_RG_SX_SEL_CHP_REGOP_HI 13
+#define CBR_RG_SX_SEL_CHP_REGOP_SZ 4
+#define CBR_RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
+#define CBR_RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
+#define CBR_RG_SX_SEL_CHP_UNIOP_SFT 14
+#define CBR_RG_SX_SEL_CHP_UNIOP_HI 17
+#define CBR_RG_SX_SEL_CHP_UNIOP_SZ 4
+#define CBR_RG_SX_CHP_IOST_POL_MSK 0x00040000
+#define CBR_RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
+#define CBR_RG_SX_CHP_IOST_POL_SFT 18
+#define CBR_RG_SX_CHP_IOST_POL_HI 18
+#define CBR_RG_SX_CHP_IOST_POL_SZ 1
+#define CBR_RG_SX_CHP_IOST_MSK 0x00380000
+#define CBR_RG_SX_CHP_IOST_I_MSK 0xffc7ffff
+#define CBR_RG_SX_CHP_IOST_SFT 19
+#define CBR_RG_SX_CHP_IOST_HI 21
+#define CBR_RG_SX_CHP_IOST_SZ 3
+#define CBR_RG_SX_PFDSEL_MSK 0x00400000
+#define CBR_RG_SX_PFDSEL_I_MSK 0xffbfffff
+#define CBR_RG_SX_PFDSEL_SFT 22
+#define CBR_RG_SX_PFDSEL_HI 22
+#define CBR_RG_SX_PFDSEL_SZ 1
+#define CBR_RG_SX_PFD_SET_MSK 0x00800000
+#define CBR_RG_SX_PFD_SET_I_MSK 0xff7fffff
+#define CBR_RG_SX_PFD_SET_SFT 23
+#define CBR_RG_SX_PFD_SET_HI 23
+#define CBR_RG_SX_PFD_SET_SZ 1
+#define CBR_RG_SX_PFD_SET1_MSK 0x01000000
+#define CBR_RG_SX_PFD_SET1_I_MSK 0xfeffffff
+#define CBR_RG_SX_PFD_SET1_SFT 24
+#define CBR_RG_SX_PFD_SET1_HI 24
+#define CBR_RG_SX_PFD_SET1_SZ 1
+#define CBR_RG_SX_PFD_SET2_MSK 0x02000000
+#define CBR_RG_SX_PFD_SET2_I_MSK 0xfdffffff
+#define CBR_RG_SX_PFD_SET2_SFT 25
+#define CBR_RG_SX_PFD_SET2_HI 25
+#define CBR_RG_SX_PFD_SET2_SZ 1
+#define CBR_RG_SX_VBNCAS_SEL_MSK 0x04000000
+#define CBR_RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
+#define CBR_RG_SX_VBNCAS_SEL_SFT 26
+#define CBR_RG_SX_VBNCAS_SEL_HI 26
+#define CBR_RG_SX_VBNCAS_SEL_SZ 1
+#define CBR_RG_SX_PFD_RST_H_MSK 0x08000000
+#define CBR_RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
+#define CBR_RG_SX_PFD_RST_H_SFT 27
+#define CBR_RG_SX_PFD_RST_H_HI 27
+#define CBR_RG_SX_PFD_RST_H_SZ 1
+#define CBR_RG_SX_PFD_TRUP_MSK 0x10000000
+#define CBR_RG_SX_PFD_TRUP_I_MSK 0xefffffff
+#define CBR_RG_SX_PFD_TRUP_SFT 28
+#define CBR_RG_SX_PFD_TRUP_HI 28
+#define CBR_RG_SX_PFD_TRUP_SZ 1
+#define CBR_RG_SX_PFD_TRDN_MSK 0x20000000
+#define CBR_RG_SX_PFD_TRDN_I_MSK 0xdfffffff
+#define CBR_RG_SX_PFD_TRDN_SFT 29
+#define CBR_RG_SX_PFD_TRDN_HI 29
+#define CBR_RG_SX_PFD_TRDN_SZ 1
+#define CBR_RG_SX_PFD_TRSEL_MSK 0x40000000
+#define CBR_RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
+#define CBR_RG_SX_PFD_TRSEL_SFT 30
+#define CBR_RG_SX_PFD_TRSEL_HI 30
+#define CBR_RG_SX_PFD_TRSEL_SZ 1
+#define CBR_RG_SX_VCOBA_R_MSK 0x00000007
+#define CBR_RG_SX_VCOBA_R_I_MSK 0xfffffff8
+#define CBR_RG_SX_VCOBA_R_SFT 0
+#define CBR_RG_SX_VCOBA_R_HI 2
+#define CBR_RG_SX_VCOBA_R_SZ 3
+#define CBR_RG_SX_VCORSEL_MSK 0x000000f8
+#define CBR_RG_SX_VCORSEL_I_MSK 0xffffff07
+#define CBR_RG_SX_VCORSEL_SFT 3
+#define CBR_RG_SX_VCORSEL_HI 7
+#define CBR_RG_SX_VCORSEL_SZ 5
+#define CBR_RG_SX_VCOCUSEL_MSK 0x00000f00
+#define CBR_RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
+#define CBR_RG_SX_VCOCUSEL_SFT 8
+#define CBR_RG_SX_VCOCUSEL_HI 11
+#define CBR_RG_SX_VCOCUSEL_SZ 4
+#define CBR_RG_SX_RXBFSEL_MSK 0x0000f000
+#define CBR_RG_SX_RXBFSEL_I_MSK 0xffff0fff
+#define CBR_RG_SX_RXBFSEL_SFT 12
+#define CBR_RG_SX_RXBFSEL_HI 15
+#define CBR_RG_SX_RXBFSEL_SZ 4
+#define CBR_RG_SX_TXBFSEL_MSK 0x000f0000
+#define CBR_RG_SX_TXBFSEL_I_MSK 0xfff0ffff
+#define CBR_RG_SX_TXBFSEL_SFT 16
+#define CBR_RG_SX_TXBFSEL_HI 19
+#define CBR_RG_SX_TXBFSEL_SZ 4
+#define CBR_RG_SX_VCOBFSEL_MSK 0x00f00000
+#define CBR_RG_SX_VCOBFSEL_I_MSK 0xff0fffff
+#define CBR_RG_SX_VCOBFSEL_SFT 20
+#define CBR_RG_SX_VCOBFSEL_HI 23
+#define CBR_RG_SX_VCOBFSEL_SZ 4
+#define CBR_RG_SX_DIVBFSEL_MSK 0x0f000000
+#define CBR_RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
+#define CBR_RG_SX_DIVBFSEL_SFT 24
+#define CBR_RG_SX_DIVBFSEL_HI 27
+#define CBR_RG_SX_DIVBFSEL_SZ 4
+#define CBR_RG_SX_GNDR_SEL_MSK 0xf0000000
+#define CBR_RG_SX_GNDR_SEL_I_MSK 0x0fffffff
+#define CBR_RG_SX_GNDR_SEL_SFT 28
+#define CBR_RG_SX_GNDR_SEL_HI 31
+#define CBR_RG_SX_GNDR_SEL_SZ 4
+#define CBR_RG_SX_DITHER_WEIGHT_MSK 0x00000003
+#define CBR_RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
+#define CBR_RG_SX_DITHER_WEIGHT_SFT 0
+#define CBR_RG_SX_DITHER_WEIGHT_HI 1
+#define CBR_RG_SX_DITHER_WEIGHT_SZ 2
+#define CBR_RG_SX_MOD_ERRCMP_MSK 0x0000000c
+#define CBR_RG_SX_MOD_ERRCMP_I_MSK 0xfffffff3
+#define CBR_RG_SX_MOD_ERRCMP_SFT 2
+#define CBR_RG_SX_MOD_ERRCMP_HI 3
+#define CBR_RG_SX_MOD_ERRCMP_SZ 2
+#define CBR_RG_SX_MOD_ORDER_MSK 0x00000030
+#define CBR_RG_SX_MOD_ORDER_I_MSK 0xffffffcf
+#define CBR_RG_SX_MOD_ORDER_SFT 4
+#define CBR_RG_SX_MOD_ORDER_HI 5
+#define CBR_RG_SX_MOD_ORDER_SZ 2
+#define CBR_RG_SX_SDM_D1_MSK 0x00000040
+#define CBR_RG_SX_SDM_D1_I_MSK 0xffffffbf
+#define CBR_RG_SX_SDM_D1_SFT 6
+#define CBR_RG_SX_SDM_D1_HI 6
+#define CBR_RG_SX_SDM_D1_SZ 1
+#define CBR_RG_SX_SDM_D2_MSK 0x00000080
+#define CBR_RG_SX_SDM_D2_I_MSK 0xffffff7f
+#define CBR_RG_SX_SDM_D2_SFT 7
+#define CBR_RG_SX_SDM_D2_HI 7
+#define CBR_RG_SX_SDM_D2_SZ 1
+#define CBR_RG_SDM_PASS_MSK 0x00000100
+#define CBR_RG_SDM_PASS_I_MSK 0xfffffeff
+#define CBR_RG_SDM_PASS_SFT 8
+#define CBR_RG_SDM_PASS_HI 8
+#define CBR_RG_SDM_PASS_SZ 1
+#define CBR_RG_SX_RST_H_DIV_MSK 0x00000200
+#define CBR_RG_SX_RST_H_DIV_I_MSK 0xfffffdff
+#define CBR_RG_SX_RST_H_DIV_SFT 9
+#define CBR_RG_SX_RST_H_DIV_HI 9
+#define CBR_RG_SX_RST_H_DIV_SZ 1
+#define CBR_RG_SX_SDM_EDGE_MSK 0x00000400
+#define CBR_RG_SX_SDM_EDGE_I_MSK 0xfffffbff
+#define CBR_RG_SX_SDM_EDGE_SFT 10
+#define CBR_RG_SX_SDM_EDGE_HI 10
+#define CBR_RG_SX_SDM_EDGE_SZ 1
+#define CBR_RG_SX_XO_GM_MSK 0x00001800
+#define CBR_RG_SX_XO_GM_I_MSK 0xffffe7ff
+#define CBR_RG_SX_XO_GM_SFT 11
+#define CBR_RG_SX_XO_GM_HI 12
+#define CBR_RG_SX_XO_GM_SZ 2
+#define CBR_RG_SX_REFBYTWO_MSK 0x00002000
+#define CBR_RG_SX_REFBYTWO_I_MSK 0xffffdfff
+#define CBR_RG_SX_REFBYTWO_SFT 13
+#define CBR_RG_SX_REFBYTWO_HI 13
+#define CBR_RG_SX_REFBYTWO_SZ 1
+#define CBR_RG_SX_XO_SWCAP_MSK 0x0003c000
+#define CBR_RG_SX_XO_SWCAP_I_MSK 0xfffc3fff
+#define CBR_RG_SX_XO_SWCAP_SFT 14
+#define CBR_RG_SX_XO_SWCAP_HI 17
+#define CBR_RG_SX_XO_SWCAP_SZ 4
+#define CBR_RG_SX_SDMLUT_INV_MSK 0x00040000
+#define CBR_RG_SX_SDMLUT_INV_I_MSK 0xfffbffff
+#define CBR_RG_SX_SDMLUT_INV_SFT 18
+#define CBR_RG_SX_SDMLUT_INV_HI 18
+#define CBR_RG_SX_SDMLUT_INV_SZ 1
+#define CBR_RG_SX_LCKEN_MSK 0x00080000
+#define CBR_RG_SX_LCKEN_I_MSK 0xfff7ffff
+#define CBR_RG_SX_LCKEN_SFT 19
+#define CBR_RG_SX_LCKEN_HI 19
+#define CBR_RG_SX_LCKEN_SZ 1
+#define CBR_RG_SX_PREVDD_MSK 0x00f00000
+#define CBR_RG_SX_PREVDD_I_MSK 0xff0fffff
+#define CBR_RG_SX_PREVDD_SFT 20
+#define CBR_RG_SX_PREVDD_HI 23
+#define CBR_RG_SX_PREVDD_SZ 4
+#define CBR_RG_SX_PSCONTERVDD_MSK 0x0f000000
+#define CBR_RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
+#define CBR_RG_SX_PSCONTERVDD_SFT 24
+#define CBR_RG_SX_PSCONTERVDD_HI 27
+#define CBR_RG_SX_PSCONTERVDD_SZ 4
+#define CBR_RG_SX_MOD_ERR_DELAY_MSK 0x30000000
+#define CBR_RG_SX_MOD_ERR_DELAY_I_MSK 0xcfffffff
+#define CBR_RG_SX_MOD_ERR_DELAY_SFT 28
+#define CBR_RG_SX_MOD_ERR_DELAY_HI 29
+#define CBR_RG_SX_MOD_ERR_DELAY_SZ 2
+#define CBR_RG_SX_MODDB_MSK 0x40000000
+#define CBR_RG_SX_MODDB_I_MSK 0xbfffffff
+#define CBR_RG_SX_MODDB_SFT 30
+#define CBR_RG_SX_MODDB_HI 30
+#define CBR_RG_SX_MODDB_SZ 1
+#define CBR_RG_SX_CV_CURVE_SEL_MSK 0x00000003
+#define CBR_RG_SX_CV_CURVE_SEL_I_MSK 0xfffffffc
+#define CBR_RG_SX_CV_CURVE_SEL_SFT 0
+#define CBR_RG_SX_CV_CURVE_SEL_HI 1
+#define CBR_RG_SX_CV_CURVE_SEL_SZ 2
+#define CBR_RG_SX_SEL_DELAY_MSK 0x0000007c
+#define CBR_RG_SX_SEL_DELAY_I_MSK 0xffffff83
+#define CBR_RG_SX_SEL_DELAY_SFT 2
+#define CBR_RG_SX_SEL_DELAY_HI 6
+#define CBR_RG_SX_SEL_DELAY_SZ 5
+#define CBR_RG_SX_REF_CYCLE_MSK 0x00000780
+#define CBR_RG_SX_REF_CYCLE_I_MSK 0xfffff87f
+#define CBR_RG_SX_REF_CYCLE_SFT 7
+#define CBR_RG_SX_REF_CYCLE_HI 10
+#define CBR_RG_SX_REF_CYCLE_SZ 4
+#define CBR_RG_SX_VCOBY16_MSK 0x00000800
+#define CBR_RG_SX_VCOBY16_I_MSK 0xfffff7ff
+#define CBR_RG_SX_VCOBY16_SFT 11
+#define CBR_RG_SX_VCOBY16_HI 11
+#define CBR_RG_SX_VCOBY16_SZ 1
+#define CBR_RG_SX_VCOBY32_MSK 0x00001000
+#define CBR_RG_SX_VCOBY32_I_MSK 0xffffefff
+#define CBR_RG_SX_VCOBY32_SFT 12
+#define CBR_RG_SX_VCOBY32_HI 12
+#define CBR_RG_SX_VCOBY32_SZ 1
+#define CBR_RG_SX_PH_MSK 0x00002000
+#define CBR_RG_SX_PH_I_MSK 0xffffdfff
+#define CBR_RG_SX_PH_SFT 13
+#define CBR_RG_SX_PH_HI 13
+#define CBR_RG_SX_PH_SZ 1
+#define CBR_RG_SX_PL_MSK 0x00004000
+#define CBR_RG_SX_PL_I_MSK 0xffffbfff
+#define CBR_RG_SX_PL_SFT 14
+#define CBR_RG_SX_PL_HI 14
+#define CBR_RG_SX_PL_SZ 1
+#define CBR_RG_SX_VT_MON_MODE_MSK 0x00000001
+#define CBR_RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
+#define CBR_RG_SX_VT_MON_MODE_SFT 0
+#define CBR_RG_SX_VT_MON_MODE_HI 0
+#define CBR_RG_SX_VT_MON_MODE_SZ 1
+#define CBR_RG_SX_VT_TH_HI_MSK 0x00000006
+#define CBR_RG_SX_VT_TH_HI_I_MSK 0xfffffff9
+#define CBR_RG_SX_VT_TH_HI_SFT 1
+#define CBR_RG_SX_VT_TH_HI_HI 2
+#define CBR_RG_SX_VT_TH_HI_SZ 2
+#define CBR_RG_SX_VT_TH_LO_MSK 0x00000018
+#define CBR_RG_SX_VT_TH_LO_I_MSK 0xffffffe7
+#define CBR_RG_SX_VT_TH_LO_SFT 3
+#define CBR_RG_SX_VT_TH_LO_HI 4
+#define CBR_RG_SX_VT_TH_LO_SZ 2
+#define CBR_RG_SX_VT_SET_MSK 0x00000020
+#define CBR_RG_SX_VT_SET_I_MSK 0xffffffdf
+#define CBR_RG_SX_VT_SET_SFT 5
+#define CBR_RG_SX_VT_SET_HI 5
+#define CBR_RG_SX_VT_SET_SZ 1
+#define CBR_RG_SX_VT_MON_TMR_MSK 0x00007fc0
+#define CBR_RG_SX_VT_MON_TMR_I_MSK 0xffff803f
+#define CBR_RG_SX_VT_MON_TMR_SFT 6
+#define CBR_RG_SX_VT_MON_TMR_HI 14
+#define CBR_RG_SX_VT_MON_TMR_SZ 9
+#define CBR_RG_IDEAL_CYCLE_MSK 0x0fff8000
+#define CBR_RG_IDEAL_CYCLE_I_MSK 0xf0007fff
+#define CBR_RG_IDEAL_CYCLE_SFT 15
+#define CBR_RG_IDEAL_CYCLE_HI 27
+#define CBR_RG_IDEAL_CYCLE_SZ 13
+#define CBR_RG_EN_DP_VT_MON_MSK 0x00000001
+#define CBR_RG_EN_DP_VT_MON_I_MSK 0xfffffffe
+#define CBR_RG_EN_DP_VT_MON_SFT 0
+#define CBR_RG_EN_DP_VT_MON_HI 0
+#define CBR_RG_EN_DP_VT_MON_SZ 1
+#define CBR_RG_DP_VT_TH_HI_MSK 0x00000006
+#define CBR_RG_DP_VT_TH_HI_I_MSK 0xfffffff9
+#define CBR_RG_DP_VT_TH_HI_SFT 1
+#define CBR_RG_DP_VT_TH_HI_HI 2
+#define CBR_RG_DP_VT_TH_HI_SZ 2
+#define CBR_RG_DP_VT_TH_LO_MSK 0x00000018
+#define CBR_RG_DP_VT_TH_LO_I_MSK 0xffffffe7
+#define CBR_RG_DP_VT_TH_LO_SFT 3
+#define CBR_RG_DP_VT_TH_LO_HI 4
+#define CBR_RG_DP_VT_TH_LO_SZ 2
+#define CBR_RG_DP_VT_MON_TMR_MSK 0x00003fe0
+#define CBR_RG_DP_VT_MON_TMR_I_MSK 0xffffc01f
+#define CBR_RG_DP_VT_MON_TMR_SFT 5
+#define CBR_RG_DP_VT_MON_TMR_HI 13
+#define CBR_RG_DP_VT_MON_TMR_SZ 9
+#define CBR_RG_DP_CK320BY2_MSK 0x00004000
+#define CBR_RG_DP_CK320BY2_I_MSK 0xffffbfff
+#define CBR_RG_DP_CK320BY2_SFT 14
+#define CBR_RG_DP_CK320BY2_HI 14
+#define CBR_RG_DP_CK320BY2_SZ 1
+#define CBR_RG_SX_DELCTRL_MSK 0x001f8000
+#define CBR_RG_SX_DELCTRL_I_MSK 0xffe07fff
+#define CBR_RG_SX_DELCTRL_SFT 15
+#define CBR_RG_SX_DELCTRL_HI 20
+#define CBR_RG_SX_DELCTRL_SZ 6
+#define CBR_RG_DP_OD_TEST_MSK 0x00200000
+#define CBR_RG_DP_OD_TEST_I_MSK 0xffdfffff
+#define CBR_RG_DP_OD_TEST_SFT 21
+#define CBR_RG_DP_OD_TEST_HI 21
+#define CBR_RG_DP_OD_TEST_SZ 1
+#define CBR_RG_DP_BBPLL_BP_MSK 0x00000001
+#define CBR_RG_DP_BBPLL_BP_I_MSK 0xfffffffe
+#define CBR_RG_DP_BBPLL_BP_SFT 0
+#define CBR_RG_DP_BBPLL_BP_HI 0
+#define CBR_RG_DP_BBPLL_BP_SZ 1
+#define CBR_RG_DP_BBPLL_ICP_MSK 0x00000006
+#define CBR_RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
+#define CBR_RG_DP_BBPLL_ICP_SFT 1
+#define CBR_RG_DP_BBPLL_ICP_HI 2
+#define CBR_RG_DP_BBPLL_ICP_SZ 2
+#define CBR_RG_DP_BBPLL_IDUAL_MSK 0x00000018
+#define CBR_RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
+#define CBR_RG_DP_BBPLL_IDUAL_SFT 3
+#define CBR_RG_DP_BBPLL_IDUAL_HI 4
+#define CBR_RG_DP_BBPLL_IDUAL_SZ 2
+#define CBR_RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
+#define CBR_RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
+#define CBR_RG_DP_BBPLL_OD_TEST_SFT 5
+#define CBR_RG_DP_BBPLL_OD_TEST_HI 8
+#define CBR_RG_DP_BBPLL_OD_TEST_SZ 4
+#define CBR_RG_DP_BBPLL_PD_MSK 0x00000200
+#define CBR_RG_DP_BBPLL_PD_I_MSK 0xfffffdff
+#define CBR_RG_DP_BBPLL_PD_SFT 9
+#define CBR_RG_DP_BBPLL_PD_HI 9
+#define CBR_RG_DP_BBPLL_PD_SZ 1
+#define CBR_RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
+#define CBR_RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
+#define CBR_RG_DP_BBPLL_TESTSEL_SFT 10
+#define CBR_RG_DP_BBPLL_TESTSEL_HI 12
+#define CBR_RG_DP_BBPLL_TESTSEL_SZ 3
+#define CBR_RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
+#define CBR_RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
+#define CBR_RG_DP_BBPLL_PFD_DLY_SFT 13
+#define CBR_RG_DP_BBPLL_PFD_DLY_HI 14
+#define CBR_RG_DP_BBPLL_PFD_DLY_SZ 2
+#define CBR_RG_DP_RP_MSK 0x00038000
+#define CBR_RG_DP_RP_I_MSK 0xfffc7fff
+#define CBR_RG_DP_RP_SFT 15
+#define CBR_RG_DP_RP_HI 17
+#define CBR_RG_DP_RP_SZ 3
+#define CBR_RG_DP_RHP_MSK 0x000c0000
+#define CBR_RG_DP_RHP_I_MSK 0xfff3ffff
+#define CBR_RG_DP_RHP_SFT 18
+#define CBR_RG_DP_RHP_HI 19
+#define CBR_RG_DP_RHP_SZ 2
+#define CBR_RG_DP_DR3_MSK 0x00700000
+#define CBR_RG_DP_DR3_I_MSK 0xff8fffff
+#define CBR_RG_DP_DR3_SFT 20
+#define CBR_RG_DP_DR3_HI 22
+#define CBR_RG_DP_DR3_SZ 3
+#define CBR_RG_DP_DCP_MSK 0x07800000
+#define CBR_RG_DP_DCP_I_MSK 0xf87fffff
+#define CBR_RG_DP_DCP_SFT 23
+#define CBR_RG_DP_DCP_HI 26
+#define CBR_RG_DP_DCP_SZ 4
+#define CBR_RG_DP_DCS_MSK 0x78000000
+#define CBR_RG_DP_DCS_I_MSK 0x87ffffff
+#define CBR_RG_DP_DCS_SFT 27
+#define CBR_RG_DP_DCS_HI 30
+#define CBR_RG_DP_DCS_SZ 4
+#define CBR_RG_DP_FBDIV_MSK 0x00000fff
+#define CBR_RG_DP_FBDIV_I_MSK 0xfffff000
+#define CBR_RG_DP_FBDIV_SFT 0
+#define CBR_RG_DP_FBDIV_HI 11
+#define CBR_RG_DP_FBDIV_SZ 12
+#define CBR_RG_DP_FODIV_MSK 0x003ff000
+#define CBR_RG_DP_FODIV_I_MSK 0xffc00fff
+#define CBR_RG_DP_FODIV_SFT 12
+#define CBR_RG_DP_FODIV_HI 21
+#define CBR_RG_DP_FODIV_SZ 10
+#define CBR_RG_DP_REFDIV_MSK 0xffc00000
+#define CBR_RG_DP_REFDIV_I_MSK 0x003fffff
+#define CBR_RG_DP_REFDIV_SFT 22
+#define CBR_RG_DP_REFDIV_HI 31
+#define CBR_RG_DP_REFDIV_SZ 10
+#define CBR_RG_IDACAI_PGAG15_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG15_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG15_SFT 0
+#define CBR_RG_IDACAI_PGAG15_HI 5
+#define CBR_RG_IDACAI_PGAG15_SZ 6
+#define CBR_RG_IDACAQ_PGAG15_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG15_SFT 6
+#define CBR_RG_IDACAQ_PGAG15_HI 11
+#define CBR_RG_IDACAQ_PGAG15_SZ 6
+#define CBR_RG_IDACAI_PGAG14_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG14_SFT 12
+#define CBR_RG_IDACAI_PGAG14_HI 17
+#define CBR_RG_IDACAI_PGAG14_SZ 6
+#define CBR_RG_IDACAQ_PGAG14_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG14_SFT 18
+#define CBR_RG_IDACAQ_PGAG14_HI 23
+#define CBR_RG_IDACAQ_PGAG14_SZ 6
+#define CBR_RG_IDACAI_PGAG13_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG13_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG13_SFT 0
+#define CBR_RG_IDACAI_PGAG13_HI 5
+#define CBR_RG_IDACAI_PGAG13_SZ 6
+#define CBR_RG_IDACAQ_PGAG13_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG13_SFT 6
+#define CBR_RG_IDACAQ_PGAG13_HI 11
+#define CBR_RG_IDACAQ_PGAG13_SZ 6
+#define CBR_RG_IDACAI_PGAG12_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG12_SFT 12
+#define CBR_RG_IDACAI_PGAG12_HI 17
+#define CBR_RG_IDACAI_PGAG12_SZ 6
+#define CBR_RG_IDACAQ_PGAG12_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG12_SFT 18
+#define CBR_RG_IDACAQ_PGAG12_HI 23
+#define CBR_RG_IDACAQ_PGAG12_SZ 6
+#define CBR_RG_IDACAI_PGAG11_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG11_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG11_SFT 0
+#define CBR_RG_IDACAI_PGAG11_HI 5
+#define CBR_RG_IDACAI_PGAG11_SZ 6
+#define CBR_RG_IDACAQ_PGAG11_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG11_SFT 6
+#define CBR_RG_IDACAQ_PGAG11_HI 11
+#define CBR_RG_IDACAQ_PGAG11_SZ 6
+#define CBR_RG_IDACAI_PGAG10_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG10_SFT 12
+#define CBR_RG_IDACAI_PGAG10_HI 17
+#define CBR_RG_IDACAI_PGAG10_SZ 6
+#define CBR_RG_IDACAQ_PGAG10_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG10_SFT 18
+#define CBR_RG_IDACAQ_PGAG10_HI 23
+#define CBR_RG_IDACAQ_PGAG10_SZ 6
+#define CBR_RG_IDACAI_PGAG9_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG9_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG9_SFT 0
+#define CBR_RG_IDACAI_PGAG9_HI 5
+#define CBR_RG_IDACAI_PGAG9_SZ 6
+#define CBR_RG_IDACAQ_PGAG9_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG9_SFT 6
+#define CBR_RG_IDACAQ_PGAG9_HI 11
+#define CBR_RG_IDACAQ_PGAG9_SZ 6
+#define CBR_RG_IDACAI_PGAG8_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG8_SFT 12
+#define CBR_RG_IDACAI_PGAG8_HI 17
+#define CBR_RG_IDACAI_PGAG8_SZ 6
+#define CBR_RG_IDACAQ_PGAG8_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG8_SFT 18
+#define CBR_RG_IDACAQ_PGAG8_HI 23
+#define CBR_RG_IDACAQ_PGAG8_SZ 6
+#define CBR_RG_IDACAI_PGAG7_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG7_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG7_SFT 0
+#define CBR_RG_IDACAI_PGAG7_HI 5
+#define CBR_RG_IDACAI_PGAG7_SZ 6
+#define CBR_RG_IDACAQ_PGAG7_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG7_SFT 6
+#define CBR_RG_IDACAQ_PGAG7_HI 11
+#define CBR_RG_IDACAQ_PGAG7_SZ 6
+#define CBR_RG_IDACAI_PGAG6_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG6_SFT 12
+#define CBR_RG_IDACAI_PGAG6_HI 17
+#define CBR_RG_IDACAI_PGAG6_SZ 6
+#define CBR_RG_IDACAQ_PGAG6_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG6_SFT 18
+#define CBR_RG_IDACAQ_PGAG6_HI 23
+#define CBR_RG_IDACAQ_PGAG6_SZ 6
+#define CBR_RG_IDACAI_PGAG5_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG5_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG5_SFT 0
+#define CBR_RG_IDACAI_PGAG5_HI 5
+#define CBR_RG_IDACAI_PGAG5_SZ 6
+#define CBR_RG_IDACAQ_PGAG5_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG5_SFT 6
+#define CBR_RG_IDACAQ_PGAG5_HI 11
+#define CBR_RG_IDACAQ_PGAG5_SZ 6
+#define CBR_RG_IDACAI_PGAG4_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG4_SFT 12
+#define CBR_RG_IDACAI_PGAG4_HI 17
+#define CBR_RG_IDACAI_PGAG4_SZ 6
+#define CBR_RG_IDACAQ_PGAG4_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG4_SFT 18
+#define CBR_RG_IDACAQ_PGAG4_HI 23
+#define CBR_RG_IDACAQ_PGAG4_SZ 6
+#define CBR_RG_IDACAI_PGAG3_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG3_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG3_SFT 0
+#define CBR_RG_IDACAI_PGAG3_HI 5
+#define CBR_RG_IDACAI_PGAG3_SZ 6
+#define CBR_RG_IDACAQ_PGAG3_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG3_SFT 6
+#define CBR_RG_IDACAQ_PGAG3_HI 11
+#define CBR_RG_IDACAQ_PGAG3_SZ 6
+#define CBR_RG_IDACAI_PGAG2_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG2_SFT 12
+#define CBR_RG_IDACAI_PGAG2_HI 17
+#define CBR_RG_IDACAI_PGAG2_SZ 6
+#define CBR_RG_IDACAQ_PGAG2_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG2_SFT 18
+#define CBR_RG_IDACAQ_PGAG2_HI 23
+#define CBR_RG_IDACAQ_PGAG2_SZ 6
+#define CBR_RG_IDACAI_PGAG1_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG1_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG1_SFT 0
+#define CBR_RG_IDACAI_PGAG1_HI 5
+#define CBR_RG_IDACAI_PGAG1_SZ 6
+#define CBR_RG_IDACAQ_PGAG1_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG1_SFT 6
+#define CBR_RG_IDACAQ_PGAG1_HI 11
+#define CBR_RG_IDACAQ_PGAG1_SZ 6
+#define CBR_RG_IDACAI_PGAG0_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG0_SFT 12
+#define CBR_RG_IDACAI_PGAG0_HI 17
+#define CBR_RG_IDACAI_PGAG0_SZ 6
+#define CBR_RG_IDACAQ_PGAG0_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG0_SFT 18
+#define CBR_RG_IDACAQ_PGAG0_HI 23
+#define CBR_RG_IDACAQ_PGAG0_SZ 6
+#define CBR_RG_EN_RCAL_MSK 0x00000001
+#define CBR_RG_EN_RCAL_I_MSK 0xfffffffe
+#define CBR_RG_EN_RCAL_SFT 0
+#define CBR_RG_EN_RCAL_HI 0
+#define CBR_RG_EN_RCAL_SZ 1
+#define CBR_RG_RCAL_SPD_MSK 0x00000002
+#define CBR_RG_RCAL_SPD_I_MSK 0xfffffffd
+#define CBR_RG_RCAL_SPD_SFT 1
+#define CBR_RG_RCAL_SPD_HI 1
+#define CBR_RG_RCAL_SPD_SZ 1
+#define CBR_RG_RCAL_TMR_MSK 0x000001fc
+#define CBR_RG_RCAL_TMR_I_MSK 0xfffffe03
+#define CBR_RG_RCAL_TMR_SFT 2
+#define CBR_RG_RCAL_TMR_HI 8
+#define CBR_RG_RCAL_TMR_SZ 7
+#define CBR_RG_RCAL_CODE_CWR_MSK 0x00000200
+#define CBR_RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
+#define CBR_RG_RCAL_CODE_CWR_SFT 9
+#define CBR_RG_RCAL_CODE_CWR_HI 9
+#define CBR_RG_RCAL_CODE_CWR_SZ 1
+#define CBR_RG_RCAL_CODE_CWD_MSK 0x00007c00
+#define CBR_RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
+#define CBR_RG_RCAL_CODE_CWD_SFT 10
+#define CBR_RG_RCAL_CODE_CWD_HI 14
+#define CBR_RG_RCAL_CODE_CWD_SZ 5
+#define CBR_RG_SX_SUB_SEL_CWR_MSK 0x00000001
+#define CBR_RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
+#define CBR_RG_SX_SUB_SEL_CWR_SFT 0
+#define CBR_RG_SX_SUB_SEL_CWR_HI 0
+#define CBR_RG_SX_SUB_SEL_CWR_SZ 1
+#define CBR_RG_SX_SUB_SEL_CWD_MSK 0x000000fe
+#define CBR_RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
+#define CBR_RG_SX_SUB_SEL_CWD_SFT 1
+#define CBR_RG_SX_SUB_SEL_CWD_HI 7
+#define CBR_RG_SX_SUB_SEL_CWD_SZ 7
+#define CBR_RG_DP_BBPLL_BS_CWR_MSK 0x00000100
+#define CBR_RG_DP_BBPLL_BS_CWR_I_MSK 0xfffffeff
+#define CBR_RG_DP_BBPLL_BS_CWR_SFT 8
+#define CBR_RG_DP_BBPLL_BS_CWR_HI 8
+#define CBR_RG_DP_BBPLL_BS_CWR_SZ 1
+#define CBR_RG_DP_BBPLL_BS_CWD_MSK 0x00007e00
+#define CBR_RG_DP_BBPLL_BS_CWD_I_MSK 0xffff81ff
+#define CBR_RG_DP_BBPLL_BS_CWD_SFT 9
+#define CBR_RG_DP_BBPLL_BS_CWD_HI 14
+#define CBR_RG_DP_BBPLL_BS_CWD_SZ 6
+#define CBR_RCAL_RDY_MSK 0x00000001
+#define CBR_RCAL_RDY_I_MSK 0xfffffffe
+#define CBR_RCAL_RDY_SFT 0
+#define CBR_RCAL_RDY_HI 0
+#define CBR_RCAL_RDY_SZ 1
+#define CBR_DA_LCK_RDY_MSK 0x00000002
+#define CBR_DA_LCK_RDY_I_MSK 0xfffffffd
+#define CBR_DA_LCK_RDY_SFT 1
+#define CBR_DA_LCK_RDY_HI 1
+#define CBR_DA_LCK_RDY_SZ 1
+#define CBR_VT_MON_RDY_MSK 0x00000004
+#define CBR_VT_MON_RDY_I_MSK 0xfffffffb
+#define CBR_VT_MON_RDY_SFT 2
+#define CBR_VT_MON_RDY_HI 2
+#define CBR_VT_MON_RDY_SZ 1
+#define CBR_DP_VT_MON_RDY_MSK 0x00000008
+#define CBR_DP_VT_MON_RDY_I_MSK 0xfffffff7
+#define CBR_DP_VT_MON_RDY_SFT 3
+#define CBR_DP_VT_MON_RDY_HI 3
+#define CBR_DP_VT_MON_RDY_SZ 1
+#define CBR_CH_RDY_MSK 0x00000010
+#define CBR_CH_RDY_I_MSK 0xffffffef
+#define CBR_CH_RDY_SFT 4
+#define CBR_CH_RDY_HI 4
+#define CBR_CH_RDY_SZ 1
+#define CBR_DA_R_CODE_LUT_MSK 0x000007c0
+#define CBR_DA_R_CODE_LUT_I_MSK 0xfffff83f
+#define CBR_DA_R_CODE_LUT_SFT 6
+#define CBR_DA_R_CODE_LUT_HI 10
+#define CBR_DA_R_CODE_LUT_SZ 5
+#define CBR_AD_SX_VT_MON_Q_MSK 0x00001800
+#define CBR_AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
+#define CBR_AD_SX_VT_MON_Q_SFT 11
+#define CBR_AD_SX_VT_MON_Q_HI 12
+#define CBR_AD_SX_VT_MON_Q_SZ 2
+#define CBR_AD_DP_VT_MON_Q_MSK 0x00006000
+#define CBR_AD_DP_VT_MON_Q_I_MSK 0xffff9fff
+#define CBR_AD_DP_VT_MON_Q_SFT 13
+#define CBR_AD_DP_VT_MON_Q_HI 14
+#define CBR_AD_DP_VT_MON_Q_SZ 2
+#define CBR_DA_R_CAL_CODE_MSK 0x0000001f
+#define CBR_DA_R_CAL_CODE_I_MSK 0xffffffe0
+#define CBR_DA_R_CAL_CODE_SFT 0
+#define CBR_DA_R_CAL_CODE_HI 4
+#define CBR_DA_R_CAL_CODE_SZ 5
+#define CBR_DA_SX_SUB_SEL_MSK 0x00000fe0
+#define CBR_DA_SX_SUB_SEL_I_MSK 0xfffff01f
+#define CBR_DA_SX_SUB_SEL_SFT 5
+#define CBR_DA_SX_SUB_SEL_HI 11
+#define CBR_DA_SX_SUB_SEL_SZ 7
+#define CBR_DA_DP_BBPLL_BS_MSK 0x0003f000
+#define CBR_DA_DP_BBPLL_BS_I_MSK 0xfffc0fff
+#define CBR_DA_DP_BBPLL_BS_SFT 12
+#define CBR_DA_DP_BBPLL_BS_HI 17
+#define CBR_DA_DP_BBPLL_BS_SZ 6
+#define CBR_TX_EN_MSK 0x00000001
+#define CBR_TX_EN_I_MSK 0xfffffffe
+#define CBR_TX_EN_SFT 0
+#define CBR_TX_EN_HI 0
+#define CBR_TX_EN_SZ 1
+#define CBR_TX_CNT_RST_MSK 0x00000002
+#define CBR_TX_CNT_RST_I_MSK 0xfffffffd
+#define CBR_TX_CNT_RST_SFT 1
+#define CBR_TX_CNT_RST_HI 1
+#define CBR_TX_CNT_RST_SZ 1
+#define CBR_IFS_TIME_MSK 0x000000fc
+#define CBR_IFS_TIME_I_MSK 0xffffff03
+#define CBR_IFS_TIME_SFT 2
+#define CBR_IFS_TIME_HI 7
+#define CBR_IFS_TIME_SZ 6
+#define CBR_LENGTH_TARGET_MSK 0x000fff00
+#define CBR_LENGTH_TARGET_I_MSK 0xfff000ff
+#define CBR_LENGTH_TARGET_SFT 8
+#define CBR_LENGTH_TARGET_HI 19
+#define CBR_LENGTH_TARGET_SZ 12
+#define CBR_TX_CNT_TARGET_MSK 0xff000000
+#define CBR_TX_CNT_TARGET_I_MSK 0x00ffffff
+#define CBR_TX_CNT_TARGET_SFT 24
+#define CBR_TX_CNT_TARGET_HI 31
+#define CBR_TX_CNT_TARGET_SZ 8
+#define CBR_TC_CNT_TARGET_MSK 0x00ffffff
+#define CBR_TC_CNT_TARGET_I_MSK 0xff000000
+#define CBR_TC_CNT_TARGET_SFT 0
+#define CBR_TC_CNT_TARGET_HI 23
+#define CBR_TC_CNT_TARGET_SZ 24
+#define CBR_PLCP_PSDU_DATA_MEM_MSK 0x000000ff
+#define CBR_PLCP_PSDU_DATA_MEM_I_MSK 0xffffff00
+#define CBR_PLCP_PSDU_DATA_MEM_SFT 0
+#define CBR_PLCP_PSDU_DATA_MEM_HI 7
+#define CBR_PLCP_PSDU_DATA_MEM_SZ 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_MSK 0x00000100
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_I_MSK 0xfffffeff
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SFT 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_HI 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SZ 1
+#define CBR_PLCP_BYTE_LENGTH_MSK 0x001ffe00
+#define CBR_PLCP_BYTE_LENGTH_I_MSK 0xffe001ff
+#define CBR_PLCP_BYTE_LENGTH_SFT 9
+#define CBR_PLCP_BYTE_LENGTH_HI 20
+#define CBR_PLCP_BYTE_LENGTH_SZ 12
+#define CBR_PLCP_PSDU_RATE_MSK 0x00600000
+#define CBR_PLCP_PSDU_RATE_I_MSK 0xff9fffff
+#define CBR_PLCP_PSDU_RATE_SFT 21
+#define CBR_PLCP_PSDU_RATE_HI 22
+#define CBR_PLCP_PSDU_RATE_SZ 2
+#define CBR_TAIL_TIME_MSK 0x1f800000
+#define CBR_TAIL_TIME_I_MSK 0xe07fffff
+#define CBR_TAIL_TIME_SFT 23
+#define CBR_TAIL_TIME_HI 28
+#define CBR_TAIL_TIME_SZ 6
+#define CBR_RG_O_PAD_PD_MSK 0x00000001
+#define CBR_RG_O_PAD_PD_I_MSK 0xfffffffe
+#define CBR_RG_O_PAD_PD_SFT 0
+#define CBR_RG_O_PAD_PD_HI 0
+#define CBR_RG_O_PAD_PD_SZ 1
+#define CBR_RG_I_PAD_PD_MSK 0x00000002
+#define CBR_RG_I_PAD_PD_I_MSK 0xfffffffd
+#define CBR_RG_I_PAD_PD_SFT 1
+#define CBR_RG_I_PAD_PD_HI 1
+#define CBR_RG_I_PAD_PD_SZ 1
+#define CBR_SEL_ADCKP_INV_MSK 0x00000004
+#define CBR_SEL_ADCKP_INV_I_MSK 0xfffffffb
+#define CBR_SEL_ADCKP_INV_SFT 2
+#define CBR_SEL_ADCKP_INV_HI 2
+#define CBR_SEL_ADCKP_INV_SZ 1
+#define CBR_RG_PAD_DS_MSK 0x00000008
+#define CBR_RG_PAD_DS_I_MSK 0xfffffff7
+#define CBR_RG_PAD_DS_SFT 3
+#define CBR_RG_PAD_DS_HI 3
+#define CBR_RG_PAD_DS_SZ 1
+#define CBR_SEL_ADCKP_MUX_MSK 0x00000010
+#define CBR_SEL_ADCKP_MUX_I_MSK 0xffffffef
+#define CBR_SEL_ADCKP_MUX_SFT 4
+#define CBR_SEL_ADCKP_MUX_HI 4
+#define CBR_SEL_ADCKP_MUX_SZ 1
+#define CBR_RG_PAD_DS_CLK_MSK 0x00000020
+#define CBR_RG_PAD_DS_CLK_I_MSK 0xffffffdf
+#define CBR_RG_PAD_DS_CLK_SFT 5
+#define CBR_RG_PAD_DS_CLK_HI 5
+#define CBR_RG_PAD_DS_CLK_SZ 1
+#define CBR_INTP_SEL_MSK 0x00000200
+#define CBR_INTP_SEL_I_MSK 0xfffffdff
+#define CBR_INTP_SEL_SFT 9
+#define CBR_INTP_SEL_HI 9
+#define CBR_INTP_SEL_SZ 1
+#define CBR_IQ_SWP_MSK 0x00000400
+#define CBR_IQ_SWP_I_MSK 0xfffffbff
+#define CBR_IQ_SWP_SFT 10
+#define CBR_IQ_SWP_HI 10
+#define CBR_IQ_SWP_SZ 1
+#define CBR_RG_EN_EXT_DA_MSK 0x00000800
+#define CBR_RG_EN_EXT_DA_I_MSK 0xfffff7ff
+#define CBR_RG_EN_EXT_DA_SFT 11
+#define CBR_RG_EN_EXT_DA_HI 11
+#define CBR_RG_EN_EXT_DA_SZ 1
+#define CBR_RG_DIS_DA_OFFSET_MSK 0x00001000
+#define CBR_RG_DIS_DA_OFFSET_I_MSK 0xffffefff
+#define CBR_RG_DIS_DA_OFFSET_SFT 12
+#define CBR_RG_DIS_DA_OFFSET_HI 12
+#define CBR_RG_DIS_DA_OFFSET_SZ 1
+#define CBR_DBG_SEL_MSK 0x000f0000
+#define CBR_DBG_SEL_I_MSK 0xfff0ffff
+#define CBR_DBG_SEL_SFT 16
+#define CBR_DBG_SEL_HI 19
+#define CBR_DBG_SEL_SZ 4
+#define CBR_DBG_EN_MSK 0x00100000
+#define CBR_DBG_EN_I_MSK 0xffefffff
+#define CBR_DBG_EN_SFT 20
+#define CBR_DBG_EN_HI 20
+#define CBR_DBG_EN_SZ 1
+#define CBR_RG_PKT_GEN_TX_CNT_MSK 0xffffffff
+#define CBR_RG_PKT_GEN_TX_CNT_I_MSK 0x00000000
+#define CBR_RG_PKT_GEN_TX_CNT_SFT 0
+#define CBR_RG_PKT_GEN_TX_CNT_HI 31
+#define CBR_RG_PKT_GEN_TX_CNT_SZ 32
+#define CBR_TP_SEL_MSK 0x0000001f
+#define CBR_TP_SEL_I_MSK 0xffffffe0
+#define CBR_TP_SEL_SFT 0
+#define CBR_TP_SEL_HI 4
+#define CBR_TP_SEL_SZ 5
+#define CBR_IDEAL_IQ_EN_MSK 0x00000020
+#define CBR_IDEAL_IQ_EN_I_MSK 0xffffffdf
+#define CBR_IDEAL_IQ_EN_SFT 5
+#define CBR_IDEAL_IQ_EN_HI 5
+#define CBR_IDEAL_IQ_EN_SZ 1
+#define CBR_DATA_OUT_SEL_MSK 0x000001c0
+#define CBR_DATA_OUT_SEL_I_MSK 0xfffffe3f
+#define CBR_DATA_OUT_SEL_SFT 6
+#define CBR_DATA_OUT_SEL_HI 8
+#define CBR_DATA_OUT_SEL_SZ 3
+#define CBR_TWO_TONE_EN_MSK 0x00000200
+#define CBR_TWO_TONE_EN_I_MSK 0xfffffdff
+#define CBR_TWO_TONE_EN_SFT 9
+#define CBR_TWO_TONE_EN_HI 9
+#define CBR_TWO_TONE_EN_SZ 1
+#define CBR_FREQ_SEL_MSK 0x00ff0000
+#define CBR_FREQ_SEL_I_MSK 0xff00ffff
+#define CBR_FREQ_SEL_SFT 16
+#define CBR_FREQ_SEL_HI 23
+#define CBR_FREQ_SEL_SZ 8
+#define CBR_IQ_SCALE_MSK 0xff000000
+#define CBR_IQ_SCALE_I_MSK 0x00ffffff
+#define CBR_IQ_SCALE_SFT 24
+#define CBR_IQ_SCALE_HI 31
+#define CBR_IQ_SCALE_SZ 8
+#define CPU_QUE_POP_MSK 0x00000001
+#define CPU_QUE_POP_I_MSK 0xfffffffe
+#define CPU_QUE_POP_SFT 0
+#define CPU_QUE_POP_HI 0
+#define CPU_QUE_POP_SZ 1
+#define CPU_INT_MSK 0x00000004
+#define CPU_INT_I_MSK 0xfffffffb
+#define CPU_INT_SFT 2
+#define CPU_INT_HI 2
+#define CPU_INT_SZ 1
+#define CPU_ID_TB0_MSK 0xffffffff
+#define CPU_ID_TB0_I_MSK 0x00000000
+#define CPU_ID_TB0_SFT 0
+#define CPU_ID_TB0_HI 31
+#define CPU_ID_TB0_SZ 32
+#define CPU_ID_TB1_MSK 0xffffffff
+#define CPU_ID_TB1_I_MSK 0x00000000
+#define CPU_ID_TB1_SFT 0
+#define CPU_ID_TB1_HI 31
+#define CPU_ID_TB1_SZ 32
+#define HW_PKTID_MSK 0x000007ff
+#define HW_PKTID_I_MSK 0xfffff800
+#define HW_PKTID_SFT 0
+#define HW_PKTID_HI 10
+#define HW_PKTID_SZ 11
+#define CH0_INT_ADDR_MSK 0xffffffff
+#define CH0_INT_ADDR_I_MSK 0x00000000
+#define CH0_INT_ADDR_SFT 0
+#define CH0_INT_ADDR_HI 31
+#define CH0_INT_ADDR_SZ 32
+#define PRI_HW_PKTID_MSK 0x000007ff
+#define PRI_HW_PKTID_I_MSK 0xfffff800
+#define PRI_HW_PKTID_SFT 0
+#define PRI_HW_PKTID_HI 10
+#define PRI_HW_PKTID_SZ 11
+#define CH0_FULL_MSK 0x00000001
+#define CH0_FULL_I_MSK 0xfffffffe
+#define CH0_FULL_SFT 0
+#define CH0_FULL_HI 0
+#define CH0_FULL_SZ 1
+#define FF0_EMPTY_MSK 0x00000002
+#define FF0_EMPTY_I_MSK 0xfffffffd
+#define FF0_EMPTY_SFT 1
+#define FF0_EMPTY_HI 1
+#define FF0_EMPTY_SZ 1
+#define RLS_BUSY_MSK 0x00000200
+#define RLS_BUSY_I_MSK 0xfffffdff
+#define RLS_BUSY_SFT 9
+#define RLS_BUSY_HI 9
+#define RLS_BUSY_SZ 1
+#define RLS_COUNT_CLR_MSK 0x00000400
+#define RLS_COUNT_CLR_I_MSK 0xfffffbff
+#define RLS_COUNT_CLR_SFT 10
+#define RLS_COUNT_CLR_HI 10
+#define RLS_COUNT_CLR_SZ 1
+#define RTN_COUNT_CLR_MSK 0x00000800
+#define RTN_COUNT_CLR_I_MSK 0xfffff7ff
+#define RTN_COUNT_CLR_SFT 11
+#define RTN_COUNT_CLR_HI 11
+#define RTN_COUNT_CLR_SZ 1
+#define RLS_COUNT_MSK 0x00ff0000
+#define RLS_COUNT_I_MSK 0xff00ffff
+#define RLS_COUNT_SFT 16
+#define RLS_COUNT_HI 23
+#define RLS_COUNT_SZ 8
+#define RTN_COUNT_MSK 0xff000000
+#define RTN_COUNT_I_MSK 0x00ffffff
+#define RTN_COUNT_SFT 24
+#define RTN_COUNT_HI 31
+#define RTN_COUNT_SZ 8
+#define FF0_CNT_MSK 0x0000001f
+#define FF0_CNT_I_MSK 0xffffffe0
+#define FF0_CNT_SFT 0
+#define FF0_CNT_HI 4
+#define FF0_CNT_SZ 5
+#define FF1_CNT_MSK 0x000001e0
+#define FF1_CNT_I_MSK 0xfffffe1f
+#define FF1_CNT_SFT 5
+#define FF1_CNT_HI 8
+#define FF1_CNT_SZ 4
+#define FF3_CNT_MSK 0x00003800
+#define FF3_CNT_I_MSK 0xffffc7ff
+#define FF3_CNT_SFT 11
+#define FF3_CNT_HI 13
+#define FF3_CNT_SZ 3
+#define FF5_CNT_MSK 0x000e0000
+#define FF5_CNT_I_MSK 0xfff1ffff
+#define FF5_CNT_SFT 17
+#define FF5_CNT_HI 19
+#define FF5_CNT_SZ 3
+#define FF6_CNT_MSK 0x00700000
+#define FF6_CNT_I_MSK 0xff8fffff
+#define FF6_CNT_SFT 20
+#define FF6_CNT_HI 22
+#define FF6_CNT_SZ 3
+#define FF7_CNT_MSK 0x03800000
+#define FF7_CNT_I_MSK 0xfc7fffff
+#define FF7_CNT_SFT 23
+#define FF7_CNT_HI 25
+#define FF7_CNT_SZ 3
+#define FF8_CNT_MSK 0x1c000000
+#define FF8_CNT_I_MSK 0xe3ffffff
+#define FF8_CNT_SFT 26
+#define FF8_CNT_HI 28
+#define FF8_CNT_SZ 3
+#define FF9_CNT_MSK 0xe0000000
+#define FF9_CNT_I_MSK 0x1fffffff
+#define FF9_CNT_SFT 29
+#define FF9_CNT_HI 31
+#define FF9_CNT_SZ 3
+#define FF10_CNT_MSK 0x00000007
+#define FF10_CNT_I_MSK 0xfffffff8
+#define FF10_CNT_SFT 0
+#define FF10_CNT_HI 2
+#define FF10_CNT_SZ 3
+#define FF11_CNT_MSK 0x00000038
+#define FF11_CNT_I_MSK 0xffffffc7
+#define FF11_CNT_SFT 3
+#define FF11_CNT_HI 5
+#define FF11_CNT_SZ 3
+#define FF12_CNT_MSK 0x000001c0
+#define FF12_CNT_I_MSK 0xfffffe3f
+#define FF12_CNT_SFT 6
+#define FF12_CNT_HI 8
+#define FF12_CNT_SZ 3
+#define FF13_CNT_MSK 0x00000600
+#define FF13_CNT_I_MSK 0xfffff9ff
+#define FF13_CNT_SFT 9
+#define FF13_CNT_HI 10
+#define FF13_CNT_SZ 2
+#define FF14_CNT_MSK 0x00001800
+#define FF14_CNT_I_MSK 0xffffe7ff
+#define FF14_CNT_SFT 11
+#define FF14_CNT_HI 12
+#define FF14_CNT_SZ 2
+#define FF15_CNT_MSK 0x00006000
+#define FF15_CNT_I_MSK 0xffff9fff
+#define FF15_CNT_SFT 13
+#define FF15_CNT_HI 14
+#define FF15_CNT_SZ 2
+#define FF4_CNT_MSK 0x000f8000
+#define FF4_CNT_I_MSK 0xfff07fff
+#define FF4_CNT_SFT 15
+#define FF4_CNT_HI 19
+#define FF4_CNT_SZ 5
+#define FF2_CNT_MSK 0x00700000
+#define FF2_CNT_I_MSK 0xff8fffff
+#define FF2_CNT_SFT 20
+#define FF2_CNT_HI 22
+#define FF2_CNT_SZ 3
+#define CH1_FULL_MSK 0x00000002
+#define CH1_FULL_I_MSK 0xfffffffd
+#define CH1_FULL_SFT 1
+#define CH1_FULL_HI 1
+#define CH1_FULL_SZ 1
+#define CH2_FULL_MSK 0x00000004
+#define CH2_FULL_I_MSK 0xfffffffb
+#define CH2_FULL_SFT 2
+#define CH2_FULL_HI 2
+#define CH2_FULL_SZ 1
+#define CH3_FULL_MSK 0x00000008
+#define CH3_FULL_I_MSK 0xfffffff7
+#define CH3_FULL_SFT 3
+#define CH3_FULL_HI 3
+#define CH3_FULL_SZ 1
+#define CH4_FULL_MSK 0x00000010
+#define CH4_FULL_I_MSK 0xffffffef
+#define CH4_FULL_SFT 4
+#define CH4_FULL_HI 4
+#define CH4_FULL_SZ 1
+#define CH5_FULL_MSK 0x00000020
+#define CH5_FULL_I_MSK 0xffffffdf
+#define CH5_FULL_SFT 5
+#define CH5_FULL_HI 5
+#define CH5_FULL_SZ 1
+#define CH6_FULL_MSK 0x00000040
+#define CH6_FULL_I_MSK 0xffffffbf
+#define CH6_FULL_SFT 6
+#define CH6_FULL_HI 6
+#define CH6_FULL_SZ 1
+#define CH7_FULL_MSK 0x00000080
+#define CH7_FULL_I_MSK 0xffffff7f
+#define CH7_FULL_SFT 7
+#define CH7_FULL_HI 7
+#define CH7_FULL_SZ 1
+#define CH8_FULL_MSK 0x00000100
+#define CH8_FULL_I_MSK 0xfffffeff
+#define CH8_FULL_SFT 8
+#define CH8_FULL_HI 8
+#define CH8_FULL_SZ 1
+#define CH9_FULL_MSK 0x00000200
+#define CH9_FULL_I_MSK 0xfffffdff
+#define CH9_FULL_SFT 9
+#define CH9_FULL_HI 9
+#define CH9_FULL_SZ 1
+#define CH10_FULL_MSK 0x00000400
+#define CH10_FULL_I_MSK 0xfffffbff
+#define CH10_FULL_SFT 10
+#define CH10_FULL_HI 10
+#define CH10_FULL_SZ 1
+#define CH11_FULL_MSK 0x00000800
+#define CH11_FULL_I_MSK 0xfffff7ff
+#define CH11_FULL_SFT 11
+#define CH11_FULL_HI 11
+#define CH11_FULL_SZ 1
+#define CH12_FULL_MSK 0x00001000
+#define CH12_FULL_I_MSK 0xffffefff
+#define CH12_FULL_SFT 12
+#define CH12_FULL_HI 12
+#define CH12_FULL_SZ 1
+#define CH13_FULL_MSK 0x00002000
+#define CH13_FULL_I_MSK 0xffffdfff
+#define CH13_FULL_SFT 13
+#define CH13_FULL_HI 13
+#define CH13_FULL_SZ 1
+#define CH14_FULL_MSK 0x00004000
+#define CH14_FULL_I_MSK 0xffffbfff
+#define CH14_FULL_SFT 14
+#define CH14_FULL_HI 14
+#define CH14_FULL_SZ 1
+#define CH15_FULL_MSK 0x00008000
+#define CH15_FULL_I_MSK 0xffff7fff
+#define CH15_FULL_SFT 15
+#define CH15_FULL_HI 15
+#define CH15_FULL_SZ 1
+#define HALT_CH0_MSK 0x00000001
+#define HALT_CH0_I_MSK 0xfffffffe
+#define HALT_CH0_SFT 0
+#define HALT_CH0_HI 0
+#define HALT_CH0_SZ 1
+#define HALT_CH1_MSK 0x00000002
+#define HALT_CH1_I_MSK 0xfffffffd
+#define HALT_CH1_SFT 1
+#define HALT_CH1_HI 1
+#define HALT_CH1_SZ 1
+#define HALT_CH2_MSK 0x00000004
+#define HALT_CH2_I_MSK 0xfffffffb
+#define HALT_CH2_SFT 2
+#define HALT_CH2_HI 2
+#define HALT_CH2_SZ 1
+#define HALT_CH3_MSK 0x00000008
+#define HALT_CH3_I_MSK 0xfffffff7
+#define HALT_CH3_SFT 3
+#define HALT_CH3_HI 3
+#define HALT_CH3_SZ 1
+#define HALT_CH4_MSK 0x00000010
+#define HALT_CH4_I_MSK 0xffffffef
+#define HALT_CH4_SFT 4
+#define HALT_CH4_HI 4
+#define HALT_CH4_SZ 1
+#define HALT_CH5_MSK 0x00000020
+#define HALT_CH5_I_MSK 0xffffffdf
+#define HALT_CH5_SFT 5
+#define HALT_CH5_HI 5
+#define HALT_CH5_SZ 1
+#define HALT_CH6_MSK 0x00000040
+#define HALT_CH6_I_MSK 0xffffffbf
+#define HALT_CH6_SFT 6
+#define HALT_CH6_HI 6
+#define HALT_CH6_SZ 1
+#define HALT_CH7_MSK 0x00000080
+#define HALT_CH7_I_MSK 0xffffff7f
+#define HALT_CH7_SFT 7
+#define HALT_CH7_HI 7
+#define HALT_CH7_SZ 1
+#define HALT_CH8_MSK 0x00000100
+#define HALT_CH8_I_MSK 0xfffffeff
+#define HALT_CH8_SFT 8
+#define HALT_CH8_HI 8
+#define HALT_CH8_SZ 1
+#define HALT_CH9_MSK 0x00000200
+#define HALT_CH9_I_MSK 0xfffffdff
+#define HALT_CH9_SFT 9
+#define HALT_CH9_HI 9
+#define HALT_CH9_SZ 1
+#define HALT_CH10_MSK 0x00000400
+#define HALT_CH10_I_MSK 0xfffffbff
+#define HALT_CH10_SFT 10
+#define HALT_CH10_HI 10
+#define HALT_CH10_SZ 1
+#define HALT_CH11_MSK 0x00000800
+#define HALT_CH11_I_MSK 0xfffff7ff
+#define HALT_CH11_SFT 11
+#define HALT_CH11_HI 11
+#define HALT_CH11_SZ 1
+#define HALT_CH12_MSK 0x00001000
+#define HALT_CH12_I_MSK 0xffffefff
+#define HALT_CH12_SFT 12
+#define HALT_CH12_HI 12
+#define HALT_CH12_SZ 1
+#define HALT_CH13_MSK 0x00002000
+#define HALT_CH13_I_MSK 0xffffdfff
+#define HALT_CH13_SFT 13
+#define HALT_CH13_HI 13
+#define HALT_CH13_SZ 1
+#define HALT_CH14_MSK 0x00004000
+#define HALT_CH14_I_MSK 0xffffbfff
+#define HALT_CH14_SFT 14
+#define HALT_CH14_HI 14
+#define HALT_CH14_SZ 1
+#define HALT_CH15_MSK 0x00008000
+#define HALT_CH15_I_MSK 0xffff7fff
+#define HALT_CH15_SFT 15
+#define HALT_CH15_HI 15
+#define HALT_CH15_SZ 1
+#define STOP_MBOX_MSK 0x00010000
+#define STOP_MBOX_I_MSK 0xfffeffff
+#define STOP_MBOX_SFT 16
+#define STOP_MBOX_HI 16
+#define STOP_MBOX_SZ 1
+#define MB_ERR_AUTO_HALT_EN_MSK 0x00100000
+#define MB_ERR_AUTO_HALT_EN_I_MSK 0xffefffff
+#define MB_ERR_AUTO_HALT_EN_SFT 20
+#define MB_ERR_AUTO_HALT_EN_HI 20
+#define MB_ERR_AUTO_HALT_EN_SZ 1
+#define MB_EXCEPT_CLR_MSK 0x00200000
+#define MB_EXCEPT_CLR_I_MSK 0xffdfffff
+#define MB_EXCEPT_CLR_SFT 21
+#define MB_EXCEPT_CLR_HI 21
+#define MB_EXCEPT_CLR_SZ 1
+#define MB_EXCEPT_CASE_MSK 0xff000000
+#define MB_EXCEPT_CASE_I_MSK 0x00ffffff
+#define MB_EXCEPT_CASE_SFT 24
+#define MB_EXCEPT_CASE_HI 31
+#define MB_EXCEPT_CASE_SZ 8
+#define MB_DBG_TIME_STEP_MSK 0x0000ffff
+#define MB_DBG_TIME_STEP_I_MSK 0xffff0000
+#define MB_DBG_TIME_STEP_SFT 0
+#define MB_DBG_TIME_STEP_HI 15
+#define MB_DBG_TIME_STEP_SZ 16
+#define DBG_TYPE_MSK 0x00030000
+#define DBG_TYPE_I_MSK 0xfffcffff
+#define DBG_TYPE_SFT 16
+#define DBG_TYPE_HI 17
+#define DBG_TYPE_SZ 2
+#define MB_DBG_CLR_MSK 0x00040000
+#define MB_DBG_CLR_I_MSK 0xfffbffff
+#define MB_DBG_CLR_SFT 18
+#define MB_DBG_CLR_HI 18
+#define MB_DBG_CLR_SZ 1
+#define DBG_ALC_LOG_EN_MSK 0x00080000
+#define DBG_ALC_LOG_EN_I_MSK 0xfff7ffff
+#define DBG_ALC_LOG_EN_SFT 19
+#define DBG_ALC_LOG_EN_HI 19
+#define DBG_ALC_LOG_EN_SZ 1
+#define MB_DBG_COUNTER_EN_MSK 0x01000000
+#define MB_DBG_COUNTER_EN_I_MSK 0xfeffffff
+#define MB_DBG_COUNTER_EN_SFT 24
+#define MB_DBG_COUNTER_EN_HI 24
+#define MB_DBG_COUNTER_EN_SZ 1
+#define MB_DBG_EN_MSK 0x80000000
+#define MB_DBG_EN_I_MSK 0x7fffffff
+#define MB_DBG_EN_SFT 31
+#define MB_DBG_EN_HI 31
+#define MB_DBG_EN_SZ 1
+#define MB_DBG_RECORD_CNT_MSK 0x0000ffff
+#define MB_DBG_RECORD_CNT_I_MSK 0xffff0000
+#define MB_DBG_RECORD_CNT_SFT 0
+#define MB_DBG_RECORD_CNT_HI 15
+#define MB_DBG_RECORD_CNT_SZ 16
+#define MB_DBG_LENGTH_MSK 0xffff0000
+#define MB_DBG_LENGTH_I_MSK 0x0000ffff
+#define MB_DBG_LENGTH_SFT 16
+#define MB_DBG_LENGTH_HI 31
+#define MB_DBG_LENGTH_SZ 16
+#define MB_DBG_CFG_ADDR_MSK 0xffffffff
+#define MB_DBG_CFG_ADDR_I_MSK 0x00000000
+#define MB_DBG_CFG_ADDR_SFT 0
+#define MB_DBG_CFG_ADDR_HI 31
+#define MB_DBG_CFG_ADDR_SZ 32
+#define DBG_HWID0_WR_EN_MSK 0x00000001
+#define DBG_HWID0_WR_EN_I_MSK 0xfffffffe
+#define DBG_HWID0_WR_EN_SFT 0
+#define DBG_HWID0_WR_EN_HI 0
+#define DBG_HWID0_WR_EN_SZ 1
+#define DBG_HWID1_WR_EN_MSK 0x00000002
+#define DBG_HWID1_WR_EN_I_MSK 0xfffffffd
+#define DBG_HWID1_WR_EN_SFT 1
+#define DBG_HWID1_WR_EN_HI 1
+#define DBG_HWID1_WR_EN_SZ 1
+#define DBG_HWID2_WR_EN_MSK 0x00000004
+#define DBG_HWID2_WR_EN_I_MSK 0xfffffffb
+#define DBG_HWID2_WR_EN_SFT 2
+#define DBG_HWID2_WR_EN_HI 2
+#define DBG_HWID2_WR_EN_SZ 1
+#define DBG_HWID3_WR_EN_MSK 0x00000008
+#define DBG_HWID3_WR_EN_I_MSK 0xfffffff7
+#define DBG_HWID3_WR_EN_SFT 3
+#define DBG_HWID3_WR_EN_HI 3
+#define DBG_HWID3_WR_EN_SZ 1
+#define DBG_HWID4_WR_EN_MSK 0x00000010
+#define DBG_HWID4_WR_EN_I_MSK 0xffffffef
+#define DBG_HWID4_WR_EN_SFT 4
+#define DBG_HWID4_WR_EN_HI 4
+#define DBG_HWID4_WR_EN_SZ 1
+#define DBG_HWID5_WR_EN_MSK 0x00000020
+#define DBG_HWID5_WR_EN_I_MSK 0xffffffdf
+#define DBG_HWID5_WR_EN_SFT 5
+#define DBG_HWID5_WR_EN_HI 5
+#define DBG_HWID5_WR_EN_SZ 1
+#define DBG_HWID6_WR_EN_MSK 0x00000040
+#define DBG_HWID6_WR_EN_I_MSK 0xffffffbf
+#define DBG_HWID6_WR_EN_SFT 6
+#define DBG_HWID6_WR_EN_HI 6
+#define DBG_HWID6_WR_EN_SZ 1
+#define DBG_HWID7_WR_EN_MSK 0x00000080
+#define DBG_HWID7_WR_EN_I_MSK 0xffffff7f
+#define DBG_HWID7_WR_EN_SFT 7
+#define DBG_HWID7_WR_EN_HI 7
+#define DBG_HWID7_WR_EN_SZ 1
+#define DBG_HWID8_WR_EN_MSK 0x00000100
+#define DBG_HWID8_WR_EN_I_MSK 0xfffffeff
+#define DBG_HWID8_WR_EN_SFT 8
+#define DBG_HWID8_WR_EN_HI 8
+#define DBG_HWID8_WR_EN_SZ 1
+#define DBG_HWID9_WR_EN_MSK 0x00000200
+#define DBG_HWID9_WR_EN_I_MSK 0xfffffdff
+#define DBG_HWID9_WR_EN_SFT 9
+#define DBG_HWID9_WR_EN_HI 9
+#define DBG_HWID9_WR_EN_SZ 1
+#define DBG_HWID10_WR_EN_MSK 0x00000400
+#define DBG_HWID10_WR_EN_I_MSK 0xfffffbff
+#define DBG_HWID10_WR_EN_SFT 10
+#define DBG_HWID10_WR_EN_HI 10
+#define DBG_HWID10_WR_EN_SZ 1
+#define DBG_HWID11_WR_EN_MSK 0x00000800
+#define DBG_HWID11_WR_EN_I_MSK 0xfffff7ff
+#define DBG_HWID11_WR_EN_SFT 11
+#define DBG_HWID11_WR_EN_HI 11
+#define DBG_HWID11_WR_EN_SZ 1
+#define DBG_HWID12_WR_EN_MSK 0x00001000
+#define DBG_HWID12_WR_EN_I_MSK 0xffffefff
+#define DBG_HWID12_WR_EN_SFT 12
+#define DBG_HWID12_WR_EN_HI 12
+#define DBG_HWID12_WR_EN_SZ 1
+#define DBG_HWID13_WR_EN_MSK 0x00002000
+#define DBG_HWID13_WR_EN_I_MSK 0xffffdfff
+#define DBG_HWID13_WR_EN_SFT 13
+#define DBG_HWID13_WR_EN_HI 13
+#define DBG_HWID13_WR_EN_SZ 1
+#define DBG_HWID14_WR_EN_MSK 0x00004000
+#define DBG_HWID14_WR_EN_I_MSK 0xffffbfff
+#define DBG_HWID14_WR_EN_SFT 14
+#define DBG_HWID14_WR_EN_HI 14
+#define DBG_HWID14_WR_EN_SZ 1
+#define DBG_HWID15_WR_EN_MSK 0x00008000
+#define DBG_HWID15_WR_EN_I_MSK 0xffff7fff
+#define DBG_HWID15_WR_EN_SFT 15
+#define DBG_HWID15_WR_EN_HI 15
+#define DBG_HWID15_WR_EN_SZ 1
+#define DBG_HWID0_RD_EN_MSK 0x00010000
+#define DBG_HWID0_RD_EN_I_MSK 0xfffeffff
+#define DBG_HWID0_RD_EN_SFT 16
+#define DBG_HWID0_RD_EN_HI 16
+#define DBG_HWID0_RD_EN_SZ 1
+#define DBG_HWID1_RD_EN_MSK 0x00020000
+#define DBG_HWID1_RD_EN_I_MSK 0xfffdffff
+#define DBG_HWID1_RD_EN_SFT 17
+#define DBG_HWID1_RD_EN_HI 17
+#define DBG_HWID1_RD_EN_SZ 1
+#define DBG_HWID2_RD_EN_MSK 0x00040000
+#define DBG_HWID2_RD_EN_I_MSK 0xfffbffff
+#define DBG_HWID2_RD_EN_SFT 18
+#define DBG_HWID2_RD_EN_HI 18
+#define DBG_HWID2_RD_EN_SZ 1
+#define DBG_HWID3_RD_EN_MSK 0x00080000
+#define DBG_HWID3_RD_EN_I_MSK 0xfff7ffff
+#define DBG_HWID3_RD_EN_SFT 19
+#define DBG_HWID3_RD_EN_HI 19
+#define DBG_HWID3_RD_EN_SZ 1
+#define DBG_HWID4_RD_EN_MSK 0x00100000
+#define DBG_HWID4_RD_EN_I_MSK 0xffefffff
+#define DBG_HWID4_RD_EN_SFT 20
+#define DBG_HWID4_RD_EN_HI 20
+#define DBG_HWID4_RD_EN_SZ 1
+#define DBG_HWID5_RD_EN_MSK 0x00200000
+#define DBG_HWID5_RD_EN_I_MSK 0xffdfffff
+#define DBG_HWID5_RD_EN_SFT 21
+#define DBG_HWID5_RD_EN_HI 21
+#define DBG_HWID5_RD_EN_SZ 1
+#define DBG_HWID6_RD_EN_MSK 0x00400000
+#define DBG_HWID6_RD_EN_I_MSK 0xffbfffff
+#define DBG_HWID6_RD_EN_SFT 22
+#define DBG_HWID6_RD_EN_HI 22
+#define DBG_HWID6_RD_EN_SZ 1
+#define DBG_HWID7_RD_EN_MSK 0x00800000
+#define DBG_HWID7_RD_EN_I_MSK 0xff7fffff
+#define DBG_HWID7_RD_EN_SFT 23
+#define DBG_HWID7_RD_EN_HI 23
+#define DBG_HWID7_RD_EN_SZ 1
+#define DBG_HWID8_RD_EN_MSK 0x01000000
+#define DBG_HWID8_RD_EN_I_MSK 0xfeffffff
+#define DBG_HWID8_RD_EN_SFT 24
+#define DBG_HWID8_RD_EN_HI 24
+#define DBG_HWID8_RD_EN_SZ 1
+#define DBG_HWID9_RD_EN_MSK 0x02000000
+#define DBG_HWID9_RD_EN_I_MSK 0xfdffffff
+#define DBG_HWID9_RD_EN_SFT 25
+#define DBG_HWID9_RD_EN_HI 25
+#define DBG_HWID9_RD_EN_SZ 1
+#define DBG_HWID10_RD_EN_MSK 0x04000000
+#define DBG_HWID10_RD_EN_I_MSK 0xfbffffff
+#define DBG_HWID10_RD_EN_SFT 26
+#define DBG_HWID10_RD_EN_HI 26
+#define DBG_HWID10_RD_EN_SZ 1
+#define DBG_HWID11_RD_EN_MSK 0x08000000
+#define DBG_HWID11_RD_EN_I_MSK 0xf7ffffff
+#define DBG_HWID11_RD_EN_SFT 27
+#define DBG_HWID11_RD_EN_HI 27
+#define DBG_HWID11_RD_EN_SZ 1
+#define DBG_HWID12_RD_EN_MSK 0x10000000
+#define DBG_HWID12_RD_EN_I_MSK 0xefffffff
+#define DBG_HWID12_RD_EN_SFT 28
+#define DBG_HWID12_RD_EN_HI 28
+#define DBG_HWID12_RD_EN_SZ 1
+#define DBG_HWID13_RD_EN_MSK 0x20000000
+#define DBG_HWID13_RD_EN_I_MSK 0xdfffffff
+#define DBG_HWID13_RD_EN_SFT 29
+#define DBG_HWID13_RD_EN_HI 29
+#define DBG_HWID13_RD_EN_SZ 1
+#define DBG_HWID14_RD_EN_MSK 0x40000000
+#define DBG_HWID14_RD_EN_I_MSK 0xbfffffff
+#define DBG_HWID14_RD_EN_SFT 30
+#define DBG_HWID14_RD_EN_HI 30
+#define DBG_HWID14_RD_EN_SZ 1
+#define DBG_HWID15_RD_EN_MSK 0x80000000
+#define DBG_HWID15_RD_EN_I_MSK 0x7fffffff
+#define DBG_HWID15_RD_EN_SFT 31
+#define DBG_HWID15_RD_EN_HI 31
+#define DBG_HWID15_RD_EN_SZ 1
+#define MB_OUT_QUEUE_EN_MSK 0x00000002
+#define MB_OUT_QUEUE_EN_I_MSK 0xfffffffd
+#define MB_OUT_QUEUE_EN_SFT 1
+#define MB_OUT_QUEUE_EN_HI 1
+#define MB_OUT_QUEUE_EN_SZ 1
+#define CH0_QUEUE_FLUSH_MSK 0x00000001
+#define CH0_QUEUE_FLUSH_I_MSK 0xfffffffe
+#define CH0_QUEUE_FLUSH_SFT 0
+#define CH0_QUEUE_FLUSH_HI 0
+#define CH0_QUEUE_FLUSH_SZ 1
+#define CH1_QUEUE_FLUSH_MSK 0x00000002
+#define CH1_QUEUE_FLUSH_I_MSK 0xfffffffd
+#define CH1_QUEUE_FLUSH_SFT 1
+#define CH1_QUEUE_FLUSH_HI 1
+#define CH1_QUEUE_FLUSH_SZ 1
+#define CH2_QUEUE_FLUSH_MSK 0x00000004
+#define CH2_QUEUE_FLUSH_I_MSK 0xfffffffb
+#define CH2_QUEUE_FLUSH_SFT 2
+#define CH2_QUEUE_FLUSH_HI 2
+#define CH2_QUEUE_FLUSH_SZ 1
+#define CH3_QUEUE_FLUSH_MSK 0x00000008
+#define CH3_QUEUE_FLUSH_I_MSK 0xfffffff7
+#define CH3_QUEUE_FLUSH_SFT 3
+#define CH3_QUEUE_FLUSH_HI 3
+#define CH3_QUEUE_FLUSH_SZ 1
+#define CH4_QUEUE_FLUSH_MSK 0x00000010
+#define CH4_QUEUE_FLUSH_I_MSK 0xffffffef
+#define CH4_QUEUE_FLUSH_SFT 4
+#define CH4_QUEUE_FLUSH_HI 4
+#define CH4_QUEUE_FLUSH_SZ 1
+#define CH5_QUEUE_FLUSH_MSK 0x00000020
+#define CH5_QUEUE_FLUSH_I_MSK 0xffffffdf
+#define CH5_QUEUE_FLUSH_SFT 5
+#define CH5_QUEUE_FLUSH_HI 5
+#define CH5_QUEUE_FLUSH_SZ 1
+#define CH6_QUEUE_FLUSH_MSK 0x00000040
+#define CH6_QUEUE_FLUSH_I_MSK 0xffffffbf
+#define CH6_QUEUE_FLUSH_SFT 6
+#define CH6_QUEUE_FLUSH_HI 6
+#define CH6_QUEUE_FLUSH_SZ 1
+#define CH7_QUEUE_FLUSH_MSK 0x00000080
+#define CH7_QUEUE_FLUSH_I_MSK 0xffffff7f
+#define CH7_QUEUE_FLUSH_SFT 7
+#define CH7_QUEUE_FLUSH_HI 7
+#define CH7_QUEUE_FLUSH_SZ 1
+#define CH8_QUEUE_FLUSH_MSK 0x00000100
+#define CH8_QUEUE_FLUSH_I_MSK 0xfffffeff
+#define CH8_QUEUE_FLUSH_SFT 8
+#define CH8_QUEUE_FLUSH_HI 8
+#define CH8_QUEUE_FLUSH_SZ 1
+#define CH9_QUEUE_FLUSH_MSK 0x00000200
+#define CH9_QUEUE_FLUSH_I_MSK 0xfffffdff
+#define CH9_QUEUE_FLUSH_SFT 9
+#define CH9_QUEUE_FLUSH_HI 9
+#define CH9_QUEUE_FLUSH_SZ 1
+#define CH10_QUEUE_FLUSH_MSK 0x00000400
+#define CH10_QUEUE_FLUSH_I_MSK 0xfffffbff
+#define CH10_QUEUE_FLUSH_SFT 10
+#define CH10_QUEUE_FLUSH_HI 10
+#define CH10_QUEUE_FLUSH_SZ 1
+#define CH11_QUEUE_FLUSH_MSK 0x00000800
+#define CH11_QUEUE_FLUSH_I_MSK 0xfffff7ff
+#define CH11_QUEUE_FLUSH_SFT 11
+#define CH11_QUEUE_FLUSH_HI 11
+#define CH11_QUEUE_FLUSH_SZ 1
+#define CH12_QUEUE_FLUSH_MSK 0x00001000
+#define CH12_QUEUE_FLUSH_I_MSK 0xffffefff
+#define CH12_QUEUE_FLUSH_SFT 12
+#define CH12_QUEUE_FLUSH_HI 12
+#define CH12_QUEUE_FLUSH_SZ 1
+#define CH13_QUEUE_FLUSH_MSK 0x00002000
+#define CH13_QUEUE_FLUSH_I_MSK 0xffffdfff
+#define CH13_QUEUE_FLUSH_SFT 13
+#define CH13_QUEUE_FLUSH_HI 13
+#define CH13_QUEUE_FLUSH_SZ 1
+#define CH14_QUEUE_FLUSH_MSK 0x00004000
+#define CH14_QUEUE_FLUSH_I_MSK 0xffffbfff
+#define CH14_QUEUE_FLUSH_SFT 14
+#define CH14_QUEUE_FLUSH_HI 14
+#define CH14_QUEUE_FLUSH_SZ 1
+#define CH15_QUEUE_FLUSH_MSK 0x00008000
+#define CH15_QUEUE_FLUSH_I_MSK 0xffff7fff
+#define CH15_QUEUE_FLUSH_SFT 15
+#define CH15_QUEUE_FLUSH_HI 15
+#define CH15_QUEUE_FLUSH_SZ 1
+#define FFO0_CNT_MSK 0x0000001f
+#define FFO0_CNT_I_MSK 0xffffffe0
+#define FFO0_CNT_SFT 0
+#define FFO0_CNT_HI 4
+#define FFO0_CNT_SZ 5
+#define FFO1_CNT_MSK 0x000003e0
+#define FFO1_CNT_I_MSK 0xfffffc1f
+#define FFO1_CNT_SFT 5
+#define FFO1_CNT_HI 9
+#define FFO1_CNT_SZ 5
+#define FFO2_CNT_MSK 0x00000c00
+#define FFO2_CNT_I_MSK 0xfffff3ff
+#define FFO2_CNT_SFT 10
+#define FFO2_CNT_HI 11
+#define FFO2_CNT_SZ 2
+#define FFO3_CNT_MSK 0x000f8000
+#define FFO3_CNT_I_MSK 0xfff07fff
+#define FFO3_CNT_SFT 15
+#define FFO3_CNT_HI 19
+#define FFO3_CNT_SZ 5
+#define FFO4_CNT_MSK 0x00300000
+#define FFO4_CNT_I_MSK 0xffcfffff
+#define FFO4_CNT_SFT 20
+#define FFO4_CNT_HI 21
+#define FFO4_CNT_SZ 2
+#define FFO5_CNT_MSK 0x0e000000
+#define FFO5_CNT_I_MSK 0xf1ffffff
+#define FFO5_CNT_SFT 25
+#define FFO5_CNT_HI 27
+#define FFO5_CNT_SZ 3
+#define FFO6_CNT_MSK 0x0000000f
+#define FFO6_CNT_I_MSK 0xfffffff0
+#define FFO6_CNT_SFT 0
+#define FFO6_CNT_HI 3
+#define FFO6_CNT_SZ 4
+#define FFO7_CNT_MSK 0x000003e0
+#define FFO7_CNT_I_MSK 0xfffffc1f
+#define FFO7_CNT_SFT 5
+#define FFO7_CNT_HI 9
+#define FFO7_CNT_SZ 5
+#define FFO8_CNT_MSK 0x00007c00
+#define FFO8_CNT_I_MSK 0xffff83ff
+#define FFO8_CNT_SFT 10
+#define FFO8_CNT_HI 14
+#define FFO8_CNT_SZ 5
+#define FFO9_CNT_MSK 0x000f8000
+#define FFO9_CNT_I_MSK 0xfff07fff
+#define FFO9_CNT_SFT 15
+#define FFO9_CNT_HI 19
+#define FFO9_CNT_SZ 5
+#define FFO10_CNT_MSK 0x00f00000
+#define FFO10_CNT_I_MSK 0xff0fffff
+#define FFO10_CNT_SFT 20
+#define FFO10_CNT_HI 23
+#define FFO10_CNT_SZ 4
+#define FFO11_CNT_MSK 0x3e000000
+#define FFO11_CNT_I_MSK 0xc1ffffff
+#define FFO11_CNT_SFT 25
+#define FFO11_CNT_HI 29
+#define FFO11_CNT_SZ 5
+#define FFO12_CNT_MSK 0x00000007
+#define FFO12_CNT_I_MSK 0xfffffff8
+#define FFO12_CNT_SFT 0
+#define FFO12_CNT_HI 2
+#define FFO12_CNT_SZ 3
+#define FFO13_CNT_MSK 0x00000060
+#define FFO13_CNT_I_MSK 0xffffff9f
+#define FFO13_CNT_SFT 5
+#define FFO13_CNT_HI 6
+#define FFO13_CNT_SZ 2
+#define FFO14_CNT_MSK 0x00000c00
+#define FFO14_CNT_I_MSK 0xfffff3ff
+#define FFO14_CNT_SFT 10
+#define FFO14_CNT_HI 11
+#define FFO14_CNT_SZ 2
+#define FFO15_CNT_MSK 0x001f8000
+#define FFO15_CNT_I_MSK 0xffe07fff
+#define FFO15_CNT_SFT 15
+#define FFO15_CNT_HI 20
+#define FFO15_CNT_SZ 6
+#define CH0_FFO_FULL_MSK 0x00000001
+#define CH0_FFO_FULL_I_MSK 0xfffffffe
+#define CH0_FFO_FULL_SFT 0
+#define CH0_FFO_FULL_HI 0
+#define CH0_FFO_FULL_SZ 1
+#define CH1_FFO_FULL_MSK 0x00000002
+#define CH1_FFO_FULL_I_MSK 0xfffffffd
+#define CH1_FFO_FULL_SFT 1
+#define CH1_FFO_FULL_HI 1
+#define CH1_FFO_FULL_SZ 1
+#define CH2_FFO_FULL_MSK 0x00000004
+#define CH2_FFO_FULL_I_MSK 0xfffffffb
+#define CH2_FFO_FULL_SFT 2
+#define CH2_FFO_FULL_HI 2
+#define CH2_FFO_FULL_SZ 1
+#define CH3_FFO_FULL_MSK 0x00000008
+#define CH3_FFO_FULL_I_MSK 0xfffffff7
+#define CH3_FFO_FULL_SFT 3
+#define CH3_FFO_FULL_HI 3
+#define CH3_FFO_FULL_SZ 1
+#define CH4_FFO_FULL_MSK 0x00000010
+#define CH4_FFO_FULL_I_MSK 0xffffffef
+#define CH4_FFO_FULL_SFT 4
+#define CH4_FFO_FULL_HI 4
+#define CH4_FFO_FULL_SZ 1
+#define CH5_FFO_FULL_MSK 0x00000020
+#define CH5_FFO_FULL_I_MSK 0xffffffdf
+#define CH5_FFO_FULL_SFT 5
+#define CH5_FFO_FULL_HI 5
+#define CH5_FFO_FULL_SZ 1
+#define CH6_FFO_FULL_MSK 0x00000040
+#define CH6_FFO_FULL_I_MSK 0xffffffbf
+#define CH6_FFO_FULL_SFT 6
+#define CH6_FFO_FULL_HI 6
+#define CH6_FFO_FULL_SZ 1
+#define CH7_FFO_FULL_MSK 0x00000080
+#define CH7_FFO_FULL_I_MSK 0xffffff7f
+#define CH7_FFO_FULL_SFT 7
+#define CH7_FFO_FULL_HI 7
+#define CH7_FFO_FULL_SZ 1
+#define CH8_FFO_FULL_MSK 0x00000100
+#define CH8_FFO_FULL_I_MSK 0xfffffeff
+#define CH8_FFO_FULL_SFT 8
+#define CH8_FFO_FULL_HI 8
+#define CH8_FFO_FULL_SZ 1
+#define CH9_FFO_FULL_MSK 0x00000200
+#define CH9_FFO_FULL_I_MSK 0xfffffdff
+#define CH9_FFO_FULL_SFT 9
+#define CH9_FFO_FULL_HI 9
+#define CH9_FFO_FULL_SZ 1
+#define CH10_FFO_FULL_MSK 0x00000400
+#define CH10_FFO_FULL_I_MSK 0xfffffbff
+#define CH10_FFO_FULL_SFT 10
+#define CH10_FFO_FULL_HI 10
+#define CH10_FFO_FULL_SZ 1
+#define CH11_FFO_FULL_MSK 0x00000800
+#define CH11_FFO_FULL_I_MSK 0xfffff7ff
+#define CH11_FFO_FULL_SFT 11
+#define CH11_FFO_FULL_HI 11
+#define CH11_FFO_FULL_SZ 1
+#define CH12_FFO_FULL_MSK 0x00001000
+#define CH12_FFO_FULL_I_MSK 0xffffefff
+#define CH12_FFO_FULL_SFT 12
+#define CH12_FFO_FULL_HI 12
+#define CH12_FFO_FULL_SZ 1
+#define CH13_FFO_FULL_MSK 0x00002000
+#define CH13_FFO_FULL_I_MSK 0xffffdfff
+#define CH13_FFO_FULL_SFT 13
+#define CH13_FFO_FULL_HI 13
+#define CH13_FFO_FULL_SZ 1
+#define CH14_FFO_FULL_MSK 0x00004000
+#define CH14_FFO_FULL_I_MSK 0xffffbfff
+#define CH14_FFO_FULL_SFT 14
+#define CH14_FFO_FULL_HI 14
+#define CH14_FFO_FULL_SZ 1
+#define CH15_FFO_FULL_MSK 0x00008000
+#define CH15_FFO_FULL_I_MSK 0xffff7fff
+#define CH15_FFO_FULL_SFT 15
+#define CH15_FFO_FULL_HI 15
+#define CH15_FFO_FULL_SZ 1
+#define CH0_LOWTHOLD_INT_MSK 0x00000001
+#define CH0_LOWTHOLD_INT_I_MSK 0xfffffffe
+#define CH0_LOWTHOLD_INT_SFT 0
+#define CH0_LOWTHOLD_INT_HI 0
+#define CH0_LOWTHOLD_INT_SZ 1
+#define CH1_LOWTHOLD_INT_MSK 0x00000002
+#define CH1_LOWTHOLD_INT_I_MSK 0xfffffffd
+#define CH1_LOWTHOLD_INT_SFT 1
+#define CH1_LOWTHOLD_INT_HI 1
+#define CH1_LOWTHOLD_INT_SZ 1
+#define CH2_LOWTHOLD_INT_MSK 0x00000004
+#define CH2_LOWTHOLD_INT_I_MSK 0xfffffffb
+#define CH2_LOWTHOLD_INT_SFT 2
+#define CH2_LOWTHOLD_INT_HI 2
+#define CH2_LOWTHOLD_INT_SZ 1
+#define CH3_LOWTHOLD_INT_MSK 0x00000008
+#define CH3_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define CH3_LOWTHOLD_INT_SFT 3
+#define CH3_LOWTHOLD_INT_HI 3
+#define CH3_LOWTHOLD_INT_SZ 1
+#define CH4_LOWTHOLD_INT_MSK 0x00000010
+#define CH4_LOWTHOLD_INT_I_MSK 0xffffffef
+#define CH4_LOWTHOLD_INT_SFT 4
+#define CH4_LOWTHOLD_INT_HI 4
+#define CH4_LOWTHOLD_INT_SZ 1
+#define CH5_LOWTHOLD_INT_MSK 0x00000020
+#define CH5_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define CH5_LOWTHOLD_INT_SFT 5
+#define CH5_LOWTHOLD_INT_HI 5
+#define CH5_LOWTHOLD_INT_SZ 1
+#define CH6_LOWTHOLD_INT_MSK 0x00000040
+#define CH6_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define CH6_LOWTHOLD_INT_SFT 6
+#define CH6_LOWTHOLD_INT_HI 6
+#define CH6_LOWTHOLD_INT_SZ 1
+#define CH7_LOWTHOLD_INT_MSK 0x00000080
+#define CH7_LOWTHOLD_INT_I_MSK 0xffffff7f
+#define CH7_LOWTHOLD_INT_SFT 7
+#define CH7_LOWTHOLD_INT_HI 7
+#define CH7_LOWTHOLD_INT_SZ 1
+#define CH8_LOWTHOLD_INT_MSK 0x00000100
+#define CH8_LOWTHOLD_INT_I_MSK 0xfffffeff
+#define CH8_LOWTHOLD_INT_SFT 8
+#define CH8_LOWTHOLD_INT_HI 8
+#define CH8_LOWTHOLD_INT_SZ 1
+#define CH9_LOWTHOLD_INT_MSK 0x00000200
+#define CH9_LOWTHOLD_INT_I_MSK 0xfffffdff
+#define CH9_LOWTHOLD_INT_SFT 9
+#define CH9_LOWTHOLD_INT_HI 9
+#define CH9_LOWTHOLD_INT_SZ 1
+#define CH10_LOWTHOLD_INT_MSK 0x00000400
+#define CH10_LOWTHOLD_INT_I_MSK 0xfffffbff
+#define CH10_LOWTHOLD_INT_SFT 10
+#define CH10_LOWTHOLD_INT_HI 10
+#define CH10_LOWTHOLD_INT_SZ 1
+#define CH11_LOWTHOLD_INT_MSK 0x00000800
+#define CH11_LOWTHOLD_INT_I_MSK 0xfffff7ff
+#define CH11_LOWTHOLD_INT_SFT 11
+#define CH11_LOWTHOLD_INT_HI 11
+#define CH11_LOWTHOLD_INT_SZ 1
+#define CH12_LOWTHOLD_INT_MSK 0x00001000
+#define CH12_LOWTHOLD_INT_I_MSK 0xffffefff
+#define CH12_LOWTHOLD_INT_SFT 12
+#define CH12_LOWTHOLD_INT_HI 12
+#define CH12_LOWTHOLD_INT_SZ 1
+#define CH13_LOWTHOLD_INT_MSK 0x00002000
+#define CH13_LOWTHOLD_INT_I_MSK 0xffffdfff
+#define CH13_LOWTHOLD_INT_SFT 13
+#define CH13_LOWTHOLD_INT_HI 13
+#define CH13_LOWTHOLD_INT_SZ 1
+#define CH14_LOWTHOLD_INT_MSK 0x00004000
+#define CH14_LOWTHOLD_INT_I_MSK 0xffffbfff
+#define CH14_LOWTHOLD_INT_SFT 14
+#define CH14_LOWTHOLD_INT_HI 14
+#define CH14_LOWTHOLD_INT_SZ 1
+#define CH15_LOWTHOLD_INT_MSK 0x00008000
+#define CH15_LOWTHOLD_INT_I_MSK 0xffff7fff
+#define CH15_LOWTHOLD_INT_SFT 15
+#define CH15_LOWTHOLD_INT_HI 15
+#define CH15_LOWTHOLD_INT_SZ 1
+#define MB_LOW_THOLD_EN_MSK 0x80000000
+#define MB_LOW_THOLD_EN_I_MSK 0x7fffffff
+#define MB_LOW_THOLD_EN_SFT 31
+#define MB_LOW_THOLD_EN_HI 31
+#define MB_LOW_THOLD_EN_SZ 1
+#define CH0_LOWTHOLD_MSK 0x0000001f
+#define CH0_LOWTHOLD_I_MSK 0xffffffe0
+#define CH0_LOWTHOLD_SFT 0
+#define CH0_LOWTHOLD_HI 4
+#define CH0_LOWTHOLD_SZ 5
+#define CH1_LOWTHOLD_MSK 0x00001f00
+#define CH1_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH1_LOWTHOLD_SFT 8
+#define CH1_LOWTHOLD_HI 12
+#define CH1_LOWTHOLD_SZ 5
+#define CH2_LOWTHOLD_MSK 0x001f0000
+#define CH2_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH2_LOWTHOLD_SFT 16
+#define CH2_LOWTHOLD_HI 20
+#define CH2_LOWTHOLD_SZ 5
+#define CH3_LOWTHOLD_MSK 0x1f000000
+#define CH3_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH3_LOWTHOLD_SFT 24
+#define CH3_LOWTHOLD_HI 28
+#define CH3_LOWTHOLD_SZ 5
+#define CH4_LOWTHOLD_MSK 0x0000001f
+#define CH4_LOWTHOLD_I_MSK 0xffffffe0
+#define CH4_LOWTHOLD_SFT 0
+#define CH4_LOWTHOLD_HI 4
+#define CH4_LOWTHOLD_SZ 5
+#define CH5_LOWTHOLD_MSK 0x00001f00
+#define CH5_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH5_LOWTHOLD_SFT 8
+#define CH5_LOWTHOLD_HI 12
+#define CH5_LOWTHOLD_SZ 5
+#define CH6_LOWTHOLD_MSK 0x001f0000
+#define CH6_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH6_LOWTHOLD_SFT 16
+#define CH6_LOWTHOLD_HI 20
+#define CH6_LOWTHOLD_SZ 5
+#define CH7_LOWTHOLD_MSK 0x1f000000
+#define CH7_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH7_LOWTHOLD_SFT 24
+#define CH7_LOWTHOLD_HI 28
+#define CH7_LOWTHOLD_SZ 5
+#define CH8_LOWTHOLD_MSK 0x0000001f
+#define CH8_LOWTHOLD_I_MSK 0xffffffe0
+#define CH8_LOWTHOLD_SFT 0
+#define CH8_LOWTHOLD_HI 4
+#define CH8_LOWTHOLD_SZ 5
+#define CH9_LOWTHOLD_MSK 0x00001f00
+#define CH9_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH9_LOWTHOLD_SFT 8
+#define CH9_LOWTHOLD_HI 12
+#define CH9_LOWTHOLD_SZ 5
+#define CH10_LOWTHOLD_MSK 0x001f0000
+#define CH10_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH10_LOWTHOLD_SFT 16
+#define CH10_LOWTHOLD_HI 20
+#define CH10_LOWTHOLD_SZ 5
+#define CH11_LOWTHOLD_MSK 0x1f000000
+#define CH11_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH11_LOWTHOLD_SFT 24
+#define CH11_LOWTHOLD_HI 28
+#define CH11_LOWTHOLD_SZ 5
+#define CH12_LOWTHOLD_MSK 0x0000001f
+#define CH12_LOWTHOLD_I_MSK 0xffffffe0
+#define CH12_LOWTHOLD_SFT 0
+#define CH12_LOWTHOLD_HI 4
+#define CH12_LOWTHOLD_SZ 5
+#define CH13_LOWTHOLD_MSK 0x00001f00
+#define CH13_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH13_LOWTHOLD_SFT 8
+#define CH13_LOWTHOLD_HI 12
+#define CH13_LOWTHOLD_SZ 5
+#define CH14_LOWTHOLD_MSK 0x001f0000
+#define CH14_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH14_LOWTHOLD_SFT 16
+#define CH14_LOWTHOLD_HI 20
+#define CH14_LOWTHOLD_SZ 5
+#define CH15_LOWTHOLD_MSK 0x1f000000
+#define CH15_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH15_LOWTHOLD_SFT 24
+#define CH15_LOWTHOLD_HI 28
+#define CH15_LOWTHOLD_SZ 5
+#define TRASH_TIMEOUT_EN_MSK 0x00000001
+#define TRASH_TIMEOUT_EN_I_MSK 0xfffffffe
+#define TRASH_TIMEOUT_EN_SFT 0
+#define TRASH_TIMEOUT_EN_HI 0
+#define TRASH_TIMEOUT_EN_SZ 1
+#define TRASH_CAN_INT_MSK 0x00000002
+#define TRASH_CAN_INT_I_MSK 0xfffffffd
+#define TRASH_CAN_INT_SFT 1
+#define TRASH_CAN_INT_HI 1
+#define TRASH_CAN_INT_SZ 1
+#define TRASH_INT_ID_MSK 0x000007f0
+#define TRASH_INT_ID_I_MSK 0xfffff80f
+#define TRASH_INT_ID_SFT 4
+#define TRASH_INT_ID_HI 10
+#define TRASH_INT_ID_SZ 7
+#define TRASH_TIMEOUT_MSK 0x03ff0000
+#define TRASH_TIMEOUT_I_MSK 0xfc00ffff
+#define TRASH_TIMEOUT_SFT 16
+#define TRASH_TIMEOUT_HI 25
+#define TRASH_TIMEOUT_SZ 10
+#define CH0_WRFF_FLUSH_MSK 0x00000001
+#define CH0_WRFF_FLUSH_I_MSK 0xfffffffe
+#define CH0_WRFF_FLUSH_SFT 0
+#define CH0_WRFF_FLUSH_HI 0
+#define CH0_WRFF_FLUSH_SZ 1
+#define CH1_WRFF_FLUSH_MSK 0x00000002
+#define CH1_WRFF_FLUSH_I_MSK 0xfffffffd
+#define CH1_WRFF_FLUSH_SFT 1
+#define CH1_WRFF_FLUSH_HI 1
+#define CH1_WRFF_FLUSH_SZ 1
+#define CH2_WRFF_FLUSH_MSK 0x00000004
+#define CH2_WRFF_FLUSH_I_MSK 0xfffffffb
+#define CH2_WRFF_FLUSH_SFT 2
+#define CH2_WRFF_FLUSH_HI 2
+#define CH2_WRFF_FLUSH_SZ 1
+#define CH3_WRFF_FLUSH_MSK 0x00000008
+#define CH3_WRFF_FLUSH_I_MSK 0xfffffff7
+#define CH3_WRFF_FLUSH_SFT 3
+#define CH3_WRFF_FLUSH_HI 3
+#define CH3_WRFF_FLUSH_SZ 1
+#define CH4_WRFF_FLUSH_MSK 0x00000010
+#define CH4_WRFF_FLUSH_I_MSK 0xffffffef
+#define CH4_WRFF_FLUSH_SFT 4
+#define CH4_WRFF_FLUSH_HI 4
+#define CH4_WRFF_FLUSH_SZ 1
+#define CH5_WRFF_FLUSH_MSK 0x00000020
+#define CH5_WRFF_FLUSH_I_MSK 0xffffffdf
+#define CH5_WRFF_FLUSH_SFT 5
+#define CH5_WRFF_FLUSH_HI 5
+#define CH5_WRFF_FLUSH_SZ 1
+#define CH6_WRFF_FLUSH_MSK 0x00000040
+#define CH6_WRFF_FLUSH_I_MSK 0xffffffbf
+#define CH6_WRFF_FLUSH_SFT 6
+#define CH6_WRFF_FLUSH_HI 6
+#define CH6_WRFF_FLUSH_SZ 1
+#define CH7_WRFF_FLUSH_MSK 0x00000080
+#define CH7_WRFF_FLUSH_I_MSK 0xffffff7f
+#define CH7_WRFF_FLUSH_SFT 7
+#define CH7_WRFF_FLUSH_HI 7
+#define CH7_WRFF_FLUSH_SZ 1
+#define CH8_WRFF_FLUSH_MSK 0x00000100
+#define CH8_WRFF_FLUSH_I_MSK 0xfffffeff
+#define CH8_WRFF_FLUSH_SFT 8
+#define CH8_WRFF_FLUSH_HI 8
+#define CH8_WRFF_FLUSH_SZ 1
+#define CH9_WRFF_FLUSH_MSK 0x00000200
+#define CH9_WRFF_FLUSH_I_MSK 0xfffffdff
+#define CH9_WRFF_FLUSH_SFT 9
+#define CH9_WRFF_FLUSH_HI 9
+#define CH9_WRFF_FLUSH_SZ 1
+#define CH10_WRFF_FLUSH_MSK 0x00000400
+#define CH10_WRFF_FLUSH_I_MSK 0xfffffbff
+#define CH10_WRFF_FLUSH_SFT 10
+#define CH10_WRFF_FLUSH_HI 10
+#define CH10_WRFF_FLUSH_SZ 1
+#define CH11_WRFF_FLUSH_MSK 0x00000800
+#define CH11_WRFF_FLUSH_I_MSK 0xfffff7ff
+#define CH11_WRFF_FLUSH_SFT 11
+#define CH11_WRFF_FLUSH_HI 11
+#define CH11_WRFF_FLUSH_SZ 1
+#define CH12_WRFF_FLUSH_MSK 0x00001000
+#define CH12_WRFF_FLUSH_I_MSK 0xffffefff
+#define CH12_WRFF_FLUSH_SFT 12
+#define CH12_WRFF_FLUSH_HI 12
+#define CH12_WRFF_FLUSH_SZ 1
+#define CH13_WRFF_FLUSH_MSK 0x00002000
+#define CH13_WRFF_FLUSH_I_MSK 0xffffdfff
+#define CH13_WRFF_FLUSH_SFT 13
+#define CH13_WRFF_FLUSH_HI 13
+#define CH13_WRFF_FLUSH_SZ 1
+#define CH14_WRFF_FLUSH_MSK 0x00004000
+#define CH14_WRFF_FLUSH_I_MSK 0xffffbfff
+#define CH14_WRFF_FLUSH_SFT 14
+#define CH14_WRFF_FLUSH_HI 14
+#define CH14_WRFF_FLUSH_SZ 1
+#define CPU_ID_TB2_MSK 0xffffffff
+#define CPU_ID_TB2_I_MSK 0x00000000
+#define CPU_ID_TB2_SFT 0
+#define CPU_ID_TB2_HI 31
+#define CPU_ID_TB2_SZ 32
+#define CPU_ID_TB3_MSK 0xffffffff
+#define CPU_ID_TB3_I_MSK 0x00000000
+#define CPU_ID_TB3_SFT 0
+#define CPU_ID_TB3_HI 31
+#define CPU_ID_TB3_SZ 32
+#define IQ_LOG_EN_MSK 0x00000001
+#define IQ_LOG_EN_I_MSK 0xfffffffe
+#define IQ_LOG_EN_SFT 0
+#define IQ_LOG_EN_HI 0
+#define IQ_LOG_EN_SZ 1
+#define IQ_LOG_STOP_MODE_MSK 0x00000001
+#define IQ_LOG_STOP_MODE_I_MSK 0xfffffffe
+#define IQ_LOG_STOP_MODE_SFT 0
+#define IQ_LOG_STOP_MODE_HI 0
+#define IQ_LOG_STOP_MODE_SZ 1
+#define GPIO_STOP_EN_MSK 0x00000010
+#define GPIO_STOP_EN_I_MSK 0xffffffef
+#define GPIO_STOP_EN_SFT 4
+#define GPIO_STOP_EN_HI 4
+#define GPIO_STOP_EN_SZ 1
+#define GPIO_STOP_POL_MSK 0x00000020
+#define GPIO_STOP_POL_I_MSK 0xffffffdf
+#define GPIO_STOP_POL_SFT 5
+#define GPIO_STOP_POL_HI 5
+#define GPIO_STOP_POL_SZ 1
+#define IQ_LOG_TIMER_MSK 0xffff0000
+#define IQ_LOG_TIMER_I_MSK 0x0000ffff
+#define IQ_LOG_TIMER_SFT 16
+#define IQ_LOG_TIMER_HI 31
+#define IQ_LOG_TIMER_SZ 16
+#define IQ_LOG_LEN_MSK 0x0000ffff
+#define IQ_LOG_LEN_I_MSK 0xffff0000
+#define IQ_LOG_LEN_SFT 0
+#define IQ_LOG_LEN_HI 15
+#define IQ_LOG_LEN_SZ 16
+#define IQ_LOG_TAIL_ADR_MSK 0x0000ffff
+#define IQ_LOG_TAIL_ADR_I_MSK 0xffff0000
+#define IQ_LOG_TAIL_ADR_SFT 0
+#define IQ_LOG_TAIL_ADR_HI 15
+#define IQ_LOG_TAIL_ADR_SZ 16
+#define ALC_LENG_MSK 0x0003ffff
+#define ALC_LENG_I_MSK 0xfffc0000
+#define ALC_LENG_SFT 0
+#define ALC_LENG_HI 17
+#define ALC_LENG_SZ 18
+#define CH0_DYN_PRI_MSK 0x00300000
+#define CH0_DYN_PRI_I_MSK 0xffcfffff
+#define CH0_DYN_PRI_SFT 20
+#define CH0_DYN_PRI_HI 21
+#define CH0_DYN_PRI_SZ 2
+#define MCU_PKTID_MSK 0xffffffff
+#define MCU_PKTID_I_MSK 0x00000000
+#define MCU_PKTID_SFT 0
+#define MCU_PKTID_HI 31
+#define MCU_PKTID_SZ 32
+#define CH0_STA_PRI_MSK 0x00000003
+#define CH0_STA_PRI_I_MSK 0xfffffffc
+#define CH0_STA_PRI_SFT 0
+#define CH0_STA_PRI_HI 1
+#define CH0_STA_PRI_SZ 2
+#define CH1_STA_PRI_MSK 0x00000030
+#define CH1_STA_PRI_I_MSK 0xffffffcf
+#define CH1_STA_PRI_SFT 4
+#define CH1_STA_PRI_HI 5
+#define CH1_STA_PRI_SZ 2
+#define CH2_STA_PRI_MSK 0x00000300
+#define CH2_STA_PRI_I_MSK 0xfffffcff
+#define CH2_STA_PRI_SFT 8
+#define CH2_STA_PRI_HI 9
+#define CH2_STA_PRI_SZ 2
+#define CH3_STA_PRI_MSK 0x00003000
+#define CH3_STA_PRI_I_MSK 0xffffcfff
+#define CH3_STA_PRI_SFT 12
+#define CH3_STA_PRI_HI 13
+#define CH3_STA_PRI_SZ 2
+#define ID_TB0_MSK 0xffffffff
+#define ID_TB0_I_MSK 0x00000000
+#define ID_TB0_SFT 0
+#define ID_TB0_HI 31
+#define ID_TB0_SZ 32
+#define ID_TB1_MSK 0xffffffff
+#define ID_TB1_I_MSK 0x00000000
+#define ID_TB1_SFT 0
+#define ID_TB1_HI 31
+#define ID_TB1_SZ 32
+#define ID_MNG_HALT_MSK 0x00000010
+#define ID_MNG_HALT_I_MSK 0xffffffef
+#define ID_MNG_HALT_SFT 4
+#define ID_MNG_HALT_HI 4
+#define ID_MNG_HALT_SZ 1
+#define ID_MNG_ERR_HALT_EN_MSK 0x00000020
+#define ID_MNG_ERR_HALT_EN_I_MSK 0xffffffdf
+#define ID_MNG_ERR_HALT_EN_SFT 5
+#define ID_MNG_ERR_HALT_EN_HI 5
+#define ID_MNG_ERR_HALT_EN_SZ 1
+#define ID_EXCEPT_FLG_CLR_MSK 0x00000040
+#define ID_EXCEPT_FLG_CLR_I_MSK 0xffffffbf
+#define ID_EXCEPT_FLG_CLR_SFT 6
+#define ID_EXCEPT_FLG_CLR_HI 6
+#define ID_EXCEPT_FLG_CLR_SZ 1
+#define ID_EXCEPT_FLG_MSK 0x00000080
+#define ID_EXCEPT_FLG_I_MSK 0xffffff7f
+#define ID_EXCEPT_FLG_SFT 7
+#define ID_EXCEPT_FLG_HI 7
+#define ID_EXCEPT_FLG_SZ 1
+#define ID_FULL_MSK 0x00000001
+#define ID_FULL_I_MSK 0xfffffffe
+#define ID_FULL_SFT 0
+#define ID_FULL_HI 0
+#define ID_FULL_SZ 1
+#define ID_MNG_BUSY_MSK 0x00000002
+#define ID_MNG_BUSY_I_MSK 0xfffffffd
+#define ID_MNG_BUSY_SFT 1
+#define ID_MNG_BUSY_HI 1
+#define ID_MNG_BUSY_SZ 1
+#define REQ_LOCK_MSK 0x00000004
+#define REQ_LOCK_I_MSK 0xfffffffb
+#define REQ_LOCK_SFT 2
+#define REQ_LOCK_HI 2
+#define REQ_LOCK_SZ 1
+#define CH0_REQ_LOCK_MSK 0x00000010
+#define CH0_REQ_LOCK_I_MSK 0xffffffef
+#define CH0_REQ_LOCK_SFT 4
+#define CH0_REQ_LOCK_HI 4
+#define CH0_REQ_LOCK_SZ 1
+#define CH1_REQ_LOCK_MSK 0x00000020
+#define CH1_REQ_LOCK_I_MSK 0xffffffdf
+#define CH1_REQ_LOCK_SFT 5
+#define CH1_REQ_LOCK_HI 5
+#define CH1_REQ_LOCK_SZ 1
+#define CH2_REQ_LOCK_MSK 0x00000040
+#define CH2_REQ_LOCK_I_MSK 0xffffffbf
+#define CH2_REQ_LOCK_SFT 6
+#define CH2_REQ_LOCK_HI 6
+#define CH2_REQ_LOCK_SZ 1
+#define CH3_REQ_LOCK_MSK 0x00000080
+#define CH3_REQ_LOCK_I_MSK 0xffffff7f
+#define CH3_REQ_LOCK_SFT 7
+#define CH3_REQ_LOCK_HI 7
+#define CH3_REQ_LOCK_SZ 1
+#define REQ_LOCK_INT_EN_MSK 0x00000100
+#define REQ_LOCK_INT_EN_I_MSK 0xfffffeff
+#define REQ_LOCK_INT_EN_SFT 8
+#define REQ_LOCK_INT_EN_HI 8
+#define REQ_LOCK_INT_EN_SZ 1
+#define REQ_LOCK_INT_MSK 0x00000200
+#define REQ_LOCK_INT_I_MSK 0xfffffdff
+#define REQ_LOCK_INT_SFT 9
+#define REQ_LOCK_INT_HI 9
+#define REQ_LOCK_INT_SZ 1
+#define MCU_ALC_READY_MSK 0x00000001
+#define MCU_ALC_READY_I_MSK 0xfffffffe
+#define MCU_ALC_READY_SFT 0
+#define MCU_ALC_READY_HI 0
+#define MCU_ALC_READY_SZ 1
+#define ALC_FAIL_MSK 0x00000002
+#define ALC_FAIL_I_MSK 0xfffffffd
+#define ALC_FAIL_SFT 1
+#define ALC_FAIL_HI 1
+#define ALC_FAIL_SZ 1
+#define ALC_BUSY_MSK 0x00000004
+#define ALC_BUSY_I_MSK 0xfffffffb
+#define ALC_BUSY_SFT 2
+#define ALC_BUSY_HI 2
+#define ALC_BUSY_SZ 1
+#define CH0_NVLD_MSK 0x00000010
+#define CH0_NVLD_I_MSK 0xffffffef
+#define CH0_NVLD_SFT 4
+#define CH0_NVLD_HI 4
+#define CH0_NVLD_SZ 1
+#define CH1_NVLD_MSK 0x00000020
+#define CH1_NVLD_I_MSK 0xffffffdf
+#define CH1_NVLD_SFT 5
+#define CH1_NVLD_HI 5
+#define CH1_NVLD_SZ 1
+#define CH2_NVLD_MSK 0x00000040
+#define CH2_NVLD_I_MSK 0xffffffbf
+#define CH2_NVLD_SFT 6
+#define CH2_NVLD_HI 6
+#define CH2_NVLD_SZ 1
+#define CH3_NVLD_MSK 0x00000080
+#define CH3_NVLD_I_MSK 0xffffff7f
+#define CH3_NVLD_SFT 7
+#define CH3_NVLD_HI 7
+#define CH3_NVLD_SZ 1
+#define ALC_INT_ID_MSK 0x00007f00
+#define ALC_INT_ID_I_MSK 0xffff80ff
+#define ALC_INT_ID_SFT 8
+#define ALC_INT_ID_HI 14
+#define ALC_INT_ID_SZ 7
+#define ALC_TIMEOUT_MSK 0x03ff0000
+#define ALC_TIMEOUT_I_MSK 0xfc00ffff
+#define ALC_TIMEOUT_SFT 16
+#define ALC_TIMEOUT_HI 25
+#define ALC_TIMEOUT_SZ 10
+#define ALC_TIMEOUT_INT_EN_MSK 0x40000000
+#define ALC_TIMEOUT_INT_EN_I_MSK 0xbfffffff
+#define ALC_TIMEOUT_INT_EN_SFT 30
+#define ALC_TIMEOUT_INT_EN_HI 30
+#define ALC_TIMEOUT_INT_EN_SZ 1
+#define ALC_TIMEOUT_INT_MSK 0x80000000
+#define ALC_TIMEOUT_INT_I_MSK 0x7fffffff
+#define ALC_TIMEOUT_INT_SFT 31
+#define ALC_TIMEOUT_INT_HI 31
+#define ALC_TIMEOUT_INT_SZ 1
+#define TX_ID_COUNT_MSK 0x000000ff
+#define TX_ID_COUNT_I_MSK 0xffffff00
+#define TX_ID_COUNT_SFT 0
+#define TX_ID_COUNT_HI 7
+#define TX_ID_COUNT_SZ 8
+#define RX_ID_COUNT_MSK 0x0000ff00
+#define RX_ID_COUNT_I_MSK 0xffff00ff
+#define RX_ID_COUNT_SFT 8
+#define RX_ID_COUNT_HI 15
+#define RX_ID_COUNT_SZ 8
+#define TX_ID_THOLD_MSK 0x000000ff
+#define TX_ID_THOLD_I_MSK 0xffffff00
+#define TX_ID_THOLD_SFT 0
+#define TX_ID_THOLD_HI 7
+#define TX_ID_THOLD_SZ 8
+#define RX_ID_THOLD_MSK 0x0000ff00
+#define RX_ID_THOLD_I_MSK 0xffff00ff
+#define RX_ID_THOLD_SFT 8
+#define RX_ID_THOLD_HI 15
+#define RX_ID_THOLD_SZ 8
+#define ID_THOLD_RX_INT_MSK 0x00010000
+#define ID_THOLD_RX_INT_I_MSK 0xfffeffff
+#define ID_THOLD_RX_INT_SFT 16
+#define ID_THOLD_RX_INT_HI 16
+#define ID_THOLD_RX_INT_SZ 1
+#define RX_INT_CH_MSK 0x000e0000
+#define RX_INT_CH_I_MSK 0xfff1ffff
+#define RX_INT_CH_SFT 17
+#define RX_INT_CH_HI 19
+#define RX_INT_CH_SZ 3
+#define ID_THOLD_TX_INT_MSK 0x00100000
+#define ID_THOLD_TX_INT_I_MSK 0xffefffff
+#define ID_THOLD_TX_INT_SFT 20
+#define ID_THOLD_TX_INT_HI 20
+#define ID_THOLD_TX_INT_SZ 1
+#define TX_INT_CH_MSK 0x00e00000
+#define TX_INT_CH_I_MSK 0xff1fffff
+#define TX_INT_CH_SFT 21
+#define TX_INT_CH_HI 23
+#define TX_INT_CH_SZ 3
+#define ID_THOLD_INT_EN_MSK 0x01000000
+#define ID_THOLD_INT_EN_I_MSK 0xfeffffff
+#define ID_THOLD_INT_EN_SFT 24
+#define ID_THOLD_INT_EN_HI 24
+#define ID_THOLD_INT_EN_SZ 1
+#define TX_ID_TB0_MSK 0xffffffff
+#define TX_ID_TB0_I_MSK 0x00000000
+#define TX_ID_TB0_SFT 0
+#define TX_ID_TB0_HI 31
+#define TX_ID_TB0_SZ 32
+#define TX_ID_TB1_MSK 0xffffffff
+#define TX_ID_TB1_I_MSK 0x00000000
+#define TX_ID_TB1_SFT 0
+#define TX_ID_TB1_HI 31
+#define TX_ID_TB1_SZ 32
+#define RX_ID_TB0_MSK 0xffffffff
+#define RX_ID_TB0_I_MSK 0x00000000
+#define RX_ID_TB0_SFT 0
+#define RX_ID_TB0_HI 31
+#define RX_ID_TB0_SZ 32
+#define RX_ID_TB1_MSK 0xffffffff
+#define RX_ID_TB1_I_MSK 0x00000000
+#define RX_ID_TB1_SFT 0
+#define RX_ID_TB1_HI 31
+#define RX_ID_TB1_SZ 32
+#define DOUBLE_RLS_INT_EN_MSK 0x00000001
+#define DOUBLE_RLS_INT_EN_I_MSK 0xfffffffe
+#define DOUBLE_RLS_INT_EN_SFT 0
+#define DOUBLE_RLS_INT_EN_HI 0
+#define DOUBLE_RLS_INT_EN_SZ 1
+#define ID_DOUBLE_RLS_INT_MSK 0x00000002
+#define ID_DOUBLE_RLS_INT_I_MSK 0xfffffffd
+#define ID_DOUBLE_RLS_INT_SFT 1
+#define ID_DOUBLE_RLS_INT_HI 1
+#define ID_DOUBLE_RLS_INT_SZ 1
+#define DOUBLE_RLS_ID_MSK 0x00007f00
+#define DOUBLE_RLS_ID_I_MSK 0xffff80ff
+#define DOUBLE_RLS_ID_SFT 8
+#define DOUBLE_RLS_ID_HI 14
+#define DOUBLE_RLS_ID_SZ 7
+#define ID_LEN_THOLD_INT_EN_MSK 0x00000001
+#define ID_LEN_THOLD_INT_EN_I_MSK 0xfffffffe
+#define ID_LEN_THOLD_INT_EN_SFT 0
+#define ID_LEN_THOLD_INT_EN_HI 0
+#define ID_LEN_THOLD_INT_EN_SZ 1
+#define ALL_ID_LEN_THOLD_INT_MSK 0x00000002
+#define ALL_ID_LEN_THOLD_INT_I_MSK 0xfffffffd
+#define ALL_ID_LEN_THOLD_INT_SFT 1
+#define ALL_ID_LEN_THOLD_INT_HI 1
+#define ALL_ID_LEN_THOLD_INT_SZ 1
+#define TX_ID_LEN_THOLD_INT_MSK 0x00000004
+#define TX_ID_LEN_THOLD_INT_I_MSK 0xfffffffb
+#define TX_ID_LEN_THOLD_INT_SFT 2
+#define TX_ID_LEN_THOLD_INT_HI 2
+#define TX_ID_LEN_THOLD_INT_SZ 1
+#define RX_ID_LEN_THOLD_INT_MSK 0x00000008
+#define RX_ID_LEN_THOLD_INT_I_MSK 0xfffffff7
+#define RX_ID_LEN_THOLD_INT_SFT 3
+#define RX_ID_LEN_THOLD_INT_HI 3
+#define RX_ID_LEN_THOLD_INT_SZ 1
+#define ID_TX_LEN_THOLD_MSK 0x00001ff0
+#define ID_TX_LEN_THOLD_I_MSK 0xffffe00f
+#define ID_TX_LEN_THOLD_SFT 4
+#define ID_TX_LEN_THOLD_HI 12
+#define ID_TX_LEN_THOLD_SZ 9
+#define ID_RX_LEN_THOLD_MSK 0x003fe000
+#define ID_RX_LEN_THOLD_I_MSK 0xffc01fff
+#define ID_RX_LEN_THOLD_SFT 13
+#define ID_RX_LEN_THOLD_HI 21
+#define ID_RX_LEN_THOLD_SZ 9
+#define ID_LEN_THOLD_MSK 0x7fc00000
+#define ID_LEN_THOLD_I_MSK 0x803fffff
+#define ID_LEN_THOLD_SFT 22
+#define ID_LEN_THOLD_HI 30
+#define ID_LEN_THOLD_SZ 9
+#define ALL_ID_ALC_LEN_MSK 0x000001ff
+#define ALL_ID_ALC_LEN_I_MSK 0xfffffe00
+#define ALL_ID_ALC_LEN_SFT 0
+#define ALL_ID_ALC_LEN_HI 8
+#define ALL_ID_ALC_LEN_SZ 9
+#define TX_ID_ALC_LEN_MSK 0x0003fe00
+#define TX_ID_ALC_LEN_I_MSK 0xfffc01ff
+#define TX_ID_ALC_LEN_SFT 9
+#define TX_ID_ALC_LEN_HI 17
+#define TX_ID_ALC_LEN_SZ 9
+#define RX_ID_ALC_LEN_MSK 0x07fc0000
+#define RX_ID_ALC_LEN_I_MSK 0xf803ffff
+#define RX_ID_ALC_LEN_SFT 18
+#define RX_ID_ALC_LEN_HI 26
+#define RX_ID_ALC_LEN_SZ 9
+#define CH_ARB_EN_MSK 0x00000001
+#define CH_ARB_EN_I_MSK 0xfffffffe
+#define CH_ARB_EN_SFT 0
+#define CH_ARB_EN_HI 0
+#define CH_ARB_EN_SZ 1
+#define CH_PRI1_MSK 0x00000030
+#define CH_PRI1_I_MSK 0xffffffcf
+#define CH_PRI1_SFT 4
+#define CH_PRI1_HI 5
+#define CH_PRI1_SZ 2
+#define CH_PRI2_MSK 0x00000300
+#define CH_PRI2_I_MSK 0xfffffcff
+#define CH_PRI2_SFT 8
+#define CH_PRI2_HI 9
+#define CH_PRI2_SZ 2
+#define CH_PRI3_MSK 0x00003000
+#define CH_PRI3_I_MSK 0xffffcfff
+#define CH_PRI3_SFT 12
+#define CH_PRI3_HI 13
+#define CH_PRI3_SZ 2
+#define CH_PRI4_MSK 0x00030000
+#define CH_PRI4_I_MSK 0xfffcffff
+#define CH_PRI4_SFT 16
+#define CH_PRI4_HI 17
+#define CH_PRI4_SZ 2
+#define TX_ID_REMAIN_MSK 0x0000007f
+#define TX_ID_REMAIN_I_MSK 0xffffff80
+#define TX_ID_REMAIN_SFT 0
+#define TX_ID_REMAIN_HI 6
+#define TX_ID_REMAIN_SZ 7
+#define TX_PAGE_REMAIN_MSK 0x0001ff00
+#define TX_PAGE_REMAIN_I_MSK 0xfffe00ff
+#define TX_PAGE_REMAIN_SFT 8
+#define TX_PAGE_REMAIN_HI 16
+#define TX_PAGE_REMAIN_SZ 9
+#define ID_PAGE_MAX_SIZE_MSK 0x000001ff
+#define ID_PAGE_MAX_SIZE_I_MSK 0xfffffe00
+#define ID_PAGE_MAX_SIZE_SFT 0
+#define ID_PAGE_MAX_SIZE_HI 8
+#define ID_PAGE_MAX_SIZE_SZ 9
+#define TX_PAGE_LIMIT_MSK 0x000001ff
+#define TX_PAGE_LIMIT_I_MSK 0xfffffe00
+#define TX_PAGE_LIMIT_SFT 0
+#define TX_PAGE_LIMIT_HI 8
+#define TX_PAGE_LIMIT_SZ 9
+#define TX_COUNT_LIMIT_MSK 0x00ff0000
+#define TX_COUNT_LIMIT_I_MSK 0xff00ffff
+#define TX_COUNT_LIMIT_SFT 16
+#define TX_COUNT_LIMIT_HI 23
+#define TX_COUNT_LIMIT_SZ 8
+#define TX_LIMIT_INT_MSK 0x40000000
+#define TX_LIMIT_INT_I_MSK 0xbfffffff
+#define TX_LIMIT_INT_SFT 30
+#define TX_LIMIT_INT_HI 30
+#define TX_LIMIT_INT_SZ 1
+#define TX_LIMIT_INT_EN_MSK 0x80000000
+#define TX_LIMIT_INT_EN_I_MSK 0x7fffffff
+#define TX_LIMIT_INT_EN_SFT 31
+#define TX_LIMIT_INT_EN_HI 31
+#define TX_LIMIT_INT_EN_SZ 1
+#define TX_PAGE_USE_7_0_MSK 0x000000ff
+#define TX_PAGE_USE_7_0_I_MSK 0xffffff00
+#define TX_PAGE_USE_7_0_SFT 0
+#define TX_PAGE_USE_7_0_HI 7
+#define TX_PAGE_USE_7_0_SZ 8
+#define TX_ID_USE_5_0_MSK 0x00003f00
+#define TX_ID_USE_5_0_I_MSK 0xffffc0ff
+#define TX_ID_USE_5_0_SFT 8
+#define TX_ID_USE_5_0_HI 13
+#define TX_ID_USE_5_0_SZ 6
+#define EDCA0_FFO_CNT_MSK 0x0003c000
+#define EDCA0_FFO_CNT_I_MSK 0xfffc3fff
+#define EDCA0_FFO_CNT_SFT 14
+#define EDCA0_FFO_CNT_HI 17
+#define EDCA0_FFO_CNT_SZ 4
+#define EDCA1_FFO_CNT_3_0_MSK 0x003c0000
+#define EDCA1_FFO_CNT_3_0_I_MSK 0xffc3ffff
+#define EDCA1_FFO_CNT_3_0_SFT 18
+#define EDCA1_FFO_CNT_3_0_HI 21
+#define EDCA1_FFO_CNT_3_0_SZ 4
+#define EDCA2_FFO_CNT_MSK 0x07c00000
+#define EDCA2_FFO_CNT_I_MSK 0xf83fffff
+#define EDCA2_FFO_CNT_SFT 22
+#define EDCA2_FFO_CNT_HI 26
+#define EDCA2_FFO_CNT_SZ 5
+#define EDCA3_FFO_CNT_MSK 0xf8000000
+#define EDCA3_FFO_CNT_I_MSK 0x07ffffff
+#define EDCA3_FFO_CNT_SFT 27
+#define EDCA3_FFO_CNT_HI 31
+#define EDCA3_FFO_CNT_SZ 5
+#define ID_TB2_MSK 0xffffffff
+#define ID_TB2_I_MSK 0x00000000
+#define ID_TB2_SFT 0
+#define ID_TB2_HI 31
+#define ID_TB2_SZ 32
+#define ID_TB3_MSK 0xffffffff
+#define ID_TB3_I_MSK 0x00000000
+#define ID_TB3_SFT 0
+#define ID_TB3_HI 31
+#define ID_TB3_SZ 32
+#define TX_ID_TB2_MSK 0xffffffff
+#define TX_ID_TB2_I_MSK 0x00000000
+#define TX_ID_TB2_SFT 0
+#define TX_ID_TB2_HI 31
+#define TX_ID_TB2_SZ 32
+#define TX_ID_TB3_MSK 0xffffffff
+#define TX_ID_TB3_I_MSK 0x00000000
+#define TX_ID_TB3_SFT 0
+#define TX_ID_TB3_HI 31
+#define TX_ID_TB3_SZ 32
+#define RX_ID_TB2_MSK 0xffffffff
+#define RX_ID_TB2_I_MSK 0x00000000
+#define RX_ID_TB2_SFT 0
+#define RX_ID_TB2_HI 31
+#define RX_ID_TB2_SZ 32
+#define RX_ID_TB3_MSK 0xffffffff
+#define RX_ID_TB3_I_MSK 0x00000000
+#define RX_ID_TB3_SFT 0
+#define RX_ID_TB3_HI 31
+#define RX_ID_TB3_SZ 32
+#define TX_PAGE_USE2_MSK 0x000001ff
+#define TX_PAGE_USE2_I_MSK 0xfffffe00
+#define TX_PAGE_USE2_SFT 0
+#define TX_PAGE_USE2_HI 8
+#define TX_PAGE_USE2_SZ 9
+#define TX_ID_USE2_MSK 0x0001fe00
+#define TX_ID_USE2_I_MSK 0xfffe01ff
+#define TX_ID_USE2_SFT 9
+#define TX_ID_USE2_HI 16
+#define TX_ID_USE2_SZ 8
+#define EDCA4_FFO_CNT_MSK 0x001e0000
+#define EDCA4_FFO_CNT_I_MSK 0xffe1ffff
+#define EDCA4_FFO_CNT_SFT 17
+#define EDCA4_FFO_CNT_HI 20
+#define EDCA4_FFO_CNT_SZ 4
+#define TX_PAGE_USE3_MSK 0x000001ff
+#define TX_PAGE_USE3_I_MSK 0xfffffe00
+#define TX_PAGE_USE3_SFT 0
+#define TX_PAGE_USE3_HI 8
+#define TX_PAGE_USE3_SZ 9
+#define TX_ID_USE3_MSK 0x0001fe00
+#define TX_ID_USE3_I_MSK 0xfffe01ff
+#define TX_ID_USE3_SFT 9
+#define TX_ID_USE3_HI 16
+#define TX_ID_USE3_SZ 8
+#define EDCA1_FFO_CNT2_MSK 0x03e00000
+#define EDCA1_FFO_CNT2_I_MSK 0xfc1fffff
+#define EDCA1_FFO_CNT2_SFT 21
+#define EDCA1_FFO_CNT2_HI 25
+#define EDCA1_FFO_CNT2_SZ 5
+#define EDCA4_FFO_CNT2_MSK 0x3c000000
+#define EDCA4_FFO_CNT2_I_MSK 0xc3ffffff
+#define EDCA4_FFO_CNT2_SFT 26
+#define EDCA4_FFO_CNT2_HI 29
+#define EDCA4_FFO_CNT2_SZ 4
+#define TX_PAGE_USE4_MSK 0x000001ff
+#define TX_PAGE_USE4_I_MSK 0xfffffe00
+#define TX_PAGE_USE4_SFT 0
+#define TX_PAGE_USE4_HI 8
+#define TX_PAGE_USE4_SZ 9
+#define TX_ID_USE4_MSK 0x0001fe00
+#define TX_ID_USE4_I_MSK 0xfffe01ff
+#define TX_ID_USE4_SFT 9
+#define TX_ID_USE4_HI 16
+#define TX_ID_USE4_SZ 8
+#define EDCA2_FFO_CNT2_MSK 0x003e0000
+#define EDCA2_FFO_CNT2_I_MSK 0xffc1ffff
+#define EDCA2_FFO_CNT2_SFT 17
+#define EDCA2_FFO_CNT2_HI 21
+#define EDCA2_FFO_CNT2_SZ 5
+#define EDCA3_FFO_CNT2_MSK 0x07c00000
+#define EDCA3_FFO_CNT2_I_MSK 0xf83fffff
+#define EDCA3_FFO_CNT2_SFT 22
+#define EDCA3_FFO_CNT2_HI 26
+#define EDCA3_FFO_CNT2_SZ 5
+#define TX_ID_IFO_LEN_MSK 0x000001ff
+#define TX_ID_IFO_LEN_I_MSK 0xfffffe00
+#define TX_ID_IFO_LEN_SFT 0
+#define TX_ID_IFO_LEN_HI 8
+#define TX_ID_IFO_LEN_SZ 9
+#define RX_ID_IFO_LEN_MSK 0x01ff0000
+#define RX_ID_IFO_LEN_I_MSK 0xfe00ffff
+#define RX_ID_IFO_LEN_SFT 16
+#define RX_ID_IFO_LEN_HI 24
+#define RX_ID_IFO_LEN_SZ 9
+#define MAX_ALL_ALC_ID_CNT_MSK 0x000000ff
+#define MAX_ALL_ALC_ID_CNT_I_MSK 0xffffff00
+#define MAX_ALL_ALC_ID_CNT_SFT 0
+#define MAX_ALL_ALC_ID_CNT_HI 7
+#define MAX_ALL_ALC_ID_CNT_SZ 8
+#define MAX_TX_ALC_ID_CNT_MSK 0x0000ff00
+#define MAX_TX_ALC_ID_CNT_I_MSK 0xffff00ff
+#define MAX_TX_ALC_ID_CNT_SFT 8
+#define MAX_TX_ALC_ID_CNT_HI 15
+#define MAX_TX_ALC_ID_CNT_SZ 8
+#define MAX_RX_ALC_ID_CNT_MSK 0x00ff0000
+#define MAX_RX_ALC_ID_CNT_I_MSK 0xff00ffff
+#define MAX_RX_ALC_ID_CNT_SFT 16
+#define MAX_RX_ALC_ID_CNT_HI 23
+#define MAX_RX_ALC_ID_CNT_SZ 8
+#define MAX_ALL_ID_ALC_LEN_MSK 0x000001ff
+#define MAX_ALL_ID_ALC_LEN_I_MSK 0xfffffe00
+#define MAX_ALL_ID_ALC_LEN_SFT 0
+#define MAX_ALL_ID_ALC_LEN_HI 8
+#define MAX_ALL_ID_ALC_LEN_SZ 9
+#define MAX_TX_ID_ALC_LEN_MSK 0x0003fe00
+#define MAX_TX_ID_ALC_LEN_I_MSK 0xfffc01ff
+#define MAX_TX_ID_ALC_LEN_SFT 9
+#define MAX_TX_ID_ALC_LEN_HI 17
+#define MAX_TX_ID_ALC_LEN_SZ 9
+#define MAX_RX_ID_ALC_LEN_MSK 0x07fc0000
+#define MAX_RX_ID_ALC_LEN_I_MSK 0xf803ffff
+#define MAX_RX_ID_ALC_LEN_SFT 18
+#define MAX_RX_ID_ALC_LEN_HI 26
+#define MAX_RX_ID_ALC_LEN_SZ 9
+#define RG_PMDLBK_MSK 0x00000001
+#define RG_PMDLBK_I_MSK 0xfffffffe
+#define RG_PMDLBK_SFT 0
+#define RG_PMDLBK_HI 0
+#define RG_PMDLBK_SZ 1
+#define RG_RDYACK_SEL_MSK 0x00000006
+#define RG_RDYACK_SEL_I_MSK 0xfffffff9
+#define RG_RDYACK_SEL_SFT 1
+#define RG_RDYACK_SEL_HI 2
+#define RG_RDYACK_SEL_SZ 2
+#define RG_ADEDGE_SEL_MSK 0x00000008
+#define RG_ADEDGE_SEL_I_MSK 0xfffffff7
+#define RG_ADEDGE_SEL_SFT 3
+#define RG_ADEDGE_SEL_HI 3
+#define RG_ADEDGE_SEL_SZ 1
+#define RG_SIGN_SWAP_MSK 0x00000010
+#define RG_SIGN_SWAP_I_MSK 0xffffffef
+#define RG_SIGN_SWAP_SFT 4
+#define RG_SIGN_SWAP_HI 4
+#define RG_SIGN_SWAP_SZ 1
+#define RG_IQ_SWAP_MSK 0x00000020
+#define RG_IQ_SWAP_I_MSK 0xffffffdf
+#define RG_IQ_SWAP_SFT 5
+#define RG_IQ_SWAP_HI 5
+#define RG_IQ_SWAP_SZ 1
+#define RG_Q_INV_MSK 0x00000040
+#define RG_Q_INV_I_MSK 0xffffffbf
+#define RG_Q_INV_SFT 6
+#define RG_Q_INV_HI 6
+#define RG_Q_INV_SZ 1
+#define RG_I_INV_MSK 0x00000080
+#define RG_I_INV_I_MSK 0xffffff7f
+#define RG_I_INV_SFT 7
+#define RG_I_INV_HI 7
+#define RG_I_INV_SZ 1
+#define RG_BYPASS_ACI_MSK 0x00000100
+#define RG_BYPASS_ACI_I_MSK 0xfffffeff
+#define RG_BYPASS_ACI_SFT 8
+#define RG_BYPASS_ACI_HI 8
+#define RG_BYPASS_ACI_SZ 1
+#define RG_LBK_ANA_PATH_MSK 0x00000200
+#define RG_LBK_ANA_PATH_I_MSK 0xfffffdff
+#define RG_LBK_ANA_PATH_SFT 9
+#define RG_LBK_ANA_PATH_HI 9
+#define RG_LBK_ANA_PATH_SZ 1
+#define RG_SPECTRUM_LEAKY_FACTOR_MSK 0x00000c00
+#define RG_SPECTRUM_LEAKY_FACTOR_I_MSK 0xfffff3ff
+#define RG_SPECTRUM_LEAKY_FACTOR_SFT 10
+#define RG_SPECTRUM_LEAKY_FACTOR_HI 11
+#define RG_SPECTRUM_LEAKY_FACTOR_SZ 2
+#define RG_SPECTRUM_BW_MSK 0x00003000
+#define RG_SPECTRUM_BW_I_MSK 0xffffcfff
+#define RG_SPECTRUM_BW_SFT 12
+#define RG_SPECTRUM_BW_HI 13
+#define RG_SPECTRUM_BW_SZ 2
+#define RG_SPECTRUM_FREQ_MANUAL_MSK 0x00004000
+#define RG_SPECTRUM_FREQ_MANUAL_I_MSK 0xffffbfff
+#define RG_SPECTRUM_FREQ_MANUAL_SFT 14
+#define RG_SPECTRUM_FREQ_MANUAL_HI 14
+#define RG_SPECTRUM_FREQ_MANUAL_SZ 1
+#define RG_SPECTRUM_EN_MSK 0x00008000
+#define RG_SPECTRUM_EN_I_MSK 0xffff7fff
+#define RG_SPECTRUM_EN_SFT 15
+#define RG_SPECTRUM_EN_HI 15
+#define RG_SPECTRUM_EN_SZ 1
+#define RG_TXPWRLVL_SET_MSK 0x00ff0000
+#define RG_TXPWRLVL_SET_I_MSK 0xff00ffff
+#define RG_TXPWRLVL_SET_SFT 16
+#define RG_TXPWRLVL_SET_HI 23
+#define RG_TXPWRLVL_SET_SZ 8
+#define RG_TXPWRLVL_SEL_MSK 0x01000000
+#define RG_TXPWRLVL_SEL_I_MSK 0xfeffffff
+#define RG_TXPWRLVL_SEL_SFT 24
+#define RG_TXPWRLVL_SEL_HI 24
+#define RG_TXPWRLVL_SEL_SZ 1
+#define RG_RF_BB_CLK_SEL_MSK 0x80000000
+#define RG_RF_BB_CLK_SEL_I_MSK 0x7fffffff
+#define RG_RF_BB_CLK_SEL_SFT 31
+#define RG_RF_BB_CLK_SEL_HI 31
+#define RG_RF_BB_CLK_SEL_SZ 1
+#define RG_PHY_MD_EN_MSK 0x00000001
+#define RG_PHY_MD_EN_I_MSK 0xfffffffe
+#define RG_PHY_MD_EN_SFT 0
+#define RG_PHY_MD_EN_HI 0
+#define RG_PHY_MD_EN_SZ 1
+#define RG_PHYRX_MD_EN_MSK 0x00000002
+#define RG_PHYRX_MD_EN_I_MSK 0xfffffffd
+#define RG_PHYRX_MD_EN_SFT 1
+#define RG_PHYRX_MD_EN_HI 1
+#define RG_PHYRX_MD_EN_SZ 1
+#define RG_PHYTX_MD_EN_MSK 0x00000004
+#define RG_PHYTX_MD_EN_I_MSK 0xfffffffb
+#define RG_PHYTX_MD_EN_SFT 2
+#define RG_PHYTX_MD_EN_HI 2
+#define RG_PHYTX_MD_EN_SZ 1
+#define RG_PHY11GN_MD_EN_MSK 0x00000008
+#define RG_PHY11GN_MD_EN_I_MSK 0xfffffff7
+#define RG_PHY11GN_MD_EN_SFT 3
+#define RG_PHY11GN_MD_EN_HI 3
+#define RG_PHY11GN_MD_EN_SZ 1
+#define RG_PHY11B_MD_EN_MSK 0x00000010
+#define RG_PHY11B_MD_EN_I_MSK 0xffffffef
+#define RG_PHY11B_MD_EN_SFT 4
+#define RG_PHY11B_MD_EN_HI 4
+#define RG_PHY11B_MD_EN_SZ 1
+#define RG_PHYRXFIFO_MD_EN_MSK 0x00000020
+#define RG_PHYRXFIFO_MD_EN_I_MSK 0xffffffdf
+#define RG_PHYRXFIFO_MD_EN_SFT 5
+#define RG_PHYRXFIFO_MD_EN_HI 5
+#define RG_PHYRXFIFO_MD_EN_SZ 1
+#define RG_PHYTXFIFO_MD_EN_MSK 0x00000040
+#define RG_PHYTXFIFO_MD_EN_I_MSK 0xffffffbf
+#define RG_PHYTXFIFO_MD_EN_SFT 6
+#define RG_PHYTXFIFO_MD_EN_HI 6
+#define RG_PHYTXFIFO_MD_EN_SZ 1
+#define RG_PHY11BGN_MD_EN_MSK 0x00000100
+#define RG_PHY11BGN_MD_EN_I_MSK 0xfffffeff
+#define RG_PHY11BGN_MD_EN_SFT 8
+#define RG_PHY11BGN_MD_EN_HI 8
+#define RG_PHY11BGN_MD_EN_SZ 1
+#define RG_FORCE_11GN_EN_MSK 0x00001000
+#define RG_FORCE_11GN_EN_I_MSK 0xffffefff
+#define RG_FORCE_11GN_EN_SFT 12
+#define RG_FORCE_11GN_EN_HI 12
+#define RG_FORCE_11GN_EN_SZ 1
+#define RG_FORCE_11B_EN_MSK 0x00002000
+#define RG_FORCE_11B_EN_I_MSK 0xffffdfff
+#define RG_FORCE_11B_EN_SFT 13
+#define RG_FORCE_11B_EN_HI 13
+#define RG_FORCE_11B_EN_SZ 1
+#define RG_FFT_MEM_CLK_EN_RX_MSK 0x00004000
+#define RG_FFT_MEM_CLK_EN_RX_I_MSK 0xffffbfff
+#define RG_FFT_MEM_CLK_EN_RX_SFT 14
+#define RG_FFT_MEM_CLK_EN_RX_HI 14
+#define RG_FFT_MEM_CLK_EN_RX_SZ 1
+#define RG_FFT_MEM_CLK_EN_TX_MSK 0x00008000
+#define RG_FFT_MEM_CLK_EN_TX_I_MSK 0xffff7fff
+#define RG_FFT_MEM_CLK_EN_TX_SFT 15
+#define RG_FFT_MEM_CLK_EN_TX_HI 15
+#define RG_FFT_MEM_CLK_EN_TX_SZ 1
+#define RG_PHY_IQ_TRIG_SEL_MSK 0x000f0000
+#define RG_PHY_IQ_TRIG_SEL_I_MSK 0xfff0ffff
+#define RG_PHY_IQ_TRIG_SEL_SFT 16
+#define RG_PHY_IQ_TRIG_SEL_HI 19
+#define RG_PHY_IQ_TRIG_SEL_SZ 4
+#define RG_SPECTRUM_FREQ_MSK 0x3ff00000
+#define RG_SPECTRUM_FREQ_I_MSK 0xc00fffff
+#define RG_SPECTRUM_FREQ_SFT 20
+#define RG_SPECTRUM_FREQ_HI 29
+#define RG_SPECTRUM_FREQ_SZ 10
+#define SVN_VERSION_MSK 0xffffffff
+#define SVN_VERSION_I_MSK 0x00000000
+#define SVN_VERSION_SFT 0
+#define SVN_VERSION_HI 31
+#define SVN_VERSION_SZ 32
+#define RG_LENGTH_MSK 0x0000ffff
+#define RG_LENGTH_I_MSK 0xffff0000
+#define RG_LENGTH_SFT 0
+#define RG_LENGTH_HI 15
+#define RG_LENGTH_SZ 16
+#define RG_PKT_MODE_MSK 0x00070000
+#define RG_PKT_MODE_I_MSK 0xfff8ffff
+#define RG_PKT_MODE_SFT 16
+#define RG_PKT_MODE_HI 18
+#define RG_PKT_MODE_SZ 3
+#define RG_CH_BW_MSK 0x00380000
+#define RG_CH_BW_I_MSK 0xffc7ffff
+#define RG_CH_BW_SFT 19
+#define RG_CH_BW_HI 21
+#define RG_CH_BW_SZ 3
+#define RG_PRM_MSK 0x00400000
+#define RG_PRM_I_MSK 0xffbfffff
+#define RG_PRM_SFT 22
+#define RG_PRM_HI 22
+#define RG_PRM_SZ 1
+#define RG_SHORTGI_MSK 0x00800000
+#define RG_SHORTGI_I_MSK 0xff7fffff
+#define RG_SHORTGI_SFT 23
+#define RG_SHORTGI_HI 23
+#define RG_SHORTGI_SZ 1
+#define RG_RATE_MSK 0x7f000000
+#define RG_RATE_I_MSK 0x80ffffff
+#define RG_RATE_SFT 24
+#define RG_RATE_HI 30
+#define RG_RATE_SZ 7
+#define RG_L_LENGTH_MSK 0x00000fff
+#define RG_L_LENGTH_I_MSK 0xfffff000
+#define RG_L_LENGTH_SFT 0
+#define RG_L_LENGTH_HI 11
+#define RG_L_LENGTH_SZ 12
+#define RG_L_RATE_MSK 0x00007000
+#define RG_L_RATE_I_MSK 0xffff8fff
+#define RG_L_RATE_SFT 12
+#define RG_L_RATE_HI 14
+#define RG_L_RATE_SZ 3
+#define RG_SERVICE_MSK 0xffff0000
+#define RG_SERVICE_I_MSK 0x0000ffff
+#define RG_SERVICE_SFT 16
+#define RG_SERVICE_HI 31
+#define RG_SERVICE_SZ 16
+#define RG_SMOOTHING_MSK 0x00000001
+#define RG_SMOOTHING_I_MSK 0xfffffffe
+#define RG_SMOOTHING_SFT 0
+#define RG_SMOOTHING_HI 0
+#define RG_SMOOTHING_SZ 1
+#define RG_NO_SOUND_MSK 0x00000002
+#define RG_NO_SOUND_I_MSK 0xfffffffd
+#define RG_NO_SOUND_SFT 1
+#define RG_NO_SOUND_HI 1
+#define RG_NO_SOUND_SZ 1
+#define RG_AGGREGATE_MSK 0x00000004
+#define RG_AGGREGATE_I_MSK 0xfffffffb
+#define RG_AGGREGATE_SFT 2
+#define RG_AGGREGATE_HI 2
+#define RG_AGGREGATE_SZ 1
+#define RG_STBC_MSK 0x00000018
+#define RG_STBC_I_MSK 0xffffffe7
+#define RG_STBC_SFT 3
+#define RG_STBC_HI 4
+#define RG_STBC_SZ 2
+#define RG_FEC_MSK 0x00000020
+#define RG_FEC_I_MSK 0xffffffdf
+#define RG_FEC_SFT 5
+#define RG_FEC_HI 5
+#define RG_FEC_SZ 1
+#define RG_N_ESS_MSK 0x000000c0
+#define RG_N_ESS_I_MSK 0xffffff3f
+#define RG_N_ESS_SFT 6
+#define RG_N_ESS_HI 7
+#define RG_N_ESS_SZ 2
+#define RG_TXPWRLVL_MSK 0x0000ff00
+#define RG_TXPWRLVL_I_MSK 0xffff00ff
+#define RG_TXPWRLVL_SFT 8
+#define RG_TXPWRLVL_HI 15
+#define RG_TXPWRLVL_SZ 8
+#define RG_TX_START_MSK 0x00000001
+#define RG_TX_START_I_MSK 0xfffffffe
+#define RG_TX_START_SFT 0
+#define RG_TX_START_HI 0
+#define RG_TX_START_SZ 1
+#define RG_IFS_TIME_MSK 0x000000fc
+#define RG_IFS_TIME_I_MSK 0xffffff03
+#define RG_IFS_TIME_SFT 2
+#define RG_IFS_TIME_HI 7
+#define RG_IFS_TIME_SZ 6
+#define RG_CONTINUOUS_DATA_MSK 0x00000100
+#define RG_CONTINUOUS_DATA_I_MSK 0xfffffeff
+#define RG_CONTINUOUS_DATA_SFT 8
+#define RG_CONTINUOUS_DATA_HI 8
+#define RG_CONTINUOUS_DATA_SZ 1
+#define RG_DATA_SEL_MSK 0x00000600
+#define RG_DATA_SEL_I_MSK 0xfffff9ff
+#define RG_DATA_SEL_SFT 9
+#define RG_DATA_SEL_HI 10
+#define RG_DATA_SEL_SZ 2
+#define RG_TX_D_MSK 0x00ff0000
+#define RG_TX_D_I_MSK 0xff00ffff
+#define RG_TX_D_SFT 16
+#define RG_TX_D_HI 23
+#define RG_TX_D_SZ 8
+#define RG_TX_CNT_TARGET_MSK 0xffffffff
+#define RG_TX_CNT_TARGET_I_MSK 0x00000000
+#define RG_TX_CNT_TARGET_SFT 0
+#define RG_TX_CNT_TARGET_HI 31
+#define RG_TX_CNT_TARGET_SZ 32
+#define RG_FFT_IFFT_MODE_MSK 0x000000c0
+#define RG_FFT_IFFT_MODE_I_MSK 0xffffff3f
+#define RG_FFT_IFFT_MODE_SFT 6
+#define RG_FFT_IFFT_MODE_HI 7
+#define RG_FFT_IFFT_MODE_SZ 2
+#define RG_DAC_DBG_MODE_MSK 0x00000100
+#define RG_DAC_DBG_MODE_I_MSK 0xfffffeff
+#define RG_DAC_DBG_MODE_SFT 8
+#define RG_DAC_DBG_MODE_HI 8
+#define RG_DAC_DBG_MODE_SZ 1
+#define RG_DAC_SGN_SWAP_MSK 0x00000200
+#define RG_DAC_SGN_SWAP_I_MSK 0xfffffdff
+#define RG_DAC_SGN_SWAP_SFT 9
+#define RG_DAC_SGN_SWAP_HI 9
+#define RG_DAC_SGN_SWAP_SZ 1
+#define RG_TXD_SEL_MSK 0x00000c00
+#define RG_TXD_SEL_I_MSK 0xfffff3ff
+#define RG_TXD_SEL_SFT 10
+#define RG_TXD_SEL_HI 11
+#define RG_TXD_SEL_SZ 2
+#define RG_UP8X_MSK 0x00ff0000
+#define RG_UP8X_I_MSK 0xff00ffff
+#define RG_UP8X_SFT 16
+#define RG_UP8X_HI 23
+#define RG_UP8X_SZ 8
+#define RG_IQ_DC_BYP_MSK 0x01000000
+#define RG_IQ_DC_BYP_I_MSK 0xfeffffff
+#define RG_IQ_DC_BYP_SFT 24
+#define RG_IQ_DC_BYP_HI 24
+#define RG_IQ_DC_BYP_SZ 1
+#define RG_IQ_DC_LEAKY_FACTOR_MSK 0x30000000
+#define RG_IQ_DC_LEAKY_FACTOR_I_MSK 0xcfffffff
+#define RG_IQ_DC_LEAKY_FACTOR_SFT 28
+#define RG_IQ_DC_LEAKY_FACTOR_HI 29
+#define RG_IQ_DC_LEAKY_FACTOR_SZ 2
+#define RG_DAC_DCEN_MSK 0x00000001
+#define RG_DAC_DCEN_I_MSK 0xfffffffe
+#define RG_DAC_DCEN_SFT 0
+#define RG_DAC_DCEN_HI 0
+#define RG_DAC_DCEN_SZ 1
+#define RG_DAC_DCQ_MSK 0x00003ff0
+#define RG_DAC_DCQ_I_MSK 0xffffc00f
+#define RG_DAC_DCQ_SFT 4
+#define RG_DAC_DCQ_HI 13
+#define RG_DAC_DCQ_SZ 10
+#define RG_DAC_DCI_MSK 0x03ff0000
+#define RG_DAC_DCI_I_MSK 0xfc00ffff
+#define RG_DAC_DCI_SFT 16
+#define RG_DAC_DCI_HI 25
+#define RG_DAC_DCI_SZ 10
+#define RG_PGA_REFDB_SAT_MSK 0x0000007f
+#define RG_PGA_REFDB_SAT_I_MSK 0xffffff80
+#define RG_PGA_REFDB_SAT_SFT 0
+#define RG_PGA_REFDB_SAT_HI 6
+#define RG_PGA_REFDB_SAT_SZ 7
+#define RG_PGA_REFDB_TOP_MSK 0x00007f00
+#define RG_PGA_REFDB_TOP_I_MSK 0xffff80ff
+#define RG_PGA_REFDB_TOP_SFT 8
+#define RG_PGA_REFDB_TOP_HI 14
+#define RG_PGA_REFDB_TOP_SZ 7
+#define RG_PGA_REF_UND_MSK 0x03ff0000
+#define RG_PGA_REF_UND_I_MSK 0xfc00ffff
+#define RG_PGA_REF_UND_SFT 16
+#define RG_PGA_REF_UND_HI 25
+#define RG_PGA_REF_UND_SZ 10
+#define RG_RF_REF_SAT_MSK 0xf0000000
+#define RG_RF_REF_SAT_I_MSK 0x0fffffff
+#define RG_RF_REF_SAT_SFT 28
+#define RG_RF_REF_SAT_HI 31
+#define RG_RF_REF_SAT_SZ 4
+#define RG_PGAGC_SET_MSK 0x0000000f
+#define RG_PGAGC_SET_I_MSK 0xfffffff0
+#define RG_PGAGC_SET_SFT 0
+#define RG_PGAGC_SET_HI 3
+#define RG_PGAGC_SET_SZ 4
+#define RG_PGAGC_OW_MSK 0x00000010
+#define RG_PGAGC_OW_I_MSK 0xffffffef
+#define RG_PGAGC_OW_SFT 4
+#define RG_PGAGC_OW_HI 4
+#define RG_PGAGC_OW_SZ 1
+#define RG_RFGC_SET_MSK 0x00000060
+#define RG_RFGC_SET_I_MSK 0xffffff9f
+#define RG_RFGC_SET_SFT 5
+#define RG_RFGC_SET_HI 6
+#define RG_RFGC_SET_SZ 2
+#define RG_RFGC_OW_MSK 0x00000080
+#define RG_RFGC_OW_I_MSK 0xffffff7f
+#define RG_RFGC_OW_SFT 7
+#define RG_RFGC_OW_HI 7
+#define RG_RFGC_OW_SZ 1
+#define RG_WAIT_T_RXAGC_MSK 0x00003f00
+#define RG_WAIT_T_RXAGC_I_MSK 0xffffc0ff
+#define RG_WAIT_T_RXAGC_SFT 8
+#define RG_WAIT_T_RXAGC_HI 13
+#define RG_WAIT_T_RXAGC_SZ 6
+#define RG_RXAGC_SET_MSK 0x00004000
+#define RG_RXAGC_SET_I_MSK 0xffffbfff
+#define RG_RXAGC_SET_SFT 14
+#define RG_RXAGC_SET_HI 14
+#define RG_RXAGC_SET_SZ 1
+#define RG_RXAGC_OW_MSK 0x00008000
+#define RG_RXAGC_OW_I_MSK 0xffff7fff
+#define RG_RXAGC_OW_SFT 15
+#define RG_RXAGC_OW_HI 15
+#define RG_RXAGC_OW_SZ 1
+#define RG_WAIT_T_FINAL_MSK 0x003f0000
+#define RG_WAIT_T_FINAL_I_MSK 0xffc0ffff
+#define RG_WAIT_T_FINAL_SFT 16
+#define RG_WAIT_T_FINAL_HI 21
+#define RG_WAIT_T_FINAL_SZ 6
+#define RG_WAIT_T_MSK 0x3f000000
+#define RG_WAIT_T_I_MSK 0xc0ffffff
+#define RG_WAIT_T_SFT 24
+#define RG_WAIT_T_HI 29
+#define RG_WAIT_T_SZ 6
+#define RG_ULG_PGA_SAT_PGA_GAIN_MSK 0x0000000f
+#define RG_ULG_PGA_SAT_PGA_GAIN_I_MSK 0xfffffff0
+#define RG_ULG_PGA_SAT_PGA_GAIN_SFT 0
+#define RG_ULG_PGA_SAT_PGA_GAIN_HI 3
+#define RG_ULG_PGA_SAT_PGA_GAIN_SZ 4
+#define RG_LG_PGA_UND_PGA_GAIN_MSK 0x000000f0
+#define RG_LG_PGA_UND_PGA_GAIN_I_MSK 0xffffff0f
+#define RG_LG_PGA_UND_PGA_GAIN_SFT 4
+#define RG_LG_PGA_UND_PGA_GAIN_HI 7
+#define RG_LG_PGA_UND_PGA_GAIN_SZ 4
+#define RG_LG_PGA_SAT_PGA_GAIN_MSK 0x00000f00
+#define RG_LG_PGA_SAT_PGA_GAIN_I_MSK 0xfffff0ff
+#define RG_LG_PGA_SAT_PGA_GAIN_SFT 8
+#define RG_LG_PGA_SAT_PGA_GAIN_HI 11
+#define RG_LG_PGA_SAT_PGA_GAIN_SZ 4
+#define RG_LG_RF_SAT_PGA_GAIN_MSK 0x0000f000
+#define RG_LG_RF_SAT_PGA_GAIN_I_MSK 0xffff0fff
+#define RG_LG_RF_SAT_PGA_GAIN_SFT 12
+#define RG_LG_RF_SAT_PGA_GAIN_HI 15
+#define RG_LG_RF_SAT_PGA_GAIN_SZ 4
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_MSK 0x000f0000
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_I_MSK 0xfff0ffff
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SFT 16
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_HI 19
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SZ 4
+#define RG_HG_PGA_SAT2_PGA_GAIN_MSK 0x00f00000
+#define RG_HG_PGA_SAT2_PGA_GAIN_I_MSK 0xff0fffff
+#define RG_HG_PGA_SAT2_PGA_GAIN_SFT 20
+#define RG_HG_PGA_SAT2_PGA_GAIN_HI 23
+#define RG_HG_PGA_SAT2_PGA_GAIN_SZ 4
+#define RG_HG_PGA_SAT1_PGA_GAIN_MSK 0x0f000000
+#define RG_HG_PGA_SAT1_PGA_GAIN_I_MSK 0xf0ffffff
+#define RG_HG_PGA_SAT1_PGA_GAIN_SFT 24
+#define RG_HG_PGA_SAT1_PGA_GAIN_HI 27
+#define RG_HG_PGA_SAT1_PGA_GAIN_SZ 4
+#define RG_HG_RF_SAT_PGA_GAIN_MSK 0xf0000000
+#define RG_HG_RF_SAT_PGA_GAIN_I_MSK 0x0fffffff
+#define RG_HG_RF_SAT_PGA_GAIN_SFT 28
+#define RG_HG_RF_SAT_PGA_GAIN_HI 31
+#define RG_HG_RF_SAT_PGA_GAIN_SZ 4
+#define RG_MG_PGA_JB_TH_MSK 0x0000000f
+#define RG_MG_PGA_JB_TH_I_MSK 0xfffffff0
+#define RG_MG_PGA_JB_TH_SFT 0
+#define RG_MG_PGA_JB_TH_HI 3
+#define RG_MG_PGA_JB_TH_SZ 4
+#define RG_MA_PGA_LOW_TH_CNT_LMT_MSK 0x001f0000
+#define RG_MA_PGA_LOW_TH_CNT_LMT_I_MSK 0xffe0ffff
+#define RG_MA_PGA_LOW_TH_CNT_LMT_SFT 16
+#define RG_MA_PGA_LOW_TH_CNT_LMT_HI 20
+#define RG_MA_PGA_LOW_TH_CNT_LMT_SZ 5
+#define RG_WR_RFGC_INIT_SET_MSK 0x00600000
+#define RG_WR_RFGC_INIT_SET_I_MSK 0xff9fffff
+#define RG_WR_RFGC_INIT_SET_SFT 21
+#define RG_WR_RFGC_INIT_SET_HI 22
+#define RG_WR_RFGC_INIT_SET_SZ 2
+#define RG_WR_RFGC_INIT_EN_MSK 0x00800000
+#define RG_WR_RFGC_INIT_EN_I_MSK 0xff7fffff
+#define RG_WR_RFGC_INIT_EN_SFT 23
+#define RG_WR_RFGC_INIT_EN_HI 23
+#define RG_WR_RFGC_INIT_EN_SZ 1
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_MSK 0x1f000000
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_I_MSK 0xe0ffffff
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_SFT 24
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_HI 28
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_SZ 5
+#define RG_AGC_THRESHOLD_MSK 0x00003fff
+#define RG_AGC_THRESHOLD_I_MSK 0xffffc000
+#define RG_AGC_THRESHOLD_SFT 0
+#define RG_AGC_THRESHOLD_HI 13
+#define RG_AGC_THRESHOLD_SZ 14
+#define RG_ACI_POINT_CNT_LMT_11B_MSK 0x007f0000
+#define RG_ACI_POINT_CNT_LMT_11B_I_MSK 0xff80ffff
+#define RG_ACI_POINT_CNT_LMT_11B_SFT 16
+#define RG_ACI_POINT_CNT_LMT_11B_HI 22
+#define RG_ACI_POINT_CNT_LMT_11B_SZ 7
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_MSK 0x03000000
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_I_MSK 0xfcffffff
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SFT 24
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_HI 25
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SZ 2
+#define RG_WR_ACI_GAIN_INI_SEL_11B_MSK 0x000000ff
+#define RG_WR_ACI_GAIN_INI_SEL_11B_I_MSK 0xffffff00
+#define RG_WR_ACI_GAIN_INI_SEL_11B_SFT 0
+#define RG_WR_ACI_GAIN_INI_SEL_11B_HI 7
+#define RG_WR_ACI_GAIN_INI_SEL_11B_SZ 8
+#define RG_WR_ACI_GAIN_SEL_11B_MSK 0x0000ff00
+#define RG_WR_ACI_GAIN_SEL_11B_I_MSK 0xffff00ff
+#define RG_WR_ACI_GAIN_SEL_11B_SFT 8
+#define RG_WR_ACI_GAIN_SEL_11B_HI 15
+#define RG_WR_ACI_GAIN_SEL_11B_SZ 8
+#define RG_ACI_DAGC_SET_VALUE_11B_MSK 0x007f0000
+#define RG_ACI_DAGC_SET_VALUE_11B_I_MSK 0xff80ffff
+#define RG_ACI_DAGC_SET_VALUE_11B_SFT 16
+#define RG_ACI_DAGC_SET_VALUE_11B_HI 22
+#define RG_ACI_DAGC_SET_VALUE_11B_SZ 7
+#define RG_WR_ACI_GAIN_OW_11B_MSK 0x80000000
+#define RG_WR_ACI_GAIN_OW_11B_I_MSK 0x7fffffff
+#define RG_WR_ACI_GAIN_OW_11B_SFT 31
+#define RG_WR_ACI_GAIN_OW_11B_HI 31
+#define RG_WR_ACI_GAIN_OW_11B_SZ 1
+#define RG_ACI_POINT_CNT_LMT_11GN_MSK 0x000000ff
+#define RG_ACI_POINT_CNT_LMT_11GN_I_MSK 0xffffff00
+#define RG_ACI_POINT_CNT_LMT_11GN_SFT 0
+#define RG_ACI_POINT_CNT_LMT_11GN_HI 7
+#define RG_ACI_POINT_CNT_LMT_11GN_SZ 8
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_MSK 0x00000300
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_I_MSK 0xfffffcff
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SFT 8
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HI 9
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SZ 2
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_MSK 0xff000000
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_I_MSK 0x00ffffff
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SFT 24
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_HI 31
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SZ 8
+#define RG_ACI_DAGC_SET_VALUE_11GN_MSK 0x0000007f
+#define RG_ACI_DAGC_SET_VALUE_11GN_I_MSK 0xffffff80
+#define RG_ACI_DAGC_SET_VALUE_11GN_SFT 0
+#define RG_ACI_DAGC_SET_VALUE_11GN_HI 6
+#define RG_ACI_DAGC_SET_VALUE_11GN_SZ 7
+#define RG_ACI_GAIN_INI_VAL_11GN_MSK 0x0000ff00
+#define RG_ACI_GAIN_INI_VAL_11GN_I_MSK 0xffff00ff
+#define RG_ACI_GAIN_INI_VAL_11GN_SFT 8
+#define RG_ACI_GAIN_INI_VAL_11GN_HI 15
+#define RG_ACI_GAIN_INI_VAL_11GN_SZ 8
+#define RG_ACI_GAIN_OW_VAL_11GN_MSK 0x00ff0000
+#define RG_ACI_GAIN_OW_VAL_11GN_I_MSK 0xff00ffff
+#define RG_ACI_GAIN_OW_VAL_11GN_SFT 16
+#define RG_ACI_GAIN_OW_VAL_11GN_HI 23
+#define RG_ACI_GAIN_OW_VAL_11GN_SZ 8
+#define RG_ACI_GAIN_OW_11GN_MSK 0x80000000
+#define RG_ACI_GAIN_OW_11GN_I_MSK 0x7fffffff
+#define RG_ACI_GAIN_OW_11GN_SFT 31
+#define RG_ACI_GAIN_OW_11GN_HI 31
+#define RG_ACI_GAIN_OW_11GN_SZ 1
+#define RO_CCA_PWR_MA_11GN_MSK 0x0000007f
+#define RO_CCA_PWR_MA_11GN_I_MSK 0xffffff80
+#define RO_CCA_PWR_MA_11GN_SFT 0
+#define RO_CCA_PWR_MA_11GN_HI 6
+#define RO_CCA_PWR_MA_11GN_SZ 7
+#define RO_ED_STATE_MSK 0x00008000
+#define RO_ED_STATE_I_MSK 0xffff7fff
+#define RO_ED_STATE_SFT 15
+#define RO_ED_STATE_HI 15
+#define RO_ED_STATE_SZ 1
+#define RO_CCA_PWR_MA_11B_MSK 0x007f0000
+#define RO_CCA_PWR_MA_11B_I_MSK 0xff80ffff
+#define RO_CCA_PWR_MA_11B_SFT 16
+#define RO_CCA_PWR_MA_11B_HI 22
+#define RO_CCA_PWR_MA_11B_SZ 7
+#define RO_PGA_PWR_FF1_MSK 0x00003fff
+#define RO_PGA_PWR_FF1_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF1_SFT 0
+#define RO_PGA_PWR_FF1_HI 13
+#define RO_PGA_PWR_FF1_SZ 14
+#define RO_RF_PWR_FF1_MSK 0x000f0000
+#define RO_RF_PWR_FF1_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF1_SFT 16
+#define RO_RF_PWR_FF1_HI 19
+#define RO_RF_PWR_FF1_SZ 4
+#define RO_PGAGC_FF1_MSK 0x0f000000
+#define RO_PGAGC_FF1_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF1_SFT 24
+#define RO_PGAGC_FF1_HI 27
+#define RO_PGAGC_FF1_SZ 4
+#define RO_RFGC_FF1_MSK 0x30000000
+#define RO_RFGC_FF1_I_MSK 0xcfffffff
+#define RO_RFGC_FF1_SFT 28
+#define RO_RFGC_FF1_HI 29
+#define RO_RFGC_FF1_SZ 2
+#define RO_PGA_PWR_FF2_MSK 0x00003fff
+#define RO_PGA_PWR_FF2_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF2_SFT 0
+#define RO_PGA_PWR_FF2_HI 13
+#define RO_PGA_PWR_FF2_SZ 14
+#define RO_RF_PWR_FF2_MSK 0x000f0000
+#define RO_RF_PWR_FF2_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF2_SFT 16
+#define RO_RF_PWR_FF2_HI 19
+#define RO_RF_PWR_FF2_SZ 4
+#define RO_PGAGC_FF2_MSK 0x0f000000
+#define RO_PGAGC_FF2_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF2_SFT 24
+#define RO_PGAGC_FF2_HI 27
+#define RO_PGAGC_FF2_SZ 4
+#define RO_RFGC_FF2_MSK 0x30000000
+#define RO_RFGC_FF2_I_MSK 0xcfffffff
+#define RO_RFGC_FF2_SFT 28
+#define RO_RFGC_FF2_HI 29
+#define RO_RFGC_FF2_SZ 2
+#define RO_PGA_PWR_FF3_MSK 0x00003fff
+#define RO_PGA_PWR_FF3_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF3_SFT 0
+#define RO_PGA_PWR_FF3_HI 13
+#define RO_PGA_PWR_FF3_SZ 14
+#define RO_RF_PWR_FF3_MSK 0x000f0000
+#define RO_RF_PWR_FF3_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF3_SFT 16
+#define RO_RF_PWR_FF3_HI 19
+#define RO_RF_PWR_FF3_SZ 4
+#define RO_PGAGC_FF3_MSK 0x0f000000
+#define RO_PGAGC_FF3_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF3_SFT 24
+#define RO_PGAGC_FF3_HI 27
+#define RO_PGAGC_FF3_SZ 4
+#define RO_RFGC_FF3_MSK 0x30000000
+#define RO_RFGC_FF3_I_MSK 0xcfffffff
+#define RO_RFGC_FF3_SFT 28
+#define RO_RFGC_FF3_HI 29
+#define RO_RFGC_FF3_SZ 2
+#define RG_TX_DES_RATE_MSK 0x0000001f
+#define RG_TX_DES_RATE_I_MSK 0xffffffe0
+#define RG_TX_DES_RATE_SFT 0
+#define RG_TX_DES_RATE_HI 4
+#define RG_TX_DES_RATE_SZ 5
+#define RG_TX_DES_MODE_MSK 0x00001f00
+#define RG_TX_DES_MODE_I_MSK 0xffffe0ff
+#define RG_TX_DES_MODE_SFT 8
+#define RG_TX_DES_MODE_HI 12
+#define RG_TX_DES_MODE_SZ 5
+#define RG_TX_DES_LEN_LO_MSK 0x001f0000
+#define RG_TX_DES_LEN_LO_I_MSK 0xffe0ffff
+#define RG_TX_DES_LEN_LO_SFT 16
+#define RG_TX_DES_LEN_LO_HI 20
+#define RG_TX_DES_LEN_LO_SZ 5
+#define RG_TX_DES_LEN_UP_MSK 0x1f000000
+#define RG_TX_DES_LEN_UP_I_MSK 0xe0ffffff
+#define RG_TX_DES_LEN_UP_SFT 24
+#define RG_TX_DES_LEN_UP_HI 28
+#define RG_TX_DES_LEN_UP_SZ 5
+#define RG_TX_DES_SRVC_UP_MSK 0x0000001f
+#define RG_TX_DES_SRVC_UP_I_MSK 0xffffffe0
+#define RG_TX_DES_SRVC_UP_SFT 0
+#define RG_TX_DES_SRVC_UP_HI 4
+#define RG_TX_DES_SRVC_UP_SZ 5
+#define RG_TX_DES_L_LEN_LO_MSK 0x00001f00
+#define RG_TX_DES_L_LEN_LO_I_MSK 0xffffe0ff
+#define RG_TX_DES_L_LEN_LO_SFT 8
+#define RG_TX_DES_L_LEN_LO_HI 12
+#define RG_TX_DES_L_LEN_LO_SZ 5
+#define RG_TX_DES_L_LEN_UP_MSK 0x001f0000
+#define RG_TX_DES_L_LEN_UP_I_MSK 0xffe0ffff
+#define RG_TX_DES_L_LEN_UP_SFT 16
+#define RG_TX_DES_L_LEN_UP_HI 20
+#define RG_TX_DES_L_LEN_UP_SZ 5
+#define RG_TX_DES_TYPE_MSK 0x1f000000
+#define RG_TX_DES_TYPE_I_MSK 0xe0ffffff
+#define RG_TX_DES_TYPE_SFT 24
+#define RG_TX_DES_TYPE_HI 28
+#define RG_TX_DES_TYPE_SZ 5
+#define RG_TX_DES_L_LEN_UP_COMB_MSK 0x00000001
+#define RG_TX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
+#define RG_TX_DES_L_LEN_UP_COMB_SFT 0
+#define RG_TX_DES_L_LEN_UP_COMB_HI 0
+#define RG_TX_DES_L_LEN_UP_COMB_SZ 1
+#define RG_TX_DES_TYPE_COMB_MSK 0x00000010
+#define RG_TX_DES_TYPE_COMB_I_MSK 0xffffffef
+#define RG_TX_DES_TYPE_COMB_SFT 4
+#define RG_TX_DES_TYPE_COMB_HI 4
+#define RG_TX_DES_TYPE_COMB_SZ 1
+#define RG_TX_DES_RATE_COMB_MSK 0x00000100
+#define RG_TX_DES_RATE_COMB_I_MSK 0xfffffeff
+#define RG_TX_DES_RATE_COMB_SFT 8
+#define RG_TX_DES_RATE_COMB_HI 8
+#define RG_TX_DES_RATE_COMB_SZ 1
+#define RG_TX_DES_MODE_COMB_MSK 0x00001000
+#define RG_TX_DES_MODE_COMB_I_MSK 0xffffefff
+#define RG_TX_DES_MODE_COMB_SFT 12
+#define RG_TX_DES_MODE_COMB_HI 12
+#define RG_TX_DES_MODE_COMB_SZ 1
+#define RG_TX_DES_PWRLVL_MSK 0x001f0000
+#define RG_TX_DES_PWRLVL_I_MSK 0xffe0ffff
+#define RG_TX_DES_PWRLVL_SFT 16
+#define RG_TX_DES_PWRLVL_HI 20
+#define RG_TX_DES_PWRLVL_SZ 5
+#define RG_TX_DES_SRVC_LO_MSK 0x1f000000
+#define RG_TX_DES_SRVC_LO_I_MSK 0xe0ffffff
+#define RG_TX_DES_SRVC_LO_SFT 24
+#define RG_TX_DES_SRVC_LO_HI 28
+#define RG_TX_DES_SRVC_LO_SZ 5
+#define RG_RX_DES_RATE_MSK 0x0000003f
+#define RG_RX_DES_RATE_I_MSK 0xffffffc0
+#define RG_RX_DES_RATE_SFT 0
+#define RG_RX_DES_RATE_HI 5
+#define RG_RX_DES_RATE_SZ 6
+#define RG_RX_DES_MODE_MSK 0x00003f00
+#define RG_RX_DES_MODE_I_MSK 0xffffc0ff
+#define RG_RX_DES_MODE_SFT 8
+#define RG_RX_DES_MODE_HI 13
+#define RG_RX_DES_MODE_SZ 6
+#define RG_RX_DES_LEN_LO_MSK 0x003f0000
+#define RG_RX_DES_LEN_LO_I_MSK 0xffc0ffff
+#define RG_RX_DES_LEN_LO_SFT 16
+#define RG_RX_DES_LEN_LO_HI 21
+#define RG_RX_DES_LEN_LO_SZ 6
+#define RG_RX_DES_LEN_UP_MSK 0x3f000000
+#define RG_RX_DES_LEN_UP_I_MSK 0xc0ffffff
+#define RG_RX_DES_LEN_UP_SFT 24
+#define RG_RX_DES_LEN_UP_HI 29
+#define RG_RX_DES_LEN_UP_SZ 6
+#define RG_RX_DES_SRVC_UP_MSK 0x0000003f
+#define RG_RX_DES_SRVC_UP_I_MSK 0xffffffc0
+#define RG_RX_DES_SRVC_UP_SFT 0
+#define RG_RX_DES_SRVC_UP_HI 5
+#define RG_RX_DES_SRVC_UP_SZ 6
+#define RG_RX_DES_L_LEN_LO_MSK 0x00003f00
+#define RG_RX_DES_L_LEN_LO_I_MSK 0xffffc0ff
+#define RG_RX_DES_L_LEN_LO_SFT 8
+#define RG_RX_DES_L_LEN_LO_HI 13
+#define RG_RX_DES_L_LEN_LO_SZ 6
+#define RG_RX_DES_L_LEN_UP_MSK 0x003f0000
+#define RG_RX_DES_L_LEN_UP_I_MSK 0xffc0ffff
+#define RG_RX_DES_L_LEN_UP_SFT 16
+#define RG_RX_DES_L_LEN_UP_HI 21
+#define RG_RX_DES_L_LEN_UP_SZ 6
+#define RG_RX_DES_TYPE_MSK 0x3f000000
+#define RG_RX_DES_TYPE_I_MSK 0xc0ffffff
+#define RG_RX_DES_TYPE_SFT 24
+#define RG_RX_DES_TYPE_HI 29
+#define RG_RX_DES_TYPE_SZ 6
+#define RG_RX_DES_L_LEN_UP_COMB_MSK 0x00000001
+#define RG_RX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
+#define RG_RX_DES_L_LEN_UP_COMB_SFT 0
+#define RG_RX_DES_L_LEN_UP_COMB_HI 0
+#define RG_RX_DES_L_LEN_UP_COMB_SZ 1
+#define RG_RX_DES_TYPE_COMB_MSK 0x00000010
+#define RG_RX_DES_TYPE_COMB_I_MSK 0xffffffef
+#define RG_RX_DES_TYPE_COMB_SFT 4
+#define RG_RX_DES_TYPE_COMB_HI 4
+#define RG_RX_DES_TYPE_COMB_SZ 1
+#define RG_RX_DES_RATE_COMB_MSK 0x00000100
+#define RG_RX_DES_RATE_COMB_I_MSK 0xfffffeff
+#define RG_RX_DES_RATE_COMB_SFT 8
+#define RG_RX_DES_RATE_COMB_HI 8
+#define RG_RX_DES_RATE_COMB_SZ 1
+#define RG_RX_DES_MODE_COMB_MSK 0x00001000
+#define RG_RX_DES_MODE_COMB_I_MSK 0xffffefff
+#define RG_RX_DES_MODE_COMB_SFT 12
+#define RG_RX_DES_MODE_COMB_HI 12
+#define RG_RX_DES_MODE_COMB_SZ 1
+#define RG_RX_DES_SNR_MSK 0x000f0000
+#define RG_RX_DES_SNR_I_MSK 0xfff0ffff
+#define RG_RX_DES_SNR_SFT 16
+#define RG_RX_DES_SNR_HI 19
+#define RG_RX_DES_SNR_SZ 4
+#define RG_RX_DES_RCPI_MSK 0x00f00000
+#define RG_RX_DES_RCPI_I_MSK 0xff0fffff
+#define RG_RX_DES_RCPI_SFT 20
+#define RG_RX_DES_RCPI_HI 23
+#define RG_RX_DES_RCPI_SZ 4
+#define RG_RX_DES_SRVC_LO_MSK 0x3f000000
+#define RG_RX_DES_SRVC_LO_I_MSK 0xc0ffffff
+#define RG_RX_DES_SRVC_LO_SFT 24
+#define RG_RX_DES_SRVC_LO_HI 29
+#define RG_RX_DES_SRVC_LO_SZ 6
+#define RO_TX_DES_EXCP_RATE_CNT_MSK 0x000000ff
+#define RO_TX_DES_EXCP_RATE_CNT_I_MSK 0xffffff00
+#define RO_TX_DES_EXCP_RATE_CNT_SFT 0
+#define RO_TX_DES_EXCP_RATE_CNT_HI 7
+#define RO_TX_DES_EXCP_RATE_CNT_SZ 8
+#define RO_TX_DES_EXCP_CH_BW_CNT_MSK 0x0000ff00
+#define RO_TX_DES_EXCP_CH_BW_CNT_I_MSK 0xffff00ff
+#define RO_TX_DES_EXCP_CH_BW_CNT_SFT 8
+#define RO_TX_DES_EXCP_CH_BW_CNT_HI 15
+#define RO_TX_DES_EXCP_CH_BW_CNT_SZ 8
+#define RO_TX_DES_EXCP_MODE_CNT_MSK 0x00ff0000
+#define RO_TX_DES_EXCP_MODE_CNT_I_MSK 0xff00ffff
+#define RO_TX_DES_EXCP_MODE_CNT_SFT 16
+#define RO_TX_DES_EXCP_MODE_CNT_HI 23
+#define RO_TX_DES_EXCP_MODE_CNT_SZ 8
+#define RG_TX_DES_EXCP_RATE_DEFAULT_MSK 0x07000000
+#define RG_TX_DES_EXCP_RATE_DEFAULT_I_MSK 0xf8ffffff
+#define RG_TX_DES_EXCP_RATE_DEFAULT_SFT 24
+#define RG_TX_DES_EXCP_RATE_DEFAULT_HI 26
+#define RG_TX_DES_EXCP_RATE_DEFAULT_SZ 3
+#define RG_TX_DES_EXCP_MODE_DEFAULT_MSK 0x70000000
+#define RG_TX_DES_EXCP_MODE_DEFAULT_I_MSK 0x8fffffff
+#define RG_TX_DES_EXCP_MODE_DEFAULT_SFT 28
+#define RG_TX_DES_EXCP_MODE_DEFAULT_HI 30
+#define RG_TX_DES_EXCP_MODE_DEFAULT_SZ 3
+#define RG_TX_DES_EXCP_CLR_MSK 0x80000000
+#define RG_TX_DES_EXCP_CLR_I_MSK 0x7fffffff
+#define RG_TX_DES_EXCP_CLR_SFT 31
+#define RG_TX_DES_EXCP_CLR_HI 31
+#define RG_TX_DES_EXCP_CLR_SZ 1
+#define RG_TX_DES_ACK_WIDTH_MSK 0x00000001
+#define RG_TX_DES_ACK_WIDTH_I_MSK 0xfffffffe
+#define RG_TX_DES_ACK_WIDTH_SFT 0
+#define RG_TX_DES_ACK_WIDTH_HI 0
+#define RG_TX_DES_ACK_WIDTH_SZ 1
+#define RG_TX_DES_ACK_PRD_MSK 0x0000000e
+#define RG_TX_DES_ACK_PRD_I_MSK 0xfffffff1
+#define RG_TX_DES_ACK_PRD_SFT 1
+#define RG_TX_DES_ACK_PRD_HI 3
+#define RG_TX_DES_ACK_PRD_SZ 3
+#define RG_RX_DES_SNR_GN_MSK 0x003f0000
+#define RG_RX_DES_SNR_GN_I_MSK 0xffc0ffff
+#define RG_RX_DES_SNR_GN_SFT 16
+#define RG_RX_DES_SNR_GN_HI 21
+#define RG_RX_DES_SNR_GN_SZ 6
+#define RG_RX_DES_RCPI_GN_MSK 0x3f000000
+#define RG_RX_DES_RCPI_GN_I_MSK 0xc0ffffff
+#define RG_RX_DES_RCPI_GN_SFT 24
+#define RG_RX_DES_RCPI_GN_HI 29
+#define RG_RX_DES_RCPI_GN_SZ 6
+#define RG_TST_TBUS_SEL_MSK 0x0000000f
+#define RG_TST_TBUS_SEL_I_MSK 0xfffffff0
+#define RG_TST_TBUS_SEL_SFT 0
+#define RG_TST_TBUS_SEL_HI 3
+#define RG_TST_TBUS_SEL_SZ 4
+#define RG_RSSI_OFFSET_MSK 0x00ff0000
+#define RG_RSSI_OFFSET_I_MSK 0xff00ffff
+#define RG_RSSI_OFFSET_SFT 16
+#define RG_RSSI_OFFSET_HI 23
+#define RG_RSSI_OFFSET_SZ 8
+#define RG_RSSI_INV_MSK 0x01000000
+#define RG_RSSI_INV_I_MSK 0xfeffffff
+#define RG_RSSI_INV_SFT 24
+#define RG_RSSI_INV_HI 24
+#define RG_RSSI_INV_SZ 1
+#define RG_TST_ADC_ON_MSK 0x40000000
+#define RG_TST_ADC_ON_I_MSK 0xbfffffff
+#define RG_TST_ADC_ON_SFT 30
+#define RG_TST_ADC_ON_HI 30
+#define RG_TST_ADC_ON_SZ 1
+#define RG_TST_EXT_GAIN_MSK 0x80000000
+#define RG_TST_EXT_GAIN_I_MSK 0x7fffffff
+#define RG_TST_EXT_GAIN_SFT 31
+#define RG_TST_EXT_GAIN_HI 31
+#define RG_TST_EXT_GAIN_SZ 1
+#define RG_DAC_Q_SET_MSK 0x000003ff
+#define RG_DAC_Q_SET_I_MSK 0xfffffc00
+#define RG_DAC_Q_SET_SFT 0
+#define RG_DAC_Q_SET_HI 9
+#define RG_DAC_Q_SET_SZ 10
+#define RG_DAC_I_SET_MSK 0x003ff000
+#define RG_DAC_I_SET_I_MSK 0xffc00fff
+#define RG_DAC_I_SET_SFT 12
+#define RG_DAC_I_SET_HI 21
+#define RG_DAC_I_SET_SZ 10
+#define RG_DAC_EN_MAN_MSK 0x10000000
+#define RG_DAC_EN_MAN_I_MSK 0xefffffff
+#define RG_DAC_EN_MAN_SFT 28
+#define RG_DAC_EN_MAN_HI 28
+#define RG_DAC_EN_MAN_SZ 1
+#define RG_IQC_FFT_EN_MSK 0x20000000
+#define RG_IQC_FFT_EN_I_MSK 0xdfffffff
+#define RG_IQC_FFT_EN_SFT 29
+#define RG_IQC_FFT_EN_HI 29
+#define RG_IQC_FFT_EN_SZ 1
+#define RG_DAC_MAN_Q_EN_MSK 0x40000000
+#define RG_DAC_MAN_Q_EN_I_MSK 0xbfffffff
+#define RG_DAC_MAN_Q_EN_SFT 30
+#define RG_DAC_MAN_Q_EN_HI 30
+#define RG_DAC_MAN_Q_EN_SZ 1
+#define RG_DAC_MAN_I_EN_MSK 0x80000000
+#define RG_DAC_MAN_I_EN_I_MSK 0x7fffffff
+#define RG_DAC_MAN_I_EN_SFT 31
+#define RG_DAC_MAN_I_EN_HI 31
+#define RG_DAC_MAN_I_EN_SZ 1
+#define RO_MRX_EN_CNT_MSK 0x0000ffff
+#define RO_MRX_EN_CNT_I_MSK 0xffff0000
+#define RO_MRX_EN_CNT_SFT 0
+#define RO_MRX_EN_CNT_HI 15
+#define RO_MRX_EN_CNT_SZ 16
+#define RG_MRX_EN_CNT_RST_N_MSK 0x80000000
+#define RG_MRX_EN_CNT_RST_N_I_MSK 0x7fffffff
+#define RG_MRX_EN_CNT_RST_N_SFT 31
+#define RG_MRX_EN_CNT_RST_N_HI 31
+#define RG_MRX_EN_CNT_RST_N_SZ 1
+#define RG_PA_RISE_TIME_MSK 0x000000ff
+#define RG_PA_RISE_TIME_I_MSK 0xffffff00
+#define RG_PA_RISE_TIME_SFT 0
+#define RG_PA_RISE_TIME_HI 7
+#define RG_PA_RISE_TIME_SZ 8
+#define RG_RFTX_RISE_TIME_MSK 0x0000ff00
+#define RG_RFTX_RISE_TIME_I_MSK 0xffff00ff
+#define RG_RFTX_RISE_TIME_SFT 8
+#define RG_RFTX_RISE_TIME_HI 15
+#define RG_RFTX_RISE_TIME_SZ 8
+#define RG_DAC_RISE_TIME_MSK 0x00ff0000
+#define RG_DAC_RISE_TIME_I_MSK 0xff00ffff
+#define RG_DAC_RISE_TIME_SFT 16
+#define RG_DAC_RISE_TIME_HI 23
+#define RG_DAC_RISE_TIME_SZ 8
+#define RG_SW_RISE_TIME_MSK 0xff000000
+#define RG_SW_RISE_TIME_I_MSK 0x00ffffff
+#define RG_SW_RISE_TIME_SFT 24
+#define RG_SW_RISE_TIME_HI 31
+#define RG_SW_RISE_TIME_SZ 8
+#define RG_PA_FALL_TIME_MSK 0x000000ff
+#define RG_PA_FALL_TIME_I_MSK 0xffffff00
+#define RG_PA_FALL_TIME_SFT 0
+#define RG_PA_FALL_TIME_HI 7
+#define RG_PA_FALL_TIME_SZ 8
+#define RG_RFTX_FALL_TIME_MSK 0x0000ff00
+#define RG_RFTX_FALL_TIME_I_MSK 0xffff00ff
+#define RG_RFTX_FALL_TIME_SFT 8
+#define RG_RFTX_FALL_TIME_HI 15
+#define RG_RFTX_FALL_TIME_SZ 8
+#define RG_DAC_FALL_TIME_MSK 0x00ff0000
+#define RG_DAC_FALL_TIME_I_MSK 0xff00ffff
+#define RG_DAC_FALL_TIME_SFT 16
+#define RG_DAC_FALL_TIME_HI 23
+#define RG_DAC_FALL_TIME_SZ 8
+#define RG_SW_FALL_TIME_MSK 0xff000000
+#define RG_SW_FALL_TIME_I_MSK 0x00ffffff
+#define RG_SW_FALL_TIME_SFT 24
+#define RG_SW_FALL_TIME_HI 31
+#define RG_SW_FALL_TIME_SZ 8
+#define RG_ANT_SW_0_MSK 0x00000007
+#define RG_ANT_SW_0_I_MSK 0xfffffff8
+#define RG_ANT_SW_0_SFT 0
+#define RG_ANT_SW_0_HI 2
+#define RG_ANT_SW_0_SZ 3
+#define RG_ANT_SW_1_MSK 0x00000038
+#define RG_ANT_SW_1_I_MSK 0xffffffc7
+#define RG_ANT_SW_1_SFT 3
+#define RG_ANT_SW_1_HI 5
+#define RG_ANT_SW_1_SZ 3
+#define RG_MTX_LEN_LOWER_TH_0_MSK 0x00001fff
+#define RG_MTX_LEN_LOWER_TH_0_I_MSK 0xffffe000
+#define RG_MTX_LEN_LOWER_TH_0_SFT 0
+#define RG_MTX_LEN_LOWER_TH_0_HI 12
+#define RG_MTX_LEN_LOWER_TH_0_SZ 13
+#define RG_MTX_LEN_UPPER_TH_0_MSK 0x1fff0000
+#define RG_MTX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
+#define RG_MTX_LEN_UPPER_TH_0_SFT 16
+#define RG_MTX_LEN_UPPER_TH_0_HI 28
+#define RG_MTX_LEN_UPPER_TH_0_SZ 13
+#define RG_MTX_LEN_CNT_EN_0_MSK 0x80000000
+#define RG_MTX_LEN_CNT_EN_0_I_MSK 0x7fffffff
+#define RG_MTX_LEN_CNT_EN_0_SFT 31
+#define RG_MTX_LEN_CNT_EN_0_HI 31
+#define RG_MTX_LEN_CNT_EN_0_SZ 1
+#define RG_MTX_LEN_LOWER_TH_1_MSK 0x00001fff
+#define RG_MTX_LEN_LOWER_TH_1_I_MSK 0xffffe000
+#define RG_MTX_LEN_LOWER_TH_1_SFT 0
+#define RG_MTX_LEN_LOWER_TH_1_HI 12
+#define RG_MTX_LEN_LOWER_TH_1_SZ 13
+#define RG_MTX_LEN_UPPER_TH_1_MSK 0x1fff0000
+#define RG_MTX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
+#define RG_MTX_LEN_UPPER_TH_1_SFT 16
+#define RG_MTX_LEN_UPPER_TH_1_HI 28
+#define RG_MTX_LEN_UPPER_TH_1_SZ 13
+#define RG_MTX_LEN_CNT_EN_1_MSK 0x80000000
+#define RG_MTX_LEN_CNT_EN_1_I_MSK 0x7fffffff
+#define RG_MTX_LEN_CNT_EN_1_SFT 31
+#define RG_MTX_LEN_CNT_EN_1_HI 31
+#define RG_MTX_LEN_CNT_EN_1_SZ 1
+#define RG_MRX_LEN_LOWER_TH_0_MSK 0x00001fff
+#define RG_MRX_LEN_LOWER_TH_0_I_MSK 0xffffe000
+#define RG_MRX_LEN_LOWER_TH_0_SFT 0
+#define RG_MRX_LEN_LOWER_TH_0_HI 12
+#define RG_MRX_LEN_LOWER_TH_0_SZ 13
+#define RG_MRX_LEN_UPPER_TH_0_MSK 0x1fff0000
+#define RG_MRX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
+#define RG_MRX_LEN_UPPER_TH_0_SFT 16
+#define RG_MRX_LEN_UPPER_TH_0_HI 28
+#define RG_MRX_LEN_UPPER_TH_0_SZ 13
+#define RG_MRX_LEN_CNT_EN_0_MSK 0x80000000
+#define RG_MRX_LEN_CNT_EN_0_I_MSK 0x7fffffff
+#define RG_MRX_LEN_CNT_EN_0_SFT 31
+#define RG_MRX_LEN_CNT_EN_0_HI 31
+#define RG_MRX_LEN_CNT_EN_0_SZ 1
+#define RG_MRX_LEN_LOWER_TH_1_MSK 0x00001fff
+#define RG_MRX_LEN_LOWER_TH_1_I_MSK 0xffffe000
+#define RG_MRX_LEN_LOWER_TH_1_SFT 0
+#define RG_MRX_LEN_LOWER_TH_1_HI 12
+#define RG_MRX_LEN_LOWER_TH_1_SZ 13
+#define RG_MRX_LEN_UPPER_TH_1_MSK 0x1fff0000
+#define RG_MRX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
+#define RG_MRX_LEN_UPPER_TH_1_SFT 16
+#define RG_MRX_LEN_UPPER_TH_1_HI 28
+#define RG_MRX_LEN_UPPER_TH_1_SZ 13
+#define RG_MRX_LEN_CNT_EN_1_MSK 0x80000000
+#define RG_MRX_LEN_CNT_EN_1_I_MSK 0x7fffffff
+#define RG_MRX_LEN_CNT_EN_1_SFT 31
+#define RG_MRX_LEN_CNT_EN_1_HI 31
+#define RG_MRX_LEN_CNT_EN_1_SZ 1
+#define RO_MTX_LEN_CNT_1_MSK 0x0000ffff
+#define RO_MTX_LEN_CNT_1_I_MSK 0xffff0000
+#define RO_MTX_LEN_CNT_1_SFT 0
+#define RO_MTX_LEN_CNT_1_HI 15
+#define RO_MTX_LEN_CNT_1_SZ 16
+#define RO_MTX_LEN_CNT_0_MSK 0xffff0000
+#define RO_MTX_LEN_CNT_0_I_MSK 0x0000ffff
+#define RO_MTX_LEN_CNT_0_SFT 16
+#define RO_MTX_LEN_CNT_0_HI 31
+#define RO_MTX_LEN_CNT_0_SZ 16
+#define RO_MRX_LEN_CNT_1_MSK 0x0000ffff
+#define RO_MRX_LEN_CNT_1_I_MSK 0xffff0000
+#define RO_MRX_LEN_CNT_1_SFT 0
+#define RO_MRX_LEN_CNT_1_HI 15
+#define RO_MRX_LEN_CNT_1_SZ 16
+#define RO_MRX_LEN_CNT_0_MSK 0xffff0000
+#define RO_MRX_LEN_CNT_0_I_MSK 0x0000ffff
+#define RO_MRX_LEN_CNT_0_SFT 16
+#define RO_MRX_LEN_CNT_0_HI 31
+#define RO_MRX_LEN_CNT_0_SZ 16
+#define RG_MODE_REG_IN_16_MSK 0x0000ffff
+#define RG_MODE_REG_IN_16_I_MSK 0xffff0000
+#define RG_MODE_REG_IN_16_SFT 0
+#define RG_MODE_REG_IN_16_HI 15
+#define RG_MODE_REG_IN_16_SZ 16
+#define RG_PARALLEL_DR_16_MSK 0x00100000
+#define RG_PARALLEL_DR_16_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_16_SFT 20
+#define RG_PARALLEL_DR_16_HI 20
+#define RG_PARALLEL_DR_16_SZ 1
+#define RG_MBRUN_16_MSK 0x01000000
+#define RG_MBRUN_16_I_MSK 0xfeffffff
+#define RG_MBRUN_16_SFT 24
+#define RG_MBRUN_16_HI 24
+#define RG_MBRUN_16_SZ 1
+#define RG_SHIFT_DR_16_MSK 0x10000000
+#define RG_SHIFT_DR_16_I_MSK 0xefffffff
+#define RG_SHIFT_DR_16_SFT 28
+#define RG_SHIFT_DR_16_HI 28
+#define RG_SHIFT_DR_16_SZ 1
+#define RG_MODE_REG_SI_16_MSK 0x20000000
+#define RG_MODE_REG_SI_16_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_16_SFT 29
+#define RG_MODE_REG_SI_16_HI 29
+#define RG_MODE_REG_SI_16_SZ 1
+#define RG_SIMULATION_MODE_16_MSK 0x40000000
+#define RG_SIMULATION_MODE_16_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_16_SFT 30
+#define RG_SIMULATION_MODE_16_HI 30
+#define RG_SIMULATION_MODE_16_SZ 1
+#define RG_DBIST_MODE_16_MSK 0x80000000
+#define RG_DBIST_MODE_16_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_16_SFT 31
+#define RG_DBIST_MODE_16_HI 31
+#define RG_DBIST_MODE_16_SZ 1
+#define RO_MODE_REG_OUT_16_MSK 0x0000ffff
+#define RO_MODE_REG_OUT_16_I_MSK 0xffff0000
+#define RO_MODE_REG_OUT_16_SFT 0
+#define RO_MODE_REG_OUT_16_HI 15
+#define RO_MODE_REG_OUT_16_SZ 16
+#define RO_MODE_REG_SO_16_MSK 0x01000000
+#define RO_MODE_REG_SO_16_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_16_SFT 24
+#define RO_MODE_REG_SO_16_HI 24
+#define RO_MODE_REG_SO_16_SZ 1
+#define RO_MONITOR_BUS_16_MSK 0x0007ffff
+#define RO_MONITOR_BUS_16_I_MSK 0xfff80000
+#define RO_MONITOR_BUS_16_SFT 0
+#define RO_MONITOR_BUS_16_HI 18
+#define RO_MONITOR_BUS_16_SZ 19
+#define RG_MRX_TYPE_1_MSK 0x000000ff
+#define RG_MRX_TYPE_1_I_MSK 0xffffff00
+#define RG_MRX_TYPE_1_SFT 0
+#define RG_MRX_TYPE_1_HI 7
+#define RG_MRX_TYPE_1_SZ 8
+#define RG_MRX_TYPE_0_MSK 0x0000ff00
+#define RG_MRX_TYPE_0_I_MSK 0xffff00ff
+#define RG_MRX_TYPE_0_SFT 8
+#define RG_MRX_TYPE_0_HI 15
+#define RG_MRX_TYPE_0_SZ 8
+#define RG_MTX_TYPE_1_MSK 0x00ff0000
+#define RG_MTX_TYPE_1_I_MSK 0xff00ffff
+#define RG_MTX_TYPE_1_SFT 16
+#define RG_MTX_TYPE_1_HI 23
+#define RG_MTX_TYPE_1_SZ 8
+#define RG_MTX_TYPE_0_MSK 0xff000000
+#define RG_MTX_TYPE_0_I_MSK 0x00ffffff
+#define RG_MTX_TYPE_0_SFT 24
+#define RG_MTX_TYPE_0_HI 31
+#define RG_MTX_TYPE_0_SZ 8
+#define RO_MTX_TYPE_CNT_1_MSK 0x0000ffff
+#define RO_MTX_TYPE_CNT_1_I_MSK 0xffff0000
+#define RO_MTX_TYPE_CNT_1_SFT 0
+#define RO_MTX_TYPE_CNT_1_HI 15
+#define RO_MTX_TYPE_CNT_1_SZ 16
+#define RO_MTX_TYPE_CNT_0_MSK 0xffff0000
+#define RO_MTX_TYPE_CNT_0_I_MSK 0x0000ffff
+#define RO_MTX_TYPE_CNT_0_SFT 16
+#define RO_MTX_TYPE_CNT_0_HI 31
+#define RO_MTX_TYPE_CNT_0_SZ 16
+#define RO_MRX_TYPE_CNT_1_MSK 0x0000ffff
+#define RO_MRX_TYPE_CNT_1_I_MSK 0xffff0000
+#define RO_MRX_TYPE_CNT_1_SFT 0
+#define RO_MRX_TYPE_CNT_1_HI 15
+#define RO_MRX_TYPE_CNT_1_SZ 16
+#define RO_MRX_TYPE_CNT_0_MSK 0xffff0000
+#define RO_MRX_TYPE_CNT_0_I_MSK 0x0000ffff
+#define RO_MRX_TYPE_CNT_0_SFT 16
+#define RO_MRX_TYPE_CNT_0_HI 31
+#define RO_MRX_TYPE_CNT_0_SZ 16
+#define RG_HB_COEF0_MSK 0x00000fff
+#define RG_HB_COEF0_I_MSK 0xfffff000
+#define RG_HB_COEF0_SFT 0
+#define RG_HB_COEF0_HI 11
+#define RG_HB_COEF0_SZ 12
+#define RG_HB_COEF1_MSK 0x0fff0000
+#define RG_HB_COEF1_I_MSK 0xf000ffff
+#define RG_HB_COEF1_SFT 16
+#define RG_HB_COEF1_HI 27
+#define RG_HB_COEF1_SZ 12
+#define RG_HB_COEF2_MSK 0x00000fff
+#define RG_HB_COEF2_I_MSK 0xfffff000
+#define RG_HB_COEF2_SFT 0
+#define RG_HB_COEF2_HI 11
+#define RG_HB_COEF2_SZ 12
+#define RG_HB_COEF3_MSK 0x0fff0000
+#define RG_HB_COEF3_I_MSK 0xf000ffff
+#define RG_HB_COEF3_SFT 16
+#define RG_HB_COEF3_HI 27
+#define RG_HB_COEF3_SZ 12
+#define RG_HB_COEF4_MSK 0x00000fff
+#define RG_HB_COEF4_I_MSK 0xfffff000
+#define RG_HB_COEF4_SFT 0
+#define RG_HB_COEF4_HI 11
+#define RG_HB_COEF4_SZ 12
+#define RO_TBUS_O_MSK 0x000fffff
+#define RO_TBUS_O_I_MSK 0xfff00000
+#define RO_TBUS_O_SFT 0
+#define RO_TBUS_O_HI 19
+#define RO_TBUS_O_SZ 20
+#define RG_LPF4_00_MSK 0x00001fff
+#define RG_LPF4_00_I_MSK 0xffffe000
+#define RG_LPF4_00_SFT 0
+#define RG_LPF4_00_HI 12
+#define RG_LPF4_00_SZ 13
+#define RG_LPF4_01_MSK 0x00001fff
+#define RG_LPF4_01_I_MSK 0xffffe000
+#define RG_LPF4_01_SFT 0
+#define RG_LPF4_01_HI 12
+#define RG_LPF4_01_SZ 13
+#define RG_LPF4_02_MSK 0x00001fff
+#define RG_LPF4_02_I_MSK 0xffffe000
+#define RG_LPF4_02_SFT 0
+#define RG_LPF4_02_HI 12
+#define RG_LPF4_02_SZ 13
+#define RG_LPF4_03_MSK 0x00001fff
+#define RG_LPF4_03_I_MSK 0xffffe000
+#define RG_LPF4_03_SFT 0
+#define RG_LPF4_03_HI 12
+#define RG_LPF4_03_SZ 13
+#define RG_LPF4_04_MSK 0x00001fff
+#define RG_LPF4_04_I_MSK 0xffffe000
+#define RG_LPF4_04_SFT 0
+#define RG_LPF4_04_HI 12
+#define RG_LPF4_04_SZ 13
+#define RG_LPF4_05_MSK 0x00001fff
+#define RG_LPF4_05_I_MSK 0xffffe000
+#define RG_LPF4_05_SFT 0
+#define RG_LPF4_05_HI 12
+#define RG_LPF4_05_SZ 13
+#define RG_LPF4_06_MSK 0x00001fff
+#define RG_LPF4_06_I_MSK 0xffffe000
+#define RG_LPF4_06_SFT 0
+#define RG_LPF4_06_HI 12
+#define RG_LPF4_06_SZ 13
+#define RG_LPF4_07_MSK 0x00001fff
+#define RG_LPF4_07_I_MSK 0xffffe000
+#define RG_LPF4_07_SFT 0
+#define RG_LPF4_07_HI 12
+#define RG_LPF4_07_SZ 13
+#define RG_LPF4_08_MSK 0x00001fff
+#define RG_LPF4_08_I_MSK 0xffffe000
+#define RG_LPF4_08_SFT 0
+#define RG_LPF4_08_HI 12
+#define RG_LPF4_08_SZ 13
+#define RG_LPF4_09_MSK 0x00001fff
+#define RG_LPF4_09_I_MSK 0xffffe000
+#define RG_LPF4_09_SFT 0
+#define RG_LPF4_09_HI 12
+#define RG_LPF4_09_SZ 13
+#define RG_LPF4_10_MSK 0x00001fff
+#define RG_LPF4_10_I_MSK 0xffffe000
+#define RG_LPF4_10_SFT 0
+#define RG_LPF4_10_HI 12
+#define RG_LPF4_10_SZ 13
+#define RG_LPF4_11_MSK 0x00001fff
+#define RG_LPF4_11_I_MSK 0xffffe000
+#define RG_LPF4_11_SFT 0
+#define RG_LPF4_11_HI 12
+#define RG_LPF4_11_SZ 13
+#define RG_LPF4_12_MSK 0x00001fff
+#define RG_LPF4_12_I_MSK 0xffffe000
+#define RG_LPF4_12_SFT 0
+#define RG_LPF4_12_HI 12
+#define RG_LPF4_12_SZ 13
+#define RG_LPF4_13_MSK 0x00001fff
+#define RG_LPF4_13_I_MSK 0xffffe000
+#define RG_LPF4_13_SFT 0
+#define RG_LPF4_13_HI 12
+#define RG_LPF4_13_SZ 13
+#define RG_LPF4_14_MSK 0x00001fff
+#define RG_LPF4_14_I_MSK 0xffffe000
+#define RG_LPF4_14_SFT 0
+#define RG_LPF4_14_HI 12
+#define RG_LPF4_14_SZ 13
+#define RG_LPF4_15_MSK 0x00001fff
+#define RG_LPF4_15_I_MSK 0xffffe000
+#define RG_LPF4_15_SFT 0
+#define RG_LPF4_15_HI 12
+#define RG_LPF4_15_SZ 13
+#define RG_LPF4_16_MSK 0x00001fff
+#define RG_LPF4_16_I_MSK 0xffffe000
+#define RG_LPF4_16_SFT 0
+#define RG_LPF4_16_HI 12
+#define RG_LPF4_16_SZ 13
+#define RG_LPF4_17_MSK 0x00001fff
+#define RG_LPF4_17_I_MSK 0xffffe000
+#define RG_LPF4_17_SFT 0
+#define RG_LPF4_17_HI 12
+#define RG_LPF4_17_SZ 13
+#define RG_LPF4_18_MSK 0x00001fff
+#define RG_LPF4_18_I_MSK 0xffffe000
+#define RG_LPF4_18_SFT 0
+#define RG_LPF4_18_HI 12
+#define RG_LPF4_18_SZ 13
+#define RG_LPF4_19_MSK 0x00001fff
+#define RG_LPF4_19_I_MSK 0xffffe000
+#define RG_LPF4_19_SFT 0
+#define RG_LPF4_19_HI 12
+#define RG_LPF4_19_SZ 13
+#define RG_LPF4_20_MSK 0x00001fff
+#define RG_LPF4_20_I_MSK 0xffffe000
+#define RG_LPF4_20_SFT 0
+#define RG_LPF4_20_HI 12
+#define RG_LPF4_20_SZ 13
+#define RG_LPF4_21_MSK 0x00001fff
+#define RG_LPF4_21_I_MSK 0xffffe000
+#define RG_LPF4_21_SFT 0
+#define RG_LPF4_21_HI 12
+#define RG_LPF4_21_SZ 13
+#define RG_LPF4_22_MSK 0x00001fff
+#define RG_LPF4_22_I_MSK 0xffffe000
+#define RG_LPF4_22_SFT 0
+#define RG_LPF4_22_HI 12
+#define RG_LPF4_22_SZ 13
+#define RG_LPF4_23_MSK 0x00001fff
+#define RG_LPF4_23_I_MSK 0xffffe000
+#define RG_LPF4_23_SFT 0
+#define RG_LPF4_23_HI 12
+#define RG_LPF4_23_SZ 13
+#define RG_LPF4_24_MSK 0x00001fff
+#define RG_LPF4_24_I_MSK 0xffffe000
+#define RG_LPF4_24_SFT 0
+#define RG_LPF4_24_HI 12
+#define RG_LPF4_24_SZ 13
+#define RG_LPF4_25_MSK 0x00001fff
+#define RG_LPF4_25_I_MSK 0xffffe000
+#define RG_LPF4_25_SFT 0
+#define RG_LPF4_25_HI 12
+#define RG_LPF4_25_SZ 13
+#define RG_LPF4_26_MSK 0x00001fff
+#define RG_LPF4_26_I_MSK 0xffffe000
+#define RG_LPF4_26_SFT 0
+#define RG_LPF4_26_HI 12
+#define RG_LPF4_26_SZ 13
+#define RG_LPF4_27_MSK 0x00001fff
+#define RG_LPF4_27_I_MSK 0xffffe000
+#define RG_LPF4_27_SFT 0
+#define RG_LPF4_27_HI 12
+#define RG_LPF4_27_SZ 13
+#define RG_LPF4_28_MSK 0x00001fff
+#define RG_LPF4_28_I_MSK 0xffffe000
+#define RG_LPF4_28_SFT 0
+#define RG_LPF4_28_HI 12
+#define RG_LPF4_28_SZ 13
+#define RG_LPF4_29_MSK 0x00001fff
+#define RG_LPF4_29_I_MSK 0xffffe000
+#define RG_LPF4_29_SFT 0
+#define RG_LPF4_29_HI 12
+#define RG_LPF4_29_SZ 13
+#define RG_LPF4_30_MSK 0x00001fff
+#define RG_LPF4_30_I_MSK 0xffffe000
+#define RG_LPF4_30_SFT 0
+#define RG_LPF4_30_HI 12
+#define RG_LPF4_30_SZ 13
+#define RG_LPF4_31_MSK 0x00001fff
+#define RG_LPF4_31_I_MSK 0xffffe000
+#define RG_LPF4_31_SFT 0
+#define RG_LPF4_31_HI 12
+#define RG_LPF4_31_SZ 13
+#define RG_LPF4_32_MSK 0x00001fff
+#define RG_LPF4_32_I_MSK 0xffffe000
+#define RG_LPF4_32_SFT 0
+#define RG_LPF4_32_HI 12
+#define RG_LPF4_32_SZ 13
+#define RG_LPF4_33_MSK 0x00001fff
+#define RG_LPF4_33_I_MSK 0xffffe000
+#define RG_LPF4_33_SFT 0
+#define RG_LPF4_33_HI 12
+#define RG_LPF4_33_SZ 13
+#define RG_LPF4_34_MSK 0x00001fff
+#define RG_LPF4_34_I_MSK 0xffffe000
+#define RG_LPF4_34_SFT 0
+#define RG_LPF4_34_HI 12
+#define RG_LPF4_34_SZ 13
+#define RG_LPF4_35_MSK 0x00001fff
+#define RG_LPF4_35_I_MSK 0xffffe000
+#define RG_LPF4_35_SFT 0
+#define RG_LPF4_35_HI 12
+#define RG_LPF4_35_SZ 13
+#define RG_LPF4_36_MSK 0x00001fff
+#define RG_LPF4_36_I_MSK 0xffffe000
+#define RG_LPF4_36_SFT 0
+#define RG_LPF4_36_HI 12
+#define RG_LPF4_36_SZ 13
+#define RG_LPF4_37_MSK 0x00001fff
+#define RG_LPF4_37_I_MSK 0xffffe000
+#define RG_LPF4_37_SFT 0
+#define RG_LPF4_37_HI 12
+#define RG_LPF4_37_SZ 13
+#define RG_LPF4_38_MSK 0x00001fff
+#define RG_LPF4_38_I_MSK 0xffffe000
+#define RG_LPF4_38_SFT 0
+#define RG_LPF4_38_HI 12
+#define RG_LPF4_38_SZ 13
+#define RG_LPF4_39_MSK 0x00001fff
+#define RG_LPF4_39_I_MSK 0xffffe000
+#define RG_LPF4_39_SFT 0
+#define RG_LPF4_39_HI 12
+#define RG_LPF4_39_SZ 13
+#define RG_LPF4_40_MSK 0x00001fff
+#define RG_LPF4_40_I_MSK 0xffffe000
+#define RG_LPF4_40_SFT 0
+#define RG_LPF4_40_HI 12
+#define RG_LPF4_40_SZ 13
+#define RG_BP_SMB_MSK 0x00002000
+#define RG_BP_SMB_I_MSK 0xffffdfff
+#define RG_BP_SMB_SFT 13
+#define RG_BP_SMB_HI 13
+#define RG_BP_SMB_SZ 1
+#define RG_EN_SRVC_MSK 0x00004000
+#define RG_EN_SRVC_I_MSK 0xffffbfff
+#define RG_EN_SRVC_SFT 14
+#define RG_EN_SRVC_HI 14
+#define RG_EN_SRVC_SZ 1
+#define RG_DES_SPD_MSK 0x00030000
+#define RG_DES_SPD_I_MSK 0xfffcffff
+#define RG_DES_SPD_SFT 16
+#define RG_DES_SPD_HI 17
+#define RG_DES_SPD_SZ 2
+#define RG_BB_11B_RISE_TIME_MSK 0x000000ff
+#define RG_BB_11B_RISE_TIME_I_MSK 0xffffff00
+#define RG_BB_11B_RISE_TIME_SFT 0
+#define RG_BB_11B_RISE_TIME_HI 7
+#define RG_BB_11B_RISE_TIME_SZ 8
+#define RG_BB_11B_FALL_TIME_MSK 0x0000ff00
+#define RG_BB_11B_FALL_TIME_I_MSK 0xffff00ff
+#define RG_BB_11B_FALL_TIME_SFT 8
+#define RG_BB_11B_FALL_TIME_HI 15
+#define RG_BB_11B_FALL_TIME_SZ 8
+#define RG_WR_TX_EN_CNT_RST_N_MSK 0x00000001
+#define RG_WR_TX_EN_CNT_RST_N_I_MSK 0xfffffffe
+#define RG_WR_TX_EN_CNT_RST_N_SFT 0
+#define RG_WR_TX_EN_CNT_RST_N_HI 0
+#define RG_WR_TX_EN_CNT_RST_N_SZ 1
+#define RO_TX_EN_CNT_MSK 0x0000ffff
+#define RO_TX_EN_CNT_I_MSK 0xffff0000
+#define RO_TX_EN_CNT_SFT 0
+#define RO_TX_EN_CNT_HI 15
+#define RO_TX_EN_CNT_SZ 16
+#define RO_TX_CNT_MSK 0xffffffff
+#define RO_TX_CNT_I_MSK 0x00000000
+#define RO_TX_CNT_SFT 0
+#define RO_TX_CNT_HI 31
+#define RO_TX_CNT_SZ 32
+#define RG_POS_DES_11B_L_EXT_MSK 0x0000000f
+#define RG_POS_DES_11B_L_EXT_I_MSK 0xfffffff0
+#define RG_POS_DES_11B_L_EXT_SFT 0
+#define RG_POS_DES_11B_L_EXT_HI 3
+#define RG_POS_DES_11B_L_EXT_SZ 4
+#define RG_PRE_DES_11B_DLY_MSK 0x000000f0
+#define RG_PRE_DES_11B_DLY_I_MSK 0xffffff0f
+#define RG_PRE_DES_11B_DLY_SFT 4
+#define RG_PRE_DES_11B_DLY_HI 7
+#define RG_PRE_DES_11B_DLY_SZ 4
+#define RG_CNT_CCA_LMT_MSK 0x000f0000
+#define RG_CNT_CCA_LMT_I_MSK 0xfff0ffff
+#define RG_CNT_CCA_LMT_SFT 16
+#define RG_CNT_CCA_LMT_HI 19
+#define RG_CNT_CCA_LMT_SZ 4
+#define RG_BYPASS_DESCRAMBLER_MSK 0x20000000
+#define RG_BYPASS_DESCRAMBLER_I_MSK 0xdfffffff
+#define RG_BYPASS_DESCRAMBLER_SFT 29
+#define RG_BYPASS_DESCRAMBLER_HI 29
+#define RG_BYPASS_DESCRAMBLER_SZ 1
+#define RG_BYPASS_AGC_MSK 0x80000000
+#define RG_BYPASS_AGC_I_MSK 0x7fffffff
+#define RG_BYPASS_AGC_SFT 31
+#define RG_BYPASS_AGC_HI 31
+#define RG_BYPASS_AGC_SZ 1
+#define RG_CCA_BIT_CNT_LMT_RX_MSK 0x000000f0
+#define RG_CCA_BIT_CNT_LMT_RX_I_MSK 0xffffff0f
+#define RG_CCA_BIT_CNT_LMT_RX_SFT 4
+#define RG_CCA_BIT_CNT_LMT_RX_HI 7
+#define RG_CCA_BIT_CNT_LMT_RX_SZ 4
+#define RG_CCA_SCALE_BF_MSK 0x007f0000
+#define RG_CCA_SCALE_BF_I_MSK 0xff80ffff
+#define RG_CCA_SCALE_BF_SFT 16
+#define RG_CCA_SCALE_BF_HI 22
+#define RG_CCA_SCALE_BF_SZ 7
+#define RG_PEAK_IDX_CNT_SEL_MSK 0x30000000
+#define RG_PEAK_IDX_CNT_SEL_I_MSK 0xcfffffff
+#define RG_PEAK_IDX_CNT_SEL_SFT 28
+#define RG_PEAK_IDX_CNT_SEL_HI 29
+#define RG_PEAK_IDX_CNT_SEL_SZ 2
+#define RG_TR_KI_T2_MSK 0x00000007
+#define RG_TR_KI_T2_I_MSK 0xfffffff8
+#define RG_TR_KI_T2_SFT 0
+#define RG_TR_KI_T2_HI 2
+#define RG_TR_KI_T2_SZ 3
+#define RG_TR_KP_T2_MSK 0x00000070
+#define RG_TR_KP_T2_I_MSK 0xffffff8f
+#define RG_TR_KP_T2_SFT 4
+#define RG_TR_KP_T2_HI 6
+#define RG_TR_KP_T2_SZ 3
+#define RG_TR_KI_T1_MSK 0x00000700
+#define RG_TR_KI_T1_I_MSK 0xfffff8ff
+#define RG_TR_KI_T1_SFT 8
+#define RG_TR_KI_T1_HI 10
+#define RG_TR_KI_T1_SZ 3
+#define RG_TR_KP_T1_MSK 0x00007000
+#define RG_TR_KP_T1_I_MSK 0xffff8fff
+#define RG_TR_KP_T1_SFT 12
+#define RG_TR_KP_T1_HI 14
+#define RG_TR_KP_T1_SZ 3
+#define RG_CR_KI_T1_MSK 0x00070000
+#define RG_CR_KI_T1_I_MSK 0xfff8ffff
+#define RG_CR_KI_T1_SFT 16
+#define RG_CR_KI_T1_HI 18
+#define RG_CR_KI_T1_SZ 3
+#define RG_CR_KP_T1_MSK 0x00700000
+#define RG_CR_KP_T1_I_MSK 0xff8fffff
+#define RG_CR_KP_T1_SFT 20
+#define RG_CR_KP_T1_HI 22
+#define RG_CR_KP_T1_SZ 3
+#define RG_CHIP_CNT_SLICER_MSK 0x0000001f
+#define RG_CHIP_CNT_SLICER_I_MSK 0xffffffe0
+#define RG_CHIP_CNT_SLICER_SFT 0
+#define RG_CHIP_CNT_SLICER_HI 4
+#define RG_CHIP_CNT_SLICER_SZ 5
+#define RG_CE_T4_CNT_LMT_MSK 0x0000ff00
+#define RG_CE_T4_CNT_LMT_I_MSK 0xffff00ff
+#define RG_CE_T4_CNT_LMT_SFT 8
+#define RG_CE_T4_CNT_LMT_HI 15
+#define RG_CE_T4_CNT_LMT_SZ 8
+#define RG_CE_T3_CNT_LMT_MSK 0x00ff0000
+#define RG_CE_T3_CNT_LMT_I_MSK 0xff00ffff
+#define RG_CE_T3_CNT_LMT_SFT 16
+#define RG_CE_T3_CNT_LMT_HI 23
+#define RG_CE_T3_CNT_LMT_SZ 8
+#define RG_CE_T2_CNT_LMT_MSK 0xff000000
+#define RG_CE_T2_CNT_LMT_I_MSK 0x00ffffff
+#define RG_CE_T2_CNT_LMT_SFT 24
+#define RG_CE_T2_CNT_LMT_HI 31
+#define RG_CE_T2_CNT_LMT_SZ 8
+#define RG_CE_MU_T1_MSK 0x00000007
+#define RG_CE_MU_T1_I_MSK 0xfffffff8
+#define RG_CE_MU_T1_SFT 0
+#define RG_CE_MU_T1_HI 2
+#define RG_CE_MU_T1_SZ 3
+#define RG_CE_DLY_SEL_MSK 0x003f0000
+#define RG_CE_DLY_SEL_I_MSK 0xffc0ffff
+#define RG_CE_DLY_SEL_SFT 16
+#define RG_CE_DLY_SEL_HI 21
+#define RG_CE_DLY_SEL_SZ 6
+#define RG_CE_MU_T8_MSK 0x00000007
+#define RG_CE_MU_T8_I_MSK 0xfffffff8
+#define RG_CE_MU_T8_SFT 0
+#define RG_CE_MU_T8_HI 2
+#define RG_CE_MU_T8_SZ 3
+#define RG_CE_MU_T7_MSK 0x00000070
+#define RG_CE_MU_T7_I_MSK 0xffffff8f
+#define RG_CE_MU_T7_SFT 4
+#define RG_CE_MU_T7_HI 6
+#define RG_CE_MU_T7_SZ 3
+#define RG_CE_MU_T6_MSK 0x00000700
+#define RG_CE_MU_T6_I_MSK 0xfffff8ff
+#define RG_CE_MU_T6_SFT 8
+#define RG_CE_MU_T6_HI 10
+#define RG_CE_MU_T6_SZ 3
+#define RG_CE_MU_T5_MSK 0x00007000
+#define RG_CE_MU_T5_I_MSK 0xffff8fff
+#define RG_CE_MU_T5_SFT 12
+#define RG_CE_MU_T5_HI 14
+#define RG_CE_MU_T5_SZ 3
+#define RG_CE_MU_T4_MSK 0x00070000
+#define RG_CE_MU_T4_I_MSK 0xfff8ffff
+#define RG_CE_MU_T4_SFT 16
+#define RG_CE_MU_T4_HI 18
+#define RG_CE_MU_T4_SZ 3
+#define RG_CE_MU_T3_MSK 0x00700000
+#define RG_CE_MU_T3_I_MSK 0xff8fffff
+#define RG_CE_MU_T3_SFT 20
+#define RG_CE_MU_T3_HI 22
+#define RG_CE_MU_T3_SZ 3
+#define RG_CE_MU_T2_MSK 0x07000000
+#define RG_CE_MU_T2_I_MSK 0xf8ffffff
+#define RG_CE_MU_T2_SFT 24
+#define RG_CE_MU_T2_HI 26
+#define RG_CE_MU_T2_SZ 3
+#define RG_EQ_MU_FB_T2_MSK 0x0000000f
+#define RG_EQ_MU_FB_T2_I_MSK 0xfffffff0
+#define RG_EQ_MU_FB_T2_SFT 0
+#define RG_EQ_MU_FB_T2_HI 3
+#define RG_EQ_MU_FB_T2_SZ 4
+#define RG_EQ_MU_FF_T2_MSK 0x000000f0
+#define RG_EQ_MU_FF_T2_I_MSK 0xffffff0f
+#define RG_EQ_MU_FF_T2_SFT 4
+#define RG_EQ_MU_FF_T2_HI 7
+#define RG_EQ_MU_FF_T2_SZ 4
+#define RG_EQ_MU_FB_T1_MSK 0x000f0000
+#define RG_EQ_MU_FB_T1_I_MSK 0xfff0ffff
+#define RG_EQ_MU_FB_T1_SFT 16
+#define RG_EQ_MU_FB_T1_HI 19
+#define RG_EQ_MU_FB_T1_SZ 4
+#define RG_EQ_MU_FF_T1_MSK 0x00f00000
+#define RG_EQ_MU_FF_T1_I_MSK 0xff0fffff
+#define RG_EQ_MU_FF_T1_SFT 20
+#define RG_EQ_MU_FF_T1_HI 23
+#define RG_EQ_MU_FF_T1_SZ 4
+#define RG_EQ_MU_FB_T4_MSK 0x0000000f
+#define RG_EQ_MU_FB_T4_I_MSK 0xfffffff0
+#define RG_EQ_MU_FB_T4_SFT 0
+#define RG_EQ_MU_FB_T4_HI 3
+#define RG_EQ_MU_FB_T4_SZ 4
+#define RG_EQ_MU_FF_T4_MSK 0x000000f0
+#define RG_EQ_MU_FF_T4_I_MSK 0xffffff0f
+#define RG_EQ_MU_FF_T4_SFT 4
+#define RG_EQ_MU_FF_T4_HI 7
+#define RG_EQ_MU_FF_T4_SZ 4
+#define RG_EQ_MU_FB_T3_MSK 0x000f0000
+#define RG_EQ_MU_FB_T3_I_MSK 0xfff0ffff
+#define RG_EQ_MU_FB_T3_SFT 16
+#define RG_EQ_MU_FB_T3_HI 19
+#define RG_EQ_MU_FB_T3_SZ 4
+#define RG_EQ_MU_FF_T3_MSK 0x00f00000
+#define RG_EQ_MU_FF_T3_I_MSK 0xff0fffff
+#define RG_EQ_MU_FF_T3_SFT 20
+#define RG_EQ_MU_FF_T3_HI 23
+#define RG_EQ_MU_FF_T3_SZ 4
+#define RG_EQ_KI_T2_MSK 0x00000700
+#define RG_EQ_KI_T2_I_MSK 0xfffff8ff
+#define RG_EQ_KI_T2_SFT 8
+#define RG_EQ_KI_T2_HI 10
+#define RG_EQ_KI_T2_SZ 3
+#define RG_EQ_KP_T2_MSK 0x00007000
+#define RG_EQ_KP_T2_I_MSK 0xffff8fff
+#define RG_EQ_KP_T2_SFT 12
+#define RG_EQ_KP_T2_HI 14
+#define RG_EQ_KP_T2_SZ 3
+#define RG_EQ_KI_T1_MSK 0x00070000
+#define RG_EQ_KI_T1_I_MSK 0xfff8ffff
+#define RG_EQ_KI_T1_SFT 16
+#define RG_EQ_KI_T1_HI 18
+#define RG_EQ_KI_T1_SZ 3
+#define RG_EQ_KP_T1_MSK 0x00700000
+#define RG_EQ_KP_T1_I_MSK 0xff8fffff
+#define RG_EQ_KP_T1_SFT 20
+#define RG_EQ_KP_T1_HI 22
+#define RG_EQ_KP_T1_SZ 3
+#define RG_TR_LPF_RATE_MSK 0x003fffff
+#define RG_TR_LPF_RATE_I_MSK 0xffc00000
+#define RG_TR_LPF_RATE_SFT 0
+#define RG_TR_LPF_RATE_HI 21
+#define RG_TR_LPF_RATE_SZ 22
+#define RG_CE_BIT_CNT_LMT_MSK 0x0000007f
+#define RG_CE_BIT_CNT_LMT_I_MSK 0xffffff80
+#define RG_CE_BIT_CNT_LMT_SFT 0
+#define RG_CE_BIT_CNT_LMT_HI 6
+#define RG_CE_BIT_CNT_LMT_SZ 7
+#define RG_CE_CH_MAIN_SET_MSK 0x00000080
+#define RG_CE_CH_MAIN_SET_I_MSK 0xffffff7f
+#define RG_CE_CH_MAIN_SET_SFT 7
+#define RG_CE_CH_MAIN_SET_HI 7
+#define RG_CE_CH_MAIN_SET_SZ 1
+#define RG_TC_BIT_CNT_LMT_MSK 0x00007f00
+#define RG_TC_BIT_CNT_LMT_I_MSK 0xffff80ff
+#define RG_TC_BIT_CNT_LMT_SFT 8
+#define RG_TC_BIT_CNT_LMT_HI 14
+#define RG_TC_BIT_CNT_LMT_SZ 7
+#define RG_CR_BIT_CNT_LMT_MSK 0x007f0000
+#define RG_CR_BIT_CNT_LMT_I_MSK 0xff80ffff
+#define RG_CR_BIT_CNT_LMT_SFT 16
+#define RG_CR_BIT_CNT_LMT_HI 22
+#define RG_CR_BIT_CNT_LMT_SZ 7
+#define RG_TR_BIT_CNT_LMT_MSK 0x7f000000
+#define RG_TR_BIT_CNT_LMT_I_MSK 0x80ffffff
+#define RG_TR_BIT_CNT_LMT_SFT 24
+#define RG_TR_BIT_CNT_LMT_HI 30
+#define RG_TR_BIT_CNT_LMT_SZ 7
+#define RG_EQ_MAIN_TAP_MAN_MSK 0x00000001
+#define RG_EQ_MAIN_TAP_MAN_I_MSK 0xfffffffe
+#define RG_EQ_MAIN_TAP_MAN_SFT 0
+#define RG_EQ_MAIN_TAP_MAN_HI 0
+#define RG_EQ_MAIN_TAP_MAN_SZ 1
+#define RG_EQ_MAIN_TAP_COEF_MSK 0x07ff0000
+#define RG_EQ_MAIN_TAP_COEF_I_MSK 0xf800ffff
+#define RG_EQ_MAIN_TAP_COEF_SFT 16
+#define RG_EQ_MAIN_TAP_COEF_HI 26
+#define RG_EQ_MAIN_TAP_COEF_SZ 11
+#define RG_PWRON_DLY_TH_11B_MSK 0x000000ff
+#define RG_PWRON_DLY_TH_11B_I_MSK 0xffffff00
+#define RG_PWRON_DLY_TH_11B_SFT 0
+#define RG_PWRON_DLY_TH_11B_HI 7
+#define RG_PWRON_DLY_TH_11B_SZ 8
+#define RG_SFD_BIT_CNT_LMT_MSK 0x00ff0000
+#define RG_SFD_BIT_CNT_LMT_I_MSK 0xff00ffff
+#define RG_SFD_BIT_CNT_LMT_SFT 16
+#define RG_SFD_BIT_CNT_LMT_HI 23
+#define RG_SFD_BIT_CNT_LMT_SZ 8
+#define RG_CCA_PWR_TH_RX_MSK 0x00007fff
+#define RG_CCA_PWR_TH_RX_I_MSK 0xffff8000
+#define RG_CCA_PWR_TH_RX_SFT 0
+#define RG_CCA_PWR_TH_RX_HI 14
+#define RG_CCA_PWR_TH_RX_SZ 15
+#define RG_CCA_PWR_CNT_TH_MSK 0x001f0000
+#define RG_CCA_PWR_CNT_TH_I_MSK 0xffe0ffff
+#define RG_CCA_PWR_CNT_TH_SFT 16
+#define RG_CCA_PWR_CNT_TH_HI 20
+#define RG_CCA_PWR_CNT_TH_SZ 5
+#define B_FREQ_OS_MSK 0x000007ff
+#define B_FREQ_OS_I_MSK 0xfffff800
+#define B_FREQ_OS_SFT 0
+#define B_FREQ_OS_HI 10
+#define B_FREQ_OS_SZ 11
+#define B_SNR_MSK 0x0000007f
+#define B_SNR_I_MSK 0xffffff80
+#define B_SNR_SFT 0
+#define B_SNR_HI 6
+#define B_SNR_SZ 7
+#define B_RCPI_MSK 0x007f0000
+#define B_RCPI_I_MSK 0xff80ffff
+#define B_RCPI_SFT 16
+#define B_RCPI_HI 22
+#define B_RCPI_SZ 7
+#define CRC_CNT_MSK 0x0000ffff
+#define CRC_CNT_I_MSK 0xffff0000
+#define CRC_CNT_SFT 0
+#define CRC_CNT_HI 15
+#define CRC_CNT_SZ 16
+#define SFD_CNT_MSK 0xffff0000
+#define SFD_CNT_I_MSK 0x0000ffff
+#define SFD_CNT_SFT 16
+#define SFD_CNT_HI 31
+#define SFD_CNT_SZ 16
+#define B_PACKET_ERR_CNT_MSK 0x0000ffff
+#define B_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define B_PACKET_ERR_CNT_SFT 0
+#define B_PACKET_ERR_CNT_HI 15
+#define B_PACKET_ERR_CNT_SZ 16
+#define PACKET_ERR_MSK 0x00010000
+#define PACKET_ERR_I_MSK 0xfffeffff
+#define PACKET_ERR_SFT 16
+#define PACKET_ERR_HI 16
+#define PACKET_ERR_SZ 1
+#define B_PACKET_CNT_MSK 0x0000ffff
+#define B_PACKET_CNT_I_MSK 0xffff0000
+#define B_PACKET_CNT_SFT 0
+#define B_PACKET_CNT_HI 15
+#define B_PACKET_CNT_SZ 16
+#define B_CCA_CNT_MSK 0xffff0000
+#define B_CCA_CNT_I_MSK 0x0000ffff
+#define B_CCA_CNT_SFT 16
+#define B_CCA_CNT_HI 31
+#define B_CCA_CNT_SZ 16
+#define B_LENGTH_FIELD_MSK 0x0000ffff
+#define B_LENGTH_FIELD_I_MSK 0xffff0000
+#define B_LENGTH_FIELD_SFT 0
+#define B_LENGTH_FIELD_HI 15
+#define B_LENGTH_FIELD_SZ 16
+#define SFD_FIELD_MSK 0xffff0000
+#define SFD_FIELD_I_MSK 0x0000ffff
+#define SFD_FIELD_SFT 16
+#define SFD_FIELD_HI 31
+#define SFD_FIELD_SZ 16
+#define SIGNAL_FIELD_MSK 0x000000ff
+#define SIGNAL_FIELD_I_MSK 0xffffff00
+#define SIGNAL_FIELD_SFT 0
+#define SIGNAL_FIELD_HI 7
+#define SIGNAL_FIELD_SZ 8
+#define B_SERVICE_FIELD_MSK 0x0000ff00
+#define B_SERVICE_FIELD_I_MSK 0xffff00ff
+#define B_SERVICE_FIELD_SFT 8
+#define B_SERVICE_FIELD_HI 15
+#define B_SERVICE_FIELD_SZ 8
+#define CRC_CORRECT_MSK 0x00010000
+#define CRC_CORRECT_I_MSK 0xfffeffff
+#define CRC_CORRECT_SFT 16
+#define CRC_CORRECT_HI 16
+#define CRC_CORRECT_SZ 1
+#define DEBUG_SEL_MSK 0x0000000f
+#define DEBUG_SEL_I_MSK 0xfffffff0
+#define DEBUG_SEL_SFT 0
+#define DEBUG_SEL_HI 3
+#define DEBUG_SEL_SZ 4
+#define RG_PACKET_STAT_EN_11B_MSK 0x00100000
+#define RG_PACKET_STAT_EN_11B_I_MSK 0xffefffff
+#define RG_PACKET_STAT_EN_11B_SFT 20
+#define RG_PACKET_STAT_EN_11B_HI 20
+#define RG_PACKET_STAT_EN_11B_SZ 1
+#define RG_BIT_REVERSE_MSK 0x00200000
+#define RG_BIT_REVERSE_I_MSK 0xffdfffff
+#define RG_BIT_REVERSE_SFT 21
+#define RG_BIT_REVERSE_HI 21
+#define RG_BIT_REVERSE_SZ 1
+#define RX_PHY_11B_SOFT_RST_N_MSK 0x00000001
+#define RX_PHY_11B_SOFT_RST_N_I_MSK 0xfffffffe
+#define RX_PHY_11B_SOFT_RST_N_SFT 0
+#define RX_PHY_11B_SOFT_RST_N_HI 0
+#define RX_PHY_11B_SOFT_RST_N_SZ 1
+#define RG_CE_BYPASS_TAP_MSK 0x000000f0
+#define RG_CE_BYPASS_TAP_I_MSK 0xffffff0f
+#define RG_CE_BYPASS_TAP_SFT 4
+#define RG_CE_BYPASS_TAP_HI 7
+#define RG_CE_BYPASS_TAP_SZ 4
+#define RG_EQ_BYPASS_FBW_TAP_MSK 0x00000f00
+#define RG_EQ_BYPASS_FBW_TAP_I_MSK 0xfffff0ff
+#define RG_EQ_BYPASS_FBW_TAP_SFT 8
+#define RG_EQ_BYPASS_FBW_TAP_HI 11
+#define RG_EQ_BYPASS_FBW_TAP_SZ 4
+#define RG_BB_11GN_RISE_TIME_MSK 0x000000ff
+#define RG_BB_11GN_RISE_TIME_I_MSK 0xffffff00
+#define RG_BB_11GN_RISE_TIME_SFT 0
+#define RG_BB_11GN_RISE_TIME_HI 7
+#define RG_BB_11GN_RISE_TIME_SZ 8
+#define RG_BB_11GN_FALL_TIME_MSK 0x0000ff00
+#define RG_BB_11GN_FALL_TIME_I_MSK 0xffff00ff
+#define RG_BB_11GN_FALL_TIME_SFT 8
+#define RG_BB_11GN_FALL_TIME_HI 15
+#define RG_BB_11GN_FALL_TIME_SZ 8
+#define RG_HTCARR52_FFT_SCALE_MSK 0x000003ff
+#define RG_HTCARR52_FFT_SCALE_I_MSK 0xfffffc00
+#define RG_HTCARR52_FFT_SCALE_SFT 0
+#define RG_HTCARR52_FFT_SCALE_HI 9
+#define RG_HTCARR52_FFT_SCALE_SZ 10
+#define RG_HTCARR56_FFT_SCALE_MSK 0x003ff000
+#define RG_HTCARR56_FFT_SCALE_I_MSK 0xffc00fff
+#define RG_HTCARR56_FFT_SCALE_SFT 12
+#define RG_HTCARR56_FFT_SCALE_HI 21
+#define RG_HTCARR56_FFT_SCALE_SZ 10
+#define RG_PACKET_STAT_EN_MSK 0x00800000
+#define RG_PACKET_STAT_EN_I_MSK 0xff7fffff
+#define RG_PACKET_STAT_EN_SFT 23
+#define RG_PACKET_STAT_EN_HI 23
+#define RG_PACKET_STAT_EN_SZ 1
+#define RG_SMB_DEF_MSK 0x7f000000
+#define RG_SMB_DEF_I_MSK 0x80ffffff
+#define RG_SMB_DEF_SFT 24
+#define RG_SMB_DEF_HI 30
+#define RG_SMB_DEF_SZ 7
+#define RG_CONTINUOUS_DATA_11GN_MSK 0x80000000
+#define RG_CONTINUOUS_DATA_11GN_I_MSK 0x7fffffff
+#define RG_CONTINUOUS_DATA_11GN_SFT 31
+#define RG_CONTINUOUS_DATA_11GN_HI 31
+#define RG_CONTINUOUS_DATA_11GN_SZ 1
+#define RO_TX_CNT_R_MSK 0xffffffff
+#define RO_TX_CNT_R_I_MSK 0x00000000
+#define RO_TX_CNT_R_SFT 0
+#define RO_TX_CNT_R_HI 31
+#define RO_TX_CNT_R_SZ 32
+#define RO_PACKET_ERR_CNT_MSK 0x0000ffff
+#define RO_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define RO_PACKET_ERR_CNT_SFT 0
+#define RO_PACKET_ERR_CNT_HI 15
+#define RO_PACKET_ERR_CNT_SZ 16
+#define RG_POS_DES_11GN_L_EXT_MSK 0x0000000f
+#define RG_POS_DES_11GN_L_EXT_I_MSK 0xfffffff0
+#define RG_POS_DES_11GN_L_EXT_SFT 0
+#define RG_POS_DES_11GN_L_EXT_HI 3
+#define RG_POS_DES_11GN_L_EXT_SZ 4
+#define RG_PRE_DES_11GN_DLY_MSK 0x000000f0
+#define RG_PRE_DES_11GN_DLY_I_MSK 0xffffff0f
+#define RG_PRE_DES_11GN_DLY_SFT 4
+#define RG_PRE_DES_11GN_DLY_HI 7
+#define RG_PRE_DES_11GN_DLY_SZ 4
+#define RG_TR_LPF_KI_G_T1_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_T1_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_T1_SFT 0
+#define RG_TR_LPF_KI_G_T1_HI 3
+#define RG_TR_LPF_KI_G_T1_SZ 4
+#define RG_TR_LPF_KP_G_T1_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_T1_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_T1_SFT 4
+#define RG_TR_LPF_KP_G_T1_HI 7
+#define RG_TR_LPF_KP_G_T1_SZ 4
+#define RG_TR_CNT_T1_MSK 0x0000ff00
+#define RG_TR_CNT_T1_I_MSK 0xffff00ff
+#define RG_TR_CNT_T1_SFT 8
+#define RG_TR_CNT_T1_HI 15
+#define RG_TR_CNT_T1_SZ 8
+#define RG_TR_LPF_KI_G_T0_MSK 0x000f0000
+#define RG_TR_LPF_KI_G_T0_I_MSK 0xfff0ffff
+#define RG_TR_LPF_KI_G_T0_SFT 16
+#define RG_TR_LPF_KI_G_T0_HI 19
+#define RG_TR_LPF_KI_G_T0_SZ 4
+#define RG_TR_LPF_KP_G_T0_MSK 0x00f00000
+#define RG_TR_LPF_KP_G_T0_I_MSK 0xff0fffff
+#define RG_TR_LPF_KP_G_T0_SFT 20
+#define RG_TR_LPF_KP_G_T0_HI 23
+#define RG_TR_LPF_KP_G_T0_SZ 4
+#define RG_TR_CNT_T0_MSK 0xff000000
+#define RG_TR_CNT_T0_I_MSK 0x00ffffff
+#define RG_TR_CNT_T0_SFT 24
+#define RG_TR_CNT_T0_HI 31
+#define RG_TR_CNT_T0_SZ 8
+#define RG_TR_LPF_KI_G_T2_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_T2_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_T2_SFT 0
+#define RG_TR_LPF_KI_G_T2_HI 3
+#define RG_TR_LPF_KI_G_T2_SZ 4
+#define RG_TR_LPF_KP_G_T2_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_T2_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_T2_SFT 4
+#define RG_TR_LPF_KP_G_T2_HI 7
+#define RG_TR_LPF_KP_G_T2_SZ 4
+#define RG_TR_CNT_T2_MSK 0x0000ff00
+#define RG_TR_CNT_T2_I_MSK 0xffff00ff
+#define RG_TR_CNT_T2_SFT 8
+#define RG_TR_CNT_T2_HI 15
+#define RG_TR_CNT_T2_SZ 8
+#define RG_TR_LPF_KI_G_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_SFT 0
+#define RG_TR_LPF_KI_G_HI 3
+#define RG_TR_LPF_KI_G_SZ 4
+#define RG_TR_LPF_KP_G_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_SFT 4
+#define RG_TR_LPF_KP_G_HI 7
+#define RG_TR_LPF_KP_G_SZ 4
+#define RG_TR_LPF_RATE_G_MSK 0x3fffff00
+#define RG_TR_LPF_RATE_G_I_MSK 0xc00000ff
+#define RG_TR_LPF_RATE_G_SFT 8
+#define RG_TR_LPF_RATE_G_HI 29
+#define RG_TR_LPF_RATE_G_SZ 22
+#define RG_CR_LPF_KI_G_MSK 0x00000007
+#define RG_CR_LPF_KI_G_I_MSK 0xfffffff8
+#define RG_CR_LPF_KI_G_SFT 0
+#define RG_CR_LPF_KI_G_HI 2
+#define RG_CR_LPF_KI_G_SZ 3
+#define RG_SYM_BOUND_CNT_MSK 0x00007f00
+#define RG_SYM_BOUND_CNT_I_MSK 0xffff80ff
+#define RG_SYM_BOUND_CNT_SFT 8
+#define RG_SYM_BOUND_CNT_HI 14
+#define RG_SYM_BOUND_CNT_SZ 7
+#define RG_XSCOR32_RATIO_MSK 0x007f0000
+#define RG_XSCOR32_RATIO_I_MSK 0xff80ffff
+#define RG_XSCOR32_RATIO_SFT 16
+#define RG_XSCOR32_RATIO_HI 22
+#define RG_XSCOR32_RATIO_SZ 7
+#define RG_ATCOR64_CNT_LMT_MSK 0x7f000000
+#define RG_ATCOR64_CNT_LMT_I_MSK 0x80ffffff
+#define RG_ATCOR64_CNT_LMT_SFT 24
+#define RG_ATCOR64_CNT_LMT_HI 30
+#define RG_ATCOR64_CNT_LMT_SZ 7
+#define RG_ATCOR16_CNT_LMT2_MSK 0x00007f00
+#define RG_ATCOR16_CNT_LMT2_I_MSK 0xffff80ff
+#define RG_ATCOR16_CNT_LMT2_SFT 8
+#define RG_ATCOR16_CNT_LMT2_HI 14
+#define RG_ATCOR16_CNT_LMT2_SZ 7
+#define RG_ATCOR16_CNT_LMT1_MSK 0x007f0000
+#define RG_ATCOR16_CNT_LMT1_I_MSK 0xff80ffff
+#define RG_ATCOR16_CNT_LMT1_SFT 16
+#define RG_ATCOR16_CNT_LMT1_HI 22
+#define RG_ATCOR16_CNT_LMT1_SZ 7
+#define RG_ATCOR16_RATIO_SB_MSK 0x7f000000
+#define RG_ATCOR16_RATIO_SB_I_MSK 0x80ffffff
+#define RG_ATCOR16_RATIO_SB_SFT 24
+#define RG_ATCOR16_RATIO_SB_HI 30
+#define RG_ATCOR16_RATIO_SB_SZ 7
+#define RG_XSCOR64_CNT_LMT2_MSK 0x007f0000
+#define RG_XSCOR64_CNT_LMT2_I_MSK 0xff80ffff
+#define RG_XSCOR64_CNT_LMT2_SFT 16
+#define RG_XSCOR64_CNT_LMT2_HI 22
+#define RG_XSCOR64_CNT_LMT2_SZ 7
+#define RG_XSCOR64_CNT_LMT1_MSK 0x7f000000
+#define RG_XSCOR64_CNT_LMT1_I_MSK 0x80ffffff
+#define RG_XSCOR64_CNT_LMT1_SFT 24
+#define RG_XSCOR64_CNT_LMT1_HI 30
+#define RG_XSCOR64_CNT_LMT1_SZ 7
+#define RG_RX_FFT_SCALE_MSK 0x000003ff
+#define RG_RX_FFT_SCALE_I_MSK 0xfffffc00
+#define RG_RX_FFT_SCALE_SFT 0
+#define RG_RX_FFT_SCALE_HI 9
+#define RG_RX_FFT_SCALE_SZ 10
+#define RG_VITERBI_AB_SWAP_MSK 0x00010000
+#define RG_VITERBI_AB_SWAP_I_MSK 0xfffeffff
+#define RG_VITERBI_AB_SWAP_SFT 16
+#define RG_VITERBI_AB_SWAP_HI 16
+#define RG_VITERBI_AB_SWAP_SZ 1
+#define RG_ATCOR16_CNT_TH_MSK 0x0f000000
+#define RG_ATCOR16_CNT_TH_I_MSK 0xf0ffffff
+#define RG_ATCOR16_CNT_TH_SFT 24
+#define RG_ATCOR16_CNT_TH_HI 27
+#define RG_ATCOR16_CNT_TH_SZ 4
+#define RG_NORMSQUARE_LOW_SNR_7_MSK 0x000000ff
+#define RG_NORMSQUARE_LOW_SNR_7_I_MSK 0xffffff00
+#define RG_NORMSQUARE_LOW_SNR_7_SFT 0
+#define RG_NORMSQUARE_LOW_SNR_7_HI 7
+#define RG_NORMSQUARE_LOW_SNR_7_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_6_MSK 0x0000ff00
+#define RG_NORMSQUARE_LOW_SNR_6_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_LOW_SNR_6_SFT 8
+#define RG_NORMSQUARE_LOW_SNR_6_HI 15
+#define RG_NORMSQUARE_LOW_SNR_6_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_5_MSK 0x00ff0000
+#define RG_NORMSQUARE_LOW_SNR_5_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_LOW_SNR_5_SFT 16
+#define RG_NORMSQUARE_LOW_SNR_5_HI 23
+#define RG_NORMSQUARE_LOW_SNR_5_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_4_MSK 0xff000000
+#define RG_NORMSQUARE_LOW_SNR_4_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_LOW_SNR_4_SFT 24
+#define RG_NORMSQUARE_LOW_SNR_4_HI 31
+#define RG_NORMSQUARE_LOW_SNR_4_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_8_MSK 0xff000000
+#define RG_NORMSQUARE_LOW_SNR_8_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_LOW_SNR_8_SFT 24
+#define RG_NORMSQUARE_LOW_SNR_8_HI 31
+#define RG_NORMSQUARE_LOW_SNR_8_SZ 8
+#define RG_NORMSQUARE_SNR_3_MSK 0x000000ff
+#define RG_NORMSQUARE_SNR_3_I_MSK 0xffffff00
+#define RG_NORMSQUARE_SNR_3_SFT 0
+#define RG_NORMSQUARE_SNR_3_HI 7
+#define RG_NORMSQUARE_SNR_3_SZ 8
+#define RG_NORMSQUARE_SNR_2_MSK 0x0000ff00
+#define RG_NORMSQUARE_SNR_2_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_SNR_2_SFT 8
+#define RG_NORMSQUARE_SNR_2_HI 15
+#define RG_NORMSQUARE_SNR_2_SZ 8
+#define RG_NORMSQUARE_SNR_1_MSK 0x00ff0000
+#define RG_NORMSQUARE_SNR_1_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_SNR_1_SFT 16
+#define RG_NORMSQUARE_SNR_1_HI 23
+#define RG_NORMSQUARE_SNR_1_SZ 8
+#define RG_NORMSQUARE_SNR_0_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_0_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_0_SFT 24
+#define RG_NORMSQUARE_SNR_0_HI 31
+#define RG_NORMSQUARE_SNR_0_SZ 8
+#define RG_NORMSQUARE_SNR_7_MSK 0x000000ff
+#define RG_NORMSQUARE_SNR_7_I_MSK 0xffffff00
+#define RG_NORMSQUARE_SNR_7_SFT 0
+#define RG_NORMSQUARE_SNR_7_HI 7
+#define RG_NORMSQUARE_SNR_7_SZ 8
+#define RG_NORMSQUARE_SNR_6_MSK 0x0000ff00
+#define RG_NORMSQUARE_SNR_6_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_SNR_6_SFT 8
+#define RG_NORMSQUARE_SNR_6_HI 15
+#define RG_NORMSQUARE_SNR_6_SZ 8
+#define RG_NORMSQUARE_SNR_5_MSK 0x00ff0000
+#define RG_NORMSQUARE_SNR_5_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_SNR_5_SFT 16
+#define RG_NORMSQUARE_SNR_5_HI 23
+#define RG_NORMSQUARE_SNR_5_SZ 8
+#define RG_NORMSQUARE_SNR_4_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_4_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_4_SFT 24
+#define RG_NORMSQUARE_SNR_4_HI 31
+#define RG_NORMSQUARE_SNR_4_SZ 8
+#define RG_NORMSQUARE_SNR_8_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_8_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_8_SFT 24
+#define RG_NORMSQUARE_SNR_8_HI 31
+#define RG_NORMSQUARE_SNR_8_SZ 8
+#define RG_SNR_TH_64QAM_MSK 0x0000007f
+#define RG_SNR_TH_64QAM_I_MSK 0xffffff80
+#define RG_SNR_TH_64QAM_SFT 0
+#define RG_SNR_TH_64QAM_HI 6
+#define RG_SNR_TH_64QAM_SZ 7
+#define RG_SNR_TH_16QAM_MSK 0x00007f00
+#define RG_SNR_TH_16QAM_I_MSK 0xffff80ff
+#define RG_SNR_TH_16QAM_SFT 8
+#define RG_SNR_TH_16QAM_HI 14
+#define RG_SNR_TH_16QAM_SZ 7
+#define RG_ATCOR16_CNT_PLUS_LMT2_MSK 0x0000007f
+#define RG_ATCOR16_CNT_PLUS_LMT2_I_MSK 0xffffff80
+#define RG_ATCOR16_CNT_PLUS_LMT2_SFT 0
+#define RG_ATCOR16_CNT_PLUS_LMT2_HI 6
+#define RG_ATCOR16_CNT_PLUS_LMT2_SZ 7
+#define RG_ATCOR16_CNT_PLUS_LMT1_MSK 0x00007f00
+#define RG_ATCOR16_CNT_PLUS_LMT1_I_MSK 0xffff80ff
+#define RG_ATCOR16_CNT_PLUS_LMT1_SFT 8
+#define RG_ATCOR16_CNT_PLUS_LMT1_HI 14
+#define RG_ATCOR16_CNT_PLUS_LMT1_SZ 7
+#define RG_SYM_BOUND_METHOD_MSK 0x00030000
+#define RG_SYM_BOUND_METHOD_I_MSK 0xfffcffff
+#define RG_SYM_BOUND_METHOD_SFT 16
+#define RG_SYM_BOUND_METHOD_HI 17
+#define RG_SYM_BOUND_METHOD_SZ 2
+#define RG_PWRON_DLY_TH_11GN_MSK 0x000000ff
+#define RG_PWRON_DLY_TH_11GN_I_MSK 0xffffff00
+#define RG_PWRON_DLY_TH_11GN_SFT 0
+#define RG_PWRON_DLY_TH_11GN_HI 7
+#define RG_PWRON_DLY_TH_11GN_SZ 8
+#define RG_SB_START_CNT_MSK 0x00007f00
+#define RG_SB_START_CNT_I_MSK 0xffff80ff
+#define RG_SB_START_CNT_SFT 8
+#define RG_SB_START_CNT_HI 14
+#define RG_SB_START_CNT_SZ 7
+#define RG_POW16_CNT_TH_MSK 0x000000f0
+#define RG_POW16_CNT_TH_I_MSK 0xffffff0f
+#define RG_POW16_CNT_TH_SFT 4
+#define RG_POW16_CNT_TH_HI 7
+#define RG_POW16_CNT_TH_SZ 4
+#define RG_POW16_SHORT_CNT_LMT_MSK 0x00000700
+#define RG_POW16_SHORT_CNT_LMT_I_MSK 0xfffff8ff
+#define RG_POW16_SHORT_CNT_LMT_SFT 8
+#define RG_POW16_SHORT_CNT_LMT_HI 10
+#define RG_POW16_SHORT_CNT_LMT_SZ 3
+#define RG_POW16_TH_L_MSK 0x7f000000
+#define RG_POW16_TH_L_I_MSK 0x80ffffff
+#define RG_POW16_TH_L_SFT 24
+#define RG_POW16_TH_L_HI 30
+#define RG_POW16_TH_L_SZ 7
+#define RG_XSCOR16_SHORT_CNT_LMT_MSK 0x00000007
+#define RG_XSCOR16_SHORT_CNT_LMT_I_MSK 0xfffffff8
+#define RG_XSCOR16_SHORT_CNT_LMT_SFT 0
+#define RG_XSCOR16_SHORT_CNT_LMT_HI 2
+#define RG_XSCOR16_SHORT_CNT_LMT_SZ 3
+#define RG_XSCOR16_RATIO_MSK 0x00007f00
+#define RG_XSCOR16_RATIO_I_MSK 0xffff80ff
+#define RG_XSCOR16_RATIO_SFT 8
+#define RG_XSCOR16_RATIO_HI 14
+#define RG_XSCOR16_RATIO_SZ 7
+#define RG_ATCOR16_SHORT_CNT_LMT_MSK 0x00070000
+#define RG_ATCOR16_SHORT_CNT_LMT_I_MSK 0xfff8ffff
+#define RG_ATCOR16_SHORT_CNT_LMT_SFT 16
+#define RG_ATCOR16_SHORT_CNT_LMT_HI 18
+#define RG_ATCOR16_SHORT_CNT_LMT_SZ 3
+#define RG_ATCOR16_RATIO_CCD_MSK 0x7f000000
+#define RG_ATCOR16_RATIO_CCD_I_MSK 0x80ffffff
+#define RG_ATCOR16_RATIO_CCD_SFT 24
+#define RG_ATCOR16_RATIO_CCD_HI 30
+#define RG_ATCOR16_RATIO_CCD_SZ 7
+#define RG_ATCOR64_ACC_LMT_MSK 0x0000007f
+#define RG_ATCOR64_ACC_LMT_I_MSK 0xffffff80
+#define RG_ATCOR64_ACC_LMT_SFT 0
+#define RG_ATCOR64_ACC_LMT_HI 6
+#define RG_ATCOR64_ACC_LMT_SZ 7
+#define RG_ATCOR16_SHORT_CNT_LMT2_MSK 0x00070000
+#define RG_ATCOR16_SHORT_CNT_LMT2_I_MSK 0xfff8ffff
+#define RG_ATCOR16_SHORT_CNT_LMT2_SFT 16
+#define RG_ATCOR16_SHORT_CNT_LMT2_HI 18
+#define RG_ATCOR16_SHORT_CNT_LMT2_SZ 3
+#define RG_VITERBI_TB_BITS_MSK 0xff000000
+#define RG_VITERBI_TB_BITS_I_MSK 0x00ffffff
+#define RG_VITERBI_TB_BITS_SFT 24
+#define RG_VITERBI_TB_BITS_HI 31
+#define RG_VITERBI_TB_BITS_SZ 8
+#define RG_CR_CNT_UPDATE_MSK 0x000000ff
+#define RG_CR_CNT_UPDATE_I_MSK 0xffffff00
+#define RG_CR_CNT_UPDATE_SFT 0
+#define RG_CR_CNT_UPDATE_HI 7
+#define RG_CR_CNT_UPDATE_SZ 8
+#define RG_TR_CNT_UPDATE_MSK 0x00ff0000
+#define RG_TR_CNT_UPDATE_I_MSK 0xff00ffff
+#define RG_TR_CNT_UPDATE_SFT 16
+#define RG_TR_CNT_UPDATE_HI 23
+#define RG_TR_CNT_UPDATE_SZ 8
+#define RG_BYPASS_CPE_MA_MSK 0x00000010
+#define RG_BYPASS_CPE_MA_I_MSK 0xffffffef
+#define RG_BYPASS_CPE_MA_SFT 4
+#define RG_BYPASS_CPE_MA_HI 4
+#define RG_BYPASS_CPE_MA_SZ 1
+#define RG_PILOT_BNDRY_SHIFT_MSK 0x00000700
+#define RG_PILOT_BNDRY_SHIFT_I_MSK 0xfffff8ff
+#define RG_PILOT_BNDRY_SHIFT_SFT 8
+#define RG_PILOT_BNDRY_SHIFT_HI 10
+#define RG_PILOT_BNDRY_SHIFT_SZ 3
+#define RG_EQ_SHORT_GI_SHIFT_MSK 0x00007000
+#define RG_EQ_SHORT_GI_SHIFT_I_MSK 0xffff8fff
+#define RG_EQ_SHORT_GI_SHIFT_SFT 12
+#define RG_EQ_SHORT_GI_SHIFT_HI 14
+#define RG_EQ_SHORT_GI_SHIFT_SZ 3
+#define RG_FFT_WDW_SHORT_SHIFT_MSK 0x00070000
+#define RG_FFT_WDW_SHORT_SHIFT_I_MSK 0xfff8ffff
+#define RG_FFT_WDW_SHORT_SHIFT_SFT 16
+#define RG_FFT_WDW_SHORT_SHIFT_HI 18
+#define RG_FFT_WDW_SHORT_SHIFT_SZ 3
+#define RG_CHSMTH_COEF_MSK 0x00030000
+#define RG_CHSMTH_COEF_I_MSK 0xfffcffff
+#define RG_CHSMTH_COEF_SFT 16
+#define RG_CHSMTH_COEF_HI 17
+#define RG_CHSMTH_COEF_SZ 2
+#define RG_CHSMTH_EN_MSK 0x00040000
+#define RG_CHSMTH_EN_I_MSK 0xfffbffff
+#define RG_CHSMTH_EN_SFT 18
+#define RG_CHSMTH_EN_HI 18
+#define RG_CHSMTH_EN_SZ 1
+#define RG_CHEST_DD_FACTOR_MSK 0x07000000
+#define RG_CHEST_DD_FACTOR_I_MSK 0xf8ffffff
+#define RG_CHEST_DD_FACTOR_SFT 24
+#define RG_CHEST_DD_FACTOR_HI 26
+#define RG_CHEST_DD_FACTOR_SZ 3
+#define RG_CH_UPDATE_MSK 0x80000000
+#define RG_CH_UPDATE_I_MSK 0x7fffffff
+#define RG_CH_UPDATE_SFT 31
+#define RG_CH_UPDATE_HI 31
+#define RG_CH_UPDATE_SZ 1
+#define RG_FMT_DET_MM_TH_MSK 0x000000ff
+#define RG_FMT_DET_MM_TH_I_MSK 0xffffff00
+#define RG_FMT_DET_MM_TH_SFT 0
+#define RG_FMT_DET_MM_TH_HI 7
+#define RG_FMT_DET_MM_TH_SZ 8
+#define RG_FMT_DET_GF_TH_MSK 0x0000ff00
+#define RG_FMT_DET_GF_TH_I_MSK 0xffff00ff
+#define RG_FMT_DET_GF_TH_SFT 8
+#define RG_FMT_DET_GF_TH_HI 15
+#define RG_FMT_DET_GF_TH_SZ 8
+#define RG_DO_NOT_CHECK_L_RATE_MSK 0x02000000
+#define RG_DO_NOT_CHECK_L_RATE_I_MSK 0xfdffffff
+#define RG_DO_NOT_CHECK_L_RATE_SFT 25
+#define RG_DO_NOT_CHECK_L_RATE_HI 25
+#define RG_DO_NOT_CHECK_L_RATE_SZ 1
+#define RG_FMT_DET_LENGTH_TH_MSK 0x0000ffff
+#define RG_FMT_DET_LENGTH_TH_I_MSK 0xffff0000
+#define RG_FMT_DET_LENGTH_TH_SFT 0
+#define RG_FMT_DET_LENGTH_TH_HI 15
+#define RG_FMT_DET_LENGTH_TH_SZ 16
+#define RG_L_LENGTH_MAX_MSK 0xffff0000
+#define RG_L_LENGTH_MAX_I_MSK 0x0000ffff
+#define RG_L_LENGTH_MAX_SFT 16
+#define RG_L_LENGTH_MAX_HI 31
+#define RG_L_LENGTH_MAX_SZ 16
+#define RG_TX_TIME_EXT_MSK 0x000000ff
+#define RG_TX_TIME_EXT_I_MSK 0xffffff00
+#define RG_TX_TIME_EXT_SFT 0
+#define RG_TX_TIME_EXT_HI 7
+#define RG_TX_TIME_EXT_SZ 8
+#define RG_MAC_DES_SPACE_MSK 0x00f00000
+#define RG_MAC_DES_SPACE_I_MSK 0xff0fffff
+#define RG_MAC_DES_SPACE_SFT 20
+#define RG_MAC_DES_SPACE_HI 23
+#define RG_MAC_DES_SPACE_SZ 4
+#define RG_TR_LPF_STBC_GF_KI_G_MSK 0x0000000f
+#define RG_TR_LPF_STBC_GF_KI_G_I_MSK 0xfffffff0
+#define RG_TR_LPF_STBC_GF_KI_G_SFT 0
+#define RG_TR_LPF_STBC_GF_KI_G_HI 3
+#define RG_TR_LPF_STBC_GF_KI_G_SZ 4
+#define RG_TR_LPF_STBC_GF_KP_G_MSK 0x000000f0
+#define RG_TR_LPF_STBC_GF_KP_G_I_MSK 0xffffff0f
+#define RG_TR_LPF_STBC_GF_KP_G_SFT 4
+#define RG_TR_LPF_STBC_GF_KP_G_HI 7
+#define RG_TR_LPF_STBC_GF_KP_G_SZ 4
+#define RG_TR_LPF_STBC_MF_KI_G_MSK 0x00000f00
+#define RG_TR_LPF_STBC_MF_KI_G_I_MSK 0xfffff0ff
+#define RG_TR_LPF_STBC_MF_KI_G_SFT 8
+#define RG_TR_LPF_STBC_MF_KI_G_HI 11
+#define RG_TR_LPF_STBC_MF_KI_G_SZ 4
+#define RG_TR_LPF_STBC_MF_KP_G_MSK 0x0000f000
+#define RG_TR_LPF_STBC_MF_KP_G_I_MSK 0xffff0fff
+#define RG_TR_LPF_STBC_MF_KP_G_SFT 12
+#define RG_TR_LPF_STBC_MF_KP_G_HI 15
+#define RG_TR_LPF_STBC_MF_KP_G_SZ 4
+#define RG_MODE_REG_IN_80_MSK 0x0001ffff
+#define RG_MODE_REG_IN_80_I_MSK 0xfffe0000
+#define RG_MODE_REG_IN_80_SFT 0
+#define RG_MODE_REG_IN_80_HI 16
+#define RG_MODE_REG_IN_80_SZ 17
+#define RG_PARALLEL_DR_80_MSK 0x00100000
+#define RG_PARALLEL_DR_80_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_80_SFT 20
+#define RG_PARALLEL_DR_80_HI 20
+#define RG_PARALLEL_DR_80_SZ 1
+#define RG_MBRUN_80_MSK 0x01000000
+#define RG_MBRUN_80_I_MSK 0xfeffffff
+#define RG_MBRUN_80_SFT 24
+#define RG_MBRUN_80_HI 24
+#define RG_MBRUN_80_SZ 1
+#define RG_SHIFT_DR_80_MSK 0x10000000
+#define RG_SHIFT_DR_80_I_MSK 0xefffffff
+#define RG_SHIFT_DR_80_SFT 28
+#define RG_SHIFT_DR_80_HI 28
+#define RG_SHIFT_DR_80_SZ 1
+#define RG_MODE_REG_SI_80_MSK 0x20000000
+#define RG_MODE_REG_SI_80_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_80_SFT 29
+#define RG_MODE_REG_SI_80_HI 29
+#define RG_MODE_REG_SI_80_SZ 1
+#define RG_SIMULATION_MODE_80_MSK 0x40000000
+#define RG_SIMULATION_MODE_80_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_80_SFT 30
+#define RG_SIMULATION_MODE_80_HI 30
+#define RG_SIMULATION_MODE_80_SZ 1
+#define RG_DBIST_MODE_80_MSK 0x80000000
+#define RG_DBIST_MODE_80_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_80_SFT 31
+#define RG_DBIST_MODE_80_HI 31
+#define RG_DBIST_MODE_80_SZ 1
+#define RG_MODE_REG_IN_64_MSK 0x0000ffff
+#define RG_MODE_REG_IN_64_I_MSK 0xffff0000
+#define RG_MODE_REG_IN_64_SFT 0
+#define RG_MODE_REG_IN_64_HI 15
+#define RG_MODE_REG_IN_64_SZ 16
+#define RG_PARALLEL_DR_64_MSK 0x00100000
+#define RG_PARALLEL_DR_64_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_64_SFT 20
+#define RG_PARALLEL_DR_64_HI 20
+#define RG_PARALLEL_DR_64_SZ 1
+#define RG_MBRUN_64_MSK 0x01000000
+#define RG_MBRUN_64_I_MSK 0xfeffffff
+#define RG_MBRUN_64_SFT 24
+#define RG_MBRUN_64_HI 24
+#define RG_MBRUN_64_SZ 1
+#define RG_SHIFT_DR_64_MSK 0x10000000
+#define RG_SHIFT_DR_64_I_MSK 0xefffffff
+#define RG_SHIFT_DR_64_SFT 28
+#define RG_SHIFT_DR_64_HI 28
+#define RG_SHIFT_DR_64_SZ 1
+#define RG_MODE_REG_SI_64_MSK 0x20000000
+#define RG_MODE_REG_SI_64_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_64_SFT 29
+#define RG_MODE_REG_SI_64_HI 29
+#define RG_MODE_REG_SI_64_SZ 1
+#define RG_SIMULATION_MODE_64_MSK 0x40000000
+#define RG_SIMULATION_MODE_64_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_64_SFT 30
+#define RG_SIMULATION_MODE_64_HI 30
+#define RG_SIMULATION_MODE_64_SZ 1
+#define RG_DBIST_MODE_64_MSK 0x80000000
+#define RG_DBIST_MODE_64_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_64_SFT 31
+#define RG_DBIST_MODE_64_HI 31
+#define RG_DBIST_MODE_64_SZ 1
+#define RO_MODE_REG_OUT_80_MSK 0x0001ffff
+#define RO_MODE_REG_OUT_80_I_MSK 0xfffe0000
+#define RO_MODE_REG_OUT_80_SFT 0
+#define RO_MODE_REG_OUT_80_HI 16
+#define RO_MODE_REG_OUT_80_SZ 17
+#define RO_MODE_REG_SO_80_MSK 0x01000000
+#define RO_MODE_REG_SO_80_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_80_SFT 24
+#define RO_MODE_REG_SO_80_HI 24
+#define RO_MODE_REG_SO_80_SZ 1
+#define RO_MONITOR_BUS_80_MSK 0x003fffff
+#define RO_MONITOR_BUS_80_I_MSK 0xffc00000
+#define RO_MONITOR_BUS_80_SFT 0
+#define RO_MONITOR_BUS_80_HI 21
+#define RO_MONITOR_BUS_80_SZ 22
+#define RO_MODE_REG_OUT_64_MSK 0x0000ffff
+#define RO_MODE_REG_OUT_64_I_MSK 0xffff0000
+#define RO_MODE_REG_OUT_64_SFT 0
+#define RO_MODE_REG_OUT_64_HI 15
+#define RO_MODE_REG_OUT_64_SZ 16
+#define RO_MODE_REG_SO_64_MSK 0x01000000
+#define RO_MODE_REG_SO_64_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_64_SFT 24
+#define RO_MODE_REG_SO_64_HI 24
+#define RO_MODE_REG_SO_64_SZ 1
+#define RO_MONITOR_BUS_64_MSK 0x0007ffff
+#define RO_MONITOR_BUS_64_I_MSK 0xfff80000
+#define RO_MONITOR_BUS_64_SFT 0
+#define RO_MONITOR_BUS_64_HI 18
+#define RO_MONITOR_BUS_64_SZ 19
+#define RO_SPECTRUM_DATA_MSK 0xffffffff
+#define RO_SPECTRUM_DATA_I_MSK 0x00000000
+#define RO_SPECTRUM_DATA_SFT 0
+#define RO_SPECTRUM_DATA_HI 31
+#define RO_SPECTRUM_DATA_SZ 32
+#define GN_SNR_MSK 0x0000007f
+#define GN_SNR_I_MSK 0xffffff80
+#define GN_SNR_SFT 0
+#define GN_SNR_HI 6
+#define GN_SNR_SZ 7
+#define GN_NOISE_PWR_MSK 0x00007f00
+#define GN_NOISE_PWR_I_MSK 0xffff80ff
+#define GN_NOISE_PWR_SFT 8
+#define GN_NOISE_PWR_HI 14
+#define GN_NOISE_PWR_SZ 7
+#define GN_RCPI_MSK 0x007f0000
+#define GN_RCPI_I_MSK 0xff80ffff
+#define GN_RCPI_SFT 16
+#define GN_RCPI_HI 22
+#define GN_RCPI_SZ 7
+#define GN_SIGNAL_PWR_MSK 0x7f000000
+#define GN_SIGNAL_PWR_I_MSK 0x80ffffff
+#define GN_SIGNAL_PWR_SFT 24
+#define GN_SIGNAL_PWR_HI 30
+#define GN_SIGNAL_PWR_SZ 7
+#define RO_FREQ_OS_LTS_MSK 0x00007fff
+#define RO_FREQ_OS_LTS_I_MSK 0xffff8000
+#define RO_FREQ_OS_LTS_SFT 0
+#define RO_FREQ_OS_LTS_HI 14
+#define RO_FREQ_OS_LTS_SZ 15
+#define CSTATE_MSK 0x000f0000
+#define CSTATE_I_MSK 0xfff0ffff
+#define CSTATE_SFT 16
+#define CSTATE_HI 19
+#define CSTATE_SZ 4
+#define SIGNAL_FIELD0_MSK 0x00ffffff
+#define SIGNAL_FIELD0_I_MSK 0xff000000
+#define SIGNAL_FIELD0_SFT 0
+#define SIGNAL_FIELD0_HI 23
+#define SIGNAL_FIELD0_SZ 24
+#define SIGNAL_FIELD1_MSK 0x00ffffff
+#define SIGNAL_FIELD1_I_MSK 0xff000000
+#define SIGNAL_FIELD1_SFT 0
+#define SIGNAL_FIELD1_HI 23
+#define SIGNAL_FIELD1_SZ 24
+#define GN_PACKET_ERR_CNT_MSK 0x0000ffff
+#define GN_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define GN_PACKET_ERR_CNT_SFT 0
+#define GN_PACKET_ERR_CNT_HI 15
+#define GN_PACKET_ERR_CNT_SZ 16
+#define GN_PACKET_CNT_MSK 0x0000ffff
+#define GN_PACKET_CNT_I_MSK 0xffff0000
+#define GN_PACKET_CNT_SFT 0
+#define GN_PACKET_CNT_HI 15
+#define GN_PACKET_CNT_SZ 16
+#define GN_CCA_CNT_MSK 0xffff0000
+#define GN_CCA_CNT_I_MSK 0x0000ffff
+#define GN_CCA_CNT_SFT 16
+#define GN_CCA_CNT_HI 31
+#define GN_CCA_CNT_SZ 16
+#define GN_LENGTH_FIELD_MSK 0x0000ffff
+#define GN_LENGTH_FIELD_I_MSK 0xffff0000
+#define GN_LENGTH_FIELD_SFT 0
+#define GN_LENGTH_FIELD_HI 15
+#define GN_LENGTH_FIELD_SZ 16
+#define GN_SERVICE_FIELD_MSK 0xffff0000
+#define GN_SERVICE_FIELD_I_MSK 0x0000ffff
+#define GN_SERVICE_FIELD_SFT 16
+#define GN_SERVICE_FIELD_HI 31
+#define GN_SERVICE_FIELD_SZ 16
+#define RO_HT_MCS_40M_MSK 0x0000007f
+#define RO_HT_MCS_40M_I_MSK 0xffffff80
+#define RO_HT_MCS_40M_SFT 0
+#define RO_HT_MCS_40M_HI 6
+#define RO_HT_MCS_40M_SZ 7
+#define RO_L_RATE_40M_MSK 0x00003f00
+#define RO_L_RATE_40M_I_MSK 0xffffc0ff
+#define RO_L_RATE_40M_SFT 8
+#define RO_L_RATE_40M_HI 13
+#define RO_L_RATE_40M_SZ 6
+#define RG_DAGC_CNT_TH_MSK 0x00000003
+#define RG_DAGC_CNT_TH_I_MSK 0xfffffffc
+#define RG_DAGC_CNT_TH_SFT 0
+#define RG_DAGC_CNT_TH_HI 1
+#define RG_DAGC_CNT_TH_SZ 2
+#define RG_PACKET_STAT_EN_11GN_MSK 0x00100000
+#define RG_PACKET_STAT_EN_11GN_I_MSK 0xffefffff
+#define RG_PACKET_STAT_EN_11GN_SFT 20
+#define RG_PACKET_STAT_EN_11GN_HI 20
+#define RG_PACKET_STAT_EN_11GN_SZ 1
+#define RX_PHY_11GN_SOFT_RST_N_MSK 0x00000001
+#define RX_PHY_11GN_SOFT_RST_N_I_MSK 0xfffffffe
+#define RX_PHY_11GN_SOFT_RST_N_SFT 0
+#define RX_PHY_11GN_SOFT_RST_N_HI 0
+#define RX_PHY_11GN_SOFT_RST_N_SZ 1
+#define RG_RIFS_EN_MSK 0x00000002
+#define RG_RIFS_EN_I_MSK 0xfffffffd
+#define RG_RIFS_EN_SFT 1
+#define RG_RIFS_EN_HI 1
+#define RG_RIFS_EN_SZ 1
+#define RG_STBC_EN_MSK 0x00000004
+#define RG_STBC_EN_I_MSK 0xfffffffb
+#define RG_STBC_EN_SFT 2
+#define RG_STBC_EN_HI 2
+#define RG_STBC_EN_SZ 1
+#define RG_COR_SEL_MSK 0x00000008
+#define RG_COR_SEL_I_MSK 0xfffffff7
+#define RG_COR_SEL_SFT 3
+#define RG_COR_SEL_HI 3
+#define RG_COR_SEL_SZ 1
+#define RG_INI_PHASE_MSK 0x00000030
+#define RG_INI_PHASE_I_MSK 0xffffffcf
+#define RG_INI_PHASE_SFT 4
+#define RG_INI_PHASE_HI 5
+#define RG_INI_PHASE_SZ 2
+#define RG_HT_LTF_SEL_EQ_MSK 0x00000040
+#define RG_HT_LTF_SEL_EQ_I_MSK 0xffffffbf
+#define RG_HT_LTF_SEL_EQ_SFT 6
+#define RG_HT_LTF_SEL_EQ_HI 6
+#define RG_HT_LTF_SEL_EQ_SZ 1
+#define RG_HT_LTF_SEL_PILOT_MSK 0x00000080
+#define RG_HT_LTF_SEL_PILOT_I_MSK 0xffffff7f
+#define RG_HT_LTF_SEL_PILOT_SFT 7
+#define RG_HT_LTF_SEL_PILOT_HI 7
+#define RG_HT_LTF_SEL_PILOT_SZ 1
+#define RG_CCA_PWR_SEL_MSK 0x00000200
+#define RG_CCA_PWR_SEL_I_MSK 0xfffffdff
+#define RG_CCA_PWR_SEL_SFT 9
+#define RG_CCA_PWR_SEL_HI 9
+#define RG_CCA_PWR_SEL_SZ 1
+#define RG_CCA_XSCOR_PWR_SEL_MSK 0x00000400
+#define RG_CCA_XSCOR_PWR_SEL_I_MSK 0xfffffbff
+#define RG_CCA_XSCOR_PWR_SEL_SFT 10
+#define RG_CCA_XSCOR_PWR_SEL_HI 10
+#define RG_CCA_XSCOR_PWR_SEL_SZ 1
+#define RG_CCA_XSCOR_AVGPWR_SEL_MSK 0x00000800
+#define RG_CCA_XSCOR_AVGPWR_SEL_I_MSK 0xfffff7ff
+#define RG_CCA_XSCOR_AVGPWR_SEL_SFT 11
+#define RG_CCA_XSCOR_AVGPWR_SEL_HI 11
+#define RG_CCA_XSCOR_AVGPWR_SEL_SZ 1
+#define RG_DEBUG_SEL_MSK 0x0000f000
+#define RG_DEBUG_SEL_I_MSK 0xffff0fff
+#define RG_DEBUG_SEL_SFT 12
+#define RG_DEBUG_SEL_HI 15
+#define RG_DEBUG_SEL_SZ 4
+#define RG_POST_CLK_EN_MSK 0x00010000
+#define RG_POST_CLK_EN_I_MSK 0xfffeffff
+#define RG_POST_CLK_EN_SFT 16
+#define RG_POST_CLK_EN_HI 16
+#define RG_POST_CLK_EN_SZ 1
+#define IQCAL_RF_TX_EN_MSK 0x00000001
+#define IQCAL_RF_TX_EN_I_MSK 0xfffffffe
+#define IQCAL_RF_TX_EN_SFT 0
+#define IQCAL_RF_TX_EN_HI 0
+#define IQCAL_RF_TX_EN_SZ 1
+#define IQCAL_RF_TX_PA_EN_MSK 0x00000002
+#define IQCAL_RF_TX_PA_EN_I_MSK 0xfffffffd
+#define IQCAL_RF_TX_PA_EN_SFT 1
+#define IQCAL_RF_TX_PA_EN_HI 1
+#define IQCAL_RF_TX_PA_EN_SZ 1
+#define IQCAL_RF_TX_DAC_EN_MSK 0x00000004
+#define IQCAL_RF_TX_DAC_EN_I_MSK 0xfffffffb
+#define IQCAL_RF_TX_DAC_EN_SFT 2
+#define IQCAL_RF_TX_DAC_EN_HI 2
+#define IQCAL_RF_TX_DAC_EN_SZ 1
+#define IQCAL_RF_RX_AGC_MSK 0x00000008
+#define IQCAL_RF_RX_AGC_I_MSK 0xfffffff7
+#define IQCAL_RF_RX_AGC_SFT 3
+#define IQCAL_RF_RX_AGC_HI 3
+#define IQCAL_RF_RX_AGC_SZ 1
+#define IQCAL_RF_PGAG_MSK 0x00000f00
+#define IQCAL_RF_PGAG_I_MSK 0xfffff0ff
+#define IQCAL_RF_PGAG_SFT 8
+#define IQCAL_RF_PGAG_HI 11
+#define IQCAL_RF_PGAG_SZ 4
+#define IQCAL_RF_RFG_MSK 0x00003000
+#define IQCAL_RF_RFG_I_MSK 0xffffcfff
+#define IQCAL_RF_RFG_SFT 12
+#define IQCAL_RF_RFG_HI 13
+#define IQCAL_RF_RFG_SZ 2
+#define RG_TONEGEN_FREQ_MSK 0x007f0000
+#define RG_TONEGEN_FREQ_I_MSK 0xff80ffff
+#define RG_TONEGEN_FREQ_SFT 16
+#define RG_TONEGEN_FREQ_HI 22
+#define RG_TONEGEN_FREQ_SZ 7
+#define RG_TONEGEN_EN_MSK 0x00800000
+#define RG_TONEGEN_EN_I_MSK 0xff7fffff
+#define RG_TONEGEN_EN_SFT 23
+#define RG_TONEGEN_EN_HI 23
+#define RG_TONEGEN_EN_SZ 1
+#define RG_TONEGEN_INIT_PH_MSK 0x7f000000
+#define RG_TONEGEN_INIT_PH_I_MSK 0x80ffffff
+#define RG_TONEGEN_INIT_PH_SFT 24
+#define RG_TONEGEN_INIT_PH_HI 30
+#define RG_TONEGEN_INIT_PH_SZ 7
+#define RG_TONEGEN2_FREQ_MSK 0x0000007f
+#define RG_TONEGEN2_FREQ_I_MSK 0xffffff80
+#define RG_TONEGEN2_FREQ_SFT 0
+#define RG_TONEGEN2_FREQ_HI 6
+#define RG_TONEGEN2_FREQ_SZ 7
+#define RG_TONEGEN2_EN_MSK 0x00000080
+#define RG_TONEGEN2_EN_I_MSK 0xffffff7f
+#define RG_TONEGEN2_EN_SFT 7
+#define RG_TONEGEN2_EN_HI 7
+#define RG_TONEGEN2_EN_SZ 1
+#define RG_TONEGEN2_SCALE_MSK 0x0000ff00
+#define RG_TONEGEN2_SCALE_I_MSK 0xffff00ff
+#define RG_TONEGEN2_SCALE_SFT 8
+#define RG_TONEGEN2_SCALE_HI 15
+#define RG_TONEGEN2_SCALE_SZ 8
+#define RG_TXIQ_CLP_THD_I_MSK 0x000003ff
+#define RG_TXIQ_CLP_THD_I_I_MSK 0xfffffc00
+#define RG_TXIQ_CLP_THD_I_SFT 0
+#define RG_TXIQ_CLP_THD_I_HI 9
+#define RG_TXIQ_CLP_THD_I_SZ 10
+#define RG_TXIQ_CLP_THD_Q_MSK 0x03ff0000
+#define RG_TXIQ_CLP_THD_Q_I_MSK 0xfc00ffff
+#define RG_TXIQ_CLP_THD_Q_SFT 16
+#define RG_TXIQ_CLP_THD_Q_HI 25
+#define RG_TXIQ_CLP_THD_Q_SZ 10
+#define RG_TX_I_SCALE_MSK 0x000000ff
+#define RG_TX_I_SCALE_I_MSK 0xffffff00
+#define RG_TX_I_SCALE_SFT 0
+#define RG_TX_I_SCALE_HI 7
+#define RG_TX_I_SCALE_SZ 8
+#define RG_TX_Q_SCALE_MSK 0x0000ff00
+#define RG_TX_Q_SCALE_I_MSK 0xffff00ff
+#define RG_TX_Q_SCALE_SFT 8
+#define RG_TX_Q_SCALE_HI 15
+#define RG_TX_Q_SCALE_SZ 8
+#define RG_TX_IQ_SWP_MSK 0x00010000
+#define RG_TX_IQ_SWP_I_MSK 0xfffeffff
+#define RG_TX_IQ_SWP_SFT 16
+#define RG_TX_IQ_SWP_HI 16
+#define RG_TX_IQ_SWP_SZ 1
+#define RG_TX_SGN_OUT_MSK 0x00020000
+#define RG_TX_SGN_OUT_I_MSK 0xfffdffff
+#define RG_TX_SGN_OUT_SFT 17
+#define RG_TX_SGN_OUT_HI 17
+#define RG_TX_SGN_OUT_SZ 1
+#define RG_TXIQ_EMU_IDX_MSK 0x003c0000
+#define RG_TXIQ_EMU_IDX_I_MSK 0xffc3ffff
+#define RG_TXIQ_EMU_IDX_SFT 18
+#define RG_TXIQ_EMU_IDX_HI 21
+#define RG_TXIQ_EMU_IDX_SZ 4
+#define RG_TX_IQ_SRC_MSK 0x03000000
+#define RG_TX_IQ_SRC_I_MSK 0xfcffffff
+#define RG_TX_IQ_SRC_SFT 24
+#define RG_TX_IQ_SRC_HI 25
+#define RG_TX_IQ_SRC_SZ 2
+#define RG_TX_I_DC_MSK 0x000003ff
+#define RG_TX_I_DC_I_MSK 0xfffffc00
+#define RG_TX_I_DC_SFT 0
+#define RG_TX_I_DC_HI 9
+#define RG_TX_I_DC_SZ 10
+#define RG_TX_Q_DC_MSK 0x03ff0000
+#define RG_TX_Q_DC_I_MSK 0xfc00ffff
+#define RG_TX_Q_DC_SFT 16
+#define RG_TX_Q_DC_HI 25
+#define RG_TX_Q_DC_SZ 10
+#define RG_TX_IQ_THETA_MSK 0x0000001f
+#define RG_TX_IQ_THETA_I_MSK 0xffffffe0
+#define RG_TX_IQ_THETA_SFT 0
+#define RG_TX_IQ_THETA_HI 4
+#define RG_TX_IQ_THETA_SZ 5
+#define RG_TX_IQ_ALPHA_MSK 0x00001f00
+#define RG_TX_IQ_ALPHA_I_MSK 0xffffe0ff
+#define RG_TX_IQ_ALPHA_SFT 8
+#define RG_TX_IQ_ALPHA_HI 12
+#define RG_TX_IQ_ALPHA_SZ 5
+#define RG_TXIQ_NOSHRINK_MSK 0x00002000
+#define RG_TXIQ_NOSHRINK_I_MSK 0xffffdfff
+#define RG_TXIQ_NOSHRINK_SFT 13
+#define RG_TXIQ_NOSHRINK_HI 13
+#define RG_TXIQ_NOSHRINK_SZ 1
+#define RG_TX_I_OFFSET_MSK 0x00ff0000
+#define RG_TX_I_OFFSET_I_MSK 0xff00ffff
+#define RG_TX_I_OFFSET_SFT 16
+#define RG_TX_I_OFFSET_HI 23
+#define RG_TX_I_OFFSET_SZ 8
+#define RG_TX_Q_OFFSET_MSK 0xff000000
+#define RG_TX_Q_OFFSET_I_MSK 0x00ffffff
+#define RG_TX_Q_OFFSET_SFT 24
+#define RG_TX_Q_OFFSET_HI 31
+#define RG_TX_Q_OFFSET_SZ 8
+#define RG_RX_IQ_THETA_MSK 0x0000001f
+#define RG_RX_IQ_THETA_I_MSK 0xffffffe0
+#define RG_RX_IQ_THETA_SFT 0
+#define RG_RX_IQ_THETA_HI 4
+#define RG_RX_IQ_THETA_SZ 5
+#define RG_RX_IQ_ALPHA_MSK 0x00001f00
+#define RG_RX_IQ_ALPHA_I_MSK 0xffffe0ff
+#define RG_RX_IQ_ALPHA_SFT 8
+#define RG_RX_IQ_ALPHA_HI 12
+#define RG_RX_IQ_ALPHA_SZ 5
+#define RG_RXIQ_NOSHRINK_MSK 0x00002000
+#define RG_RXIQ_NOSHRINK_I_MSK 0xffffdfff
+#define RG_RXIQ_NOSHRINK_SFT 13
+#define RG_RXIQ_NOSHRINK_HI 13
+#define RG_RXIQ_NOSHRINK_SZ 1
+#define RG_MA_DPTH_MSK 0x0000000f
+#define RG_MA_DPTH_I_MSK 0xfffffff0
+#define RG_MA_DPTH_SFT 0
+#define RG_MA_DPTH_HI 3
+#define RG_MA_DPTH_SZ 4
+#define RG_INTG_PH_MSK 0x000003f0
+#define RG_INTG_PH_I_MSK 0xfffffc0f
+#define RG_INTG_PH_SFT 4
+#define RG_INTG_PH_HI 9
+#define RG_INTG_PH_SZ 6
+#define RG_INTG_PRD_MSK 0x00001c00
+#define RG_INTG_PRD_I_MSK 0xffffe3ff
+#define RG_INTG_PRD_SFT 10
+#define RG_INTG_PRD_HI 12
+#define RG_INTG_PRD_SZ 3
+#define RG_INTG_MU_MSK 0x00006000
+#define RG_INTG_MU_I_MSK 0xffff9fff
+#define RG_INTG_MU_SFT 13
+#define RG_INTG_MU_HI 14
+#define RG_INTG_MU_SZ 2
+#define RG_IQCAL_SPRM_SELQ_MSK 0x00010000
+#define RG_IQCAL_SPRM_SELQ_I_MSK 0xfffeffff
+#define RG_IQCAL_SPRM_SELQ_SFT 16
+#define RG_IQCAL_SPRM_SELQ_HI 16
+#define RG_IQCAL_SPRM_SELQ_SZ 1
+#define RG_IQCAL_SPRM_EN_MSK 0x00020000
+#define RG_IQCAL_SPRM_EN_I_MSK 0xfffdffff
+#define RG_IQCAL_SPRM_EN_SFT 17
+#define RG_IQCAL_SPRM_EN_HI 17
+#define RG_IQCAL_SPRM_EN_SZ 1
+#define RG_IQCAL_SPRM_FREQ_MSK 0x00fc0000
+#define RG_IQCAL_SPRM_FREQ_I_MSK 0xff03ffff
+#define RG_IQCAL_SPRM_FREQ_SFT 18
+#define RG_IQCAL_SPRM_FREQ_HI 23
+#define RG_IQCAL_SPRM_FREQ_SZ 6
+#define RG_IQCAL_IQCOL_EN_MSK 0x01000000
+#define RG_IQCAL_IQCOL_EN_I_MSK 0xfeffffff
+#define RG_IQCAL_IQCOL_EN_SFT 24
+#define RG_IQCAL_IQCOL_EN_HI 24
+#define RG_IQCAL_IQCOL_EN_SZ 1
+#define RG_IQCAL_ALPHA_ESTM_EN_MSK 0x02000000
+#define RG_IQCAL_ALPHA_ESTM_EN_I_MSK 0xfdffffff
+#define RG_IQCAL_ALPHA_ESTM_EN_SFT 25
+#define RG_IQCAL_ALPHA_ESTM_EN_HI 25
+#define RG_IQCAL_ALPHA_ESTM_EN_SZ 1
+#define RG_IQCAL_DC_EN_MSK 0x04000000
+#define RG_IQCAL_DC_EN_I_MSK 0xfbffffff
+#define RG_IQCAL_DC_EN_SFT 26
+#define RG_IQCAL_DC_EN_HI 26
+#define RG_IQCAL_DC_EN_SZ 1
+#define RG_PHEST_STBY_MSK 0x08000000
+#define RG_PHEST_STBY_I_MSK 0xf7ffffff
+#define RG_PHEST_STBY_SFT 27
+#define RG_PHEST_STBY_HI 27
+#define RG_PHEST_STBY_SZ 1
+#define RG_PHEST_EN_MSK 0x10000000
+#define RG_PHEST_EN_I_MSK 0xefffffff
+#define RG_PHEST_EN_SFT 28
+#define RG_PHEST_EN_HI 28
+#define RG_PHEST_EN_SZ 1
+#define RG_GP_DIV_EN_MSK 0x20000000
+#define RG_GP_DIV_EN_I_MSK 0xdfffffff
+#define RG_GP_DIV_EN_SFT 29
+#define RG_GP_DIV_EN_HI 29
+#define RG_GP_DIV_EN_SZ 1
+#define RG_DPD_GAIN_EST_EN_MSK 0x40000000
+#define RG_DPD_GAIN_EST_EN_I_MSK 0xbfffffff
+#define RG_DPD_GAIN_EST_EN_SFT 30
+#define RG_DPD_GAIN_EST_EN_HI 30
+#define RG_DPD_GAIN_EST_EN_SZ 1
+#define RG_IQCAL_MULT_OP0_MSK 0x000003ff
+#define RG_IQCAL_MULT_OP0_I_MSK 0xfffffc00
+#define RG_IQCAL_MULT_OP0_SFT 0
+#define RG_IQCAL_MULT_OP0_HI 9
+#define RG_IQCAL_MULT_OP0_SZ 10
+#define RG_IQCAL_MULT_OP1_MSK 0x03ff0000
+#define RG_IQCAL_MULT_OP1_I_MSK 0xfc00ffff
+#define RG_IQCAL_MULT_OP1_SFT 16
+#define RG_IQCAL_MULT_OP1_HI 25
+#define RG_IQCAL_MULT_OP1_SZ 10
+#define RO_IQCAL_O_MSK 0x000fffff
+#define RO_IQCAL_O_I_MSK 0xfff00000
+#define RO_IQCAL_O_SFT 0
+#define RO_IQCAL_O_HI 19
+#define RO_IQCAL_O_SZ 20
+#define RO_IQCAL_SPRM_RDY_MSK 0x00100000
+#define RO_IQCAL_SPRM_RDY_I_MSK 0xffefffff
+#define RO_IQCAL_SPRM_RDY_SFT 20
+#define RO_IQCAL_SPRM_RDY_HI 20
+#define RO_IQCAL_SPRM_RDY_SZ 1
+#define RO_IQCAL_IQCOL_RDY_MSK 0x00200000
+#define RO_IQCAL_IQCOL_RDY_I_MSK 0xffdfffff
+#define RO_IQCAL_IQCOL_RDY_SFT 21
+#define RO_IQCAL_IQCOL_RDY_HI 21
+#define RO_IQCAL_IQCOL_RDY_SZ 1
+#define RO_IQCAL_ALPHA_ESTM_RDY_MSK 0x00400000
+#define RO_IQCAL_ALPHA_ESTM_RDY_I_MSK 0xffbfffff
+#define RO_IQCAL_ALPHA_ESTM_RDY_SFT 22
+#define RO_IQCAL_ALPHA_ESTM_RDY_HI 22
+#define RO_IQCAL_ALPHA_ESTM_RDY_SZ 1
+#define RO_IQCAL_DC_RDY_MSK 0x00800000
+#define RO_IQCAL_DC_RDY_I_MSK 0xff7fffff
+#define RO_IQCAL_DC_RDY_SFT 23
+#define RO_IQCAL_DC_RDY_HI 23
+#define RO_IQCAL_DC_RDY_SZ 1
+#define RO_IQCAL_MULT_RDY_MSK 0x01000000
+#define RO_IQCAL_MULT_RDY_I_MSK 0xfeffffff
+#define RO_IQCAL_MULT_RDY_SFT 24
+#define RO_IQCAL_MULT_RDY_HI 24
+#define RO_IQCAL_MULT_RDY_SZ 1
+#define RO_FFT_ENRG_RDY_MSK 0x02000000
+#define RO_FFT_ENRG_RDY_I_MSK 0xfdffffff
+#define RO_FFT_ENRG_RDY_SFT 25
+#define RO_FFT_ENRG_RDY_HI 25
+#define RO_FFT_ENRG_RDY_SZ 1
+#define RO_PHEST_RDY_MSK 0x04000000
+#define RO_PHEST_RDY_I_MSK 0xfbffffff
+#define RO_PHEST_RDY_SFT 26
+#define RO_PHEST_RDY_HI 26
+#define RO_PHEST_RDY_SZ 1
+#define RO_GP_DIV_RDY_MSK 0x08000000
+#define RO_GP_DIV_RDY_I_MSK 0xf7ffffff
+#define RO_GP_DIV_RDY_SFT 27
+#define RO_GP_DIV_RDY_HI 27
+#define RO_GP_DIV_RDY_SZ 1
+#define RO_GAIN_EST_RDY_MSK 0x10000000
+#define RO_GAIN_EST_RDY_I_MSK 0xefffffff
+#define RO_GAIN_EST_RDY_SFT 28
+#define RO_GAIN_EST_RDY_HI 28
+#define RO_GAIN_EST_RDY_SZ 1
+#define RO_AMP_O_MSK 0x000001ff
+#define RO_AMP_O_I_MSK 0xfffffe00
+#define RO_AMP_O_SFT 0
+#define RO_AMP_O_HI 8
+#define RO_AMP_O_SZ 9
+#define RG_RX_I_SCALE_MSK 0x000000ff
+#define RG_RX_I_SCALE_I_MSK 0xffffff00
+#define RG_RX_I_SCALE_SFT 0
+#define RG_RX_I_SCALE_HI 7
+#define RG_RX_I_SCALE_SZ 8
+#define RG_RX_Q_SCALE_MSK 0x0000ff00
+#define RG_RX_Q_SCALE_I_MSK 0xffff00ff
+#define RG_RX_Q_SCALE_SFT 8
+#define RG_RX_Q_SCALE_HI 15
+#define RG_RX_Q_SCALE_SZ 8
+#define RG_RX_I_OFFSET_MSK 0x00ff0000
+#define RG_RX_I_OFFSET_I_MSK 0xff00ffff
+#define RG_RX_I_OFFSET_SFT 16
+#define RG_RX_I_OFFSET_HI 23
+#define RG_RX_I_OFFSET_SZ 8
+#define RG_RX_Q_OFFSET_MSK 0xff000000
+#define RG_RX_Q_OFFSET_I_MSK 0x00ffffff
+#define RG_RX_Q_OFFSET_SFT 24
+#define RG_RX_Q_OFFSET_HI 31
+#define RG_RX_Q_OFFSET_SZ 8
+#define RG_RX_IQ_SWP_MSK 0x00000001
+#define RG_RX_IQ_SWP_I_MSK 0xfffffffe
+#define RG_RX_IQ_SWP_SFT 0
+#define RG_RX_IQ_SWP_HI 0
+#define RG_RX_IQ_SWP_SZ 1
+#define RG_RX_SGN_IN_MSK 0x00000002
+#define RG_RX_SGN_IN_I_MSK 0xfffffffd
+#define RG_RX_SGN_IN_SFT 1
+#define RG_RX_SGN_IN_HI 1
+#define RG_RX_SGN_IN_SZ 1
+#define RG_RX_IQ_SRC_MSK 0x0000000c
+#define RG_RX_IQ_SRC_I_MSK 0xfffffff3
+#define RG_RX_IQ_SRC_SFT 2
+#define RG_RX_IQ_SRC_HI 3
+#define RG_RX_IQ_SRC_SZ 2
+#define RG_ACI_GAIN_MSK 0x00000ff0
+#define RG_ACI_GAIN_I_MSK 0xfffff00f
+#define RG_ACI_GAIN_SFT 4
+#define RG_ACI_GAIN_HI 11
+#define RG_ACI_GAIN_SZ 8
+#define RG_FFT_EN_MSK 0x00001000
+#define RG_FFT_EN_I_MSK 0xffffefff
+#define RG_FFT_EN_SFT 12
+#define RG_FFT_EN_HI 12
+#define RG_FFT_EN_SZ 1
+#define RG_FFT_MOD_MSK 0x00002000
+#define RG_FFT_MOD_I_MSK 0xffffdfff
+#define RG_FFT_MOD_SFT 13
+#define RG_FFT_MOD_HI 13
+#define RG_FFT_MOD_SZ 1
+#define RG_FFT_SCALE_MSK 0x00ffc000
+#define RG_FFT_SCALE_I_MSK 0xff003fff
+#define RG_FFT_SCALE_SFT 14
+#define RG_FFT_SCALE_HI 23
+#define RG_FFT_SCALE_SZ 10
+#define RG_FFT_ENRG_FREQ_MSK 0x3f000000
+#define RG_FFT_ENRG_FREQ_I_MSK 0xc0ffffff
+#define RG_FFT_ENRG_FREQ_SFT 24
+#define RG_FFT_ENRG_FREQ_HI 29
+#define RG_FFT_ENRG_FREQ_SZ 6
+#define RG_FPGA_80M_PH_UP_MSK 0x40000000
+#define RG_FPGA_80M_PH_UP_I_MSK 0xbfffffff
+#define RG_FPGA_80M_PH_UP_SFT 30
+#define RG_FPGA_80M_PH_UP_HI 30
+#define RG_FPGA_80M_PH_UP_SZ 1
+#define RG_FPGA_80M_PH_STP_MSK 0x80000000
+#define RG_FPGA_80M_PH_STP_I_MSK 0x7fffffff
+#define RG_FPGA_80M_PH_STP_SFT 31
+#define RG_FPGA_80M_PH_STP_HI 31
+#define RG_FPGA_80M_PH_STP_SZ 1
+#define RG_ADC2LA_SEL_MSK 0x00000001
+#define RG_ADC2LA_SEL_I_MSK 0xfffffffe
+#define RG_ADC2LA_SEL_SFT 0
+#define RG_ADC2LA_SEL_HI 0
+#define RG_ADC2LA_SEL_SZ 1
+#define RG_ADC2LA_CLKPH_MSK 0x00000002
+#define RG_ADC2LA_CLKPH_I_MSK 0xfffffffd
+#define RG_ADC2LA_CLKPH_SFT 1
+#define RG_ADC2LA_CLKPH_HI 1
+#define RG_ADC2LA_CLKPH_SZ 1
+#define RG_RXIQ_EMU_IDX_MSK 0x0000000f
+#define RG_RXIQ_EMU_IDX_I_MSK 0xfffffff0
+#define RG_RXIQ_EMU_IDX_SFT 0
+#define RG_RXIQ_EMU_IDX_HI 3
+#define RG_RXIQ_EMU_IDX_SZ 4
+#define RG_IQCAL_BP_ACI_MSK 0x00000010
+#define RG_IQCAL_BP_ACI_I_MSK 0xffffffef
+#define RG_IQCAL_BP_ACI_SFT 4
+#define RG_IQCAL_BP_ACI_HI 4
+#define RG_IQCAL_BP_ACI_SZ 1
+#define RG_DPD_AM_EN_MSK 0x00000001
+#define RG_DPD_AM_EN_I_MSK 0xfffffffe
+#define RG_DPD_AM_EN_SFT 0
+#define RG_DPD_AM_EN_HI 0
+#define RG_DPD_AM_EN_SZ 1
+#define RG_DPD_PM_EN_MSK 0x00000002
+#define RG_DPD_PM_EN_I_MSK 0xfffffffd
+#define RG_DPD_PM_EN_SFT 1
+#define RG_DPD_PM_EN_HI 1
+#define RG_DPD_PM_EN_SZ 1
+#define RG_DPD_PM_AMSEL_MSK 0x00000004
+#define RG_DPD_PM_AMSEL_I_MSK 0xfffffffb
+#define RG_DPD_PM_AMSEL_SFT 2
+#define RG_DPD_PM_AMSEL_HI 2
+#define RG_DPD_PM_AMSEL_SZ 1
+#define RG_DPD_020_GAIN_MSK 0x000003ff
+#define RG_DPD_020_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_020_GAIN_SFT 0
+#define RG_DPD_020_GAIN_HI 9
+#define RG_DPD_020_GAIN_SZ 10
+#define RG_DPD_040_GAIN_MSK 0x03ff0000
+#define RG_DPD_040_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_040_GAIN_SFT 16
+#define RG_DPD_040_GAIN_HI 25
+#define RG_DPD_040_GAIN_SZ 10
+#define RG_DPD_060_GAIN_MSK 0x000003ff
+#define RG_DPD_060_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_060_GAIN_SFT 0
+#define RG_DPD_060_GAIN_HI 9
+#define RG_DPD_060_GAIN_SZ 10
+#define RG_DPD_080_GAIN_MSK 0x03ff0000
+#define RG_DPD_080_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_080_GAIN_SFT 16
+#define RG_DPD_080_GAIN_HI 25
+#define RG_DPD_080_GAIN_SZ 10
+#define RG_DPD_0A0_GAIN_MSK 0x000003ff
+#define RG_DPD_0A0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0A0_GAIN_SFT 0
+#define RG_DPD_0A0_GAIN_HI 9
+#define RG_DPD_0A0_GAIN_SZ 10
+#define RG_DPD_0C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_0C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_0C0_GAIN_SFT 16
+#define RG_DPD_0C0_GAIN_HI 25
+#define RG_DPD_0C0_GAIN_SZ 10
+#define RG_DPD_0D0_GAIN_MSK 0x000003ff
+#define RG_DPD_0D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0D0_GAIN_SFT 0
+#define RG_DPD_0D0_GAIN_HI 9
+#define RG_DPD_0D0_GAIN_SZ 10
+#define RG_DPD_0E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_0E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_0E0_GAIN_SFT 16
+#define RG_DPD_0E0_GAIN_HI 25
+#define RG_DPD_0E0_GAIN_SZ 10
+#define RG_DPD_0F0_GAIN_MSK 0x000003ff
+#define RG_DPD_0F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0F0_GAIN_SFT 0
+#define RG_DPD_0F0_GAIN_HI 9
+#define RG_DPD_0F0_GAIN_SZ 10
+#define RG_DPD_100_GAIN_MSK 0x03ff0000
+#define RG_DPD_100_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_100_GAIN_SFT 16
+#define RG_DPD_100_GAIN_HI 25
+#define RG_DPD_100_GAIN_SZ 10
+#define RG_DPD_110_GAIN_MSK 0x000003ff
+#define RG_DPD_110_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_110_GAIN_SFT 0
+#define RG_DPD_110_GAIN_HI 9
+#define RG_DPD_110_GAIN_SZ 10
+#define RG_DPD_120_GAIN_MSK 0x03ff0000
+#define RG_DPD_120_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_120_GAIN_SFT 16
+#define RG_DPD_120_GAIN_HI 25
+#define RG_DPD_120_GAIN_SZ 10
+#define RG_DPD_130_GAIN_MSK 0x000003ff
+#define RG_DPD_130_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_130_GAIN_SFT 0
+#define RG_DPD_130_GAIN_HI 9
+#define RG_DPD_130_GAIN_SZ 10
+#define RG_DPD_140_GAIN_MSK 0x03ff0000
+#define RG_DPD_140_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_140_GAIN_SFT 16
+#define RG_DPD_140_GAIN_HI 25
+#define RG_DPD_140_GAIN_SZ 10
+#define RG_DPD_150_GAIN_MSK 0x000003ff
+#define RG_DPD_150_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_150_GAIN_SFT 0
+#define RG_DPD_150_GAIN_HI 9
+#define RG_DPD_150_GAIN_SZ 10
+#define RG_DPD_160_GAIN_MSK 0x03ff0000
+#define RG_DPD_160_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_160_GAIN_SFT 16
+#define RG_DPD_160_GAIN_HI 25
+#define RG_DPD_160_GAIN_SZ 10
+#define RG_DPD_170_GAIN_MSK 0x000003ff
+#define RG_DPD_170_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_170_GAIN_SFT 0
+#define RG_DPD_170_GAIN_HI 9
+#define RG_DPD_170_GAIN_SZ 10
+#define RG_DPD_180_GAIN_MSK 0x03ff0000
+#define RG_DPD_180_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_180_GAIN_SFT 16
+#define RG_DPD_180_GAIN_HI 25
+#define RG_DPD_180_GAIN_SZ 10
+#define RG_DPD_190_GAIN_MSK 0x000003ff
+#define RG_DPD_190_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_190_GAIN_SFT 0
+#define RG_DPD_190_GAIN_HI 9
+#define RG_DPD_190_GAIN_SZ 10
+#define RG_DPD_1A0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1A0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1A0_GAIN_SFT 16
+#define RG_DPD_1A0_GAIN_HI 25
+#define RG_DPD_1A0_GAIN_SZ 10
+#define RG_DPD_1B0_GAIN_MSK 0x000003ff
+#define RG_DPD_1B0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1B0_GAIN_SFT 0
+#define RG_DPD_1B0_GAIN_HI 9
+#define RG_DPD_1B0_GAIN_SZ 10
+#define RG_DPD_1C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1C0_GAIN_SFT 16
+#define RG_DPD_1C0_GAIN_HI 25
+#define RG_DPD_1C0_GAIN_SZ 10
+#define RG_DPD_1D0_GAIN_MSK 0x000003ff
+#define RG_DPD_1D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1D0_GAIN_SFT 0
+#define RG_DPD_1D0_GAIN_HI 9
+#define RG_DPD_1D0_GAIN_SZ 10
+#define RG_DPD_1E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1E0_GAIN_SFT 16
+#define RG_DPD_1E0_GAIN_HI 25
+#define RG_DPD_1E0_GAIN_SZ 10
+#define RG_DPD_1F0_GAIN_MSK 0x000003ff
+#define RG_DPD_1F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1F0_GAIN_SFT 0
+#define RG_DPD_1F0_GAIN_HI 9
+#define RG_DPD_1F0_GAIN_SZ 10
+#define RG_DPD_200_GAIN_MSK 0x03ff0000
+#define RG_DPD_200_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_200_GAIN_SFT 16
+#define RG_DPD_200_GAIN_HI 25
+#define RG_DPD_200_GAIN_SZ 10
+#define RG_DPD_020_PH_MSK 0x00001fff
+#define RG_DPD_020_PH_I_MSK 0xffffe000
+#define RG_DPD_020_PH_SFT 0
+#define RG_DPD_020_PH_HI 12
+#define RG_DPD_020_PH_SZ 13
+#define RG_DPD_040_PH_MSK 0x1fff0000
+#define RG_DPD_040_PH_I_MSK 0xe000ffff
+#define RG_DPD_040_PH_SFT 16
+#define RG_DPD_040_PH_HI 28
+#define RG_DPD_040_PH_SZ 13
+#define RG_DPD_060_PH_MSK 0x00001fff
+#define RG_DPD_060_PH_I_MSK 0xffffe000
+#define RG_DPD_060_PH_SFT 0
+#define RG_DPD_060_PH_HI 12
+#define RG_DPD_060_PH_SZ 13
+#define RG_DPD_080_PH_MSK 0x1fff0000
+#define RG_DPD_080_PH_I_MSK 0xe000ffff
+#define RG_DPD_080_PH_SFT 16
+#define RG_DPD_080_PH_HI 28
+#define RG_DPD_080_PH_SZ 13
+#define RG_DPD_0A0_PH_MSK 0x00001fff
+#define RG_DPD_0A0_PH_I_MSK 0xffffe000
+#define RG_DPD_0A0_PH_SFT 0
+#define RG_DPD_0A0_PH_HI 12
+#define RG_DPD_0A0_PH_SZ 13
+#define RG_DPD_0C0_PH_MSK 0x1fff0000
+#define RG_DPD_0C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_0C0_PH_SFT 16
+#define RG_DPD_0C0_PH_HI 28
+#define RG_DPD_0C0_PH_SZ 13
+#define RG_DPD_0D0_PH_MSK 0x00001fff
+#define RG_DPD_0D0_PH_I_MSK 0xffffe000
+#define RG_DPD_0D0_PH_SFT 0
+#define RG_DPD_0D0_PH_HI 12
+#define RG_DPD_0D0_PH_SZ 13
+#define RG_DPD_0E0_PH_MSK 0x1fff0000
+#define RG_DPD_0E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_0E0_PH_SFT 16
+#define RG_DPD_0E0_PH_HI 28
+#define RG_DPD_0E0_PH_SZ 13
+#define RG_DPD_0F0_PH_MSK 0x00001fff
+#define RG_DPD_0F0_PH_I_MSK 0xffffe000
+#define RG_DPD_0F0_PH_SFT 0
+#define RG_DPD_0F0_PH_HI 12
+#define RG_DPD_0F0_PH_SZ 13
+#define RG_DPD_100_PH_MSK 0x1fff0000
+#define RG_DPD_100_PH_I_MSK 0xe000ffff
+#define RG_DPD_100_PH_SFT 16
+#define RG_DPD_100_PH_HI 28
+#define RG_DPD_100_PH_SZ 13
+#define RG_DPD_110_PH_MSK 0x00001fff
+#define RG_DPD_110_PH_I_MSK 0xffffe000
+#define RG_DPD_110_PH_SFT 0
+#define RG_DPD_110_PH_HI 12
+#define RG_DPD_110_PH_SZ 13
+#define RG_DPD_120_PH_MSK 0x1fff0000
+#define RG_DPD_120_PH_I_MSK 0xe000ffff
+#define RG_DPD_120_PH_SFT 16
+#define RG_DPD_120_PH_HI 28
+#define RG_DPD_120_PH_SZ 13
+#define RG_DPD_130_PH_MSK 0x00001fff
+#define RG_DPD_130_PH_I_MSK 0xffffe000
+#define RG_DPD_130_PH_SFT 0
+#define RG_DPD_130_PH_HI 12
+#define RG_DPD_130_PH_SZ 13
+#define RG_DPD_140_PH_MSK 0x1fff0000
+#define RG_DPD_140_PH_I_MSK 0xe000ffff
+#define RG_DPD_140_PH_SFT 16
+#define RG_DPD_140_PH_HI 28
+#define RG_DPD_140_PH_SZ 13
+#define RG_DPD_150_PH_MSK 0x00001fff
+#define RG_DPD_150_PH_I_MSK 0xffffe000
+#define RG_DPD_150_PH_SFT 0
+#define RG_DPD_150_PH_HI 12
+#define RG_DPD_150_PH_SZ 13
+#define RG_DPD_160_PH_MSK 0x1fff0000
+#define RG_DPD_160_PH_I_MSK 0xe000ffff
+#define RG_DPD_160_PH_SFT 16
+#define RG_DPD_160_PH_HI 28
+#define RG_DPD_160_PH_SZ 13
+#define RG_DPD_170_PH_MSK 0x00001fff
+#define RG_DPD_170_PH_I_MSK 0xffffe000
+#define RG_DPD_170_PH_SFT 0
+#define RG_DPD_170_PH_HI 12
+#define RG_DPD_170_PH_SZ 13
+#define RG_DPD_180_PH_MSK 0x1fff0000
+#define RG_DPD_180_PH_I_MSK 0xe000ffff
+#define RG_DPD_180_PH_SFT 16
+#define RG_DPD_180_PH_HI 28
+#define RG_DPD_180_PH_SZ 13
+#define RG_DPD_190_PH_MSK 0x00001fff
+#define RG_DPD_190_PH_I_MSK 0xffffe000
+#define RG_DPD_190_PH_SFT 0
+#define RG_DPD_190_PH_HI 12
+#define RG_DPD_190_PH_SZ 13
+#define RG_DPD_1A0_PH_MSK 0x1fff0000
+#define RG_DPD_1A0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1A0_PH_SFT 16
+#define RG_DPD_1A0_PH_HI 28
+#define RG_DPD_1A0_PH_SZ 13
+#define RG_DPD_1B0_PH_MSK 0x00001fff
+#define RG_DPD_1B0_PH_I_MSK 0xffffe000
+#define RG_DPD_1B0_PH_SFT 0
+#define RG_DPD_1B0_PH_HI 12
+#define RG_DPD_1B0_PH_SZ 13
+#define RG_DPD_1C0_PH_MSK 0x1fff0000
+#define RG_DPD_1C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1C0_PH_SFT 16
+#define RG_DPD_1C0_PH_HI 28
+#define RG_DPD_1C0_PH_SZ 13
+#define RG_DPD_1D0_PH_MSK 0x00001fff
+#define RG_DPD_1D0_PH_I_MSK 0xffffe000
+#define RG_DPD_1D0_PH_SFT 0
+#define RG_DPD_1D0_PH_HI 12
+#define RG_DPD_1D0_PH_SZ 13
+#define RG_DPD_1E0_PH_MSK 0x1fff0000
+#define RG_DPD_1E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1E0_PH_SFT 16
+#define RG_DPD_1E0_PH_HI 28
+#define RG_DPD_1E0_PH_SZ 13
+#define RG_DPD_1F0_PH_MSK 0x00001fff
+#define RG_DPD_1F0_PH_I_MSK 0xffffe000
+#define RG_DPD_1F0_PH_SFT 0
+#define RG_DPD_1F0_PH_HI 12
+#define RG_DPD_1F0_PH_SZ 13
+#define RG_DPD_200_PH_MSK 0x1fff0000
+#define RG_DPD_200_PH_I_MSK 0xe000ffff
+#define RG_DPD_200_PH_SFT 16
+#define RG_DPD_200_PH_HI 28
+#define RG_DPD_200_PH_SZ 13
+#define RG_DPD_GAIN_EST_Y0_MSK 0x000001ff
+#define RG_DPD_GAIN_EST_Y0_I_MSK 0xfffffe00
+#define RG_DPD_GAIN_EST_Y0_SFT 0
+#define RG_DPD_GAIN_EST_Y0_HI 8
+#define RG_DPD_GAIN_EST_Y0_SZ 9
+#define RG_DPD_GAIN_EST_Y1_MSK 0x01ff0000
+#define RG_DPD_GAIN_EST_Y1_I_MSK 0xfe00ffff
+#define RG_DPD_GAIN_EST_Y1_SFT 16
+#define RG_DPD_GAIN_EST_Y1_HI 24
+#define RG_DPD_GAIN_EST_Y1_SZ 9
+#define RG_DPD_LOOP_GAIN_MSK 0x000003ff
+#define RG_DPD_LOOP_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_LOOP_GAIN_SFT 0
+#define RG_DPD_LOOP_GAIN_HI 9
+#define RG_DPD_LOOP_GAIN_SZ 10
+#define RG_DPD_GAIN_EST_X0_MSK 0x000001ff
+#define RG_DPD_GAIN_EST_X0_I_MSK 0xfffffe00
+#define RG_DPD_GAIN_EST_X0_SFT 0
+#define RG_DPD_GAIN_EST_X0_HI 8
+#define RG_DPD_GAIN_EST_X0_SZ 9
+#define RO_DPD_GAIN_MSK 0x03ff0000
+#define RO_DPD_GAIN_I_MSK 0xfc00ffff
+#define RO_DPD_GAIN_SFT 16
+#define RO_DPD_GAIN_HI 25
+#define RO_DPD_GAIN_SZ 10
+#define TX_SCALE_11B_MSK 0x000000ff
+#define TX_SCALE_11B_I_MSK 0xffffff00
+#define TX_SCALE_11B_SFT 0
+#define TX_SCALE_11B_HI 7
+#define TX_SCALE_11B_SZ 8
+#define TX_SCALE_11B_P0D5_MSK 0x0000ff00
+#define TX_SCALE_11B_P0D5_I_MSK 0xffff00ff
+#define TX_SCALE_11B_P0D5_SFT 8
+#define TX_SCALE_11B_P0D5_HI 15
+#define TX_SCALE_11B_P0D5_SZ 8
+#define TX_SCALE_11G_MSK 0x00ff0000
+#define TX_SCALE_11G_I_MSK 0xff00ffff
+#define TX_SCALE_11G_SFT 16
+#define TX_SCALE_11G_HI 23
+#define TX_SCALE_11G_SZ 8
+#define TX_SCALE_11G_P0D5_MSK 0xff000000
+#define TX_SCALE_11G_P0D5_I_MSK 0x00ffffff
+#define TX_SCALE_11G_P0D5_SFT 24
+#define TX_SCALE_11G_P0D5_HI 31
+#define TX_SCALE_11G_P0D5_SZ 8
+#define RG_EN_MANUAL_MSK 0x00000001
+#define RG_EN_MANUAL_I_MSK 0xfffffffe
+#define RG_EN_MANUAL_SFT 0
+#define RG_EN_MANUAL_HI 0
+#define RG_EN_MANUAL_SZ 1
+#define RG_TX_EN_MSK 0x00000002
+#define RG_TX_EN_I_MSK 0xfffffffd
+#define RG_TX_EN_SFT 1
+#define RG_TX_EN_HI 1
+#define RG_TX_EN_SZ 1
+#define RG_TX_PA_EN_MSK 0x00000004
+#define RG_TX_PA_EN_I_MSK 0xfffffffb
+#define RG_TX_PA_EN_SFT 2
+#define RG_TX_PA_EN_HI 2
+#define RG_TX_PA_EN_SZ 1
+#define RG_TX_DAC_EN_MSK 0x00000008
+#define RG_TX_DAC_EN_I_MSK 0xfffffff7
+#define RG_TX_DAC_EN_SFT 3
+#define RG_TX_DAC_EN_HI 3
+#define RG_TX_DAC_EN_SZ 1
+#define RG_RX_AGC_MSK 0x00000010
+#define RG_RX_AGC_I_MSK 0xffffffef
+#define RG_RX_AGC_SFT 4
+#define RG_RX_AGC_HI 4
+#define RG_RX_AGC_SZ 1
+#define RG_RX_GAIN_MANUAL_MSK 0x00000020
+#define RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
+#define RG_RX_GAIN_MANUAL_SFT 5
+#define RG_RX_GAIN_MANUAL_HI 5
+#define RG_RX_GAIN_MANUAL_SZ 1
+#define RG_RFG_MSK 0x000000c0
+#define RG_RFG_I_MSK 0xffffff3f
+#define RG_RFG_SFT 6
+#define RG_RFG_HI 7
+#define RG_RFG_SZ 2
+#define RG_PGAG_MSK 0x00000f00
+#define RG_PGAG_I_MSK 0xfffff0ff
+#define RG_PGAG_SFT 8
+#define RG_PGAG_HI 11
+#define RG_PGAG_SZ 4
+#define RG_MODE_MSK 0x00003000
+#define RG_MODE_I_MSK 0xffffcfff
+#define RG_MODE_SFT 12
+#define RG_MODE_HI 13
+#define RG_MODE_SZ 2
+#define RG_EN_TX_TRSW_MSK 0x00004000
+#define RG_EN_TX_TRSW_I_MSK 0xffffbfff
+#define RG_EN_TX_TRSW_SFT 14
+#define RG_EN_TX_TRSW_HI 14
+#define RG_EN_TX_TRSW_SZ 1
+#define RG_EN_SX_MSK 0x00008000
+#define RG_EN_SX_I_MSK 0xffff7fff
+#define RG_EN_SX_SFT 15
+#define RG_EN_SX_HI 15
+#define RG_EN_SX_SZ 1
+#define RG_EN_RX_LNA_MSK 0x00010000
+#define RG_EN_RX_LNA_I_MSK 0xfffeffff
+#define RG_EN_RX_LNA_SFT 16
+#define RG_EN_RX_LNA_HI 16
+#define RG_EN_RX_LNA_SZ 1
+#define RG_EN_RX_MIXER_MSK 0x00020000
+#define RG_EN_RX_MIXER_I_MSK 0xfffdffff
+#define RG_EN_RX_MIXER_SFT 17
+#define RG_EN_RX_MIXER_HI 17
+#define RG_EN_RX_MIXER_SZ 1
+#define RG_EN_RX_DIV2_MSK 0x00040000
+#define RG_EN_RX_DIV2_I_MSK 0xfffbffff
+#define RG_EN_RX_DIV2_SFT 18
+#define RG_EN_RX_DIV2_HI 18
+#define RG_EN_RX_DIV2_SZ 1
+#define RG_EN_RX_LOBUF_MSK 0x00080000
+#define RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
+#define RG_EN_RX_LOBUF_SFT 19
+#define RG_EN_RX_LOBUF_HI 19
+#define RG_EN_RX_LOBUF_SZ 1
+#define RG_EN_RX_TZ_MSK 0x00100000
+#define RG_EN_RX_TZ_I_MSK 0xffefffff
+#define RG_EN_RX_TZ_SFT 20
+#define RG_EN_RX_TZ_HI 20
+#define RG_EN_RX_TZ_SZ 1
+#define RG_EN_RX_FILTER_MSK 0x00200000
+#define RG_EN_RX_FILTER_I_MSK 0xffdfffff
+#define RG_EN_RX_FILTER_SFT 21
+#define RG_EN_RX_FILTER_HI 21
+#define RG_EN_RX_FILTER_SZ 1
+#define RG_EN_RX_HPF_MSK 0x00400000
+#define RG_EN_RX_HPF_I_MSK 0xffbfffff
+#define RG_EN_RX_HPF_SFT 22
+#define RG_EN_RX_HPF_HI 22
+#define RG_EN_RX_HPF_SZ 1
+#define RG_EN_RX_RSSI_MSK 0x00800000
+#define RG_EN_RX_RSSI_I_MSK 0xff7fffff
+#define RG_EN_RX_RSSI_SFT 23
+#define RG_EN_RX_RSSI_HI 23
+#define RG_EN_RX_RSSI_SZ 1
+#define RG_EN_ADC_MSK 0x01000000
+#define RG_EN_ADC_I_MSK 0xfeffffff
+#define RG_EN_ADC_SFT 24
+#define RG_EN_ADC_HI 24
+#define RG_EN_ADC_SZ 1
+#define RG_EN_TX_MOD_MSK 0x02000000
+#define RG_EN_TX_MOD_I_MSK 0xfdffffff
+#define RG_EN_TX_MOD_SFT 25
+#define RG_EN_TX_MOD_HI 25
+#define RG_EN_TX_MOD_SZ 1
+#define RG_EN_TX_DIV2_MSK 0x04000000
+#define RG_EN_TX_DIV2_I_MSK 0xfbffffff
+#define RG_EN_TX_DIV2_SFT 26
+#define RG_EN_TX_DIV2_HI 26
+#define RG_EN_TX_DIV2_SZ 1
+#define RG_EN_TX_DIV2_BUF_MSK 0x08000000
+#define RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
+#define RG_EN_TX_DIV2_BUF_SFT 27
+#define RG_EN_TX_DIV2_BUF_HI 27
+#define RG_EN_TX_DIV2_BUF_SZ 1
+#define RG_EN_TX_LOBF_MSK 0x10000000
+#define RG_EN_TX_LOBF_I_MSK 0xefffffff
+#define RG_EN_TX_LOBF_SFT 28
+#define RG_EN_TX_LOBF_HI 28
+#define RG_EN_TX_LOBF_SZ 1
+#define RG_EN_RX_LOBF_MSK 0x20000000
+#define RG_EN_RX_LOBF_I_MSK 0xdfffffff
+#define RG_EN_RX_LOBF_SFT 29
+#define RG_EN_RX_LOBF_HI 29
+#define RG_EN_RX_LOBF_SZ 1
+#define RG_SEL_DPLL_CLK_MSK 0x40000000
+#define RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
+#define RG_SEL_DPLL_CLK_SFT 30
+#define RG_SEL_DPLL_CLK_HI 30
+#define RG_SEL_DPLL_CLK_SZ 1
+#define RG_EN_CLK_960MBY13_UART_MSK 0x80000000
+#define RG_EN_CLK_960MBY13_UART_I_MSK 0x7fffffff
+#define RG_EN_CLK_960MBY13_UART_SFT 31
+#define RG_EN_CLK_960MBY13_UART_HI 31
+#define RG_EN_CLK_960MBY13_UART_SZ 1
+#define RG_EN_TX_DPD_MSK 0x00000001
+#define RG_EN_TX_DPD_I_MSK 0xfffffffe
+#define RG_EN_TX_DPD_SFT 0
+#define RG_EN_TX_DPD_HI 0
+#define RG_EN_TX_DPD_SZ 1
+#define RG_EN_TX_TSSI_MSK 0x00000002
+#define RG_EN_TX_TSSI_I_MSK 0xfffffffd
+#define RG_EN_TX_TSSI_SFT 1
+#define RG_EN_TX_TSSI_HI 1
+#define RG_EN_TX_TSSI_SZ 1
+#define RG_EN_RX_IQCAL_MSK 0x00000004
+#define RG_EN_RX_IQCAL_I_MSK 0xfffffffb
+#define RG_EN_RX_IQCAL_SFT 2
+#define RG_EN_RX_IQCAL_HI 2
+#define RG_EN_RX_IQCAL_SZ 1
+#define RG_EN_TX_DAC_CAL_MSK 0x00000008
+#define RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
+#define RG_EN_TX_DAC_CAL_SFT 3
+#define RG_EN_TX_DAC_CAL_HI 3
+#define RG_EN_TX_DAC_CAL_SZ 1
+#define RG_EN_TX_SELF_MIXER_MSK 0x00000010
+#define RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
+#define RG_EN_TX_SELF_MIXER_SFT 4
+#define RG_EN_TX_SELF_MIXER_HI 4
+#define RG_EN_TX_SELF_MIXER_SZ 1
+#define RG_EN_TX_DAC_OUT_MSK 0x00000020
+#define RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
+#define RG_EN_TX_DAC_OUT_SFT 5
+#define RG_EN_TX_DAC_OUT_HI 5
+#define RG_EN_TX_DAC_OUT_SZ 1
+#define RG_EN_LDO_RX_FE_MSK 0x00000040
+#define RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
+#define RG_EN_LDO_RX_FE_SFT 6
+#define RG_EN_LDO_RX_FE_HI 6
+#define RG_EN_LDO_RX_FE_SZ 1
+#define RG_EN_LDO_ABB_MSK 0x00000080
+#define RG_EN_LDO_ABB_I_MSK 0xffffff7f
+#define RG_EN_LDO_ABB_SFT 7
+#define RG_EN_LDO_ABB_HI 7
+#define RG_EN_LDO_ABB_SZ 1
+#define RG_EN_LDO_AFE_MSK 0x00000100
+#define RG_EN_LDO_AFE_I_MSK 0xfffffeff
+#define RG_EN_LDO_AFE_SFT 8
+#define RG_EN_LDO_AFE_HI 8
+#define RG_EN_LDO_AFE_SZ 1
+#define RG_EN_SX_CHPLDO_MSK 0x00000200
+#define RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
+#define RG_EN_SX_CHPLDO_SFT 9
+#define RG_EN_SX_CHPLDO_HI 9
+#define RG_EN_SX_CHPLDO_SZ 1
+#define RG_EN_SX_LOBFLDO_MSK 0x00000400
+#define RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
+#define RG_EN_SX_LOBFLDO_SFT 10
+#define RG_EN_SX_LOBFLDO_HI 10
+#define RG_EN_SX_LOBFLDO_SZ 1
+#define RG_EN_IREF_RX_MSK 0x00000800
+#define RG_EN_IREF_RX_I_MSK 0xfffff7ff
+#define RG_EN_IREF_RX_SFT 11
+#define RG_EN_IREF_RX_HI 11
+#define RG_EN_IREF_RX_SZ 1
+#define RG_EN_TX_DAC_VOUT_MSK 0x00002000
+#define RG_EN_TX_DAC_VOUT_I_MSK 0xffffdfff
+#define RG_EN_TX_DAC_VOUT_SFT 13
+#define RG_EN_TX_DAC_VOUT_HI 13
+#define RG_EN_TX_DAC_VOUT_SZ 1
+#define RG_EN_SX_LCK_BIN_MSK 0x00004000
+#define RG_EN_SX_LCK_BIN_I_MSK 0xffffbfff
+#define RG_EN_SX_LCK_BIN_SFT 14
+#define RG_EN_SX_LCK_BIN_HI 14
+#define RG_EN_SX_LCK_BIN_SZ 1
+#define RG_RTC_CAL_MODE_MSK 0x00010000
+#define RG_RTC_CAL_MODE_I_MSK 0xfffeffff
+#define RG_RTC_CAL_MODE_SFT 16
+#define RG_RTC_CAL_MODE_HI 16
+#define RG_RTC_CAL_MODE_SZ 1
+#define RG_EN_IQPAD_IOSW_MSK 0x00020000
+#define RG_EN_IQPAD_IOSW_I_MSK 0xfffdffff
+#define RG_EN_IQPAD_IOSW_SFT 17
+#define RG_EN_IQPAD_IOSW_HI 17
+#define RG_EN_IQPAD_IOSW_SZ 1
+#define RG_EN_TESTPAD_IOSW_MSK 0x00040000
+#define RG_EN_TESTPAD_IOSW_I_MSK 0xfffbffff
+#define RG_EN_TESTPAD_IOSW_SFT 18
+#define RG_EN_TESTPAD_IOSW_HI 18
+#define RG_EN_TESTPAD_IOSW_SZ 1
+#define RG_EN_TRXBF_BYPASS_MSK 0x00080000
+#define RG_EN_TRXBF_BYPASS_I_MSK 0xfff7ffff
+#define RG_EN_TRXBF_BYPASS_SFT 19
+#define RG_EN_TRXBF_BYPASS_HI 19
+#define RG_EN_TRXBF_BYPASS_SZ 1
+#define RG_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define RG_LDO_LEVEL_RX_FE_SFT 0
+#define RG_LDO_LEVEL_RX_FE_HI 2
+#define RG_LDO_LEVEL_RX_FE_SZ 3
+#define RG_LDO_LEVEL_ABB_MSK 0x00000038
+#define RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
+#define RG_LDO_LEVEL_ABB_SFT 3
+#define RG_LDO_LEVEL_ABB_HI 5
+#define RG_LDO_LEVEL_ABB_SZ 3
+#define RG_LDO_LEVEL_AFE_MSK 0x000001c0
+#define RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
+#define RG_LDO_LEVEL_AFE_SFT 6
+#define RG_LDO_LEVEL_AFE_HI 8
+#define RG_LDO_LEVEL_AFE_SZ 3
+#define RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
+#define RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
+#define RG_SX_LDO_CHP_LEVEL_SFT 9
+#define RG_SX_LDO_CHP_LEVEL_HI 11
+#define RG_SX_LDO_CHP_LEVEL_SZ 3
+#define RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
+#define RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
+#define RG_SX_LDO_LOBF_LEVEL_SFT 12
+#define RG_SX_LDO_LOBF_LEVEL_HI 14
+#define RG_SX_LDO_LOBF_LEVEL_SZ 3
+#define RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
+#define RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
+#define RG_SX_LDO_XOSC_LEVEL_SFT 15
+#define RG_SX_LDO_XOSC_LEVEL_HI 17
+#define RG_SX_LDO_XOSC_LEVEL_SZ 3
+#define RG_DP_LDO_LEVEL_MSK 0x001c0000
+#define RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
+#define RG_DP_LDO_LEVEL_SFT 18
+#define RG_DP_LDO_LEVEL_HI 20
+#define RG_DP_LDO_LEVEL_SZ 3
+#define RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
+#define RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
+#define RG_SX_LDO_VCO_LEVEL_SFT 21
+#define RG_SX_LDO_VCO_LEVEL_HI 23
+#define RG_SX_LDO_VCO_LEVEL_SZ 3
+#define RG_TX_LDO_TX_LEVEL_MSK 0x07000000
+#define RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
+#define RG_TX_LDO_TX_LEVEL_SFT 24
+#define RG_TX_LDO_TX_LEVEL_HI 26
+#define RG_TX_LDO_TX_LEVEL_SZ 3
+#define RG_EN_RX_PADSW_MSK 0x00000001
+#define RG_EN_RX_PADSW_I_MSK 0xfffffffe
+#define RG_EN_RX_PADSW_SFT 0
+#define RG_EN_RX_PADSW_HI 0
+#define RG_EN_RX_PADSW_SZ 1
+#define RG_EN_RX_TESTNODE_MSK 0x00000002
+#define RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
+#define RG_EN_RX_TESTNODE_SFT 1
+#define RG_EN_RX_TESTNODE_HI 1
+#define RG_EN_RX_TESTNODE_SZ 1
+#define RG_RX_ABBCFIX_MSK 0x00000004
+#define RG_RX_ABBCFIX_I_MSK 0xfffffffb
+#define RG_RX_ABBCFIX_SFT 2
+#define RG_RX_ABBCFIX_HI 2
+#define RG_RX_ABBCFIX_SZ 1
+#define RG_RX_ABBCTUNE_MSK 0x000001f8
+#define RG_RX_ABBCTUNE_I_MSK 0xfffffe07
+#define RG_RX_ABBCTUNE_SFT 3
+#define RG_RX_ABBCTUNE_HI 8
+#define RG_RX_ABBCTUNE_SZ 6
+#define RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
+#define RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
+#define RG_RX_ABBOUT_TRI_STATE_SFT 9
+#define RG_RX_ABBOUT_TRI_STATE_HI 9
+#define RG_RX_ABBOUT_TRI_STATE_SZ 1
+#define RG_RX_ABB_N_MODE_MSK 0x00000400
+#define RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
+#define RG_RX_ABB_N_MODE_SFT 10
+#define RG_RX_ABB_N_MODE_HI 10
+#define RG_RX_ABB_N_MODE_SZ 1
+#define RG_RX_EN_LOOPA_MSK 0x00000800
+#define RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
+#define RG_RX_EN_LOOPA_SFT 11
+#define RG_RX_EN_LOOPA_HI 11
+#define RG_RX_EN_LOOPA_SZ 1
+#define RG_RX_FILTERI1ST_MSK 0x00003000
+#define RG_RX_FILTERI1ST_I_MSK 0xffffcfff
+#define RG_RX_FILTERI1ST_SFT 12
+#define RG_RX_FILTERI1ST_HI 13
+#define RG_RX_FILTERI1ST_SZ 2
+#define RG_RX_FILTERI2ND_MSK 0x0000c000
+#define RG_RX_FILTERI2ND_I_MSK 0xffff3fff
+#define RG_RX_FILTERI2ND_SFT 14
+#define RG_RX_FILTERI2ND_HI 15
+#define RG_RX_FILTERI2ND_SZ 2
+#define RG_RX_FILTERI3RD_MSK 0x00030000
+#define RG_RX_FILTERI3RD_I_MSK 0xfffcffff
+#define RG_RX_FILTERI3RD_SFT 16
+#define RG_RX_FILTERI3RD_HI 17
+#define RG_RX_FILTERI3RD_SZ 2
+#define RG_RX_FILTERI_COURSE_MSK 0x000c0000
+#define RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
+#define RG_RX_FILTERI_COURSE_SFT 18
+#define RG_RX_FILTERI_COURSE_HI 19
+#define RG_RX_FILTERI_COURSE_SZ 2
+#define RG_RX_FILTERVCM_MSK 0x00300000
+#define RG_RX_FILTERVCM_I_MSK 0xffcfffff
+#define RG_RX_FILTERVCM_SFT 20
+#define RG_RX_FILTERVCM_HI 21
+#define RG_RX_FILTERVCM_SZ 2
+#define RG_RX_HPF3M_MSK 0x00400000
+#define RG_RX_HPF3M_I_MSK 0xffbfffff
+#define RG_RX_HPF3M_SFT 22
+#define RG_RX_HPF3M_HI 22
+#define RG_RX_HPF3M_SZ 1
+#define RG_RX_HPF300K_MSK 0x00800000
+#define RG_RX_HPF300K_I_MSK 0xff7fffff
+#define RG_RX_HPF300K_SFT 23
+#define RG_RX_HPF300K_HI 23
+#define RG_RX_HPF300K_SZ 1
+#define RG_RX_HPFI_MSK 0x03000000
+#define RG_RX_HPFI_I_MSK 0xfcffffff
+#define RG_RX_HPFI_SFT 24
+#define RG_RX_HPFI_HI 25
+#define RG_RX_HPFI_SZ 2
+#define RG_RX_HPF_FINALCORNER_MSK 0x0c000000
+#define RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
+#define RG_RX_HPF_FINALCORNER_SFT 26
+#define RG_RX_HPF_FINALCORNER_HI 27
+#define RG_RX_HPF_FINALCORNER_SZ 2
+#define RG_RX_HPF_SETTLE1_C_MSK 0x30000000
+#define RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
+#define RG_RX_HPF_SETTLE1_C_SFT 28
+#define RG_RX_HPF_SETTLE1_C_HI 29
+#define RG_RX_HPF_SETTLE1_C_SZ 2
+#define RG_RX_HPF_SETTLE1_R_MSK 0x00000003
+#define RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
+#define RG_RX_HPF_SETTLE1_R_SFT 0
+#define RG_RX_HPF_SETTLE1_R_HI 1
+#define RG_RX_HPF_SETTLE1_R_SZ 2
+#define RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
+#define RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
+#define RG_RX_HPF_SETTLE2_C_SFT 2
+#define RG_RX_HPF_SETTLE2_C_HI 3
+#define RG_RX_HPF_SETTLE2_C_SZ 2
+#define RG_RX_HPF_SETTLE2_R_MSK 0x00000030
+#define RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
+#define RG_RX_HPF_SETTLE2_R_SFT 4
+#define RG_RX_HPF_SETTLE2_R_HI 5
+#define RG_RX_HPF_SETTLE2_R_SZ 2
+#define RG_RX_HPF_VCMCON2_MSK 0x000000c0
+#define RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
+#define RG_RX_HPF_VCMCON2_SFT 6
+#define RG_RX_HPF_VCMCON2_HI 7
+#define RG_RX_HPF_VCMCON2_SZ 2
+#define RG_RX_HPF_VCMCON_MSK 0x00000300
+#define RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
+#define RG_RX_HPF_VCMCON_SFT 8
+#define RG_RX_HPF_VCMCON_HI 9
+#define RG_RX_HPF_VCMCON_SZ 2
+#define RG_RX_OUTVCM_MSK 0x00000c00
+#define RG_RX_OUTVCM_I_MSK 0xfffff3ff
+#define RG_RX_OUTVCM_SFT 10
+#define RG_RX_OUTVCM_HI 11
+#define RG_RX_OUTVCM_SZ 2
+#define RG_RX_TZI_MSK 0x00003000
+#define RG_RX_TZI_I_MSK 0xffffcfff
+#define RG_RX_TZI_SFT 12
+#define RG_RX_TZI_HI 13
+#define RG_RX_TZI_SZ 2
+#define RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
+#define RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
+#define RG_RX_TZ_OUT_TRISTATE_SFT 14
+#define RG_RX_TZ_OUT_TRISTATE_HI 14
+#define RG_RX_TZ_OUT_TRISTATE_SZ 1
+#define RG_RX_TZ_VCM_MSK 0x00018000
+#define RG_RX_TZ_VCM_I_MSK 0xfffe7fff
+#define RG_RX_TZ_VCM_SFT 15
+#define RG_RX_TZ_VCM_HI 16
+#define RG_RX_TZ_VCM_SZ 2
+#define RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
+#define RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
+#define RG_EN_RX_RSSI_TESTNODE_SFT 17
+#define RG_EN_RX_RSSI_TESTNODE_HI 19
+#define RG_EN_RX_RSSI_TESTNODE_SZ 3
+#define RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
+#define RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
+#define RG_RX_ADCRSSI_CLKSEL_SFT 20
+#define RG_RX_ADCRSSI_CLKSEL_HI 20
+#define RG_RX_ADCRSSI_CLKSEL_SZ 1
+#define RG_RX_ADCRSSI_VCM_MSK 0x00600000
+#define RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
+#define RG_RX_ADCRSSI_VCM_SFT 21
+#define RG_RX_ADCRSSI_VCM_HI 22
+#define RG_RX_ADCRSSI_VCM_SZ 2
+#define RG_RX_REC_LPFCORNER_MSK 0x01800000
+#define RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
+#define RG_RX_REC_LPFCORNER_SFT 23
+#define RG_RX_REC_LPFCORNER_HI 24
+#define RG_RX_REC_LPFCORNER_SZ 2
+#define RG_RSSI_CLOCK_GATING_MSK 0x02000000
+#define RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
+#define RG_RSSI_CLOCK_GATING_SFT 25
+#define RG_RSSI_CLOCK_GATING_HI 25
+#define RG_RSSI_CLOCK_GATING_SZ 1
+#define RG_TXPGA_CAPSW_MSK 0x00000003
+#define RG_TXPGA_CAPSW_I_MSK 0xfffffffc
+#define RG_TXPGA_CAPSW_SFT 0
+#define RG_TXPGA_CAPSW_HI 1
+#define RG_TXPGA_CAPSW_SZ 2
+#define RG_TXPGA_MAIN_MSK 0x000000fc
+#define RG_TXPGA_MAIN_I_MSK 0xffffff03
+#define RG_TXPGA_MAIN_SFT 2
+#define RG_TXPGA_MAIN_HI 7
+#define RG_TXPGA_MAIN_SZ 6
+#define RG_TXPGA_STEER_MSK 0x00003f00
+#define RG_TXPGA_STEER_I_MSK 0xffffc0ff
+#define RG_TXPGA_STEER_SFT 8
+#define RG_TXPGA_STEER_HI 13
+#define RG_TXPGA_STEER_SZ 6
+#define RG_TXMOD_GMCELL_MSK 0x0000c000
+#define RG_TXMOD_GMCELL_I_MSK 0xffff3fff
+#define RG_TXMOD_GMCELL_SFT 14
+#define RG_TXMOD_GMCELL_HI 15
+#define RG_TXMOD_GMCELL_SZ 2
+#define RG_TXLPF_GMCELL_MSK 0x00030000
+#define RG_TXLPF_GMCELL_I_MSK 0xfffcffff
+#define RG_TXLPF_GMCELL_SFT 16
+#define RG_TXLPF_GMCELL_HI 17
+#define RG_TXLPF_GMCELL_SZ 2
+#define RG_PACELL_EN_MSK 0x001c0000
+#define RG_PACELL_EN_I_MSK 0xffe3ffff
+#define RG_PACELL_EN_SFT 18
+#define RG_PACELL_EN_HI 20
+#define RG_PACELL_EN_SZ 3
+#define RG_PABIAS_CTRL_MSK 0x01e00000
+#define RG_PABIAS_CTRL_I_MSK 0xfe1fffff
+#define RG_PABIAS_CTRL_SFT 21
+#define RG_PABIAS_CTRL_HI 24
+#define RG_PABIAS_CTRL_SZ 4
+#define RG_TX_DIV_VSET_MSK 0x0c000000
+#define RG_TX_DIV_VSET_I_MSK 0xf3ffffff
+#define RG_TX_DIV_VSET_SFT 26
+#define RG_TX_DIV_VSET_HI 27
+#define RG_TX_DIV_VSET_SZ 2
+#define RG_TX_LOBUF_VSET_MSK 0x30000000
+#define RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
+#define RG_TX_LOBUF_VSET_SFT 28
+#define RG_TX_LOBUF_VSET_HI 29
+#define RG_TX_LOBUF_VSET_SZ 2
+#define RG_RX_SQDC_MSK 0x00000007
+#define RG_RX_SQDC_I_MSK 0xfffffff8
+#define RG_RX_SQDC_SFT 0
+#define RG_RX_SQDC_HI 2
+#define RG_RX_SQDC_SZ 3
+#define RG_RX_DIV2_CORE_MSK 0x00000018
+#define RG_RX_DIV2_CORE_I_MSK 0xffffffe7
+#define RG_RX_DIV2_CORE_SFT 3
+#define RG_RX_DIV2_CORE_HI 4
+#define RG_RX_DIV2_CORE_SZ 2
+#define RG_RX_LOBUF_MSK 0x00000060
+#define RG_RX_LOBUF_I_MSK 0xffffff9f
+#define RG_RX_LOBUF_SFT 5
+#define RG_RX_LOBUF_HI 6
+#define RG_RX_LOBUF_SZ 2
+#define RG_TX_DPDGM_BIAS_MSK 0x00000780
+#define RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
+#define RG_TX_DPDGM_BIAS_SFT 7
+#define RG_TX_DPDGM_BIAS_HI 10
+#define RG_TX_DPDGM_BIAS_SZ 4
+#define RG_TX_DPD_DIV_MSK 0x00007800
+#define RG_TX_DPD_DIV_I_MSK 0xffff87ff
+#define RG_TX_DPD_DIV_SFT 11
+#define RG_TX_DPD_DIV_HI 14
+#define RG_TX_DPD_DIV_SZ 4
+#define RG_TX_TSSI_BIAS_MSK 0x00038000
+#define RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
+#define RG_TX_TSSI_BIAS_SFT 15
+#define RG_TX_TSSI_BIAS_HI 17
+#define RG_TX_TSSI_BIAS_SZ 3
+#define RG_TX_TSSI_DIV_MSK 0x001c0000
+#define RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
+#define RG_TX_TSSI_DIV_SFT 18
+#define RG_TX_TSSI_DIV_HI 20
+#define RG_TX_TSSI_DIV_SZ 3
+#define RG_TX_TSSI_TESTMODE_MSK 0x00200000
+#define RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
+#define RG_TX_TSSI_TESTMODE_SFT 21
+#define RG_TX_TSSI_TESTMODE_HI 21
+#define RG_TX_TSSI_TESTMODE_SZ 1
+#define RG_TX_TSSI_TEST_MSK 0x00c00000
+#define RG_TX_TSSI_TEST_I_MSK 0xff3fffff
+#define RG_TX_TSSI_TEST_SFT 22
+#define RG_TX_TSSI_TEST_HI 23
+#define RG_TX_TSSI_TEST_SZ 2
+#define RG_PACASCODE_CTRL_MSK 0x07000000
+#define RG_PACASCODE_CTRL_I_MSK 0xf8ffffff
+#define RG_PACASCODE_CTRL_SFT 24
+#define RG_PACASCODE_CTRL_HI 26
+#define RG_PACASCODE_CTRL_SZ 3
+#define RG_RX_HG_LNA_GC_MSK 0x00000003
+#define RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_HG_LNA_GC_SFT 0
+#define RG_RX_HG_LNA_GC_HI 1
+#define RG_RX_HG_LNA_GC_SZ 2
+#define RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_HG_LNAHGN_BIAS_SFT 2
+#define RG_RX_HG_LNAHGN_BIAS_HI 5
+#define RG_RX_HG_LNAHGN_BIAS_SZ 4
+#define RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_HG_LNAHGP_BIAS_SFT 6
+#define RG_RX_HG_LNAHGP_BIAS_HI 9
+#define RG_RX_HG_LNAHGP_BIAS_SZ 4
+#define RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_HG_LNALG_BIAS_SFT 10
+#define RG_RX_HG_LNALG_BIAS_HI 13
+#define RG_RX_HG_LNALG_BIAS_SZ 4
+#define RG_RX_HG_TZ_GC_MSK 0x0000c000
+#define RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_HG_TZ_GC_SFT 14
+#define RG_RX_HG_TZ_GC_HI 15
+#define RG_RX_HG_TZ_GC_SZ 2
+#define RG_RX_HG_TZ_CAP_MSK 0x00070000
+#define RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_HG_TZ_CAP_SFT 16
+#define RG_RX_HG_TZ_CAP_HI 18
+#define RG_RX_HG_TZ_CAP_SZ 3
+#define RG_RX_MG_LNA_GC_MSK 0x00000003
+#define RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_MG_LNA_GC_SFT 0
+#define RG_RX_MG_LNA_GC_HI 1
+#define RG_RX_MG_LNA_GC_SZ 2
+#define RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_MG_LNAHGN_BIAS_SFT 2
+#define RG_RX_MG_LNAHGN_BIAS_HI 5
+#define RG_RX_MG_LNAHGN_BIAS_SZ 4
+#define RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_MG_LNAHGP_BIAS_SFT 6
+#define RG_RX_MG_LNAHGP_BIAS_HI 9
+#define RG_RX_MG_LNAHGP_BIAS_SZ 4
+#define RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_MG_LNALG_BIAS_SFT 10
+#define RG_RX_MG_LNALG_BIAS_HI 13
+#define RG_RX_MG_LNALG_BIAS_SZ 4
+#define RG_RX_MG_TZ_GC_MSK 0x0000c000
+#define RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_MG_TZ_GC_SFT 14
+#define RG_RX_MG_TZ_GC_HI 15
+#define RG_RX_MG_TZ_GC_SZ 2
+#define RG_RX_MG_TZ_CAP_MSK 0x00070000
+#define RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_MG_TZ_CAP_SFT 16
+#define RG_RX_MG_TZ_CAP_HI 18
+#define RG_RX_MG_TZ_CAP_SZ 3
+#define RG_RX_LG_LNA_GC_MSK 0x00000003
+#define RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_LG_LNA_GC_SFT 0
+#define RG_RX_LG_LNA_GC_HI 1
+#define RG_RX_LG_LNA_GC_SZ 2
+#define RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_LG_LNAHGN_BIAS_SFT 2
+#define RG_RX_LG_LNAHGN_BIAS_HI 5
+#define RG_RX_LG_LNAHGN_BIAS_SZ 4
+#define RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_LG_LNAHGP_BIAS_SFT 6
+#define RG_RX_LG_LNAHGP_BIAS_HI 9
+#define RG_RX_LG_LNAHGP_BIAS_SZ 4
+#define RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_LG_LNALG_BIAS_SFT 10
+#define RG_RX_LG_LNALG_BIAS_HI 13
+#define RG_RX_LG_LNALG_BIAS_SZ 4
+#define RG_RX_LG_TZ_GC_MSK 0x0000c000
+#define RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_LG_TZ_GC_SFT 14
+#define RG_RX_LG_TZ_GC_HI 15
+#define RG_RX_LG_TZ_GC_SZ 2
+#define RG_RX_LG_TZ_CAP_MSK 0x00070000
+#define RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_LG_TZ_CAP_SFT 16
+#define RG_RX_LG_TZ_CAP_HI 18
+#define RG_RX_LG_TZ_CAP_SZ 3
+#define RG_RX_ULG_LNA_GC_MSK 0x00000003
+#define RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_ULG_LNA_GC_SFT 0
+#define RG_RX_ULG_LNA_GC_HI 1
+#define RG_RX_ULG_LNA_GC_SZ 2
+#define RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_ULG_LNAHGN_BIAS_SFT 2
+#define RG_RX_ULG_LNAHGN_BIAS_HI 5
+#define RG_RX_ULG_LNAHGN_BIAS_SZ 4
+#define RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_ULG_LNAHGP_BIAS_SFT 6
+#define RG_RX_ULG_LNAHGP_BIAS_HI 9
+#define RG_RX_ULG_LNAHGP_BIAS_SZ 4
+#define RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_ULG_LNALG_BIAS_SFT 10
+#define RG_RX_ULG_LNALG_BIAS_HI 13
+#define RG_RX_ULG_LNALG_BIAS_SZ 4
+#define RG_RX_ULG_TZ_GC_MSK 0x0000c000
+#define RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_ULG_TZ_GC_SFT 14
+#define RG_RX_ULG_TZ_GC_HI 15
+#define RG_RX_ULG_TZ_GC_SZ 2
+#define RG_RX_ULG_TZ_CAP_MSK 0x00070000
+#define RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_ULG_TZ_CAP_SFT 16
+#define RG_RX_ULG_TZ_CAP_HI 18
+#define RG_RX_ULG_TZ_CAP_SZ 3
+#define RG_HPF1_FAST_SET_X_MSK 0x00000001
+#define RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
+#define RG_HPF1_FAST_SET_X_SFT 0
+#define RG_HPF1_FAST_SET_X_HI 0
+#define RG_HPF1_FAST_SET_X_SZ 1
+#define RG_HPF1_FAST_SET_Y_MSK 0x00000002
+#define RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
+#define RG_HPF1_FAST_SET_Y_SFT 1
+#define RG_HPF1_FAST_SET_Y_HI 1
+#define RG_HPF1_FAST_SET_Y_SZ 1
+#define RG_HPF1_FAST_SET_Z_MSK 0x00000004
+#define RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
+#define RG_HPF1_FAST_SET_Z_SFT 2
+#define RG_HPF1_FAST_SET_Z_HI 2
+#define RG_HPF1_FAST_SET_Z_SZ 1
+#define RG_HPF_T1A_MSK 0x00000018
+#define RG_HPF_T1A_I_MSK 0xffffffe7
+#define RG_HPF_T1A_SFT 3
+#define RG_HPF_T1A_HI 4
+#define RG_HPF_T1A_SZ 2
+#define RG_HPF_T1B_MSK 0x00000060
+#define RG_HPF_T1B_I_MSK 0xffffff9f
+#define RG_HPF_T1B_SFT 5
+#define RG_HPF_T1B_HI 6
+#define RG_HPF_T1B_SZ 2
+#define RG_HPF_T1C_MSK 0x00000180
+#define RG_HPF_T1C_I_MSK 0xfffffe7f
+#define RG_HPF_T1C_SFT 7
+#define RG_HPF_T1C_HI 8
+#define RG_HPF_T1C_SZ 2
+#define RG_RX_LNA_TRI_SEL_MSK 0x00000600
+#define RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
+#define RG_RX_LNA_TRI_SEL_SFT 9
+#define RG_RX_LNA_TRI_SEL_HI 10
+#define RG_RX_LNA_TRI_SEL_SZ 2
+#define RG_RX_LNA_SETTLE_MSK 0x00001800
+#define RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
+#define RG_RX_LNA_SETTLE_SFT 11
+#define RG_RX_LNA_SETTLE_HI 12
+#define RG_RX_LNA_SETTLE_SZ 2
+#define RG_TXGAIN_PHYCTRL_MSK 0x00002000
+#define RG_TXGAIN_PHYCTRL_I_MSK 0xffffdfff
+#define RG_TXGAIN_PHYCTRL_SFT 13
+#define RG_TXGAIN_PHYCTRL_HI 13
+#define RG_TXGAIN_PHYCTRL_SZ 1
+#define RG_TX_GAIN_MSK 0x003fc000
+#define RG_TX_GAIN_I_MSK 0xffc03fff
+#define RG_TX_GAIN_SFT 14
+#define RG_TX_GAIN_HI 21
+#define RG_TX_GAIN_SZ 8
+#define RG_TXGAIN_MANUAL_MSK 0x00400000
+#define RG_TXGAIN_MANUAL_I_MSK 0xffbfffff
+#define RG_TXGAIN_MANUAL_SFT 22
+#define RG_TXGAIN_MANUAL_HI 22
+#define RG_TXGAIN_MANUAL_SZ 1
+#define RG_TX_GAIN_OFFSET_MSK 0x07800000
+#define RG_TX_GAIN_OFFSET_I_MSK 0xf87fffff
+#define RG_TX_GAIN_OFFSET_SFT 23
+#define RG_TX_GAIN_OFFSET_HI 26
+#define RG_TX_GAIN_OFFSET_SZ 4
+#define RG_ADC_CLKSEL_MSK 0x00000001
+#define RG_ADC_CLKSEL_I_MSK 0xfffffffe
+#define RG_ADC_CLKSEL_SFT 0
+#define RG_ADC_CLKSEL_HI 0
+#define RG_ADC_CLKSEL_SZ 1
+#define RG_ADC_DIBIAS_MSK 0x00000006
+#define RG_ADC_DIBIAS_I_MSK 0xfffffff9
+#define RG_ADC_DIBIAS_SFT 1
+#define RG_ADC_DIBIAS_HI 2
+#define RG_ADC_DIBIAS_SZ 2
+#define RG_ADC_DIVR_MSK 0x00000008
+#define RG_ADC_DIVR_I_MSK 0xfffffff7
+#define RG_ADC_DIVR_SFT 3
+#define RG_ADC_DIVR_HI 3
+#define RG_ADC_DIVR_SZ 1
+#define RG_ADC_DVCMI_MSK 0x00000030
+#define RG_ADC_DVCMI_I_MSK 0xffffffcf
+#define RG_ADC_DVCMI_SFT 4
+#define RG_ADC_DVCMI_HI 5
+#define RG_ADC_DVCMI_SZ 2
+#define RG_ADC_SAMSEL_MSK 0x000003c0
+#define RG_ADC_SAMSEL_I_MSK 0xfffffc3f
+#define RG_ADC_SAMSEL_SFT 6
+#define RG_ADC_SAMSEL_HI 9
+#define RG_ADC_SAMSEL_SZ 4
+#define RG_ADC_STNBY_MSK 0x00000400
+#define RG_ADC_STNBY_I_MSK 0xfffffbff
+#define RG_ADC_STNBY_SFT 10
+#define RG_ADC_STNBY_HI 10
+#define RG_ADC_STNBY_SZ 1
+#define RG_ADC_TESTMODE_MSK 0x00000800
+#define RG_ADC_TESTMODE_I_MSK 0xfffff7ff
+#define RG_ADC_TESTMODE_SFT 11
+#define RG_ADC_TESTMODE_HI 11
+#define RG_ADC_TESTMODE_SZ 1
+#define RG_ADC_TSEL_MSK 0x0000f000
+#define RG_ADC_TSEL_I_MSK 0xffff0fff
+#define RG_ADC_TSEL_SFT 12
+#define RG_ADC_TSEL_HI 15
+#define RG_ADC_TSEL_SZ 4
+#define RG_ADC_VRSEL_MSK 0x00030000
+#define RG_ADC_VRSEL_I_MSK 0xfffcffff
+#define RG_ADC_VRSEL_SFT 16
+#define RG_ADC_VRSEL_HI 17
+#define RG_ADC_VRSEL_SZ 2
+#define RG_DICMP_MSK 0x000c0000
+#define RG_DICMP_I_MSK 0xfff3ffff
+#define RG_DICMP_SFT 18
+#define RG_DICMP_HI 19
+#define RG_DICMP_SZ 2
+#define RG_DIOP_MSK 0x00300000
+#define RG_DIOP_I_MSK 0xffcfffff
+#define RG_DIOP_SFT 20
+#define RG_DIOP_HI 21
+#define RG_DIOP_SZ 2
+#define RG_SARADC_VRSEL_MSK 0x00c00000
+#define RG_SARADC_VRSEL_I_MSK 0xff3fffff
+#define RG_SARADC_VRSEL_SFT 22
+#define RG_SARADC_VRSEL_HI 23
+#define RG_SARADC_VRSEL_SZ 2
+#define RG_EN_SAR_TEST_MSK 0x03000000
+#define RG_EN_SAR_TEST_I_MSK 0xfcffffff
+#define RG_EN_SAR_TEST_SFT 24
+#define RG_EN_SAR_TEST_HI 25
+#define RG_EN_SAR_TEST_SZ 2
+#define RG_SARADC_THERMAL_MSK 0x04000000
+#define RG_SARADC_THERMAL_I_MSK 0xfbffffff
+#define RG_SARADC_THERMAL_SFT 26
+#define RG_SARADC_THERMAL_HI 26
+#define RG_SARADC_THERMAL_SZ 1
+#define RG_SARADC_TSSI_MSK 0x08000000
+#define RG_SARADC_TSSI_I_MSK 0xf7ffffff
+#define RG_SARADC_TSSI_SFT 27
+#define RG_SARADC_TSSI_HI 27
+#define RG_SARADC_TSSI_SZ 1
+#define RG_CLK_SAR_SEL_MSK 0x30000000
+#define RG_CLK_SAR_SEL_I_MSK 0xcfffffff
+#define RG_CLK_SAR_SEL_SFT 28
+#define RG_CLK_SAR_SEL_HI 29
+#define RG_CLK_SAR_SEL_SZ 2
+#define RG_EN_SARADC_MSK 0x40000000
+#define RG_EN_SARADC_I_MSK 0xbfffffff
+#define RG_EN_SARADC_SFT 30
+#define RG_EN_SARADC_HI 30
+#define RG_EN_SARADC_SZ 1
+#define RG_DACI1ST_MSK 0x00000003
+#define RG_DACI1ST_I_MSK 0xfffffffc
+#define RG_DACI1ST_SFT 0
+#define RG_DACI1ST_HI 1
+#define RG_DACI1ST_SZ 2
+#define RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
+#define RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
+#define RG_TX_DACLPF_ICOURSE_SFT 2
+#define RG_TX_DACLPF_ICOURSE_HI 3
+#define RG_TX_DACLPF_ICOURSE_SZ 2
+#define RG_TX_DACLPF_IFINE_MSK 0x00000030
+#define RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define RG_TX_DACLPF_IFINE_SFT 4
+#define RG_TX_DACLPF_IFINE_HI 5
+#define RG_TX_DACLPF_IFINE_SZ 2
+#define RG_TX_DACLPF_VCM_MSK 0x000000c0
+#define RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define RG_TX_DACLPF_VCM_SFT 6
+#define RG_TX_DACLPF_VCM_HI 7
+#define RG_TX_DACLPF_VCM_SZ 2
+#define RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
+#define RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
+#define RG_TX_DAC_CKEDGE_SEL_SFT 8
+#define RG_TX_DAC_CKEDGE_SEL_HI 8
+#define RG_TX_DAC_CKEDGE_SEL_SZ 1
+#define RG_TX_DAC_IBIAS_MSK 0x00000600
+#define RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
+#define RG_TX_DAC_IBIAS_SFT 9
+#define RG_TX_DAC_IBIAS_HI 10
+#define RG_TX_DAC_IBIAS_SZ 2
+#define RG_TX_DAC_OS_MSK 0x00003800
+#define RG_TX_DAC_OS_I_MSK 0xffffc7ff
+#define RG_TX_DAC_OS_SFT 11
+#define RG_TX_DAC_OS_HI 13
+#define RG_TX_DAC_OS_SZ 3
+#define RG_TX_DAC_RCAL_MSK 0x0000c000
+#define RG_TX_DAC_RCAL_I_MSK 0xffff3fff
+#define RG_TX_DAC_RCAL_SFT 14
+#define RG_TX_DAC_RCAL_HI 15
+#define RG_TX_DAC_RCAL_SZ 2
+#define RG_TX_DAC_TSEL_MSK 0x000f0000
+#define RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
+#define RG_TX_DAC_TSEL_SFT 16
+#define RG_TX_DAC_TSEL_HI 19
+#define RG_TX_DAC_TSEL_SZ 4
+#define RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
+#define RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
+#define RG_TX_EN_VOLTAGE_IN_SFT 20
+#define RG_TX_EN_VOLTAGE_IN_HI 20
+#define RG_TX_EN_VOLTAGE_IN_SZ 1
+#define RG_TXLPF_BYPASS_MSK 0x00200000
+#define RG_TXLPF_BYPASS_I_MSK 0xffdfffff
+#define RG_TXLPF_BYPASS_SFT 21
+#define RG_TXLPF_BYPASS_HI 21
+#define RG_TXLPF_BYPASS_SZ 1
+#define RG_TXLPF_BOOSTI_MSK 0x00400000
+#define RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
+#define RG_TXLPF_BOOSTI_SFT 22
+#define RG_TXLPF_BOOSTI_HI 22
+#define RG_TXLPF_BOOSTI_SZ 1
+#define RG_TX_DAC_IOFFSET_MSK 0x07800000
+#define RG_TX_DAC_IOFFSET_I_MSK 0xf87fffff
+#define RG_TX_DAC_IOFFSET_SFT 23
+#define RG_TX_DAC_IOFFSET_HI 26
+#define RG_TX_DAC_IOFFSET_SZ 4
+#define RG_TX_DAC_QOFFSET_MSK 0x78000000
+#define RG_TX_DAC_QOFFSET_I_MSK 0x87ffffff
+#define RG_TX_DAC_QOFFSET_SFT 27
+#define RG_TX_DAC_QOFFSET_HI 30
+#define RG_TX_DAC_QOFFSET_SZ 4
+#define RG_EN_SX_R3_MSK 0x00000001
+#define RG_EN_SX_R3_I_MSK 0xfffffffe
+#define RG_EN_SX_R3_SFT 0
+#define RG_EN_SX_R3_HI 0
+#define RG_EN_SX_R3_SZ 1
+#define RG_EN_SX_CH_MSK 0x00000002
+#define RG_EN_SX_CH_I_MSK 0xfffffffd
+#define RG_EN_SX_CH_SFT 1
+#define RG_EN_SX_CH_HI 1
+#define RG_EN_SX_CH_SZ 1
+#define RG_EN_SX_CHP_MSK 0x00000004
+#define RG_EN_SX_CHP_I_MSK 0xfffffffb
+#define RG_EN_SX_CHP_SFT 2
+#define RG_EN_SX_CHP_HI 2
+#define RG_EN_SX_CHP_SZ 1
+#define RG_EN_SX_DIVCK_MSK 0x00000008
+#define RG_EN_SX_DIVCK_I_MSK 0xfffffff7
+#define RG_EN_SX_DIVCK_SFT 3
+#define RG_EN_SX_DIVCK_HI 3
+#define RG_EN_SX_DIVCK_SZ 1
+#define RG_EN_SX_VCOBF_MSK 0x00000010
+#define RG_EN_SX_VCOBF_I_MSK 0xffffffef
+#define RG_EN_SX_VCOBF_SFT 4
+#define RG_EN_SX_VCOBF_HI 4
+#define RG_EN_SX_VCOBF_SZ 1
+#define RG_EN_SX_VCO_MSK 0x00000020
+#define RG_EN_SX_VCO_I_MSK 0xffffffdf
+#define RG_EN_SX_VCO_SFT 5
+#define RG_EN_SX_VCO_HI 5
+#define RG_EN_SX_VCO_SZ 1
+#define RG_EN_SX_MOD_MSK 0x00000040
+#define RG_EN_SX_MOD_I_MSK 0xffffffbf
+#define RG_EN_SX_MOD_SFT 6
+#define RG_EN_SX_MOD_HI 6
+#define RG_EN_SX_MOD_SZ 1
+#define RG_EN_SX_DITHER_MSK 0x00000100
+#define RG_EN_SX_DITHER_I_MSK 0xfffffeff
+#define RG_EN_SX_DITHER_SFT 8
+#define RG_EN_SX_DITHER_HI 8
+#define RG_EN_SX_DITHER_SZ 1
+#define RG_EN_SX_VT_MON_MSK 0x00000800
+#define RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
+#define RG_EN_SX_VT_MON_SFT 11
+#define RG_EN_SX_VT_MON_HI 11
+#define RG_EN_SX_VT_MON_SZ 1
+#define RG_EN_SX_VT_MON_DG_MSK 0x00001000
+#define RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
+#define RG_EN_SX_VT_MON_DG_SFT 12
+#define RG_EN_SX_VT_MON_DG_HI 12
+#define RG_EN_SX_VT_MON_DG_SZ 1
+#define RG_EN_SX_DIV_MSK 0x00002000
+#define RG_EN_SX_DIV_I_MSK 0xffffdfff
+#define RG_EN_SX_DIV_SFT 13
+#define RG_EN_SX_DIV_HI 13
+#define RG_EN_SX_DIV_SZ 1
+#define RG_EN_SX_LPF_MSK 0x00004000
+#define RG_EN_SX_LPF_I_MSK 0xffffbfff
+#define RG_EN_SX_LPF_SFT 14
+#define RG_EN_SX_LPF_HI 14
+#define RG_EN_SX_LPF_SZ 1
+#define RG_EN_DPL_MOD_MSK 0x00008000
+#define RG_EN_DPL_MOD_I_MSK 0xffff7fff
+#define RG_EN_DPL_MOD_SFT 15
+#define RG_EN_DPL_MOD_HI 15
+#define RG_EN_DPL_MOD_SZ 1
+#define RG_DPL_MOD_ORDER_MSK 0x00030000
+#define RG_DPL_MOD_ORDER_I_MSK 0xfffcffff
+#define RG_DPL_MOD_ORDER_SFT 16
+#define RG_DPL_MOD_ORDER_HI 17
+#define RG_DPL_MOD_ORDER_SZ 2
+#define RG_SX_RFCTRL_F_MSK 0x00ffffff
+#define RG_SX_RFCTRL_F_I_MSK 0xff000000
+#define RG_SX_RFCTRL_F_SFT 0
+#define RG_SX_RFCTRL_F_HI 23
+#define RG_SX_RFCTRL_F_SZ 24
+#define RG_SX_SEL_CP_MSK 0x0f000000
+#define RG_SX_SEL_CP_I_MSK 0xf0ffffff
+#define RG_SX_SEL_CP_SFT 24
+#define RG_SX_SEL_CP_HI 27
+#define RG_SX_SEL_CP_SZ 4
+#define RG_SX_SEL_CS_MSK 0xf0000000
+#define RG_SX_SEL_CS_I_MSK 0x0fffffff
+#define RG_SX_SEL_CS_SFT 28
+#define RG_SX_SEL_CS_HI 31
+#define RG_SX_SEL_CS_SZ 4
+#define RG_SX_RFCTRL_CH_MSK 0x000007ff
+#define RG_SX_RFCTRL_CH_I_MSK 0xfffff800
+#define RG_SX_RFCTRL_CH_SFT 0
+#define RG_SX_RFCTRL_CH_HI 10
+#define RG_SX_RFCTRL_CH_SZ 11
+#define RG_SX_SEL_C3_MSK 0x00007800
+#define RG_SX_SEL_C3_I_MSK 0xffff87ff
+#define RG_SX_SEL_C3_SFT 11
+#define RG_SX_SEL_C3_HI 14
+#define RG_SX_SEL_C3_SZ 4
+#define RG_SX_SEL_RS_MSK 0x000f8000
+#define RG_SX_SEL_RS_I_MSK 0xfff07fff
+#define RG_SX_SEL_RS_SFT 15
+#define RG_SX_SEL_RS_HI 19
+#define RG_SX_SEL_RS_SZ 5
+#define RG_SX_SEL_R3_MSK 0x01f00000
+#define RG_SX_SEL_R3_I_MSK 0xfe0fffff
+#define RG_SX_SEL_R3_SFT 20
+#define RG_SX_SEL_R3_HI 24
+#define RG_SX_SEL_R3_SZ 5
+#define RG_SX_SEL_ICHP_MSK 0x0000001f
+#define RG_SX_SEL_ICHP_I_MSK 0xffffffe0
+#define RG_SX_SEL_ICHP_SFT 0
+#define RG_SX_SEL_ICHP_HI 4
+#define RG_SX_SEL_ICHP_SZ 5
+#define RG_SX_SEL_PCHP_MSK 0x000003e0
+#define RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
+#define RG_SX_SEL_PCHP_SFT 5
+#define RG_SX_SEL_PCHP_HI 9
+#define RG_SX_SEL_PCHP_SZ 5
+#define RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
+#define RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
+#define RG_SX_SEL_CHP_REGOP_SFT 10
+#define RG_SX_SEL_CHP_REGOP_HI 13
+#define RG_SX_SEL_CHP_REGOP_SZ 4
+#define RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
+#define RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
+#define RG_SX_SEL_CHP_UNIOP_SFT 14
+#define RG_SX_SEL_CHP_UNIOP_HI 17
+#define RG_SX_SEL_CHP_UNIOP_SZ 4
+#define RG_SX_CHP_IOST_POL_MSK 0x00040000
+#define RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
+#define RG_SX_CHP_IOST_POL_SFT 18
+#define RG_SX_CHP_IOST_POL_HI 18
+#define RG_SX_CHP_IOST_POL_SZ 1
+#define RG_SX_CHP_IOST_MSK 0x00380000
+#define RG_SX_CHP_IOST_I_MSK 0xffc7ffff
+#define RG_SX_CHP_IOST_SFT 19
+#define RG_SX_CHP_IOST_HI 21
+#define RG_SX_CHP_IOST_SZ 3
+#define RG_SX_PFDSEL_MSK 0x00400000
+#define RG_SX_PFDSEL_I_MSK 0xffbfffff
+#define RG_SX_PFDSEL_SFT 22
+#define RG_SX_PFDSEL_HI 22
+#define RG_SX_PFDSEL_SZ 1
+#define RG_SX_PFD_SET_MSK 0x00800000
+#define RG_SX_PFD_SET_I_MSK 0xff7fffff
+#define RG_SX_PFD_SET_SFT 23
+#define RG_SX_PFD_SET_HI 23
+#define RG_SX_PFD_SET_SZ 1
+#define RG_SX_PFD_SET1_MSK 0x01000000
+#define RG_SX_PFD_SET1_I_MSK 0xfeffffff
+#define RG_SX_PFD_SET1_SFT 24
+#define RG_SX_PFD_SET1_HI 24
+#define RG_SX_PFD_SET1_SZ 1
+#define RG_SX_PFD_SET2_MSK 0x02000000
+#define RG_SX_PFD_SET2_I_MSK 0xfdffffff
+#define RG_SX_PFD_SET2_SFT 25
+#define RG_SX_PFD_SET2_HI 25
+#define RG_SX_PFD_SET2_SZ 1
+#define RG_SX_VBNCAS_SEL_MSK 0x04000000
+#define RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
+#define RG_SX_VBNCAS_SEL_SFT 26
+#define RG_SX_VBNCAS_SEL_HI 26
+#define RG_SX_VBNCAS_SEL_SZ 1
+#define RG_SX_PFD_RST_H_MSK 0x08000000
+#define RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
+#define RG_SX_PFD_RST_H_SFT 27
+#define RG_SX_PFD_RST_H_HI 27
+#define RG_SX_PFD_RST_H_SZ 1
+#define RG_SX_PFD_TRUP_MSK 0x10000000
+#define RG_SX_PFD_TRUP_I_MSK 0xefffffff
+#define RG_SX_PFD_TRUP_SFT 28
+#define RG_SX_PFD_TRUP_HI 28
+#define RG_SX_PFD_TRUP_SZ 1
+#define RG_SX_PFD_TRDN_MSK 0x20000000
+#define RG_SX_PFD_TRDN_I_MSK 0xdfffffff
+#define RG_SX_PFD_TRDN_SFT 29
+#define RG_SX_PFD_TRDN_HI 29
+#define RG_SX_PFD_TRDN_SZ 1
+#define RG_SX_PFD_TRSEL_MSK 0x40000000
+#define RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
+#define RG_SX_PFD_TRSEL_SFT 30
+#define RG_SX_PFD_TRSEL_HI 30
+#define RG_SX_PFD_TRSEL_SZ 1
+#define RG_SX_VCOBA_R_MSK 0x00000007
+#define RG_SX_VCOBA_R_I_MSK 0xfffffff8
+#define RG_SX_VCOBA_R_SFT 0
+#define RG_SX_VCOBA_R_HI 2
+#define RG_SX_VCOBA_R_SZ 3
+#define RG_SX_VCORSEL_MSK 0x000000f8
+#define RG_SX_VCORSEL_I_MSK 0xffffff07
+#define RG_SX_VCORSEL_SFT 3
+#define RG_SX_VCORSEL_HI 7
+#define RG_SX_VCORSEL_SZ 5
+#define RG_SX_VCOCUSEL_MSK 0x00000f00
+#define RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
+#define RG_SX_VCOCUSEL_SFT 8
+#define RG_SX_VCOCUSEL_HI 11
+#define RG_SX_VCOCUSEL_SZ 4
+#define RG_SX_RXBFSEL_MSK 0x0000f000
+#define RG_SX_RXBFSEL_I_MSK 0xffff0fff
+#define RG_SX_RXBFSEL_SFT 12
+#define RG_SX_RXBFSEL_HI 15
+#define RG_SX_RXBFSEL_SZ 4
+#define RG_SX_TXBFSEL_MSK 0x000f0000
+#define RG_SX_TXBFSEL_I_MSK 0xfff0ffff
+#define RG_SX_TXBFSEL_SFT 16
+#define RG_SX_TXBFSEL_HI 19
+#define RG_SX_TXBFSEL_SZ 4
+#define RG_SX_VCOBFSEL_MSK 0x00f00000
+#define RG_SX_VCOBFSEL_I_MSK 0xff0fffff
+#define RG_SX_VCOBFSEL_SFT 20
+#define RG_SX_VCOBFSEL_HI 23
+#define RG_SX_VCOBFSEL_SZ 4
+#define RG_SX_DIVBFSEL_MSK 0x0f000000
+#define RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
+#define RG_SX_DIVBFSEL_SFT 24
+#define RG_SX_DIVBFSEL_HI 27
+#define RG_SX_DIVBFSEL_SZ 4
+#define RG_SX_GNDR_SEL_MSK 0xf0000000
+#define RG_SX_GNDR_SEL_I_MSK 0x0fffffff
+#define RG_SX_GNDR_SEL_SFT 28
+#define RG_SX_GNDR_SEL_HI 31
+#define RG_SX_GNDR_SEL_SZ 4
+#define RG_SX_DITHER_WEIGHT_MSK 0x00000003
+#define RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
+#define RG_SX_DITHER_WEIGHT_SFT 0
+#define RG_SX_DITHER_WEIGHT_HI 1
+#define RG_SX_DITHER_WEIGHT_SZ 2
+#define RG_SX_MOD_ORDER_MSK 0x00000030
+#define RG_SX_MOD_ORDER_I_MSK 0xffffffcf
+#define RG_SX_MOD_ORDER_SFT 4
+#define RG_SX_MOD_ORDER_HI 5
+#define RG_SX_MOD_ORDER_SZ 2
+#define RG_SX_RST_H_DIV_MSK 0x00000200
+#define RG_SX_RST_H_DIV_I_MSK 0xfffffdff
+#define RG_SX_RST_H_DIV_SFT 9
+#define RG_SX_RST_H_DIV_HI 9
+#define RG_SX_RST_H_DIV_SZ 1
+#define RG_SX_SDM_EDGE_MSK 0x00000400
+#define RG_SX_SDM_EDGE_I_MSK 0xfffffbff
+#define RG_SX_SDM_EDGE_SFT 10
+#define RG_SX_SDM_EDGE_HI 10
+#define RG_SX_SDM_EDGE_SZ 1
+#define RG_SX_XO_GM_MSK 0x00001800
+#define RG_SX_XO_GM_I_MSK 0xffffe7ff
+#define RG_SX_XO_GM_SFT 11
+#define RG_SX_XO_GM_HI 12
+#define RG_SX_XO_GM_SZ 2
+#define RG_SX_REFBYTWO_MSK 0x00002000
+#define RG_SX_REFBYTWO_I_MSK 0xffffdfff
+#define RG_SX_REFBYTWO_SFT 13
+#define RG_SX_REFBYTWO_HI 13
+#define RG_SX_REFBYTWO_SZ 1
+#define RG_SX_LCKEN_MSK 0x00080000
+#define RG_SX_LCKEN_I_MSK 0xfff7ffff
+#define RG_SX_LCKEN_SFT 19
+#define RG_SX_LCKEN_HI 19
+#define RG_SX_LCKEN_SZ 1
+#define RG_SX_PREVDD_MSK 0x00f00000
+#define RG_SX_PREVDD_I_MSK 0xff0fffff
+#define RG_SX_PREVDD_SFT 20
+#define RG_SX_PREVDD_HI 23
+#define RG_SX_PREVDD_SZ 4
+#define RG_SX_PSCONTERVDD_MSK 0x0f000000
+#define RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
+#define RG_SX_PSCONTERVDD_SFT 24
+#define RG_SX_PSCONTERVDD_HI 27
+#define RG_SX_PSCONTERVDD_SZ 4
+#define RG_SX_PH_MSK 0x00002000
+#define RG_SX_PH_I_MSK 0xffffdfff
+#define RG_SX_PH_SFT 13
+#define RG_SX_PH_HI 13
+#define RG_SX_PH_SZ 1
+#define RG_SX_PL_MSK 0x00004000
+#define RG_SX_PL_I_MSK 0xffffbfff
+#define RG_SX_PL_SFT 14
+#define RG_SX_PL_HI 14
+#define RG_SX_PL_SZ 1
+#define RG_XOSC_CBANK_XO_MSK 0x00078000
+#define RG_XOSC_CBANK_XO_I_MSK 0xfff87fff
+#define RG_XOSC_CBANK_XO_SFT 15
+#define RG_XOSC_CBANK_XO_HI 18
+#define RG_XOSC_CBANK_XO_SZ 4
+#define RG_XOSC_CBANK_XI_MSK 0x00780000
+#define RG_XOSC_CBANK_XI_I_MSK 0xff87ffff
+#define RG_XOSC_CBANK_XI_SFT 19
+#define RG_XOSC_CBANK_XI_HI 22
+#define RG_XOSC_CBANK_XI_SZ 4
+#define RG_SX_VT_MON_MODE_MSK 0x00000001
+#define RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
+#define RG_SX_VT_MON_MODE_SFT 0
+#define RG_SX_VT_MON_MODE_HI 0
+#define RG_SX_VT_MON_MODE_SZ 1
+#define RG_SX_VT_TH_HI_MSK 0x00000006
+#define RG_SX_VT_TH_HI_I_MSK 0xfffffff9
+#define RG_SX_VT_TH_HI_SFT 1
+#define RG_SX_VT_TH_HI_HI 2
+#define RG_SX_VT_TH_HI_SZ 2
+#define RG_SX_VT_TH_LO_MSK 0x00000018
+#define RG_SX_VT_TH_LO_I_MSK 0xffffffe7
+#define RG_SX_VT_TH_LO_SFT 3
+#define RG_SX_VT_TH_LO_HI 4
+#define RG_SX_VT_TH_LO_SZ 2
+#define RG_SX_VT_SET_MSK 0x00000020
+#define RG_SX_VT_SET_I_MSK 0xffffffdf
+#define RG_SX_VT_SET_SFT 5
+#define RG_SX_VT_SET_HI 5
+#define RG_SX_VT_SET_SZ 1
+#define RG_SX_VT_MON_TMR_MSK 0x00007fc0
+#define RG_SX_VT_MON_TMR_I_MSK 0xffff803f
+#define RG_SX_VT_MON_TMR_SFT 6
+#define RG_SX_VT_MON_TMR_HI 14
+#define RG_SX_VT_MON_TMR_SZ 9
+#define RG_EN_DP_VT_MON_MSK 0x00000001
+#define RG_EN_DP_VT_MON_I_MSK 0xfffffffe
+#define RG_EN_DP_VT_MON_SFT 0
+#define RG_EN_DP_VT_MON_HI 0
+#define RG_EN_DP_VT_MON_SZ 1
+#define RG_DP_VT_TH_HI_MSK 0x00000006
+#define RG_DP_VT_TH_HI_I_MSK 0xfffffff9
+#define RG_DP_VT_TH_HI_SFT 1
+#define RG_DP_VT_TH_HI_HI 2
+#define RG_DP_VT_TH_HI_SZ 2
+#define RG_DP_VT_TH_LO_MSK 0x00000018
+#define RG_DP_VT_TH_LO_I_MSK 0xffffffe7
+#define RG_DP_VT_TH_LO_SFT 3
+#define RG_DP_VT_TH_LO_HI 4
+#define RG_DP_VT_TH_LO_SZ 2
+#define RG_DP_CK320BY2_MSK 0x00004000
+#define RG_DP_CK320BY2_I_MSK 0xffffbfff
+#define RG_DP_CK320BY2_SFT 14
+#define RG_DP_CK320BY2_HI 14
+#define RG_DP_CK320BY2_SZ 1
+#define RG_DP_OD_TEST_MSK 0x00200000
+#define RG_DP_OD_TEST_I_MSK 0xffdfffff
+#define RG_DP_OD_TEST_SFT 21
+#define RG_DP_OD_TEST_HI 21
+#define RG_DP_OD_TEST_SZ 1
+#define RG_DP_BBPLL_BP_MSK 0x00000001
+#define RG_DP_BBPLL_BP_I_MSK 0xfffffffe
+#define RG_DP_BBPLL_BP_SFT 0
+#define RG_DP_BBPLL_BP_HI 0
+#define RG_DP_BBPLL_BP_SZ 1
+#define RG_DP_BBPLL_ICP_MSK 0x00000006
+#define RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
+#define RG_DP_BBPLL_ICP_SFT 1
+#define RG_DP_BBPLL_ICP_HI 2
+#define RG_DP_BBPLL_ICP_SZ 2
+#define RG_DP_BBPLL_IDUAL_MSK 0x00000018
+#define RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
+#define RG_DP_BBPLL_IDUAL_SFT 3
+#define RG_DP_BBPLL_IDUAL_HI 4
+#define RG_DP_BBPLL_IDUAL_SZ 2
+#define RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
+#define RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
+#define RG_DP_BBPLL_OD_TEST_SFT 5
+#define RG_DP_BBPLL_OD_TEST_HI 8
+#define RG_DP_BBPLL_OD_TEST_SZ 4
+#define RG_DP_BBPLL_PD_MSK 0x00000200
+#define RG_DP_BBPLL_PD_I_MSK 0xfffffdff
+#define RG_DP_BBPLL_PD_SFT 9
+#define RG_DP_BBPLL_PD_HI 9
+#define RG_DP_BBPLL_PD_SZ 1
+#define RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
+#define RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
+#define RG_DP_BBPLL_TESTSEL_SFT 10
+#define RG_DP_BBPLL_TESTSEL_HI 12
+#define RG_DP_BBPLL_TESTSEL_SZ 3
+#define RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
+#define RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
+#define RG_DP_BBPLL_PFD_DLY_SFT 13
+#define RG_DP_BBPLL_PFD_DLY_HI 14
+#define RG_DP_BBPLL_PFD_DLY_SZ 2
+#define RG_DP_RP_MSK 0x00038000
+#define RG_DP_RP_I_MSK 0xfffc7fff
+#define RG_DP_RP_SFT 15
+#define RG_DP_RP_HI 17
+#define RG_DP_RP_SZ 3
+#define RG_DP_RHP_MSK 0x000c0000
+#define RG_DP_RHP_I_MSK 0xfff3ffff
+#define RG_DP_RHP_SFT 18
+#define RG_DP_RHP_HI 19
+#define RG_DP_RHP_SZ 2
+#define RG_DP_BBPLL_SDM_EDGE_MSK 0x80000000
+#define RG_DP_BBPLL_SDM_EDGE_I_MSK 0x7fffffff
+#define RG_DP_BBPLL_SDM_EDGE_SFT 31
+#define RG_DP_BBPLL_SDM_EDGE_HI 31
+#define RG_DP_BBPLL_SDM_EDGE_SZ 1
+#define RG_DP_FODIV_MSK 0x0007f000
+#define RG_DP_FODIV_I_MSK 0xfff80fff
+#define RG_DP_FODIV_SFT 12
+#define RG_DP_FODIV_HI 18
+#define RG_DP_FODIV_SZ 7
+#define RG_DP_REFDIV_MSK 0x1fc00000
+#define RG_DP_REFDIV_I_MSK 0xe03fffff
+#define RG_DP_REFDIV_SFT 22
+#define RG_DP_REFDIV_HI 28
+#define RG_DP_REFDIV_SZ 7
+#define RG_IDACAI_PGAG15_MSK 0x0000003f
+#define RG_IDACAI_PGAG15_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG15_SFT 0
+#define RG_IDACAI_PGAG15_HI 5
+#define RG_IDACAI_PGAG15_SZ 6
+#define RG_IDACAQ_PGAG15_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG15_SFT 6
+#define RG_IDACAQ_PGAG15_HI 11
+#define RG_IDACAQ_PGAG15_SZ 6
+#define RG_IDACAI_PGAG14_MSK 0x0003f000
+#define RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG14_SFT 12
+#define RG_IDACAI_PGAG14_HI 17
+#define RG_IDACAI_PGAG14_SZ 6
+#define RG_IDACAQ_PGAG14_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG14_SFT 18
+#define RG_IDACAQ_PGAG14_HI 23
+#define RG_IDACAQ_PGAG14_SZ 6
+#define RG_DP_BBPLL_BS_MSK 0x3f000000
+#define RG_DP_BBPLL_BS_I_MSK 0xc0ffffff
+#define RG_DP_BBPLL_BS_SFT 24
+#define RG_DP_BBPLL_BS_HI 29
+#define RG_DP_BBPLL_BS_SZ 6
+#define RG_IDACAI_PGAG13_MSK 0x0000003f
+#define RG_IDACAI_PGAG13_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG13_SFT 0
+#define RG_IDACAI_PGAG13_HI 5
+#define RG_IDACAI_PGAG13_SZ 6
+#define RG_IDACAQ_PGAG13_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG13_SFT 6
+#define RG_IDACAQ_PGAG13_HI 11
+#define RG_IDACAQ_PGAG13_SZ 6
+#define RG_IDACAI_PGAG12_MSK 0x0003f000
+#define RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG12_SFT 12
+#define RG_IDACAI_PGAG12_HI 17
+#define RG_IDACAI_PGAG12_SZ 6
+#define RG_IDACAQ_PGAG12_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG12_SFT 18
+#define RG_IDACAQ_PGAG12_HI 23
+#define RG_IDACAQ_PGAG12_SZ 6
+#define RG_IDACAI_PGAG11_MSK 0x0000003f
+#define RG_IDACAI_PGAG11_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG11_SFT 0
+#define RG_IDACAI_PGAG11_HI 5
+#define RG_IDACAI_PGAG11_SZ 6
+#define RG_IDACAQ_PGAG11_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG11_SFT 6
+#define RG_IDACAQ_PGAG11_HI 11
+#define RG_IDACAQ_PGAG11_SZ 6
+#define RG_IDACAI_PGAG10_MSK 0x0003f000
+#define RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG10_SFT 12
+#define RG_IDACAI_PGAG10_HI 17
+#define RG_IDACAI_PGAG10_SZ 6
+#define RG_IDACAQ_PGAG10_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG10_SFT 18
+#define RG_IDACAQ_PGAG10_HI 23
+#define RG_IDACAQ_PGAG10_SZ 6
+#define RG_IDACAI_PGAG9_MSK 0x0000003f
+#define RG_IDACAI_PGAG9_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG9_SFT 0
+#define RG_IDACAI_PGAG9_HI 5
+#define RG_IDACAI_PGAG9_SZ 6
+#define RG_IDACAQ_PGAG9_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG9_SFT 6
+#define RG_IDACAQ_PGAG9_HI 11
+#define RG_IDACAQ_PGAG9_SZ 6
+#define RG_IDACAI_PGAG8_MSK 0x0003f000
+#define RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG8_SFT 12
+#define RG_IDACAI_PGAG8_HI 17
+#define RG_IDACAI_PGAG8_SZ 6
+#define RG_IDACAQ_PGAG8_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG8_SFT 18
+#define RG_IDACAQ_PGAG8_HI 23
+#define RG_IDACAQ_PGAG8_SZ 6
+#define RG_IDACAI_PGAG7_MSK 0x0000003f
+#define RG_IDACAI_PGAG7_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG7_SFT 0
+#define RG_IDACAI_PGAG7_HI 5
+#define RG_IDACAI_PGAG7_SZ 6
+#define RG_IDACAQ_PGAG7_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG7_SFT 6
+#define RG_IDACAQ_PGAG7_HI 11
+#define RG_IDACAQ_PGAG7_SZ 6
+#define RG_IDACAI_PGAG6_MSK 0x0003f000
+#define RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG6_SFT 12
+#define RG_IDACAI_PGAG6_HI 17
+#define RG_IDACAI_PGAG6_SZ 6
+#define RG_IDACAQ_PGAG6_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG6_SFT 18
+#define RG_IDACAQ_PGAG6_HI 23
+#define RG_IDACAQ_PGAG6_SZ 6
+#define RG_IDACAI_PGAG5_MSK 0x0000003f
+#define RG_IDACAI_PGAG5_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG5_SFT 0
+#define RG_IDACAI_PGAG5_HI 5
+#define RG_IDACAI_PGAG5_SZ 6
+#define RG_IDACAQ_PGAG5_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG5_SFT 6
+#define RG_IDACAQ_PGAG5_HI 11
+#define RG_IDACAQ_PGAG5_SZ 6
+#define RG_IDACAI_PGAG4_MSK 0x0003f000
+#define RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG4_SFT 12
+#define RG_IDACAI_PGAG4_HI 17
+#define RG_IDACAI_PGAG4_SZ 6
+#define RG_IDACAQ_PGAG4_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG4_SFT 18
+#define RG_IDACAQ_PGAG4_HI 23
+#define RG_IDACAQ_PGAG4_SZ 6
+#define RG_IDACAI_PGAG3_MSK 0x0000003f
+#define RG_IDACAI_PGAG3_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG3_SFT 0
+#define RG_IDACAI_PGAG3_HI 5
+#define RG_IDACAI_PGAG3_SZ 6
+#define RG_IDACAQ_PGAG3_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG3_SFT 6
+#define RG_IDACAQ_PGAG3_HI 11
+#define RG_IDACAQ_PGAG3_SZ 6
+#define RG_IDACAI_PGAG2_MSK 0x0003f000
+#define RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG2_SFT 12
+#define RG_IDACAI_PGAG2_HI 17
+#define RG_IDACAI_PGAG2_SZ 6
+#define RG_IDACAQ_PGAG2_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG2_SFT 18
+#define RG_IDACAQ_PGAG2_HI 23
+#define RG_IDACAQ_PGAG2_SZ 6
+#define RG_IDACAI_PGAG1_MSK 0x0000003f
+#define RG_IDACAI_PGAG1_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG1_SFT 0
+#define RG_IDACAI_PGAG1_HI 5
+#define RG_IDACAI_PGAG1_SZ 6
+#define RG_IDACAQ_PGAG1_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG1_SFT 6
+#define RG_IDACAQ_PGAG1_HI 11
+#define RG_IDACAQ_PGAG1_SZ 6
+#define RG_IDACAI_PGAG0_MSK 0x0003f000
+#define RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG0_SFT 12
+#define RG_IDACAI_PGAG0_HI 17
+#define RG_IDACAI_PGAG0_SZ 6
+#define RG_IDACAQ_PGAG0_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG0_SFT 18
+#define RG_IDACAQ_PGAG0_HI 23
+#define RG_IDACAQ_PGAG0_SZ 6
+#define RG_EN_RCAL_MSK 0x00000001
+#define RG_EN_RCAL_I_MSK 0xfffffffe
+#define RG_EN_RCAL_SFT 0
+#define RG_EN_RCAL_HI 0
+#define RG_EN_RCAL_SZ 1
+#define RG_RCAL_SPD_MSK 0x00000002
+#define RG_RCAL_SPD_I_MSK 0xfffffffd
+#define RG_RCAL_SPD_SFT 1
+#define RG_RCAL_SPD_HI 1
+#define RG_RCAL_SPD_SZ 1
+#define RG_RCAL_TMR_MSK 0x000001fc
+#define RG_RCAL_TMR_I_MSK 0xfffffe03
+#define RG_RCAL_TMR_SFT 2
+#define RG_RCAL_TMR_HI 8
+#define RG_RCAL_TMR_SZ 7
+#define RG_RCAL_CODE_CWR_MSK 0x00000200
+#define RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
+#define RG_RCAL_CODE_CWR_SFT 9
+#define RG_RCAL_CODE_CWR_HI 9
+#define RG_RCAL_CODE_CWR_SZ 1
+#define RG_RCAL_CODE_CWD_MSK 0x00007c00
+#define RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
+#define RG_RCAL_CODE_CWD_SFT 10
+#define RG_RCAL_CODE_CWD_HI 14
+#define RG_RCAL_CODE_CWD_SZ 5
+#define RG_SX_SUB_SEL_CWR_MSK 0x00000001
+#define RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
+#define RG_SX_SUB_SEL_CWR_SFT 0
+#define RG_SX_SUB_SEL_CWR_HI 0
+#define RG_SX_SUB_SEL_CWR_SZ 1
+#define RG_SX_SUB_SEL_CWD_MSK 0x000000fe
+#define RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
+#define RG_SX_SUB_SEL_CWD_SFT 1
+#define RG_SX_SUB_SEL_CWD_HI 7
+#define RG_SX_SUB_SEL_CWD_SZ 7
+#define RG_SX_LCK_BIN_OFFSET_MSK 0x00078000
+#define RG_SX_LCK_BIN_OFFSET_I_MSK 0xfff87fff
+#define RG_SX_LCK_BIN_OFFSET_SFT 15
+#define RG_SX_LCK_BIN_OFFSET_HI 18
+#define RG_SX_LCK_BIN_OFFSET_SZ 4
+#define RG_SX_LCK_BIN_PRECISION_MSK 0x00080000
+#define RG_SX_LCK_BIN_PRECISION_I_MSK 0xfff7ffff
+#define RG_SX_LCK_BIN_PRECISION_SFT 19
+#define RG_SX_LCK_BIN_PRECISION_HI 19
+#define RG_SX_LCK_BIN_PRECISION_SZ 1
+#define RG_SX_LOCK_EN_N_MSK 0x00100000
+#define RG_SX_LOCK_EN_N_I_MSK 0xffefffff
+#define RG_SX_LOCK_EN_N_SFT 20
+#define RG_SX_LOCK_EN_N_HI 20
+#define RG_SX_LOCK_EN_N_SZ 1
+#define RG_SX_LOCK_MANUAL_MSK 0x00200000
+#define RG_SX_LOCK_MANUAL_I_MSK 0xffdfffff
+#define RG_SX_LOCK_MANUAL_SFT 21
+#define RG_SX_LOCK_MANUAL_HI 21
+#define RG_SX_LOCK_MANUAL_SZ 1
+#define RG_SX_SUB_MANUAL_MSK 0x00400000
+#define RG_SX_SUB_MANUAL_I_MSK 0xffbfffff
+#define RG_SX_SUB_MANUAL_SFT 22
+#define RG_SX_SUB_MANUAL_HI 22
+#define RG_SX_SUB_MANUAL_SZ 1
+#define RG_SX_SUB_SEL_MSK 0x3f800000
+#define RG_SX_SUB_SEL_I_MSK 0xc07fffff
+#define RG_SX_SUB_SEL_SFT 23
+#define RG_SX_SUB_SEL_HI 29
+#define RG_SX_SUB_SEL_SZ 7
+#define RG_SX_MUX_SEL_VTH_BINL_MSK 0x40000000
+#define RG_SX_MUX_SEL_VTH_BINL_I_MSK 0xbfffffff
+#define RG_SX_MUX_SEL_VTH_BINL_SFT 30
+#define RG_SX_MUX_SEL_VTH_BINL_HI 30
+#define RG_SX_MUX_SEL_VTH_BINL_SZ 1
+#define RG_TRX_DUMMMY_MSK 0xffffffff
+#define RG_TRX_DUMMMY_I_MSK 0x00000000
+#define RG_TRX_DUMMMY_SFT 0
+#define RG_TRX_DUMMMY_HI 31
+#define RG_TRX_DUMMMY_SZ 32
+#define RG_SX_DUMMMY_MSK 0xffffffff
+#define RG_SX_DUMMMY_I_MSK 0x00000000
+#define RG_SX_DUMMMY_SFT 0
+#define RG_SX_DUMMMY_HI 31
+#define RG_SX_DUMMMY_SZ 32
+#define RCAL_RDY_MSK 0x00000001
+#define RCAL_RDY_I_MSK 0xfffffffe
+#define RCAL_RDY_SFT 0
+#define RCAL_RDY_HI 0
+#define RCAL_RDY_SZ 1
+#define LCK_BIN_RDY_MSK 0x00000002
+#define LCK_BIN_RDY_I_MSK 0xfffffffd
+#define LCK_BIN_RDY_SFT 1
+#define LCK_BIN_RDY_HI 1
+#define LCK_BIN_RDY_SZ 1
+#define VT_MON_RDY_MSK 0x00000004
+#define VT_MON_RDY_I_MSK 0xfffffffb
+#define VT_MON_RDY_SFT 2
+#define VT_MON_RDY_HI 2
+#define VT_MON_RDY_SZ 1
+#define DA_R_CODE_LUT_MSK 0x000007c0
+#define DA_R_CODE_LUT_I_MSK 0xfffff83f
+#define DA_R_CODE_LUT_SFT 6
+#define DA_R_CODE_LUT_HI 10
+#define DA_R_CODE_LUT_SZ 5
+#define AD_SX_VT_MON_Q_MSK 0x00001800
+#define AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
+#define AD_SX_VT_MON_Q_SFT 11
+#define AD_SX_VT_MON_Q_HI 12
+#define AD_SX_VT_MON_Q_SZ 2
+#define AD_DP_VT_MON_Q_MSK 0x00006000
+#define AD_DP_VT_MON_Q_I_MSK 0xffff9fff
+#define AD_DP_VT_MON_Q_SFT 13
+#define AD_DP_VT_MON_Q_HI 14
+#define AD_DP_VT_MON_Q_SZ 2
+#define RTC_CAL_RDY_MSK 0x00008000
+#define RTC_CAL_RDY_I_MSK 0xffff7fff
+#define RTC_CAL_RDY_SFT 15
+#define RTC_CAL_RDY_HI 15
+#define RTC_CAL_RDY_SZ 1
+#define RG_SARADC_BIT_MSK 0x003f0000
+#define RG_SARADC_BIT_I_MSK 0xffc0ffff
+#define RG_SARADC_BIT_SFT 16
+#define RG_SARADC_BIT_HI 21
+#define RG_SARADC_BIT_SZ 6
+#define SAR_ADC_FSM_RDY_MSK 0x00400000
+#define SAR_ADC_FSM_RDY_I_MSK 0xffbfffff
+#define SAR_ADC_FSM_RDY_SFT 22
+#define SAR_ADC_FSM_RDY_HI 22
+#define SAR_ADC_FSM_RDY_SZ 1
+#define AD_CIRCUIT_VERSION_MSK 0x07800000
+#define AD_CIRCUIT_VERSION_I_MSK 0xf87fffff
+#define AD_CIRCUIT_VERSION_SFT 23
+#define AD_CIRCUIT_VERSION_HI 26
+#define AD_CIRCUIT_VERSION_SZ 4
+#define DA_R_CAL_CODE_MSK 0x0000001f
+#define DA_R_CAL_CODE_I_MSK 0xffffffe0
+#define DA_R_CAL_CODE_SFT 0
+#define DA_R_CAL_CODE_HI 4
+#define DA_R_CAL_CODE_SZ 5
+#define DA_SX_SUB_SEL_MSK 0x00000fe0
+#define DA_SX_SUB_SEL_I_MSK 0xfffff01f
+#define DA_SX_SUB_SEL_SFT 5
+#define DA_SX_SUB_SEL_HI 11
+#define DA_SX_SUB_SEL_SZ 7
+#define RG_DPL_RFCTRL_CH_MSK 0x000007ff
+#define RG_DPL_RFCTRL_CH_I_MSK 0xfffff800
+#define RG_DPL_RFCTRL_CH_SFT 0
+#define RG_DPL_RFCTRL_CH_HI 10
+#define RG_DPL_RFCTRL_CH_SZ 11
+#define RG_RSSIADC_RO_BIT_MSK 0x00007800
+#define RG_RSSIADC_RO_BIT_I_MSK 0xffff87ff
+#define RG_RSSIADC_RO_BIT_SFT 11
+#define RG_RSSIADC_RO_BIT_HI 14
+#define RG_RSSIADC_RO_BIT_SZ 4
+#define RG_RX_ADC_I_RO_BIT_MSK 0x007f8000
+#define RG_RX_ADC_I_RO_BIT_I_MSK 0xff807fff
+#define RG_RX_ADC_I_RO_BIT_SFT 15
+#define RG_RX_ADC_I_RO_BIT_HI 22
+#define RG_RX_ADC_I_RO_BIT_SZ 8
+#define RG_RX_ADC_Q_RO_BIT_MSK 0x7f800000
+#define RG_RX_ADC_Q_RO_BIT_I_MSK 0x807fffff
+#define RG_RX_ADC_Q_RO_BIT_SFT 23
+#define RG_RX_ADC_Q_RO_BIT_HI 30
+#define RG_RX_ADC_Q_RO_BIT_SZ 8
+#define RG_DPL_RFCTRL_F_MSK 0x00ffffff
+#define RG_DPL_RFCTRL_F_I_MSK 0xff000000
+#define RG_DPL_RFCTRL_F_SFT 0
+#define RG_DPL_RFCTRL_F_HI 23
+#define RG_DPL_RFCTRL_F_SZ 24
+#define RG_SX_TARGET_CNT_MSK 0x00001fff
+#define RG_SX_TARGET_CNT_I_MSK 0xffffe000
+#define RG_SX_TARGET_CNT_SFT 0
+#define RG_SX_TARGET_CNT_HI 12
+#define RG_SX_TARGET_CNT_SZ 13
+#define RG_RTC_OFFSET_MSK 0x000000ff
+#define RG_RTC_OFFSET_I_MSK 0xffffff00
+#define RG_RTC_OFFSET_SFT 0
+#define RG_RTC_OFFSET_HI 7
+#define RG_RTC_OFFSET_SZ 8
+#define RG_RTC_CAL_TARGET_COUNT_MSK 0x000fff00
+#define RG_RTC_CAL_TARGET_COUNT_I_MSK 0xfff000ff
+#define RG_RTC_CAL_TARGET_COUNT_SFT 8
+#define RG_RTC_CAL_TARGET_COUNT_HI 19
+#define RG_RTC_CAL_TARGET_COUNT_SZ 12
+#define RG_RF_D_REG_MSK 0x0000ffff
+#define RG_RF_D_REG_I_MSK 0xffff0000
+#define RG_RF_D_REG_SFT 0
+#define RG_RF_D_REG_HI 15
+#define RG_RF_D_REG_SZ 16
+#define DIRECT_MODE_MSK 0x00000001
+#define DIRECT_MODE_I_MSK 0xfffffffe
+#define DIRECT_MODE_SFT 0
+#define DIRECT_MODE_HI 0
+#define DIRECT_MODE_SZ 1
+#define TAG_INTERLEAVE_MD_MSK 0x00000002
+#define TAG_INTERLEAVE_MD_I_MSK 0xfffffffd
+#define TAG_INTERLEAVE_MD_SFT 1
+#define TAG_INTERLEAVE_MD_HI 1
+#define TAG_INTERLEAVE_MD_SZ 1
+#define DIS_DEMAND_MSK 0x00000004
+#define DIS_DEMAND_I_MSK 0xfffffffb
+#define DIS_DEMAND_SFT 2
+#define DIS_DEMAND_HI 2
+#define DIS_DEMAND_SZ 1
+#define SAME_ID_ALLOC_MD_MSK 0x00000008
+#define SAME_ID_ALLOC_MD_I_MSK 0xfffffff7
+#define SAME_ID_ALLOC_MD_SFT 3
+#define SAME_ID_ALLOC_MD_HI 3
+#define SAME_ID_ALLOC_MD_SZ 1
+#define HS_ACCESS_MD_MSK 0x00000010
+#define HS_ACCESS_MD_I_MSK 0xffffffef
+#define HS_ACCESS_MD_SFT 4
+#define HS_ACCESS_MD_HI 4
+#define HS_ACCESS_MD_SZ 1
+#define SRAM_ACCESS_MD_MSK 0x00000020
+#define SRAM_ACCESS_MD_I_MSK 0xffffffdf
+#define SRAM_ACCESS_MD_SFT 5
+#define SRAM_ACCESS_MD_HI 5
+#define SRAM_ACCESS_MD_SZ 1
+#define NOHIT_RPASS_MD_MSK 0x00000040
+#define NOHIT_RPASS_MD_I_MSK 0xffffffbf
+#define NOHIT_RPASS_MD_SFT 6
+#define NOHIT_RPASS_MD_HI 6
+#define NOHIT_RPASS_MD_SZ 1
+#define DMN_FLAG_CLR_MSK 0x00000080
+#define DMN_FLAG_CLR_I_MSK 0xffffff7f
+#define DMN_FLAG_CLR_SFT 7
+#define DMN_FLAG_CLR_HI 7
+#define DMN_FLAG_CLR_SZ 1
+#define ERR_SW_RST_N_MSK 0x00000100
+#define ERR_SW_RST_N_I_MSK 0xfffffeff
+#define ERR_SW_RST_N_SFT 8
+#define ERR_SW_RST_N_HI 8
+#define ERR_SW_RST_N_SZ 1
+#define ALR_SW_RST_N_MSK 0x00000200
+#define ALR_SW_RST_N_I_MSK 0xfffffdff
+#define ALR_SW_RST_N_SFT 9
+#define ALR_SW_RST_N_HI 9
+#define ALR_SW_RST_N_SZ 1
+#define MCH_SW_RST_N_MSK 0x00000400
+#define MCH_SW_RST_N_I_MSK 0xfffffbff
+#define MCH_SW_RST_N_SFT 10
+#define MCH_SW_RST_N_HI 10
+#define MCH_SW_RST_N_SZ 1
+#define TAG_SW_RST_N_MSK 0x00000800
+#define TAG_SW_RST_N_I_MSK 0xfffff7ff
+#define TAG_SW_RST_N_SFT 11
+#define TAG_SW_RST_N_HI 11
+#define TAG_SW_RST_N_SZ 1
+#define ABT_SW_RST_N_MSK 0x00001000
+#define ABT_SW_RST_N_I_MSK 0xffffefff
+#define ABT_SW_RST_N_SFT 12
+#define ABT_SW_RST_N_HI 12
+#define ABT_SW_RST_N_SZ 1
+#define MMU_VER_MSK 0x0000e000
+#define MMU_VER_I_MSK 0xffff1fff
+#define MMU_VER_SFT 13
+#define MMU_VER_HI 15
+#define MMU_VER_SZ 3
+#define MMU_SHARE_MCU_MSK 0x00ff0000
+#define MMU_SHARE_MCU_I_MSK 0xff00ffff
+#define MMU_SHARE_MCU_SFT 16
+#define MMU_SHARE_MCU_HI 23
+#define MMU_SHARE_MCU_SZ 8
+#define HS_WR_MSK 0x00000001
+#define HS_WR_I_MSK 0xfffffffe
+#define HS_WR_SFT 0
+#define HS_WR_HI 0
+#define HS_WR_SZ 1
+#define HS_FLAG_MSK 0x00000010
+#define HS_FLAG_I_MSK 0xffffffef
+#define HS_FLAG_SFT 4
+#define HS_FLAG_HI 4
+#define HS_FLAG_SZ 1
+#define HS_ID_MSK 0x00007f00
+#define HS_ID_I_MSK 0xffff80ff
+#define HS_ID_SFT 8
+#define HS_ID_HI 14
+#define HS_ID_SZ 7
+#define HS_CHANNEL_MSK 0x000f0000
+#define HS_CHANNEL_I_MSK 0xfff0ffff
+#define HS_CHANNEL_SFT 16
+#define HS_CHANNEL_HI 19
+#define HS_CHANNEL_SZ 4
+#define HS_PAGE_MSK 0x00f00000
+#define HS_PAGE_I_MSK 0xff0fffff
+#define HS_PAGE_SFT 20
+#define HS_PAGE_HI 23
+#define HS_PAGE_SZ 4
+#define HS_DATA_MSK 0xff000000
+#define HS_DATA_I_MSK 0x00ffffff
+#define HS_DATA_SFT 24
+#define HS_DATA_HI 31
+#define HS_DATA_SZ 8
+#define CPU_POR0_MSK 0x0000000f
+#define CPU_POR0_I_MSK 0xfffffff0
+#define CPU_POR0_SFT 0
+#define CPU_POR0_HI 3
+#define CPU_POR0_SZ 4
+#define CPU_POR1_MSK 0x000000f0
+#define CPU_POR1_I_MSK 0xffffff0f
+#define CPU_POR1_SFT 4
+#define CPU_POR1_HI 7
+#define CPU_POR1_SZ 4
+#define CPU_POR2_MSK 0x00000f00
+#define CPU_POR2_I_MSK 0xfffff0ff
+#define CPU_POR2_SFT 8
+#define CPU_POR2_HI 11
+#define CPU_POR2_SZ 4
+#define CPU_POR3_MSK 0x0000f000
+#define CPU_POR3_I_MSK 0xffff0fff
+#define CPU_POR3_SFT 12
+#define CPU_POR3_HI 15
+#define CPU_POR3_SZ 4
+#define CPU_POR4_MSK 0x000f0000
+#define CPU_POR4_I_MSK 0xfff0ffff
+#define CPU_POR4_SFT 16
+#define CPU_POR4_HI 19
+#define CPU_POR4_SZ 4
+#define CPU_POR5_MSK 0x00f00000
+#define CPU_POR5_I_MSK 0xff0fffff
+#define CPU_POR5_SFT 20
+#define CPU_POR5_HI 23
+#define CPU_POR5_SZ 4
+#define CPU_POR6_MSK 0x0f000000
+#define CPU_POR6_I_MSK 0xf0ffffff
+#define CPU_POR6_SFT 24
+#define CPU_POR6_HI 27
+#define CPU_POR6_SZ 4
+#define CPU_POR7_MSK 0xf0000000
+#define CPU_POR7_I_MSK 0x0fffffff
+#define CPU_POR7_SFT 28
+#define CPU_POR7_HI 31
+#define CPU_POR7_SZ 4
+#define CPU_POR8_MSK 0x0000000f
+#define CPU_POR8_I_MSK 0xfffffff0
+#define CPU_POR8_SFT 0
+#define CPU_POR8_HI 3
+#define CPU_POR8_SZ 4
+#define CPU_POR9_MSK 0x000000f0
+#define CPU_POR9_I_MSK 0xffffff0f
+#define CPU_POR9_SFT 4
+#define CPU_POR9_HI 7
+#define CPU_POR9_SZ 4
+#define CPU_PORA_MSK 0x00000f00
+#define CPU_PORA_I_MSK 0xfffff0ff
+#define CPU_PORA_SFT 8
+#define CPU_PORA_HI 11
+#define CPU_PORA_SZ 4
+#define CPU_PORB_MSK 0x0000f000
+#define CPU_PORB_I_MSK 0xffff0fff
+#define CPU_PORB_SFT 12
+#define CPU_PORB_HI 15
+#define CPU_PORB_SZ 4
+#define CPU_PORC_MSK 0x000f0000
+#define CPU_PORC_I_MSK 0xfff0ffff
+#define CPU_PORC_SFT 16
+#define CPU_PORC_HI 19
+#define CPU_PORC_SZ 4
+#define CPU_PORD_MSK 0x00f00000
+#define CPU_PORD_I_MSK 0xff0fffff
+#define CPU_PORD_SFT 20
+#define CPU_PORD_HI 23
+#define CPU_PORD_SZ 4
+#define CPU_PORE_MSK 0x0f000000
+#define CPU_PORE_I_MSK 0xf0ffffff
+#define CPU_PORE_SFT 24
+#define CPU_PORE_HI 27
+#define CPU_PORE_SZ 4
+#define CPU_PORF_MSK 0xf0000000
+#define CPU_PORF_I_MSK 0x0fffffff
+#define CPU_PORF_SFT 28
+#define CPU_PORF_HI 31
+#define CPU_PORF_SZ 4
+#define ACC_WR_LEN_MSK 0x0000003f
+#define ACC_WR_LEN_I_MSK 0xffffffc0
+#define ACC_WR_LEN_SFT 0
+#define ACC_WR_LEN_HI 5
+#define ACC_WR_LEN_SZ 6
+#define ACC_RD_LEN_MSK 0x00003f00
+#define ACC_RD_LEN_I_MSK 0xffffc0ff
+#define ACC_RD_LEN_SFT 8
+#define ACC_RD_LEN_HI 13
+#define ACC_RD_LEN_SZ 6
+#define REQ_NACK_CLR_MSK 0x00008000
+#define REQ_NACK_CLR_I_MSK 0xffff7fff
+#define REQ_NACK_CLR_SFT 15
+#define REQ_NACK_CLR_HI 15
+#define REQ_NACK_CLR_SZ 1
+#define NACK_FLAG_BUS_MSK 0xffff0000
+#define NACK_FLAG_BUS_I_MSK 0x0000ffff
+#define NACK_FLAG_BUS_SFT 16
+#define NACK_FLAG_BUS_HI 31
+#define NACK_FLAG_BUS_SZ 16
+#define DMN_R_PASS_MSK 0x0000ffff
+#define DMN_R_PASS_I_MSK 0xffff0000
+#define DMN_R_PASS_SFT 0
+#define DMN_R_PASS_HI 15
+#define DMN_R_PASS_SZ 16
+#define PARA_ALC_RLS_MSK 0x00010000
+#define PARA_ALC_RLS_I_MSK 0xfffeffff
+#define PARA_ALC_RLS_SFT 16
+#define PARA_ALC_RLS_HI 16
+#define PARA_ALC_RLS_SZ 1
+#define REQ_PORNS_CHGEN_MSK 0x01000000
+#define REQ_PORNS_CHGEN_I_MSK 0xfeffffff
+#define REQ_PORNS_CHGEN_SFT 24
+#define REQ_PORNS_CHGEN_HI 24
+#define REQ_PORNS_CHGEN_SZ 1
+#define ALC_ABT_ID_MSK 0x0000007f
+#define ALC_ABT_ID_I_MSK 0xffffff80
+#define ALC_ABT_ID_SFT 0
+#define ALC_ABT_ID_HI 6
+#define ALC_ABT_ID_SZ 7
+#define ALC_ABT_INT_MSK 0x00008000
+#define ALC_ABT_INT_I_MSK 0xffff7fff
+#define ALC_ABT_INT_SFT 15
+#define ALC_ABT_INT_HI 15
+#define ALC_ABT_INT_SZ 1
+#define RLS_ABT_ID_MSK 0x007f0000
+#define RLS_ABT_ID_I_MSK 0xff80ffff
+#define RLS_ABT_ID_SFT 16
+#define RLS_ABT_ID_HI 22
+#define RLS_ABT_ID_SZ 7
+#define RLS_ABT_INT_MSK 0x80000000
+#define RLS_ABT_INT_I_MSK 0x7fffffff
+#define RLS_ABT_INT_SFT 31
+#define RLS_ABT_INT_HI 31
+#define RLS_ABT_INT_SZ 1
+#define DEBUG_CTL_MSK 0x000000ff
+#define DEBUG_CTL_I_MSK 0xffffff00
+#define DEBUG_CTL_SFT 0
+#define DEBUG_CTL_HI 7
+#define DEBUG_CTL_SZ 8
+#define DEBUG_H16_MSK 0x00000100
+#define DEBUG_H16_I_MSK 0xfffffeff
+#define DEBUG_H16_SFT 8
+#define DEBUG_H16_HI 8
+#define DEBUG_H16_SZ 1
+#define DEBUG_OUT_MSK 0xffffffff
+#define DEBUG_OUT_I_MSK 0x00000000
+#define DEBUG_OUT_SFT 0
+#define DEBUG_OUT_HI 31
+#define DEBUG_OUT_SZ 32
+#define ALC_ERR_MSK 0x00000001
+#define ALC_ERR_I_MSK 0xfffffffe
+#define ALC_ERR_SFT 0
+#define ALC_ERR_HI 0
+#define ALC_ERR_SZ 1
+#define RLS_ERR_MSK 0x00000002
+#define RLS_ERR_I_MSK 0xfffffffd
+#define RLS_ERR_SFT 1
+#define RLS_ERR_HI 1
+#define RLS_ERR_SZ 1
+#define AL_STATE_MSK 0x00000700
+#define AL_STATE_I_MSK 0xfffff8ff
+#define AL_STATE_SFT 8
+#define AL_STATE_HI 10
+#define AL_STATE_SZ 3
+#define RL_STATE_MSK 0x00007000
+#define RL_STATE_I_MSK 0xffff8fff
+#define RL_STATE_SFT 12
+#define RL_STATE_HI 14
+#define RL_STATE_SZ 3
+#define ALC_ERR_ID_MSK 0x007f0000
+#define ALC_ERR_ID_I_MSK 0xff80ffff
+#define ALC_ERR_ID_SFT 16
+#define ALC_ERR_ID_HI 22
+#define ALC_ERR_ID_SZ 7
+#define RLS_ERR_ID_MSK 0x7f000000
+#define RLS_ERR_ID_I_MSK 0x80ffffff
+#define RLS_ERR_ID_SFT 24
+#define RLS_ERR_ID_HI 30
+#define RLS_ERR_ID_SZ 7
+#define DMN_NOHIT_FLAG_MSK 0x00000001
+#define DMN_NOHIT_FLAG_I_MSK 0xfffffffe
+#define DMN_NOHIT_FLAG_SFT 0
+#define DMN_NOHIT_FLAG_HI 0
+#define DMN_NOHIT_FLAG_SZ 1
+#define DMN_FLAG_MSK 0x00000002
+#define DMN_FLAG_I_MSK 0xfffffffd
+#define DMN_FLAG_SFT 1
+#define DMN_FLAG_HI 1
+#define DMN_FLAG_SZ 1
+#define DMN_WR_MSK 0x00000008
+#define DMN_WR_I_MSK 0xfffffff7
+#define DMN_WR_SFT 3
+#define DMN_WR_HI 3
+#define DMN_WR_SZ 1
+#define DMN_PORT_MSK 0x000000f0
+#define DMN_PORT_I_MSK 0xffffff0f
+#define DMN_PORT_SFT 4
+#define DMN_PORT_HI 7
+#define DMN_PORT_SZ 4
+#define DMN_NHIT_ID_MSK 0x00007f00
+#define DMN_NHIT_ID_I_MSK 0xffff80ff
+#define DMN_NHIT_ID_SFT 8
+#define DMN_NHIT_ID_HI 14
+#define DMN_NHIT_ID_SZ 7
+#define DMN_NHIT_ADDR_MSK 0xffff0000
+#define DMN_NHIT_ADDR_I_MSK 0x0000ffff
+#define DMN_NHIT_ADDR_SFT 16
+#define DMN_NHIT_ADDR_HI 31
+#define DMN_NHIT_ADDR_SZ 16
+#define TX_MOUNT_MSK 0x000000ff
+#define TX_MOUNT_I_MSK 0xffffff00
+#define TX_MOUNT_SFT 0
+#define TX_MOUNT_HI 7
+#define TX_MOUNT_SZ 8
+#define RX_MOUNT_MSK 0x0000ff00
+#define RX_MOUNT_I_MSK 0xffff00ff
+#define RX_MOUNT_SFT 8
+#define RX_MOUNT_HI 15
+#define RX_MOUNT_SZ 8
+#define AVA_TAG_MSK 0x01ff0000
+#define AVA_TAG_I_MSK 0xfe00ffff
+#define AVA_TAG_SFT 16
+#define AVA_TAG_HI 24
+#define AVA_TAG_SZ 9
+#define PKTBUF_FULL_MSK 0x80000000
+#define PKTBUF_FULL_I_MSK 0x7fffffff
+#define PKTBUF_FULL_SFT 31
+#define PKTBUF_FULL_HI 31
+#define PKTBUF_FULL_SZ 1
+#define DMN_NOHIT_MCU_MSK 0x00000001
+#define DMN_NOHIT_MCU_I_MSK 0xfffffffe
+#define DMN_NOHIT_MCU_SFT 0
+#define DMN_NOHIT_MCU_HI 0
+#define DMN_NOHIT_MCU_SZ 1
+#define DMN_MCU_FLAG_MSK 0x00000002
+#define DMN_MCU_FLAG_I_MSK 0xfffffffd
+#define DMN_MCU_FLAG_SFT 1
+#define DMN_MCU_FLAG_HI 1
+#define DMN_MCU_FLAG_SZ 1
+#define DMN_MCU_WR_MSK 0x00000008
+#define DMN_MCU_WR_I_MSK 0xfffffff7
+#define DMN_MCU_WR_SFT 3
+#define DMN_MCU_WR_HI 3
+#define DMN_MCU_WR_SZ 1
+#define DMN_MCU_PORT_MSK 0x000000f0
+#define DMN_MCU_PORT_I_MSK 0xffffff0f
+#define DMN_MCU_PORT_SFT 4
+#define DMN_MCU_PORT_HI 7
+#define DMN_MCU_PORT_SZ 4
+#define DMN_MCU_ID_MSK 0x00007f00
+#define DMN_MCU_ID_I_MSK 0xffff80ff
+#define DMN_MCU_ID_SFT 8
+#define DMN_MCU_ID_HI 14
+#define DMN_MCU_ID_SZ 7
+#define DMN_MCU_ADDR_MSK 0xffff0000
+#define DMN_MCU_ADDR_I_MSK 0x0000ffff
+#define DMN_MCU_ADDR_SFT 16
+#define DMN_MCU_ADDR_HI 31
+#define DMN_MCU_ADDR_SZ 16
+#define MB_IDTBL_31_0_MSK 0xffffffff
+#define MB_IDTBL_31_0_I_MSK 0x00000000
+#define MB_IDTBL_31_0_SFT 0
+#define MB_IDTBL_31_0_HI 31
+#define MB_IDTBL_31_0_SZ 32
+#define MB_IDTBL_63_32_MSK 0xffffffff
+#define MB_IDTBL_63_32_I_MSK 0x00000000
+#define MB_IDTBL_63_32_SFT 0
+#define MB_IDTBL_63_32_HI 31
+#define MB_IDTBL_63_32_SZ 32
+#define MB_IDTBL_95_64_MSK 0xffffffff
+#define MB_IDTBL_95_64_I_MSK 0x00000000
+#define MB_IDTBL_95_64_SFT 0
+#define MB_IDTBL_95_64_HI 31
+#define MB_IDTBL_95_64_SZ 32
+#define MB_IDTBL_127_96_MSK 0xffffffff
+#define MB_IDTBL_127_96_I_MSK 0x00000000
+#define MB_IDTBL_127_96_SFT 0
+#define MB_IDTBL_127_96_HI 31
+#define MB_IDTBL_127_96_SZ 32
+#define PKT_IDTBL_31_0_MSK 0xffffffff
+#define PKT_IDTBL_31_0_I_MSK 0x00000000
+#define PKT_IDTBL_31_0_SFT 0
+#define PKT_IDTBL_31_0_HI 31
+#define PKT_IDTBL_31_0_SZ 32
+#define PKT_IDTBL_63_32_MSK 0xffffffff
+#define PKT_IDTBL_63_32_I_MSK 0x00000000
+#define PKT_IDTBL_63_32_SFT 0
+#define PKT_IDTBL_63_32_HI 31
+#define PKT_IDTBL_63_32_SZ 32
+#define PKT_IDTBL_95_64_MSK 0xffffffff
+#define PKT_IDTBL_95_64_I_MSK 0x00000000
+#define PKT_IDTBL_95_64_SFT 0
+#define PKT_IDTBL_95_64_HI 31
+#define PKT_IDTBL_95_64_SZ 32
+#define PKT_IDTBL_127_96_MSK 0xffffffff
+#define PKT_IDTBL_127_96_I_MSK 0x00000000
+#define PKT_IDTBL_127_96_SFT 0
+#define PKT_IDTBL_127_96_HI 31
+#define PKT_IDTBL_127_96_SZ 32
+#define DMN_IDTBL_31_0_MSK 0xffffffff
+#define DMN_IDTBL_31_0_I_MSK 0x00000000
+#define DMN_IDTBL_31_0_SFT 0
+#define DMN_IDTBL_31_0_HI 31
+#define DMN_IDTBL_31_0_SZ 32
+#define DMN_IDTBL_63_32_MSK 0xffffffff
+#define DMN_IDTBL_63_32_I_MSK 0x00000000
+#define DMN_IDTBL_63_32_SFT 0
+#define DMN_IDTBL_63_32_HI 31
+#define DMN_IDTBL_63_32_SZ 32
+#define DMN_IDTBL_95_64_MSK 0xffffffff
+#define DMN_IDTBL_95_64_I_MSK 0x00000000
+#define DMN_IDTBL_95_64_SFT 0
+#define DMN_IDTBL_95_64_HI 31
+#define DMN_IDTBL_95_64_SZ 32
+#define DMN_IDTBL_127_96_MSK 0xffffffff
+#define DMN_IDTBL_127_96_I_MSK 0x00000000
+#define DMN_IDTBL_127_96_SFT 0
+#define DMN_IDTBL_127_96_HI 31
+#define DMN_IDTBL_127_96_SZ 32
+#define NEQ_MB_ID_31_0_MSK 0xffffffff
+#define NEQ_MB_ID_31_0_I_MSK 0x00000000
+#define NEQ_MB_ID_31_0_SFT 0
+#define NEQ_MB_ID_31_0_HI 31
+#define NEQ_MB_ID_31_0_SZ 32
+#define NEQ_MB_ID_63_32_MSK 0xffffffff
+#define NEQ_MB_ID_63_32_I_MSK 0x00000000
+#define NEQ_MB_ID_63_32_SFT 0
+#define NEQ_MB_ID_63_32_HI 31
+#define NEQ_MB_ID_63_32_SZ 32
+#define NEQ_MB_ID_95_64_MSK 0xffffffff
+#define NEQ_MB_ID_95_64_I_MSK 0x00000000
+#define NEQ_MB_ID_95_64_SFT 0
+#define NEQ_MB_ID_95_64_HI 31
+#define NEQ_MB_ID_95_64_SZ 32
+#define NEQ_MB_ID_127_96_MSK 0xffffffff
+#define NEQ_MB_ID_127_96_I_MSK 0x00000000
+#define NEQ_MB_ID_127_96_SFT 0
+#define NEQ_MB_ID_127_96_HI 31
+#define NEQ_MB_ID_127_96_SZ 32
+#define NEQ_PKT_ID_31_0_MSK 0xffffffff
+#define NEQ_PKT_ID_31_0_I_MSK 0x00000000
+#define NEQ_PKT_ID_31_0_SFT 0
+#define NEQ_PKT_ID_31_0_HI 31
+#define NEQ_PKT_ID_31_0_SZ 32
+#define NEQ_PKT_ID_63_32_MSK 0xffffffff
+#define NEQ_PKT_ID_63_32_I_MSK 0x00000000
+#define NEQ_PKT_ID_63_32_SFT 0
+#define NEQ_PKT_ID_63_32_HI 31
+#define NEQ_PKT_ID_63_32_SZ 32
+#define NEQ_PKT_ID_95_64_MSK 0xffffffff
+#define NEQ_PKT_ID_95_64_I_MSK 0x00000000
+#define NEQ_PKT_ID_95_64_SFT 0
+#define NEQ_PKT_ID_95_64_HI 31
+#define NEQ_PKT_ID_95_64_SZ 32
+#define NEQ_PKT_ID_127_96_MSK 0xffffffff
+#define NEQ_PKT_ID_127_96_I_MSK 0x00000000
+#define NEQ_PKT_ID_127_96_SFT 0
+#define NEQ_PKT_ID_127_96_HI 31
+#define NEQ_PKT_ID_127_96_SZ 32
+#define ALC_NOCHG_ID_MSK 0x0000007f
+#define ALC_NOCHG_ID_I_MSK 0xffffff80
+#define ALC_NOCHG_ID_SFT 0
+#define ALC_NOCHG_ID_HI 6
+#define ALC_NOCHG_ID_SZ 7
+#define ALC_NOCHG_INT_MSK 0x00008000
+#define ALC_NOCHG_INT_I_MSK 0xffff7fff
+#define ALC_NOCHG_INT_SFT 15
+#define ALC_NOCHG_INT_HI 15
+#define ALC_NOCHG_INT_SZ 1
+#define NEQ_PKT_FLAG_MSK 0x00010000
+#define NEQ_PKT_FLAG_I_MSK 0xfffeffff
+#define NEQ_PKT_FLAG_SFT 16
+#define NEQ_PKT_FLAG_HI 16
+#define NEQ_PKT_FLAG_SZ 1
+#define NEQ_MB_FLAG_MSK 0x01000000
+#define NEQ_MB_FLAG_I_MSK 0xfeffffff
+#define NEQ_MB_FLAG_SFT 24
+#define NEQ_MB_FLAG_HI 24
+#define NEQ_MB_FLAG_SZ 1
+#define SRAM_TAG_0_MSK 0x0000ffff
+#define SRAM_TAG_0_I_MSK 0xffff0000
+#define SRAM_TAG_0_SFT 0
+#define SRAM_TAG_0_HI 15
+#define SRAM_TAG_0_SZ 16
+#define SRAM_TAG_1_MSK 0xffff0000
+#define SRAM_TAG_1_I_MSK 0x0000ffff
+#define SRAM_TAG_1_SFT 16
+#define SRAM_TAG_1_HI 31
+#define SRAM_TAG_1_SZ 16
+#define SRAM_TAG_2_MSK 0x0000ffff
+#define SRAM_TAG_2_I_MSK 0xffff0000
+#define SRAM_TAG_2_SFT 0
+#define SRAM_TAG_2_HI 15
+#define SRAM_TAG_2_SZ 16
+#define SRAM_TAG_3_MSK 0xffff0000
+#define SRAM_TAG_3_I_MSK 0x0000ffff
+#define SRAM_TAG_3_SFT 16
+#define SRAM_TAG_3_HI 31
+#define SRAM_TAG_3_SZ 16
+#define SRAM_TAG_4_MSK 0x0000ffff
+#define SRAM_TAG_4_I_MSK 0xffff0000
+#define SRAM_TAG_4_SFT 0
+#define SRAM_TAG_4_HI 15
+#define SRAM_TAG_4_SZ 16
+#define SRAM_TAG_5_MSK 0xffff0000
+#define SRAM_TAG_5_I_MSK 0x0000ffff
+#define SRAM_TAG_5_SFT 16
+#define SRAM_TAG_5_HI 31
+#define SRAM_TAG_5_SZ 16
+#define SRAM_TAG_6_MSK 0x0000ffff
+#define SRAM_TAG_6_I_MSK 0xffff0000
+#define SRAM_TAG_6_SFT 0
+#define SRAM_TAG_6_HI 15
+#define SRAM_TAG_6_SZ 16
+#define SRAM_TAG_7_MSK 0xffff0000
+#define SRAM_TAG_7_I_MSK 0x0000ffff
+#define SRAM_TAG_7_SFT 16
+#define SRAM_TAG_7_HI 31
+#define SRAM_TAG_7_SZ 16
+#define SRAM_TAG_8_MSK 0x0000ffff
+#define SRAM_TAG_8_I_MSK 0xffff0000
+#define SRAM_TAG_8_SFT 0
+#define SRAM_TAG_8_HI 15
+#define SRAM_TAG_8_SZ 16
+#define SRAM_TAG_9_MSK 0xffff0000
+#define SRAM_TAG_9_I_MSK 0x0000ffff
+#define SRAM_TAG_9_SFT 16
+#define SRAM_TAG_9_HI 31
+#define SRAM_TAG_9_SZ 16
+#define SRAM_TAG_10_MSK 0x0000ffff
+#define SRAM_TAG_10_I_MSK 0xffff0000
+#define SRAM_TAG_10_SFT 0
+#define SRAM_TAG_10_HI 15
+#define SRAM_TAG_10_SZ 16
+#define SRAM_TAG_11_MSK 0xffff0000
+#define SRAM_TAG_11_I_MSK 0x0000ffff
+#define SRAM_TAG_11_SFT 16
+#define SRAM_TAG_11_HI 31
+#define SRAM_TAG_11_SZ 16
+#define SRAM_TAG_12_MSK 0x0000ffff
+#define SRAM_TAG_12_I_MSK 0xffff0000
+#define SRAM_TAG_12_SFT 0
+#define SRAM_TAG_12_HI 15
+#define SRAM_TAG_12_SZ 16
+#define SRAM_TAG_13_MSK 0xffff0000
+#define SRAM_TAG_13_I_MSK 0x0000ffff
+#define SRAM_TAG_13_SFT 16
+#define SRAM_TAG_13_HI 31
+#define SRAM_TAG_13_SZ 16
+#define SRAM_TAG_14_MSK 0x0000ffff
+#define SRAM_TAG_14_I_MSK 0xffff0000
+#define SRAM_TAG_14_SFT 0
+#define SRAM_TAG_14_HI 15
+#define SRAM_TAG_14_SZ 16
+#define SRAM_TAG_15_MSK 0xffff0000
+#define SRAM_TAG_15_I_MSK 0x0000ffff
+#define SRAM_TAG_15_SFT 16
+#define SRAM_TAG_15_HI 31
+#define SRAM_TAG_15_SZ 16
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_common.h b/drivers/net/wireless/ssv6051/include/ssv6200_common.h
new file mode 100644
index 000000000000..e6d30f3714f7
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_common.h
@@ -0,0 +1,452 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV6200_COMMON_H_
+#define _SSV6200_COMMON_H_
+#define FW_VERSION_REG ADR_TX_SEG
+#define M_ENG_CPU 0x00
+#define M_ENG_HWHCI 0x01
+#define M_ENG_EMPTY 0x02
+#define M_ENG_ENCRYPT 0x03
+#define M_ENG_MACRX 0x04
+#define M_ENG_MIC 0x05
+#define M_ENG_TX_EDCA0 0x06
+#define M_ENG_TX_EDCA1 0x07
+#define M_ENG_TX_EDCA2 0x08
+#define M_ENG_TX_EDCA3 0x09
+#define M_ENG_TX_MNG 0x0A
+#define M_ENG_ENCRYPT_SEC 0x0B
+#define M_ENG_MIC_SEC 0x0C
+#define M_ENG_RESERVED_1 0x0D
+#define M_ENG_RESERVED_2 0x0E
+#define M_ENG_TRASH_CAN 0x0F
+#define M_ENG_MAX (M_ENG_TRASH_CAN+1)
+#define M_CPU_HWENG 0x00
+#define M_CPU_TXL34CS 0x01
+#define M_CPU_RXL34CS 0x02
+#define M_CPU_DEFRAG 0x03
+#define M_CPU_EDCATX 0x04
+#define M_CPU_RXDATA 0x05
+#define M_CPU_RXMGMT 0x06
+#define M_CPU_RXCTRL 0x07
+#define M_CPU_FRAG 0x08
+#define M_CPU_TXTPUT 0x09
+#ifndef ID_TRAP_SW_TXTPUT
+#define ID_TRAP_SW_TXTPUT 50
+#endif
+#define M0_TXREQ 0
+#define M1_TXREQ 1
+#define M2_TXREQ 2
+#define M0_RXEVENT 3
+#define M2_RXEVENT 4
+#define HOST_CMD 5
+#define HOST_EVENT 6
+#define TEST_CMD 7
+#define SSV6XXX_RX_DESC_LEN \
+ (sizeof(struct ssv6200_rx_desc) + \
+ sizeof(struct ssv6200_rxphy_info))
+#define SSV6XXX_TX_DESC_LEN \
+ (sizeof(struct ssv6200_tx_desc) + 0)
+#define TXPB_OFFSET 80
+#define RXPB_OFFSET 80
+#define SSV6200_TX_PKT_RSVD_SETTING 0x3
+#define SSV6200_TX_PKT_RSVD SSV6200_TX_PKT_RSVD_SETTING*16
+#define SSV6200_ALLOC_RSVD TXPB_OFFSET+SSV6200_TX_PKT_RSVD
+#define SSV62XX_TX_MAX_RATES 3
+
+enum ssv6xxx_sr_bhvr {
+ SUSPEND_RESUME_0,
+ SUSPEND_RESUME_1,
+ SUSPEND_RESUME_MAX
+};
+
+enum ssv6xxx_reboot_bhvr {
+ SSV_SYS_REBOOT = 1,
+ SSV_SYS_HALF,
+ SSV_SYS_POWER_OFF
+};
+
+struct fw_rc_retry_params {
+ u32 count:4;
+ u32 drate:6;
+ u32 crate:6;
+ u32 rts_cts_nav:16;
+ u32 frame_consume_time:10;
+ u32 dl_length:12;
+ u32 RSVD:10;
+} __attribute__((packed));
+struct ssv6200_tx_desc {
+ u32 len:16;
+ u32 c_type:3;
+ u32 f80211:1;
+ u32 qos:1;
+ u32 ht:1;
+ u32 use_4addr:1;
+ u32 RSVD_0:3;
+ u32 bc_que:1;
+ u32 security:1;
+ u32 more_data:1;
+ u32 stype_b5b4:2;
+ u32 extra_info:1;
+ u32 fCmd;
+ u32 hdr_offset:8;
+ u32 frag:1;
+ u32 unicast:1;
+ u32 hdr_len:6;
+ u32 tx_report:1;
+ u32 tx_burst:1;
+ u32 ack_policy:2;
+ u32 aggregation:1;
+ u32 RSVD_1:3;
+ u32 do_rts_cts:2;
+ u32 reason:6;
+ u32 payload_offset:8;
+ u32 RSVD_4:7;
+ u32 RSVD_2:1;
+ u32 fCmdIdx:3;
+ u32 wsid:4;
+ u32 txq_idx:3;
+ u32 TxF_ID:6;
+ u32 rts_cts_nav:16;
+ u32 frame_consume_time:10;
+ u32 crate_idx:6;
+ u32 drate_idx:6;
+ u32 dl_length:12;
+ u32 RSVD_3:14;
+ u32 RESERVED[8];
+ struct fw_rc_retry_params rc_params[SSV62XX_TX_MAX_RATES];
+};
+struct ssv6200_rx_desc {
+ u32 len:16;
+ u32 c_type:3;
+ u32 f80211:1;
+ u32 qos:1;
+ u32 ht:1;
+ u32 use_4addr:1;
+ u32 l3cs_err:1;
+ u32 l4cs_err:1;
+ u32 align2:1;
+ u32 RSVD_0:2;
+ u32 psm:1;
+ u32 stype_b5b4:2;
+ u32 extra_info:1;
+ u32 edca0_used:4;
+ u32 edca1_used:5;
+ u32 edca2_used:5;
+ u32 edca3_used:5;
+ u32 mng_used:4;
+ u32 tx_page_used:9;
+ u32 hdr_offset:8;
+ u32 frag:1;
+ u32 unicast:1;
+ u32 hdr_len:6;
+ u32 RxResult:8;
+ u32 wildcard_bssid:1;
+ u32 RSVD_1:1;
+ u32 reason:6;
+ u32 payload_offset:8;
+ u32 tx_id_used:8;
+ u32 fCmdIdx:3;
+ u32 wsid:4;
+ u32 RSVD_3:3;
+ u32 rate_idx:6;
+};
+struct ssv6200_rxphy_info {
+ u32 len:16;
+ u32 rsvd0:16;
+ u32 mode:3;
+ u32 ch_bw:3;
+ u32 preamble:1;
+ u32 ht_short_gi:1;
+ u32 rate:7;
+ u32 rsvd1:1;
+ u32 smoothing:1;
+ u32 no_sounding:1;
+ u32 aggregate:1;
+ u32 stbc:2;
+ u32 fec:1;
+ u32 n_ess:2;
+ u32 rsvd2:8;
+ u32 l_length:12;
+ u32 l_rate:3;
+ u32 rsvd3:17;
+ u32 rsvd4;
+ u32 rpci:8;
+ u32 snr:8;
+ u32 service:16;
+};
+struct ssv6200_rxphy_info_padding {
+ u32 rpci:8;
+ u32 snr:8;
+ u32 RSVD:16;
+};
+struct ssv6200_txphy_info {
+ u32 rsvd[7];
+};
+#ifdef CONFIG_P2P_NOA
+struct ssv6xxx_p2p_noa_param {
+ u32 duration;
+ u32 interval;
+ u32 start_time;
+ u32 enable:8;
+ u32 count:8;
+ u8 addr[6];
+ u8 vif_id;
+} __attribute__((packed));
+#endif
+typedef struct cfg_host_cmd {
+ u32 len:16;
+ u32 c_type:3;
+ u32 RSVD0:5;
+ u32 h_cmd:8;
+ u32 cmd_seq_no;
+ union {
+ u32 dummy;
+ u8 dat8[0];
+ u16 dat16[0];
+ u32 dat32[0];
+ };
+} HDR_HostCmd;
+#define HOST_CMD_HDR_LEN ((size_t)(((HDR_HostCmd *)100)->dat8)-100U)
+struct sdio_rxtput_cfg {
+ u32 size_per_frame;
+ u32 total_frames;
+};
+typedef enum {
+ SSV6XXX_HOST_CMD_START = 0,
+ SSV6XXX_HOST_CMD_LOG,
+ SSV6XXX_HOST_CMD_PS,
+ SSV6XXX_HOST_CMD_INIT_CALI,
+ SSV6XXX_HOST_CMD_RX_TPUT,
+ SSV6XXX_HOST_CMD_TX_TPUT,
+ SSV6XXX_HOST_CMD_WATCHDOG_START,
+ SSV6XXX_HOST_CMD_WATCHDOG_STOP,
+ SSV6XXX_HOST_CMD_WSID_OP,
+#ifdef CONFIG_P2P_NOA
+ SSV6XXX_HOST_CMD_SET_NOA,
+#endif
+ SSV6XXX_HOST_SOC_CMD_MAXID,
+} ssv6xxx_host_cmd_id;
+#define SSV_NUM_HW_STA 2
+typedef struct cfg_host_event {
+ u32 len:16;
+ u32 c_type:3;
+ u32 RSVD0:5;
+ u32 h_event:8;
+ u32 evt_seq_no;
+ u8 dat[0];
+} HDR_HostEvent;
+typedef enum {
+#ifdef USE_CMD_RESP
+ SOC_EVT_CMD_RESP,
+ SOC_EVT_SCAN_RESULT,
+ SOC_EVT_DEAUTH,
+#else
+ SOC_EVT_GET_REG_RESP,
+#endif
+ SOC_EVT_NO_BA,
+ SOC_EVT_RC_MPDU_REPORT,
+ SOC_EVT_RC_AMPDU_REPORT,
+ SOC_EVT_LOG,
+#ifdef CONFIG_P2P_NOA
+ SOC_EVT_NOA,
+#endif
+ SOC_EVT_USER_END,
+ SOC_EVT_SDIO_TEST_COMMAND,
+ SOC_EVT_RESET_HOST,
+ SOC_EVT_SDIO_TXTPUT_RESULT,
+ SOC_EVT_WATCHDOG_TRIGGER,
+ SOC_EVT_TXLOOPBK_RESULT,
+ SOC_EVT_MAXID,
+} ssv6xxx_soc_event;
+#ifdef CONFIG_P2P_NOA
+typedef enum {
+ SSV6XXX_NOA_START = 0,
+ SSV6XXX_NOA_STOP,
+} ssv6xxx_host_noa_event;
+struct ssv62xx_noa_evt {
+ u8 evt_id;
+ u8 vif;
+} __attribute__((packed));
+#endif
+typedef enum {
+ SSV6XXX_RC_COUNTER_CLEAR = 1,
+ SSV6XXX_RC_REPORT,
+} ssv6xxx_host_rate_control_event;
+#define MAX_AGGR_NUM (24)
+struct ssv62xx_tx_rate {
+ s8 data_rate;
+ u8 count;
+} __attribute__((packed));
+struct ampdu_ba_notify_data {
+ u8 wsid;
+ struct ssv62xx_tx_rate tried_rates[SSV62XX_TX_MAX_RATES];
+ u16 seq_no[MAX_AGGR_NUM];
+} __attribute__((packed));
+struct firmware_rate_control_report_data {
+ u8 wsid;
+ struct ssv62xx_tx_rate rates[SSV62XX_TX_MAX_RATES];
+ u16 ampdu_len;
+ u16 ampdu_ack_len;
+ int ack_signal;
+} __attribute__((packed));
+#define RC_RETRY_PARAM_OFFSET ((sizeof(struct fw_rc_retry_params))*SSV62XX_TX_MAX_RATES)
+#define SSV_RC_RATE_MAX 39
+enum SSV6XXX_WSID_OPS {
+ SSV6XXX_WSID_OPS_ADD,
+ SSV6XXX_WSID_OPS_DEL,
+ SSV6XXX_WSID_OPS_RESETALL,
+ SSV6XXX_WSID_OPS_ENABLE_CAPS,
+ SSV6XXX_WSID_OPS_DISABLE_CAPS,
+ SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE,
+ SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE,
+ SSV6XXX_WSID_OPS_MAX
+};
+enum SSV6XXX_WSID_SEC {
+ SSV6XXX_WSID_SEC_NONE = 0,
+ SSV6XXX_WSID_SEC_PAIRWISE = 1 << 0,
+ SSV6XXX_WSID_SEC_GROUP = 1 << 1,
+};
+enum SSV6XXX_WSID_SEC_TYPE {
+ SSV6XXX_WSID_SEC_SW,
+ SSV6XXX_WSID_SEC_HW,
+ SSV6XXX_WSID_SEC_TYPE_MAX
+};
+enum SSV6XXX_RETURN_STATE {
+ SSV6XXX_STATE_OK,
+ SSV6XXX_STATE_NG,
+ SSV6XXX_STATE_MAX
+};
+struct ssv6xxx_wsid_params {
+ u8 cmd;
+ u8 wsid_idx;
+ u8 target_wsid[6];
+ u8 hw_security;
+};
+struct ssv6xxx_iqk_cfg {
+ u32 cfg_xtal:8;
+ u32 cfg_pa:8;
+ u32 cfg_pabias_ctrl:8;
+ u32 cfg_pacascode_ctrl:8;
+ u32 cfg_tssi_trgt:8;
+ u32 cfg_tssi_div:8;
+ u32 cfg_def_tx_scale_11b:8;
+ u32 cfg_def_tx_scale_11b_p0d5:8;
+ u32 cfg_def_tx_scale_11g:8;
+ u32 cfg_def_tx_scale_11g_p0d5:8;
+ u32 cmd_sel;
+ union {
+ u32 fx_sel;
+ u32 argv;
+ };
+ u32 phy_tbl_size;
+ u32 rf_tbl_size;
+};
+#define PHY_SETTING_SIZE sizeof(phy_setting)
+struct ssv6xxx_ch_cfg {
+ u32 reg_addr;
+ u32 ch1_12_value;
+ u32 ch13_14_value;
+};
+#define IQK_CFG_LEN (sizeof(struct ssv6xxx_iqk_cfg))
+#define RF_SETTING_SIZE (sizeof(asic_rf_setting))
+#define MAX_PHY_SETTING_TABLE_SIZE 1920
+#define MAX_RF_SETTING_TABLE_SIZE 512
+typedef enum {
+ SSV6XXX_VOLT_DCDC_CONVERT = 0,
+ SSV6XXX_VOLT_LDO_CONVERT,
+} ssv6xxx_cfg_volt;
+typedef enum {
+ SSV6XXX_VOLT_33V = 0,
+ SSV6XXX_VOLT_42V,
+} ssv6xxx_cfg_volt_value;
+typedef enum {
+ SSV6XXX_IQK_CFG_XTAL_26M = 0,
+ SSV6XXX_IQK_CFG_XTAL_40M,
+ SSV6XXX_IQK_CFG_XTAL_24M,
+ SSV6XXX_IQK_CFG_XTAL_MAX,
+} ssv6xxx_iqk_cfg_xtal;
+typedef enum {
+ SSV6XXX_IQK_CFG_PA_DEF = 0,
+ SSV6XXX_IQK_CFG_PA_LI_MPB,
+ SSV6XXX_IQK_CFG_PA_LI_EVB,
+ SSV6XXX_IQK_CFG_PA_HP,
+} ssv6xxx_iqk_cfg_pa;
+typedef enum {
+ SSV6XXX_IQK_CMD_INIT_CALI = 0,
+ SSV6XXX_IQK_CMD_RTBL_LOAD,
+ SSV6XXX_IQK_CMD_RTBL_LOAD_DEF,
+ SSV6XXX_IQK_CMD_RTBL_RESET,
+ SSV6XXX_IQK_CMD_RTBL_SET,
+ SSV6XXX_IQK_CMD_RTBL_EXPORT,
+ SSV6XXX_IQK_CMD_TK_EVM,
+ SSV6XXX_IQK_CMD_TK_TONE,
+ SSV6XXX_IQK_CMD_TK_CHCH,
+} ssv6xxx_iqk_cmd_sel;
+#define SSV6XXX_IQK_TEMPERATURE 0x00000004
+#define SSV6XXX_IQK_RXDC 0x00000008
+#define SSV6XXX_IQK_RXRC 0x00000010
+#define SSV6XXX_IQK_TXDC 0x00000020
+#define SSV6XXX_IQK_TXIQ 0x00000040
+#define SSV6XXX_IQK_RXIQ 0x00000080
+#define SSV6XXX_IQK_TSSI 0x00000100
+#define SSV6XXX_IQK_PAPD 0x00000200
+typedef struct ssv_cabrio_reg_st {
+ u32 address;
+ u32 data;
+} ssv_cabrio_reg;
+typedef enum __PBuf_Type_E {
+ NOTYPE_BUF = 0,
+ TX_BUF = 1,
+ RX_BUF = 2
+} PBuf_Type_E;
+struct SKB_info_st {
+ struct ieee80211_sta *sta;
+ u16 mpdu_retry_counter;
+ unsigned long aggr_timestamp;
+ u16 ampdu_tx_status;
+ u16 ampdu_tx_final_retry_count;
+ u16 lowest_rate;
+ struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+ ktime_t timestamp;
+#endif
+};
+typedef struct SKB_info_st SKB_info;
+typedef struct SKB_info_st *p_SKB_info;
+#define SSV_SKB_info_size (sizeof(struct SKB_info_st))
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+#define SKB_DURATION_TIMEOUT_MS 100
+enum ssv_debug_skb_timestamp {
+ SKB_DURATION_STAGE_TX_ENQ,
+ SKB_DURATION_STAGE_TO_SDIO,
+ SKB_DURATION_STAGE_IN_HWQ,
+ SKB_DURATION_STAGE_END
+};
+#endif
+#define SSV6051Q_P1 0x00000000
+#define SSV6051Q_P2 0x70000000
+#define SSV6051Z 0x71000000
+#define SSV6051Q 0x73000000
+#define SSV6051P 0x75000000
+struct ssv6xxx_tx_loopback {
+ u32 reg;
+ u32 val;
+ u32 restore_val;
+ u8 restore;
+ u8 delay_ms;
+};
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h b/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
new file mode 100644
index 000000000000..0327393de3f5
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static ssv_cabrio_reg phy_setting[] = {
+ {0xce0071bc, 0x565B565B},
+ {0xce000008, 0x0000006a},
+ {0xce00000c, 0x00000064},
+ {0xce000010, 0x00007FFF},
+ {0xce000014, 0x00000003},
+ {0xce000018, 0x0055003C},
+ {0xce00001c, 0x00000064},
+ {0xce000020, 0x20000000},
+ {0xce00002c, 0x00000000},
+ {0xce000030, 0x80046072},
+ {0xce000034, 0x1f300f6f},
+ {0xce000038, 0x660F36D0},
+ {0xce00003c, 0x106C0004},
+ {0xce000040, 0x01601400},
+ {0xce000044, 0x00600008},
+ {0xce000048, 0xff000160},
+ {0xce00004c, 0x00000840},
+ {0xce000060, 0x01000405},
+ {0xce000064, 0x06090813},
+ {0xce000068, 0x12070000},
+ {0xce00006c, 0x01000405},
+ {0xce000070, 0x06090813},
+ {0xce000074, 0x12010000},
+ {0xce000078, 0x00000000},
+ {0xce00007c, 0x10110003},
+ {0xce000080, 0x0110000F},
+ {0xce000084, 0x00000000},
+ {0xce000088, 0x00000000},
+ {0xce000094, 0x01012425},
+ {0xce000098, 0x01010101},
+ {0xce00009c, 0x00000011},
+ {0xce0000a0, 0x1fff0000},
+ {0xce0000a4, 0x1fff0000},
+ {0xce0000a8, 0x1fff0000},
+ {0xce0000ac, 0x1fff0000},
+ {0xce0000b8, 0x0000fe3e},
+ {0xce0000fc, 0xffffffff},
+ {0xce000108, 0x0ead04f5},
+ {0xce00010c, 0x0fd60080},
+ {0xce000110, 0x00000009},
+ {0xce0010a4, 0x0000002c},
+ {0xce0010b4, 0x00003001},
+ {0xce0010d4, 0x00000001},
+ {0xce002000, 0x00000044},
+ {0xce002004, 0x00040000},
+ {0xce002008, 0x20300050},
+ {0xce00200c, 0x00003467},
+ {0xce002010, 0x00430000},
+ {0xce002014, 0x20304015},
+ {0xce002018, 0x00390005},
+ {0xce00201c, 0x05555555},
+ {0xce002020, 0x00570057},
+ {0xce002024, 0x00570057},
+ {0xce002028, 0x00236700},
+ {0xce00202c, 0x000d1746},
+ {0xce002030, 0x05061787},
+ {0xce002034, 0x07800000},
+ {0xce00209c, 0x00900008},
+ {0xce0020a0, 0x00000000},
+ {0xce0023f8, 0x00000000},
+ {0xce0023fc, 0x00000001},
+ {0xce0030a4, 0x00001901},
+ {0xce0030b8, 0x5d08908e},
+ {0xce004000, 0x00000044},
+ {0xce004004, 0x00750075},
+ {0xce004008, 0x00000075},
+ {0xce00400c, 0x10000075},
+ {0xce004010, 0x3F384905},
+ {0xce004014, 0x40182000},
+ {0xce004018, 0x20600000},
+ {0xce00401c, 0x0C010120},
+ {0xce004020, 0x50505050},
+ {0xce004024, 0x50000000},
+ {0xce004028, 0x50505050},
+ {0xce00402c, 0x506070A0},
+ {0xce004030, 0xF0000000},
+ {0xce004034, 0x00002424},
+ {0xce004038, 0x00001420},
+ {0xce00409c, 0x0000300A},
+ {0xce0040c0, 0x20000280},
+ {0xce0040c4, 0x30023002},
+ {0xce0040c8, 0x0000003a},
+ {0xce004130, 0x40000000},
+ {0xce004164, 0x009C007E},
+ {0xce004180, 0x00044400},
+ {0xce004188, 0x82000000},
+ {0xce004190, 0x00000000},
+ {0xce004194, 0xffffffff},
+ {0xce004380, 0x00700010},
+ {0xce004384, 0x00007575},
+ {0xce004388, 0x0001fe3e},
+ {0xce00438c, 0x0000fe3e},
+ {0xce0043f8, 0x00000001},
+ {0xce007000, 0x00000000},
+ {0xce007004, 0x00008000},
+ {0xce007008, 0x00000000},
+ {0xce00700c, 0x00000000},
+ {0xce007010, 0x00000000},
+ {0xce007014, 0x00000000},
+ {0xce007018, 0x00000000},
+ {0xce00701c, 0x00000000},
+ {0xce007020, 0x00000000},
+ {0xce007024, 0x00000000},
+ {0xce007028, 0x00000000},
+ {0xce00702c, 0x00000000},
+ {0xce007030, 0x00000000},
+ {0xce007034, 0x00000000},
+ {0xce007038, 0x00000000},
+ {0xce00703c, 0x00000000},
+ {0xce007040, 0x02000200},
+ {0xce007048, 0x00000000},
+ {0xce00704c, 0x00000000},
+ {0xce007050, 0x00000000},
+ {0xce007054, 0x00000000},
+ {0xce007058, 0x000028ff},
+ {0xce00705c, 0x00000000},
+ {0xce007060, 0x00000000},
+ {0xce007064, 0x00000000},
+ {0xce007068, 0x00000000},
+ {0xce00706c, 0x00000202},
+ {0xce007070, 0x80ffc200},
+ {0xce007074, 0x00000000},
+ {0xce007078, 0x00000000},
+ {0xce00707c, 0x00000000},
+ {0xce007080, 0x00000000},
+ {0xce007084, 0x00000000},
+ {0xce007088, 0x00000000},
+ {0xce00708c, 0x00000000},
+ {0xce007090, 0x00000000},
+ {0xce007094, 0x00000000},
+ {0xce007098, 0x00000000},
+ {0xce00709c, 0x00000000},
+ {0xce0070a0, 0x00000000},
+ {0xce0070a4, 0x00000000},
+ {0xce0070a8, 0x00000000},
+ {0xce0070ac, 0x00000000},
+ {0xce0070b0, 0x00000000},
+ {0xce0070b4, 0x00000000},
+ {0xce0070b8, 0x00000000},
+ {0xce0070bc, 0x00000000},
+ {0xce0070c0, 0x00000000},
+ {0xce0070c4, 0x00000000},
+ {0xce0070c8, 0x00000000},
+ {0xce0070cc, 0x00000000},
+ {0xce0070d0, 0x00000000},
+ {0xce0070d4, 0x00000000},
+ {0xce0070d8, 0x00000000},
+ {0xce0070dc, 0x00000000},
+ {0xce0070e0, 0x00000000},
+ {0xce0070e4, 0x00000000},
+ {0xce0070e8, 0x00000000},
+ {0xce0070ec, 0x00000000},
+ {0xce0070f0, 0x00000000},
+ {0xce0070f4, 0x00000000},
+ {0xce0070f8, 0x00000000},
+ {0xce0070fc, 0x00000000},
+ {0xce007100, 0x00000000},
+ {0xce007104, 0x00000000},
+ {0xce007108, 0x00000000},
+ {0xce00710c, 0x00000000},
+ {0xce007110, 0x00000000},
+ {0xce007114, 0x00000000},
+ {0xce007118, 0x00000000},
+ {0xce00711c, 0x00000000},
+ {0xce007120, 0x02000200},
+ {0xce007124, 0x02000200},
+ {0xce007128, 0x02000200},
+ {0xce00712c, 0x02000200},
+ {0xce007130, 0x02000200},
+ {0xce007134, 0x02000200},
+ {0xce007138, 0x02000200},
+ {0xce00713c, 0x02000200},
+ {0xce007140, 0x02000200},
+ {0xce007144, 0x02000200},
+ {0xce007148, 0x02000200},
+ {0xce00714c, 0x02000200},
+ {0xce007150, 0x02000200},
+ {0xce007154, 0x02000200},
+ {0xce007158, 0x00000000},
+ {0xce00715c, 0x00000000},
+ {0xce007160, 0x00000000},
+ {0xce007164, 0x00000000},
+ {0xce007168, 0x00000000},
+ {0xce00716c, 0x00000000},
+ {0xce007170, 0x00000000},
+ {0xce007174, 0x00000000},
+ {0xce007178, 0x00000000},
+ {0xce00717c, 0x00000000},
+ {0xce007180, 0x00000000},
+ {0xce007184, 0x00000000},
+ {0xce007188, 0x00000000},
+ {0xce00718c, 0x00000000},
+ {0xce007190, 0x00000000},
+ {0xce007194, 0x00000000},
+ {0xce007198, 0x00000000},
+ {0xce00719c, 0x00000000},
+ {0xce0071a0, 0x00000000},
+ {0xce0071a4, 0x00000000},
+ {0xce0071a8, 0x00000000},
+ {0xce0071ac, 0x00000000},
+ {0xce0071b0, 0x00000000},
+ {0xce0071b4, 0x00000100},
+ {0xce0071b8, 0x00000000},
+ {0xce0071c0, 0x00000000},
+ {0xce0071c4, 0x00000000},
+ {0xce0071c8, 0x00000000},
+ {0xce0071cc, 0x00000000},
+ {0xce0071d0, 0x00000000},
+ {0xce0071d4, 0x00000000},
+ {0xce0071d8, 0x00000000},
+ {0xce0071dc, 0x00000000},
+ {0xce0071e0, 0x00000000},
+ {0xce0071e4, 0x00000000},
+ {0xce0071e8, 0x00000000},
+ {0xce0071ec, 0x00000000},
+ {0xce0071f0, 0x00000000},
+ {0xce0071f4, 0x00000000},
+ {0xce0071f8, 0x00000000},
+ {0xce0071fc, 0x00000000},
+ {0xce0043fc, 0x000104E5},
+ {0xce007044, 0x00028080},
+ {0xce000000, 0x80000016},
+};
+
+static const u32 wifi_tx_gain[] = {
+ 0x79807980,
+ 0x72797279,
+ 0x6C726C72,
+ 0x666C666C,
+ 0x60666066,
+ 0x5B605B60,
+ 0x565B565B,
+ 0x51565156,
+ 0x4C514C51,
+ 0x484C484C,
+ 0x44484448,
+ 0x40444044,
+ 0x3C403C40,
+ 0x3A3D3A3D,
+ 0x36393639,
+};
+
+static ssv_cabrio_reg asic_rf_setting[] = {
+ {0xCE010038, 0x0003E07C},
+ {0xCE010060, 0x00406000},
+ {0xCE01009C, 0x00000024},
+ {0xCE0100A0, 0x00EC4CC5},
+ {0xCE010000, 0x40002000},
+ {0xCE010004, 0x00020FC0},
+ {0xCE010008, 0x000DF69B},
+ {0xCE010014, 0x3D3E84FE},
+ {0xCE010018, 0x01457D79},
+ {0xCE01001C, 0x000103A7},
+ {0xCE010020, 0x000103A6},
+ {0xCE01002C, 0x00032CA8},
+ {0xCE010048, 0xFCCCCF27},
+ {0xCE010050, 0x00444000},
+ {0xCE01000C, 0x151558C5},
+ {0xCE010010, 0x01011A88},
+ {0xCE010024, 0x00012001},
+ {0xCE010028, 0x00036000},
+ {0xCE010030, 0x20EA0224},
+ {0xCE010034, 0x44000755},
+ {0xCE01003C, 0x55D89D8A},
+ {0xCE010040, 0x005508BB},
+ {0xCE010044, 0x07C08BFF},
+ {0xCE01004C, 0x07700830},
+ {0xCE010054, 0x00007FF4},
+ {0xCE010058, 0x0000000E},
+ {0xCE01005C, 0x00088018},
+ {0xCE010064, 0x08820820},
+ {0xCE010068, 0x00820820},
+ {0xCE01006C, 0x00820820},
+ {0xCE010070, 0x00820820},
+ {0xCE010074, 0x00820820},
+ {0xCE010078, 0x00820820},
+ {0xCE01007C, 0x00820820},
+ {0xCE010080, 0x00820820},
+ {0xCE010084, 0x00004080},
+ {0xCE010088, 0x200800FE},
+ {0xCE01008C, 0xAAAAAAAA},
+ {0xCE010090, 0xAAAAAAAA},
+ {0xCE010094, 0x0000A487},
+ {0xCE010098, 0x0000070E},
+ {0xCE0100A4, 0x00000F43},
+ {0xCE0100A8, 0x00098900},
+ {0xCE0100AC, 0x00000000},
+ {0xC00003AC, 0x00000000},
+ {0xC00003B0, 0x00000000},
+ {0xC00003B4, 0x00000000},
+ {0xC00003BC, 0x00000000},
+ {0xC0001D00, 0x5E000040},
+ {0xC0001D04, 0x015D015D},
+ {0xC0001D08, 0x00000001},
+ {0xC0001D0C, 0x55550000},
+ {0xC0001D20, 0x7FFF0000},
+ {0xC0001D24, 0x00000003},
+ {0xC0001D28, 0x00000000},
+ {0xC0001D2C, 0x00000000},
+};
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_reg.h b/drivers/net/wireless/ssv6051/include/ssv6200_reg.h
new file mode 100644
index 000000000000..d4a99b25d61f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_reg.h
@@ -0,0 +1,9694 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define SYS_REG_BASE 0xc0000000
+#define WBOOT_REG_BASE 0xc0000100
+#define TU0_US_REG_BASE 0xc0000200
+#define TU1_US_REG_BASE 0xc0000210
+#define TU2_US_REG_BASE 0xc0000220
+#define TU3_US_REG_BASE 0xc0000230
+#define TM0_MS_REG_BASE 0xc0000240
+#define TM1_MS_REG_BASE 0xc0000250
+#define TM2_MS_REG_BASE 0xc0000260
+#define TM3_MS_REG_BASE 0xc0000270
+#define MCU_WDT_REG_BASE 0xc0000280
+#define SYS_WDT_REG_BASE 0xc0000284
+#define GPIO_REG_BASE 0xc0000300
+#define SD_REG_BASE 0xc0000800
+#define SPI_REG_BASE 0xc0000a00
+#define CSR_I2C_MST_BASE 0xc0000b00
+#define UART_REG_BASE 0xc0000c00
+#define DAT_UART_REG_BASE 0xc0000d00
+#define INT_REG_BASE 0xc0000e00
+#define DBG_SPI_REG_BASE 0xc0000f00
+#define FLASH_SPI_REG_BASE 0xc0001000
+#define DMA_REG_BASE 0xc0001c00
+#define CSR_PMU_BASE 0xc0001d00
+#define CSR_RTC_BASE 0xc0001d20
+#define RTC_RAM_BASE 0xc0001d80
+#define D2_DMA_REG_BASE 0xc0001e00
+#define HCI_REG_BASE 0xc1000000
+#define CO_REG_BASE 0xc2000000
+#define EFS_REG_BASE 0xc2000100
+#define SMS4_REG_BASE 0xc3000000
+#define MRX_REG_BASE 0xc6000000
+#define AMPDU_REG_BASE 0xc6001000
+#define MT_REG_CSR_BASE 0xc6002000
+#define TXQ0_MT_Q_REG_CSR_BASE 0xc6002100
+#define TXQ1_MT_Q_REG_CSR_BASE 0xc6002200
+#define TXQ2_MT_Q_REG_CSR_BASE 0xc6002300
+#define TXQ3_MT_Q_REG_CSR_BASE 0xc6002400
+#define TXQ4_MT_Q_REG_CSR_BASE 0xc6002500
+#define HIF_INFO_BASE 0xca000000
+#define PHY_RATE_INFO_BASE 0xca000200
+#define MAC_GLB_SET_BASE 0xca000300
+#define BTCX_REG_BASE 0xca000400
+#define MIB_REG_BASE 0xca000800
+#define CBR_A_REG_BASE 0xcb000000
+#define MB_REG_BASE 0xcd000000
+#define ID_MNG_REG_BASE 0xcd010000
+#define CSR_PHY_BASE 0xce000000
+#define CSR_RF_BASE 0xce010000
+#define MMU_REG_BASE 0xcf000000
+#define SYS_REG_BANK_SIZE 0x000000b4
+#define WBOOT_REG_BANK_SIZE 0x0000000c
+#define TU0_US_REG_BANK_SIZE 0x00000010
+#define TU1_US_REG_BANK_SIZE 0x00000010
+#define TU2_US_REG_BANK_SIZE 0x00000010
+#define TU3_US_REG_BANK_SIZE 0x00000010
+#define TM0_MS_REG_BANK_SIZE 0x00000010
+#define TM1_MS_REG_BANK_SIZE 0x00000010
+#define TM2_MS_REG_BANK_SIZE 0x00000010
+#define TM3_MS_REG_BANK_SIZE 0x00000010
+#define MCU_WDT_REG_BANK_SIZE 0x00000004
+#define SYS_WDT_REG_BANK_SIZE 0x00000004
+#define GPIO_REG_BANK_SIZE 0x000000d4
+#define SD_REG_BANK_SIZE 0x00000180
+#define SPI_REG_BANK_SIZE 0x00000040
+#define CSR_I2C_MST_BANK_SIZE 0x00000018
+#define UART_REG_BANK_SIZE 0x00000028
+#define DAT_UART_REG_BANK_SIZE 0x00000028
+#define INT_REG_BANK_SIZE 0x0000004c
+#define DBG_SPI_REG_BANK_SIZE 0x00000040
+#define FLASH_SPI_REG_BANK_SIZE 0x0000002c
+#define DMA_REG_BANK_SIZE 0x00000014
+#define CSR_PMU_BANK_SIZE 0x00000100
+#define CSR_RTC_BANK_SIZE 0x000000e0
+#define RTC_RAM_BANK_SIZE 0x00000080
+#define D2_DMA_REG_BANK_SIZE 0x00000014
+#define HCI_REG_BANK_SIZE 0x000000cc
+#define CO_REG_BANK_SIZE 0x000000ac
+#define EFS_REG_BANK_SIZE 0x0000006c
+#define SMS4_REG_BANK_SIZE 0x00000070
+#define MRX_REG_BANK_SIZE 0x00000198
+#define AMPDU_REG_BANK_SIZE 0x00000014
+#define MT_REG_CSR_BANK_SIZE 0x00000100
+#define TXQ0_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ1_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ2_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ3_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ4_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define HIF_INFO_BANK_SIZE 0x0000009c
+#define PHY_RATE_INFO_BANK_SIZE 0x000000b8
+#define MAC_GLB_SET_BANK_SIZE 0x0000003c
+#define BTCX_REG_BANK_SIZE 0x0000000c
+#define MIB_REG_BANK_SIZE 0x00000480
+#define CBR_A_REG_BANK_SIZE 0x001203fc
+#define MB_REG_BANK_SIZE 0x000000a0
+#define ID_MNG_REG_BANK_SIZE 0x00000084
+#define CSR_PHY_BANK_SIZE 0x000071c0
+#define CSR_RF_BANK_SIZE 0x000000b0
+#define MMU_REG_BANK_SIZE 0x000000c0
+#define ADR_BRG_SW_RST (SYS_REG_BASE+0x00000000)
+#define ADR_BOOT (SYS_REG_BASE+0x00000004)
+#define ADR_CHIP_ID_0 (SYS_REG_BASE+0x00000008)
+#define ADR_CHIP_ID_1 (SYS_REG_BASE+0x0000000c)
+#define ADR_CHIP_ID_2 (SYS_REG_BASE+0x00000010)
+#define ADR_CHIP_ID_3 (SYS_REG_BASE+0x00000014)
+#define ADR_CLOCK_SELECTION (SYS_REG_BASE+0x00000018)
+#define ADR_PLATFORM_CLOCK_ENABLE (SYS_REG_BASE+0x0000001c)
+#define ADR_SYS_CSR_CLOCK_ENABLE (SYS_REG_BASE+0x00000020)
+#define ADR_MCU_DBG_SEL (SYS_REG_BASE+0x00000024)
+#define ADR_MCU_DBG_DATA (SYS_REG_BASE+0x00000028)
+#define ADR_AHB_BRG_STATUS (SYS_REG_BASE+0x0000002c)
+#define ADR_BIST_BIST_CTRL (SYS_REG_BASE+0x00000030)
+#define ADR_BIST_MODE_REG_IN (SYS_REG_BASE+0x00000034)
+#define ADR_BIST_MODE_REG_OUT (SYS_REG_BASE+0x00000038)
+#define ADR_BIST_MONITOR_BUS_LSB (SYS_REG_BASE+0x0000003c)
+#define ADR_BIST_MONITOR_BUS_MSB (SYS_REG_BASE+0x00000040)
+#define ADR_TB_ADR_SEL (SYS_REG_BASE+0x00000044)
+#define ADR_TB_RDATA (SYS_REG_BASE+0x00000048)
+#define ADR_UART_W2B (SYS_REG_BASE+0x0000004c)
+#define ADR_AHB_ILL_ADDR (SYS_REG_BASE+0x00000050)
+#define ADR_AHB_FEN_ADDR (SYS_REG_BASE+0x00000054)
+#define ADR_AHB_ILLFEN_STATUS (SYS_REG_BASE+0x00000058)
+#define ADR_PWM_A (SYS_REG_BASE+0x00000080)
+#define ADR_PWM_B (SYS_REG_BASE+0x00000084)
+#define ADR_HBUSREQ_LOCK (SYS_REG_BASE+0x00000090)
+#define ADR_HBURST_LOCK (SYS_REG_BASE+0x00000094)
+#define ADR_PRESCALER_USTIMER (SYS_REG_BASE+0x000000a0)
+#define ADR_BIST_MODE_REG_IN_MMU (SYS_REG_BASE+0x000000a4)
+#define ADR_BIST_MODE_REG_OUT_MMU (SYS_REG_BASE+0x000000a8)
+#define ADR_BIST_MONITOR_BUS_MMU (SYS_REG_BASE+0x000000ac)
+#define ADR_TEST_MODE (SYS_REG_BASE+0x000000b0)
+#define ADR_BOOT_INFO (WBOOT_REG_BASE+0x00000000)
+#define ADR_SD_INIT_CFG (WBOOT_REG_BASE+0x00000004)
+#define ADR_SPARE_UART_INFO (WBOOT_REG_BASE+0x00000008)
+#define ADR_TU0_MICROSECOND_TIMER (TU0_US_REG_BASE+0x00000000)
+#define ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE (TU0_US_REG_BASE+0x00000004)
+#define ADR_TU0_DUMMY_BIT_0 (TU0_US_REG_BASE+0x00000008)
+#define ADR_TU0_DUMMY_BIT_1 (TU0_US_REG_BASE+0x0000000c)
+#define ADR_TU1_MICROSECOND_TIMER (TU1_US_REG_BASE+0x00000000)
+#define ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE (TU1_US_REG_BASE+0x00000004)
+#define ADR_TU1_DUMMY_BIT_0 (TU1_US_REG_BASE+0x00000008)
+#define ADR_TU1_DUMMY_BIT_1 (TU1_US_REG_BASE+0x0000000c)
+#define ADR_TU2_MICROSECOND_TIMER (TU2_US_REG_BASE+0x00000000)
+#define ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE (TU2_US_REG_BASE+0x00000004)
+#define ADR_TU2_DUMMY_BIT_0 (TU2_US_REG_BASE+0x00000008)
+#define ADR_TU2_DUMMY_BIT_1 (TU2_US_REG_BASE+0x0000000c)
+#define ADR_TU3_MICROSECOND_TIMER (TU3_US_REG_BASE+0x00000000)
+#define ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE (TU3_US_REG_BASE+0x00000004)
+#define ADR_TU3_DUMMY_BIT_0 (TU3_US_REG_BASE+0x00000008)
+#define ADR_TU3_DUMMY_BIT_1 (TU3_US_REG_BASE+0x0000000c)
+#define ADR_TM0_MILISECOND_TIMER (TM0_MS_REG_BASE+0x00000000)
+#define ADR_TM0_CURRENT_MILISECOND_TIME_VALUE (TM0_MS_REG_BASE+0x00000004)
+#define ADR_TM0_DUMMY_BIT_0 (TM0_MS_REG_BASE+0x00000008)
+#define ADR_TM0_DUMMY_BIT_1 (TM0_MS_REG_BASE+0x0000000c)
+#define ADR_TM1_MILISECOND_TIMER (TM1_MS_REG_BASE+0x00000000)
+#define ADR_TM1_CURRENT_MILISECOND_TIME_VALUE (TM1_MS_REG_BASE+0x00000004)
+#define ADR_TM1_DUMMY_BIT_0 (TM1_MS_REG_BASE+0x00000008)
+#define ADR_TM1_DUMMY_BIT_1 (TM1_MS_REG_BASE+0x0000000c)
+#define ADR_TM2_MILISECOND_TIMER (TM2_MS_REG_BASE+0x00000000)
+#define ADR_TM2_CURRENT_MILISECOND_TIME_VALUE (TM2_MS_REG_BASE+0x00000004)
+#define ADR_TM2_DUMMY_BIT_0 (TM2_MS_REG_BASE+0x00000008)
+#define ADR_TM2_DUMMY_BIT_1 (TM2_MS_REG_BASE+0x0000000c)
+#define ADR_TM3_MILISECOND_TIMER (TM3_MS_REG_BASE+0x00000000)
+#define ADR_TM3_CURRENT_MILISECOND_TIME_VALUE (TM3_MS_REG_BASE+0x00000004)
+#define ADR_TM3_DUMMY_BIT_0 (TM3_MS_REG_BASE+0x00000008)
+#define ADR_TM3_DUMMY_BIT_1 (TM3_MS_REG_BASE+0x0000000c)
+#define ADR_MCU_WDOG_REG (MCU_WDT_REG_BASE+0x00000000)
+#define ADR_SYS_WDOG_REG (SYS_WDT_REG_BASE+0x00000000)
+#define ADR_PAD6 (GPIO_REG_BASE+0x00000000)
+#define ADR_PAD7 (GPIO_REG_BASE+0x00000004)
+#define ADR_PAD8 (GPIO_REG_BASE+0x00000008)
+#define ADR_PAD9 (GPIO_REG_BASE+0x0000000c)
+#define ADR_PAD11 (GPIO_REG_BASE+0x00000010)
+#define ADR_PAD15 (GPIO_REG_BASE+0x00000014)
+#define ADR_PAD16 (GPIO_REG_BASE+0x00000018)
+#define ADR_PAD17 (GPIO_REG_BASE+0x0000001c)
+#define ADR_PAD18 (GPIO_REG_BASE+0x00000020)
+#define ADR_PAD19 (GPIO_REG_BASE+0x00000024)
+#define ADR_PAD20 (GPIO_REG_BASE+0x00000028)
+#define ADR_PAD21 (GPIO_REG_BASE+0x0000002c)
+#define ADR_PAD22 (GPIO_REG_BASE+0x00000030)
+#define ADR_PAD24 (GPIO_REG_BASE+0x00000034)
+#define ADR_PAD25 (GPIO_REG_BASE+0x00000038)
+#define ADR_PAD27 (GPIO_REG_BASE+0x0000003c)
+#define ADR_PAD28 (GPIO_REG_BASE+0x00000040)
+#define ADR_PAD29 (GPIO_REG_BASE+0x00000044)
+#define ADR_PAD30 (GPIO_REG_BASE+0x00000048)
+#define ADR_PAD31 (GPIO_REG_BASE+0x0000004c)
+#define ADR_PAD32 (GPIO_REG_BASE+0x00000050)
+#define ADR_PAD33 (GPIO_REG_BASE+0x00000054)
+#define ADR_PAD34 (GPIO_REG_BASE+0x00000058)
+#define ADR_PAD42 (GPIO_REG_BASE+0x0000005c)
+#define ADR_PAD43 (GPIO_REG_BASE+0x00000060)
+#define ADR_PAD44 (GPIO_REG_BASE+0x00000064)
+#define ADR_PAD45 (GPIO_REG_BASE+0x00000068)
+#define ADR_PAD46 (GPIO_REG_BASE+0x0000006c)
+#define ADR_PAD47 (GPIO_REG_BASE+0x00000070)
+#define ADR_PAD48 (GPIO_REG_BASE+0x00000074)
+#define ADR_PAD49 (GPIO_REG_BASE+0x00000078)
+#define ADR_PAD50 (GPIO_REG_BASE+0x0000007c)
+#define ADR_PAD51 (GPIO_REG_BASE+0x00000080)
+#define ADR_PAD52 (GPIO_REG_BASE+0x00000084)
+#define ADR_PAD53 (GPIO_REG_BASE+0x00000088)
+#define ADR_PAD54 (GPIO_REG_BASE+0x0000008c)
+#define ADR_PAD56 (GPIO_REG_BASE+0x00000090)
+#define ADR_PAD57 (GPIO_REG_BASE+0x00000094)
+#define ADR_PAD58 (GPIO_REG_BASE+0x00000098)
+#define ADR_PAD59 (GPIO_REG_BASE+0x0000009c)
+#define ADR_PAD60 (GPIO_REG_BASE+0x000000a0)
+#define ADR_PAD61 (GPIO_REG_BASE+0x000000a4)
+#define ADR_PAD62 (GPIO_REG_BASE+0x000000a8)
+#define ADR_PAD64 (GPIO_REG_BASE+0x000000ac)
+#define ADR_PAD65 (GPIO_REG_BASE+0x000000b0)
+#define ADR_PAD66 (GPIO_REG_BASE+0x000000b4)
+#define ADR_PAD68 (GPIO_REG_BASE+0x000000b8)
+#define ADR_PAD67 (GPIO_REG_BASE+0x000000bc)
+#define ADR_PAD69 (GPIO_REG_BASE+0x000000c0)
+#define ADR_PAD70 (GPIO_REG_BASE+0x000000c4)
+#define ADR_PAD231 (GPIO_REG_BASE+0x000000c8)
+#define ADR_PIN_SEL_0 (GPIO_REG_BASE+0x000000cc)
+#define ADR_PIN_SEL_1 (GPIO_REG_BASE+0x000000d0)
+#define ADR_IO_PORT_REG (SD_REG_BASE+0x00000000)
+#define ADR_INT_MASK_REG (SD_REG_BASE+0x00000004)
+#define ADR_INT_STATUS_REG (SD_REG_BASE+0x00000008)
+#define ADR_FN1_STATUS_REG (SD_REG_BASE+0x0000000c)
+#define ADR_CARD_PKT_STATUS_TEST (SD_REG_BASE+0x00000010)
+#define ADR_SYSTEM_INFORMATION_REG (SD_REG_BASE+0x0000001c)
+#define ADR_CARD_RCA_REG (SD_REG_BASE+0x00000020)
+#define ADR_SDIO_FIFO_WR_THLD_REG (SD_REG_BASE+0x00000024)
+#define ADR_SDIO_FIFO_WR_LIMIT_REG (SD_REG_BASE+0x00000028)
+#define ADR_SDIO_TX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x0000002c)
+#define ADR_SDIO_THLD_FOR_CMD53RD_REG (SD_REG_BASE+0x00000030)
+#define ADR_SDIO_RX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x00000034)
+#define ADR_SDIO_LOG_START_END_DATA_REG (SD_REG_BASE+0x00000038)
+#define ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG (SD_REG_BASE+0x00000040)
+#define ADR_SDIO_LAST_CMD_INDEX_CRC_REG (SD_REG_BASE+0x00000044)
+#define ADR_SDIO_LAST_CMD_ARG_REG (SD_REG_BASE+0x00000048)
+#define ADR_SDIO_BUS_STATE_DEBUG_MONITOR (SD_REG_BASE+0x0000004c)
+#define ADR_SDIO_CARD_STATUS_REG (SD_REG_BASE+0x00000050)
+#define ADR_R5_RESP_FLAG_OUT_TIMING (SD_REG_BASE+0x00000054)
+#define ADR_CMD52_DATA_FOR_LAST_TIME (SD_REG_BASE+0x0000005c)
+#define ADR_FN1_DMA_START_ADDR_REG (SD_REG_BASE+0x00000060)
+#define ADR_FN1_INT_CTRL_RESET (SD_REG_BASE+0x00000064)
+#define ADR_IO_REG_PORT_REG (SD_REG_BASE+0x00000070)
+#define ADR_SDIO_FIFO_ERROR_CNT (SD_REG_BASE+0x0000007c)
+#define ADR_SDIO_CRC7_CRC16_ERROR_REG (SD_REG_BASE+0x00000080)
+#define ADR_SDIO_BLOCK_CNT_INFO (SD_REG_BASE+0x00000084)
+#define ADR_RX_DATA_CMD52_ABORT_COUNT (SD_REG_BASE+0x0000008c)
+#define ADR_FIFO_PTR_READ_BLOCK_CNT (SD_REG_BASE+0x00000090)
+#define ADR_TX_TIME_OUT_READ_CTRL (SD_REG_BASE+0x00000094)
+#define ADR_SDIO_TX_ALLOC_REG (SD_REG_BASE+0x00000098)
+#define ADR_SDIO_TX_INFORM (SD_REG_BASE+0x0000009c)
+#define ADR_F1_BLOCK_SIZE_0_REG (SD_REG_BASE+0x000000a0)
+#define ADR_SDIO_COMMAND_LOG_DATA_31_0 (SD_REG_BASE+0x000000b0)
+#define ADR_SDIO_COMMAND_LOG_DATA_63_32 (SD_REG_BASE+0x000000b4)
+#define ADR_SYSTEM_INFORMATION_REGISTER (SD_REG_BASE+0x000000bc)
+#define ADR_CCCR_00H_REG (SD_REG_BASE+0x000000c0)
+#define ADR_CCCR_04H_REG (SD_REG_BASE+0x000000c4)
+#define ADR_CCCR_08H_REG (SD_REG_BASE+0x000000c8)
+#define ADR_CCCR_13H_REG (SD_REG_BASE+0x000000d0)
+#define ADR_FBR_100H_REG (SD_REG_BASE+0x000000e0)
+#define ADR_FBR_109H_REG (SD_REG_BASE+0x000000e8)
+#define ADR_F0_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000100)
+#define ADR_F0_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000104)
+#define ADR_F0_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000108)
+#define ADR_F0_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000010c)
+#define ADR_F0_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000110)
+#define ADR_F0_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000114)
+#define ADR_F0_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000118)
+#define ADR_F0_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000011c)
+#define ADR_F0_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000120)
+#define ADR_F0_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000124)
+#define ADR_F0_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000128)
+#define ADR_F0_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000012c)
+#define ADR_F0_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000130)
+#define ADR_F0_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000134)
+#define ADR_F0_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000138)
+#define ADR_F0_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000013c)
+#define ADR_F1_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000140)
+#define ADR_F1_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000144)
+#define ADR_F1_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000148)
+#define ADR_F1_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000014c)
+#define ADR_F1_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000150)
+#define ADR_F1_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000154)
+#define ADR_F1_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000158)
+#define ADR_F1_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000015c)
+#define ADR_F1_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000160)
+#define ADR_F1_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000164)
+#define ADR_F1_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000168)
+#define ADR_F1_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000016c)
+#define ADR_F1_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000170)
+#define ADR_F1_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000174)
+#define ADR_F1_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000178)
+#define ADR_F1_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000017c)
+#define ADR_SPI_MODE (SPI_REG_BASE+0x00000000)
+#define ADR_RX_QUOTA (SPI_REG_BASE+0x00000004)
+#define ADR_CONDITION_NUMBER (SPI_REG_BASE+0x00000008)
+#define ADR_HOST_PATH (SPI_REG_BASE+0x0000000c)
+#define ADR_TX_SEG (SPI_REG_BASE+0x00000010)
+#define ADR_DEBUG_BURST_MODE (SPI_REG_BASE+0x00000014)
+#define ADR_SPI_TO_PHY_PARAM1 (SPI_REG_BASE+0x00000018)
+#define ADR_SPI_TO_PHY_PARAM2 (SPI_REG_BASE+0x0000001c)
+#define ADR_SPI_STS (SPI_REG_BASE+0x00000020)
+#define ADR_TX_ALLOC_SET (SPI_REG_BASE+0x00000024)
+#define ADR_TX_ALLOC (SPI_REG_BASE+0x00000028)
+#define ADR_DBG_CNT (SPI_REG_BASE+0x0000002c)
+#define ADR_DBG_CNT2 (SPI_REG_BASE+0x00000030)
+#define ADR_DBG_CNT3 (SPI_REG_BASE+0x00000034)
+#define ADR_DBG_CNT4 (SPI_REG_BASE+0x00000038)
+#define ADR_INT_TAG (SPI_REG_BASE+0x0000003c)
+#define ADR_I2CM_EN (CSR_I2C_MST_BASE+0x00000000)
+#define ADR_I2CM_DEV_A (CSR_I2C_MST_BASE+0x00000004)
+#define ADR_I2CM_LEN (CSR_I2C_MST_BASE+0x00000008)
+#define ADR_I2CM_WDAT (CSR_I2C_MST_BASE+0x0000000c)
+#define ADR_I2CM_RDAT (CSR_I2C_MST_BASE+0x00000010)
+#define ADR_I2CM_EN_2 (CSR_I2C_MST_BASE+0x00000014)
+#define ADR_UART_DATA (UART_REG_BASE+0x00000000)
+#define ADR_UART_IER (UART_REG_BASE+0x00000004)
+#define ADR_UART_FCR (UART_REG_BASE+0x00000008)
+#define ADR_UART_LCR (UART_REG_BASE+0x0000000c)
+#define ADR_UART_MCR (UART_REG_BASE+0x00000010)
+#define ADR_UART_LSR (UART_REG_BASE+0x00000014)
+#define ADR_UART_MSR (UART_REG_BASE+0x00000018)
+#define ADR_UART_SPR (UART_REG_BASE+0x0000001c)
+#define ADR_UART_RTHR (UART_REG_BASE+0x00000020)
+#define ADR_UART_ISR (UART_REG_BASE+0x00000024)
+#define ADR_DAT_UART_DATA (DAT_UART_REG_BASE+0x00000000)
+#define ADR_DAT_UART_IER (DAT_UART_REG_BASE+0x00000004)
+#define ADR_DAT_UART_FCR (DAT_UART_REG_BASE+0x00000008)
+#define ADR_DAT_UART_LCR (DAT_UART_REG_BASE+0x0000000c)
+#define ADR_DAT_UART_MCR (DAT_UART_REG_BASE+0x00000010)
+#define ADR_DAT_UART_LSR (DAT_UART_REG_BASE+0x00000014)
+#define ADR_DAT_UART_MSR (DAT_UART_REG_BASE+0x00000018)
+#define ADR_DAT_UART_SPR (DAT_UART_REG_BASE+0x0000001c)
+#define ADR_DAT_UART_RTHR (DAT_UART_REG_BASE+0x00000020)
+#define ADR_DAT_UART_ISR (DAT_UART_REG_BASE+0x00000024)
+#define ADR_INT_MASK (INT_REG_BASE+0x00000000)
+#define ADR_INT_MODE (INT_REG_BASE+0x00000004)
+#define ADR_INT_IRQ_STS (INT_REG_BASE+0x00000008)
+#define ADR_INT_FIQ_STS (INT_REG_BASE+0x0000000c)
+#define ADR_INT_IRQ_RAW (INT_REG_BASE+0x00000010)
+#define ADR_INT_FIQ_RAW (INT_REG_BASE+0x00000014)
+#define ADR_INT_PERI_MASK (INT_REG_BASE+0x00000018)
+#define ADR_INT_PERI_STS (INT_REG_BASE+0x0000001c)
+#define ADR_INT_PERI_RAW (INT_REG_BASE+0x00000020)
+#define ADR_INT_GPI_CFG (INT_REG_BASE+0x00000024)
+#define ADR_SYS_INT_FOR_HOST (INT_REG_BASE+0x00000028)
+#define ADR_SPI_IPC (INT_REG_BASE+0x00000034)
+#define ADR_SDIO_IPC (INT_REG_BASE+0x00000038)
+#define ADR_SDIO_MASK (INT_REG_BASE+0x0000003c)
+#define ADR_SDIO_IRQ_STS (INT_REG_BASE+0x00000040)
+#define ADR_SD_PERI_MASK (INT_REG_BASE+0x00000044)
+#define ADR_SD_PERI_STS (INT_REG_BASE+0x00000048)
+#define ADR_DBG_SPI_MODE (DBG_SPI_REG_BASE+0x00000000)
+#define ADR_DBG_RX_QUOTA (DBG_SPI_REG_BASE+0x00000004)
+#define ADR_DBG_CONDITION_NUMBER (DBG_SPI_REG_BASE+0x00000008)
+#define ADR_DBG_HOST_PATH (DBG_SPI_REG_BASE+0x0000000c)
+#define ADR_DBG_TX_SEG (DBG_SPI_REG_BASE+0x00000010)
+#define ADR_DBG_DEBUG_BURST_MODE (DBG_SPI_REG_BASE+0x00000014)
+#define ADR_DBG_SPI_TO_PHY_PARAM1 (DBG_SPI_REG_BASE+0x00000018)
+#define ADR_DBG_SPI_TO_PHY_PARAM2 (DBG_SPI_REG_BASE+0x0000001c)
+#define ADR_DBG_SPI_STS (DBG_SPI_REG_BASE+0x00000020)
+#define ADR_DBG_TX_ALLOC_SET (DBG_SPI_REG_BASE+0x00000024)
+#define ADR_DBG_TX_ALLOC (DBG_SPI_REG_BASE+0x00000028)
+#define ADR_DBG_DBG_CNT (DBG_SPI_REG_BASE+0x0000002c)
+#define ADR_DBG_DBG_CNT2 (DBG_SPI_REG_BASE+0x00000030)
+#define ADR_DBG_DBG_CNT3 (DBG_SPI_REG_BASE+0x00000034)
+#define ADR_DBG_DBG_CNT4 (DBG_SPI_REG_BASE+0x00000038)
+#define ADR_DBG_INT_TAG (DBG_SPI_REG_BASE+0x0000003c)
+#define ADR_BOOT_ADDR (FLASH_SPI_REG_BASE+0x00000000)
+#define ADR_VERIFY_DATA (FLASH_SPI_REG_BASE+0x00000004)
+#define ADR_FLASH_ADDR (FLASH_SPI_REG_BASE+0x00000008)
+#define ADR_SRAM_ADDR (FLASH_SPI_REG_BASE+0x0000000c)
+#define ADR_LEN (FLASH_SPI_REG_BASE+0x00000010)
+#define ADR_SPI_PARAM (FLASH_SPI_REG_BASE+0x00000014)
+#define ADR_SPI_PARAM2 (FLASH_SPI_REG_BASE+0x00000018)
+#define ADR_CHECK_SUM_RESULT (FLASH_SPI_REG_BASE+0x0000001c)
+#define ADR_CHECK_SUM_IN_FILE (FLASH_SPI_REG_BASE+0x00000020)
+#define ADR_COMMAND_LEN (FLASH_SPI_REG_BASE+0x00000024)
+#define ADR_COMMAND_ADDR (FLASH_SPI_REG_BASE+0x00000028)
+#define ADR_DMA_ADR_SRC (DMA_REG_BASE+0x00000000)
+#define ADR_DMA_ADR_DST (DMA_REG_BASE+0x00000004)
+#define ADR_DMA_CTRL (DMA_REG_BASE+0x00000008)
+#define ADR_DMA_INT (DMA_REG_BASE+0x0000000c)
+#define ADR_DMA_FILL_CONST (DMA_REG_BASE+0x00000010)
+#define ADR_PMU_0 (CSR_PMU_BASE+0x00000000)
+#define ADR_PMU_1 (CSR_PMU_BASE+0x00000004)
+#define ADR_PMU_2 (CSR_PMU_BASE+0x00000008)
+#define ADR_PMU_3 (CSR_PMU_BASE+0x0000000c)
+#define ADR_RTC_1 (CSR_RTC_BASE+0x00000000)
+#define ADR_RTC_2 (CSR_RTC_BASE+0x00000004)
+#define ADR_RTC_3W (CSR_RTC_BASE+0x00000008)
+#define ADR_RTC_3R (CSR_RTC_BASE+0x00000008)
+#define ADR_RTC_4 (CSR_RTC_BASE+0x0000000c)
+#define ADR_RTC_RAM (RTC_RAM_BASE+0x00000000)
+#define ADR_D2_DMA_ADR_SRC (D2_DMA_REG_BASE+0x00000000)
+#define ADR_D2_DMA_ADR_DST (D2_DMA_REG_BASE+0x00000004)
+#define ADR_D2_DMA_CTRL (D2_DMA_REG_BASE+0x00000008)
+#define ADR_D2_DMA_INT (D2_DMA_REG_BASE+0x0000000c)
+#define ADR_D2_DMA_FILL_CONST (D2_DMA_REG_BASE+0x00000010)
+#define ADR_CONTROL (HCI_REG_BASE+0x00000000)
+#define ADR_SDIO_WAKE_MODE (HCI_REG_BASE+0x00000004)
+#define ADR_TX_FLOW_0 (HCI_REG_BASE+0x00000008)
+#define ADR_TX_FLOW_1 (HCI_REG_BASE+0x0000000c)
+#define ADR_THREASHOLD (HCI_REG_BASE+0x00000018)
+#define ADR_TXFID_INCREASE (HCI_REG_BASE+0x00000020)
+#define ADR_GLOBAL_SEQUENCE (HCI_REG_BASE+0x00000028)
+#define ADR_HCI_TX_RX_INFO_SIZE (HCI_REG_BASE+0x00000030)
+#define ADR_HCI_TX_INFO_CLEAR (HCI_REG_BASE+0x00000034)
+#define ADR_TX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000050)
+#define ADR_TX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000054)
+#define ADR_RX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000060)
+#define ADR_RX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000064)
+#define ADR_PACKET_COUNTER_INFO_0 (HCI_REG_BASE+0x00000070)
+#define ADR_PACKET_COUNTER_INFO_1 (HCI_REG_BASE+0x00000074)
+#define ADR_PACKET_COUNTER_INFO_2 (HCI_REG_BASE+0x00000078)
+#define ADR_PACKET_COUNTER_INFO_3 (HCI_REG_BASE+0x0000007c)
+#define ADR_PACKET_COUNTER_INFO_4 (HCI_REG_BASE+0x00000080)
+#define ADR_PACKET_COUNTER_INFO_5 (HCI_REG_BASE+0x00000084)
+#define ADR_PACKET_COUNTER_INFO_6 (HCI_REG_BASE+0x00000088)
+#define ADR_PACKET_COUNTER_INFO_7 (HCI_REG_BASE+0x0000008c)
+#define ADR_SDIO_TX_RX_FAIL_COUNTER_0 (HCI_REG_BASE+0x00000090)
+#define ADR_SDIO_TX_RX_FAIL_COUNTER_1 (HCI_REG_BASE+0x00000094)
+#define ADR_HCI_STATE_DEBUG_MODE_0 (HCI_REG_BASE+0x000000a0)
+#define ADR_HCI_STATE_DEBUG_MODE_1 (HCI_REG_BASE+0x000000a4)
+#define ADR_HCI_STATE_DEBUG_MODE_2 (HCI_REG_BASE+0x000000a8)
+#define ADR_HCI_STATE_DEBUG_MODE_3 (HCI_REG_BASE+0x000000ac)
+#define ADR_HCI_STATE_DEBUG_MODE_4 (HCI_REG_BASE+0x000000b0)
+#define ADR_HCI_STATE_DEBUG_MODE_5 (HCI_REG_BASE+0x000000b4)
+#define ADR_HCI_STATE_DEBUG_MODE_6 (HCI_REG_BASE+0x000000b8)
+#define ADR_HCI_STATE_DEBUG_MODE_7 (HCI_REG_BASE+0x000000bc)
+#define ADR_HCI_STATE_DEBUG_MODE_8 (HCI_REG_BASE+0x000000c0)
+#define ADR_HCI_STATE_DEBUG_MODE_9 (HCI_REG_BASE+0x000000c4)
+#define ADR_HCI_STATE_DEBUG_MODE_10 (HCI_REG_BASE+0x000000c8)
+#define ADR_CS_START_ADDR (CO_REG_BASE+0x00000000)
+#define ADR_CS_ADD_LEN (CO_REG_BASE+0x00000004)
+#define ADR_CS_CMD (CO_REG_BASE+0x00000008)
+#define ADR_CS_INI_BUF (CO_REG_BASE+0x0000000c)
+#define ADR_CS_PSEUDO_BUF (CO_REG_BASE+0x00000010)
+#define ADR_CS_CHECK_SUM (CO_REG_BASE+0x00000014)
+#define ADR_RAND_EN (CO_REG_BASE+0x00000018)
+#define ADR_RAND_NUM (CO_REG_BASE+0x0000001c)
+#define ADR_MUL_OP1 (CO_REG_BASE+0x00000060)
+#define ADR_MUL_OP2 (CO_REG_BASE+0x00000064)
+#define ADR_MUL_ANS0 (CO_REG_BASE+0x00000068)
+#define ADR_MUL_ANS1 (CO_REG_BASE+0x0000006c)
+#define ADR_DMA_RDATA (CO_REG_BASE+0x00000070)
+#define ADR_DMA_WDATA (CO_REG_BASE+0x00000074)
+#define ADR_DMA_LEN (CO_REG_BASE+0x00000078)
+#define ADR_DMA_CLR (CO_REG_BASE+0x0000007c)
+#define ADR_NAV_DATA (CO_REG_BASE+0x00000080)
+#define ADR_CO_NAV (CO_REG_BASE+0x00000084)
+#define ADR_SHA_DST_ADDR (CO_REG_BASE+0x000000a0)
+#define ADR_SHA_SRC_ADDR (CO_REG_BASE+0x000000a4)
+#define ADR_SHA_SETTING (CO_REG_BASE+0x000000a8)
+#define ADR_EFUSE_CLK_FREQ (EFS_REG_BASE+0x00000000)
+#define ADR_EFUSE_LDO_TIME (EFS_REG_BASE+0x00000004)
+#define ADR_EFUSE_AHB_RDATA_0 (EFS_REG_BASE+0x00000008)
+#define ADR_EFUSE_WDATA_0 (EFS_REG_BASE+0x00000008)
+#define ADR_EFUSE_AHB_RDATA_1 (EFS_REG_BASE+0x0000000c)
+#define ADR_EFUSE_WDATA_1 (EFS_REG_BASE+0x0000000c)
+#define ADR_EFUSE_AHB_RDATA_2 (EFS_REG_BASE+0x00000010)
+#define ADR_EFUSE_WDATA_2 (EFS_REG_BASE+0x00000010)
+#define ADR_EFUSE_AHB_RDATA_3 (EFS_REG_BASE+0x00000014)
+#define ADR_EFUSE_WDATA_3 (EFS_REG_BASE+0x00000014)
+#define ADR_EFUSE_AHB_RDATA_4 (EFS_REG_BASE+0x00000018)
+#define ADR_EFUSE_WDATA_4 (EFS_REG_BASE+0x00000018)
+#define ADR_EFUSE_AHB_RDATA_5 (EFS_REG_BASE+0x0000001c)
+#define ADR_EFUSE_WDATA_5 (EFS_REG_BASE+0x0000001c)
+#define ADR_EFUSE_AHB_RDATA_6 (EFS_REG_BASE+0x00000020)
+#define ADR_EFUSE_WDATA_6 (EFS_REG_BASE+0x00000020)
+#define ADR_EFUSE_AHB_RDATA_7 (EFS_REG_BASE+0x00000024)
+#define ADR_EFUSE_WDATA_7 (EFS_REG_BASE+0x00000024)
+#define ADR_EFUSE_SPI_RD0_EN (EFS_REG_BASE+0x00000028)
+#define ADR_EFUSE_SPI_RD1_EN (EFS_REG_BASE+0x0000002c)
+#define ADR_EFUSE_SPI_RD2_EN (EFS_REG_BASE+0x00000030)
+#define ADR_EFUSE_SPI_RD3_EN (EFS_REG_BASE+0x00000034)
+#define ADR_EFUSE_SPI_RD4_EN (EFS_REG_BASE+0x00000038)
+#define ADR_EFUSE_SPI_RD5_EN (EFS_REG_BASE+0x0000003c)
+#define ADR_EFUSE_SPI_RD6_EN (EFS_REG_BASE+0x00000040)
+#define ADR_EFUSE_SPI_RD7_EN (EFS_REG_BASE+0x00000044)
+#define ADR_EFUSE_SPI_BUSY (EFS_REG_BASE+0x00000048)
+#define ADR_EFUSE_SPI_RDATA_0 (EFS_REG_BASE+0x0000004c)
+#define ADR_EFUSE_SPI_RDATA_1 (EFS_REG_BASE+0x00000050)
+#define ADR_EFUSE_SPI_RDATA_2 (EFS_REG_BASE+0x00000054)
+#define ADR_EFUSE_SPI_RDATA_3 (EFS_REG_BASE+0x00000058)
+#define ADR_EFUSE_SPI_RDATA_4 (EFS_REG_BASE+0x0000005c)
+#define ADR_EFUSE_SPI_RDATA_5 (EFS_REG_BASE+0x00000060)
+#define ADR_EFUSE_SPI_RDATA_6 (EFS_REG_BASE+0x00000064)
+#define ADR_EFUSE_SPI_RDATA_7 (EFS_REG_BASE+0x00000068)
+#define ADR_SMS4_CFG1 (SMS4_REG_BASE+0x00000000)
+#define ADR_SMS4_CFG2 (SMS4_REG_BASE+0x00000004)
+#define ADR_SMS4_MODE1 (SMS4_REG_BASE+0x00000008)
+#define ADR_SMS4_TRIG (SMS4_REG_BASE+0x00000010)
+#define ADR_SMS4_STATUS1 (SMS4_REG_BASE+0x00000014)
+#define ADR_SMS4_STATUS2 (SMS4_REG_BASE+0x00000018)
+#define ADR_SMS4_DATA_IN0 (SMS4_REG_BASE+0x00000020)
+#define ADR_SMS4_DATA_IN1 (SMS4_REG_BASE+0x00000024)
+#define ADR_SMS4_DATA_IN2 (SMS4_REG_BASE+0x00000028)
+#define ADR_SMS4_DATA_IN3 (SMS4_REG_BASE+0x0000002c)
+#define ADR_SMS4_DATA_OUT0 (SMS4_REG_BASE+0x00000030)
+#define ADR_SMS4_DATA_OUT1 (SMS4_REG_BASE+0x00000034)
+#define ADR_SMS4_DATA_OUT2 (SMS4_REG_BASE+0x00000038)
+#define ADR_SMS4_DATA_OUT3 (SMS4_REG_BASE+0x0000003c)
+#define ADR_SMS4_KEY_0 (SMS4_REG_BASE+0x00000040)
+#define ADR_SMS4_KEY_1 (SMS4_REG_BASE+0x00000044)
+#define ADR_SMS4_KEY_2 (SMS4_REG_BASE+0x00000048)
+#define ADR_SMS4_KEY_3 (SMS4_REG_BASE+0x0000004c)
+#define ADR_SMS4_MODE_IV0 (SMS4_REG_BASE+0x00000050)
+#define ADR_SMS4_MODE_IV1 (SMS4_REG_BASE+0x00000054)
+#define ADR_SMS4_MODE_IV2 (SMS4_REG_BASE+0x00000058)
+#define ADR_SMS4_MODE_IV3 (SMS4_REG_BASE+0x0000005c)
+#define ADR_SMS4_OFB_ENC0 (SMS4_REG_BASE+0x00000060)
+#define ADR_SMS4_OFB_ENC1 (SMS4_REG_BASE+0x00000064)
+#define ADR_SMS4_OFB_ENC2 (SMS4_REG_BASE+0x00000068)
+#define ADR_SMS4_OFB_ENC3 (SMS4_REG_BASE+0x0000006c)
+#define ADR_MRX_MCAST_TB0_0 (MRX_REG_BASE+0x00000000)
+#define ADR_MRX_MCAST_TB0_1 (MRX_REG_BASE+0x00000004)
+#define ADR_MRX_MCAST_MK0_0 (MRX_REG_BASE+0x00000008)
+#define ADR_MRX_MCAST_MK0_1 (MRX_REG_BASE+0x0000000c)
+#define ADR_MRX_MCAST_CTRL0 (MRX_REG_BASE+0x00000010)
+#define ADR_MRX_MCAST_TB1_0 (MRX_REG_BASE+0x00000014)
+#define ADR_MRX_MCAST_TB1_1 (MRX_REG_BASE+0x00000018)
+#define ADR_MRX_MCAST_MK1_0 (MRX_REG_BASE+0x0000001c)
+#define ADR_MRX_MCAST_MK1_1 (MRX_REG_BASE+0x00000020)
+#define ADR_MRX_MCAST_CTRL1 (MRX_REG_BASE+0x00000024)
+#define ADR_MRX_MCAST_TB2_0 (MRX_REG_BASE+0x00000028)
+#define ADR_MRX_MCAST_TB2_1 (MRX_REG_BASE+0x0000002c)
+#define ADR_MRX_MCAST_MK2_0 (MRX_REG_BASE+0x00000030)
+#define ADR_MRX_MCAST_MK2_1 (MRX_REG_BASE+0x00000034)
+#define ADR_MRX_MCAST_CTRL2 (MRX_REG_BASE+0x00000038)
+#define ADR_MRX_MCAST_TB3_0 (MRX_REG_BASE+0x0000003c)
+#define ADR_MRX_MCAST_TB3_1 (MRX_REG_BASE+0x00000040)
+#define ADR_MRX_MCAST_MK3_0 (MRX_REG_BASE+0x00000044)
+#define ADR_MRX_MCAST_MK3_1 (MRX_REG_BASE+0x00000048)
+#define ADR_MRX_MCAST_CTRL3 (MRX_REG_BASE+0x0000004c)
+#define ADR_MRX_PHY_INFO (MRX_REG_BASE+0x00000050)
+#define ADR_MRX_BA_DBG (MRX_REG_BASE+0x00000054)
+#define ADR_MRX_FLT_TB0 (MRX_REG_BASE+0x00000070)
+#define ADR_MRX_FLT_TB1 (MRX_REG_BASE+0x00000074)
+#define ADR_MRX_FLT_TB2 (MRX_REG_BASE+0x00000078)
+#define ADR_MRX_FLT_TB3 (MRX_REG_BASE+0x0000007c)
+#define ADR_MRX_FLT_TB4 (MRX_REG_BASE+0x00000080)
+#define ADR_MRX_FLT_TB5 (MRX_REG_BASE+0x00000084)
+#define ADR_MRX_FLT_TB6 (MRX_REG_BASE+0x00000088)
+#define ADR_MRX_FLT_TB7 (MRX_REG_BASE+0x0000008c)
+#define ADR_MRX_FLT_TB8 (MRX_REG_BASE+0x00000090)
+#define ADR_MRX_FLT_TB9 (MRX_REG_BASE+0x00000094)
+#define ADR_MRX_FLT_TB10 (MRX_REG_BASE+0x00000098)
+#define ADR_MRX_FLT_TB11 (MRX_REG_BASE+0x0000009c)
+#define ADR_MRX_FLT_TB12 (MRX_REG_BASE+0x000000a0)
+#define ADR_MRX_FLT_TB13 (MRX_REG_BASE+0x000000a4)
+#define ADR_MRX_FLT_TB14 (MRX_REG_BASE+0x000000a8)
+#define ADR_MRX_FLT_TB15 (MRX_REG_BASE+0x000000ac)
+#define ADR_MRX_FLT_EN0 (MRX_REG_BASE+0x000000b0)
+#define ADR_MRX_FLT_EN1 (MRX_REG_BASE+0x000000b4)
+#define ADR_MRX_FLT_EN2 (MRX_REG_BASE+0x000000b8)
+#define ADR_MRX_FLT_EN3 (MRX_REG_BASE+0x000000bc)
+#define ADR_MRX_FLT_EN4 (MRX_REG_BASE+0x000000c0)
+#define ADR_MRX_FLT_EN5 (MRX_REG_BASE+0x000000c4)
+#define ADR_MRX_FLT_EN6 (MRX_REG_BASE+0x000000c8)
+#define ADR_MRX_FLT_EN7 (MRX_REG_BASE+0x000000cc)
+#define ADR_MRX_FLT_EN8 (MRX_REG_BASE+0x000000d0)
+#define ADR_MRX_LEN_FLT (MRX_REG_BASE+0x000000d4)
+#define ADR_RX_FLOW_DATA (MRX_REG_BASE+0x000000e0)
+#define ADR_RX_FLOW_MNG (MRX_REG_BASE+0x000000e4)
+#define ADR_RX_FLOW_CTRL (MRX_REG_BASE+0x000000e8)
+#define ADR_RX_TIME_STAMP_CFG (MRX_REG_BASE+0x000000ec)
+#define ADR_DBG_FF_FULL (MRX_REG_BASE+0x000000f0)
+#define ADR_DBG_WFF_FULL (MRX_REG_BASE+0x000000f4)
+#define ADR_DBG_MB_FULL (MRX_REG_BASE+0x000000f8)
+#define ADR_BA_CTRL (MRX_REG_BASE+0x00000100)
+#define ADR_BA_TA_0 (MRX_REG_BASE+0x00000104)
+#define ADR_BA_TA_1 (MRX_REG_BASE+0x00000108)
+#define ADR_BA_TID (MRX_REG_BASE+0x0000010c)
+#define ADR_BA_ST_SEQ (MRX_REG_BASE+0x00000110)
+#define ADR_BA_SB0 (MRX_REG_BASE+0x00000114)
+#define ADR_BA_SB1 (MRX_REG_BASE+0x00000118)
+#define ADR_MRX_WATCH_DOG (MRX_REG_BASE+0x0000011c)
+#define ADR_ACK_GEN_EN (MRX_REG_BASE+0x00000120)
+#define ADR_ACK_GEN_PARA (MRX_REG_BASE+0x00000124)
+#define ADR_ACK_GEN_RA_0 (MRX_REG_BASE+0x00000128)
+#define ADR_ACK_GEN_RA_1 (MRX_REG_BASE+0x0000012c)
+#define ADR_MIB_LEN_FAIL (MRX_REG_BASE+0x00000130)
+#define ADR_TRAP_HW_ID (MRX_REG_BASE+0x00000134)
+#define ADR_ID_IN_USE (MRX_REG_BASE+0x00000138)
+#define ADR_MRX_ERR (MRX_REG_BASE+0x0000013c)
+#define ADR_WSID0_TID0_RX_SEQ (MRX_REG_BASE+0x00000140)
+#define ADR_WSID0_TID1_RX_SEQ (MRX_REG_BASE+0x00000144)
+#define ADR_WSID0_TID2_RX_SEQ (MRX_REG_BASE+0x00000148)
+#define ADR_WSID0_TID3_RX_SEQ (MRX_REG_BASE+0x0000014c)
+#define ADR_WSID0_TID4_RX_SEQ (MRX_REG_BASE+0x00000150)
+#define ADR_WSID0_TID5_RX_SEQ (MRX_REG_BASE+0x00000154)
+#define ADR_WSID0_TID6_RX_SEQ (MRX_REG_BASE+0x00000158)
+#define ADR_WSID0_TID7_RX_SEQ (MRX_REG_BASE+0x0000015c)
+#define ADR_WSID1_TID0_RX_SEQ (MRX_REG_BASE+0x00000170)
+#define ADR_WSID1_TID1_RX_SEQ (MRX_REG_BASE+0x00000174)
+#define ADR_WSID1_TID2_RX_SEQ (MRX_REG_BASE+0x00000178)
+#define ADR_WSID1_TID3_RX_SEQ (MRX_REG_BASE+0x0000017c)
+#define ADR_WSID1_TID4_RX_SEQ (MRX_REG_BASE+0x00000180)
+#define ADR_WSID1_TID5_RX_SEQ (MRX_REG_BASE+0x00000184)
+#define ADR_WSID1_TID6_RX_SEQ (MRX_REG_BASE+0x00000188)
+#define ADR_WSID1_TID7_RX_SEQ (MRX_REG_BASE+0x0000018c)
+#define ADR_HDR_ADDR_SEL (MRX_REG_BASE+0x00000190)
+#define ADR_FRAME_TYPE_CNTR_SET (MRX_REG_BASE+0x00000194)
+#define ADR_PHY_INFO (AMPDU_REG_BASE+0x00000000)
+#define ADR_AMPDU_SIG (AMPDU_REG_BASE+0x00000004)
+#define ADR_MIB_AMPDU (AMPDU_REG_BASE+0x00000008)
+#define ADR_LEN_FLT (AMPDU_REG_BASE+0x0000000c)
+#define ADR_MIB_DELIMITER (AMPDU_REG_BASE+0x00000010)
+#define ADR_MTX_INT_STS (MT_REG_CSR_BASE+0x00000000)
+#define ADR_MTX_INT_EN (MT_REG_CSR_BASE+0x00000004)
+#define ADR_MTX_MISC_EN (MT_REG_CSR_BASE+0x00000008)
+#define ADR_MTX_EDCCA_TOUT (MT_REG_CSR_BASE+0x00000010)
+#define ADR_MTX_BCN_INT_STS (MT_REG_CSR_BASE+0x000000a0)
+#define ADR_MTX_BCN_EN_INT (MT_REG_CSR_BASE+0x000000a4)
+#define ADR_MTX_BCN_EN_MISC (MT_REG_CSR_BASE+0x000000a8)
+#define ADR_MTX_BCN_MISC (MT_REG_CSR_BASE+0x000000ac)
+#define ADR_MTX_BCN_PRD (MT_REG_CSR_BASE+0x000000b0)
+#define ADR_MTX_BCN_TSF_L (MT_REG_CSR_BASE+0x000000b4)
+#define ADR_MTX_BCN_TSF_U (MT_REG_CSR_BASE+0x000000b8)
+#define ADR_MTX_BCN_CFG0 (MT_REG_CSR_BASE+0x000000bc)
+#define ADR_MTX_BCN_CFG1 (MT_REG_CSR_BASE+0x000000c0)
+#define ADR_MTX_STATUS (MT_REG_CSR_BASE+0x000000cc)
+#define ADR_MTX_DBG_CTRL (MT_REG_CSR_BASE+0x000000d0)
+#define ADR_MTX_DBG_DAT0 (MT_REG_CSR_BASE+0x000000d4)
+#define ADR_MTX_DBG_DAT1 (MT_REG_CSR_BASE+0x000000d8)
+#define ADR_MTX_DBG_DAT2 (MT_REG_CSR_BASE+0x000000dc)
+#define ADR_MTX_DUR_TOUT (MT_REG_CSR_BASE+0x000000e0)
+#define ADR_MTX_DUR_IFS (MT_REG_CSR_BASE+0x000000e4)
+#define ADR_MTX_DUR_SIFS_G (MT_REG_CSR_BASE+0x000000e8)
+#define ADR_MTX_DBG_DAT3 (MT_REG_CSR_BASE+0x000000ec)
+#define ADR_MTX_NAV (MT_REG_CSR_BASE+0x000000f0)
+#define ADR_MTX_MIB_WSID0 (MT_REG_CSR_BASE+0x000000f4)
+#define ADR_MTX_MIB_WSID1 (MT_REG_CSR_BASE+0x000000f8)
+#define ADR_MTX_DBG_DAT4 (MT_REG_CSR_BASE+0x000000fc)
+#define ADR_TXQ0_MTX_Q_MISC_EN (TXQ0_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ0_MTX_Q_AIFSN (TXQ0_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ0_MTX_Q_BKF_CNT (TXQ0_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ0_MTX_Q_RC_LIMIT (TXQ0_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ0_MTX_Q_ID_MAP_L (TXQ0_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ0_MTX_Q_TXOP_CH_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ0_MTX_Q_TXOP_OV_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ1_MTX_Q_MISC_EN (TXQ1_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ1_MTX_Q_AIFSN (TXQ1_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ1_MTX_Q_BKF_CNT (TXQ1_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ1_MTX_Q_RC_LIMIT (TXQ1_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ1_MTX_Q_ID_MAP_L (TXQ1_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ1_MTX_Q_TXOP_CH_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ1_MTX_Q_TXOP_OV_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ2_MTX_Q_MISC_EN (TXQ2_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ2_MTX_Q_AIFSN (TXQ2_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ2_MTX_Q_BKF_CNT (TXQ2_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ2_MTX_Q_RC_LIMIT (TXQ2_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ2_MTX_Q_ID_MAP_L (TXQ2_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ2_MTX_Q_TXOP_CH_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ2_MTX_Q_TXOP_OV_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ3_MTX_Q_MISC_EN (TXQ3_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ3_MTX_Q_AIFSN (TXQ3_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ3_MTX_Q_BKF_CNT (TXQ3_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ3_MTX_Q_RC_LIMIT (TXQ3_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ3_MTX_Q_ID_MAP_L (TXQ3_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ3_MTX_Q_TXOP_CH_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ3_MTX_Q_TXOP_OV_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ4_MTX_Q_MISC_EN (TXQ4_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ4_MTX_Q_AIFSN (TXQ4_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ4_MTX_Q_BKF_CNT (TXQ4_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ4_MTX_Q_RC_LIMIT (TXQ4_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ4_MTX_Q_ID_MAP_L (TXQ4_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ4_MTX_Q_TXOP_CH_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ4_MTX_Q_TXOP_OV_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_WSID0 (HIF_INFO_BASE+0x00000000)
+#define ADR_PEER_MAC0_0 (HIF_INFO_BASE+0x00000004)
+#define ADR_PEER_MAC0_1 (HIF_INFO_BASE+0x00000008)
+#define ADR_TX_ACK_POLICY_0_0 (HIF_INFO_BASE+0x0000000c)
+#define ADR_TX_SEQ_CTRL_0_0 (HIF_INFO_BASE+0x00000010)
+#define ADR_TX_ACK_POLICY_0_1 (HIF_INFO_BASE+0x00000014)
+#define ADR_TX_SEQ_CTRL_0_1 (HIF_INFO_BASE+0x00000018)
+#define ADR_TX_ACK_POLICY_0_2 (HIF_INFO_BASE+0x0000001c)
+#define ADR_TX_SEQ_CTRL_0_2 (HIF_INFO_BASE+0x00000020)
+#define ADR_TX_ACK_POLICY_0_3 (HIF_INFO_BASE+0x00000024)
+#define ADR_TX_SEQ_CTRL_0_3 (HIF_INFO_BASE+0x00000028)
+#define ADR_TX_ACK_POLICY_0_4 (HIF_INFO_BASE+0x0000002c)
+#define ADR_TX_SEQ_CTRL_0_4 (HIF_INFO_BASE+0x00000030)
+#define ADR_TX_ACK_POLICY_0_5 (HIF_INFO_BASE+0x00000034)
+#define ADR_TX_SEQ_CTRL_0_5 (HIF_INFO_BASE+0x00000038)
+#define ADR_TX_ACK_POLICY_0_6 (HIF_INFO_BASE+0x0000003c)
+#define ADR_TX_SEQ_CTRL_0_6 (HIF_INFO_BASE+0x00000040)
+#define ADR_TX_ACK_POLICY_0_7 (HIF_INFO_BASE+0x00000044)
+#define ADR_TX_SEQ_CTRL_0_7 (HIF_INFO_BASE+0x00000048)
+#define ADR_WSID1 (HIF_INFO_BASE+0x00000050)
+#define ADR_PEER_MAC1_0 (HIF_INFO_BASE+0x00000054)
+#define ADR_PEER_MAC1_1 (HIF_INFO_BASE+0x00000058)
+#define ADR_TX_ACK_POLICY_1_0 (HIF_INFO_BASE+0x0000005c)
+#define ADR_TX_SEQ_CTRL_1_0 (HIF_INFO_BASE+0x00000060)
+#define ADR_TX_ACK_POLICY_1_1 (HIF_INFO_BASE+0x00000064)
+#define ADR_TX_SEQ_CTRL_1_1 (HIF_INFO_BASE+0x00000068)
+#define ADR_TX_ACK_POLICY_1_2 (HIF_INFO_BASE+0x0000006c)
+#define ADR_TX_SEQ_CTRL_1_2 (HIF_INFO_BASE+0x00000070)
+#define ADR_TX_ACK_POLICY_1_3 (HIF_INFO_BASE+0x00000074)
+#define ADR_TX_SEQ_CTRL_1_3 (HIF_INFO_BASE+0x00000078)
+#define ADR_TX_ACK_POLICY_1_4 (HIF_INFO_BASE+0x0000007c)
+#define ADR_TX_SEQ_CTRL_1_4 (HIF_INFO_BASE+0x00000080)
+#define ADR_TX_ACK_POLICY_1_5 (HIF_INFO_BASE+0x00000084)
+#define ADR_TX_SEQ_CTRL_1_5 (HIF_INFO_BASE+0x00000088)
+#define ADR_TX_ACK_POLICY_1_6 (HIF_INFO_BASE+0x0000008c)
+#define ADR_TX_SEQ_CTRL_1_6 (HIF_INFO_BASE+0x00000090)
+#define ADR_TX_ACK_POLICY_1_7 (HIF_INFO_BASE+0x00000094)
+#define ADR_TX_SEQ_CTRL_1_7 (HIF_INFO_BASE+0x00000098)
+#define ADR_INFO0 (PHY_RATE_INFO_BASE+0x00000000)
+#define ADR_INFO1 (PHY_RATE_INFO_BASE+0x00000004)
+#define ADR_INFO2 (PHY_RATE_INFO_BASE+0x00000008)
+#define ADR_INFO3 (PHY_RATE_INFO_BASE+0x0000000c)
+#define ADR_INFO4 (PHY_RATE_INFO_BASE+0x00000010)
+#define ADR_INFO5 (PHY_RATE_INFO_BASE+0x00000014)
+#define ADR_INFO6 (PHY_RATE_INFO_BASE+0x00000018)
+#define ADR_INFO7 (PHY_RATE_INFO_BASE+0x0000001c)
+#define ADR_INFO8 (PHY_RATE_INFO_BASE+0x00000020)
+#define ADR_INFO9 (PHY_RATE_INFO_BASE+0x00000024)
+#define ADR_INFO10 (PHY_RATE_INFO_BASE+0x00000028)
+#define ADR_INFO11 (PHY_RATE_INFO_BASE+0x0000002c)
+#define ADR_INFO12 (PHY_RATE_INFO_BASE+0x00000030)
+#define ADR_INFO13 (PHY_RATE_INFO_BASE+0x00000034)
+#define ADR_INFO14 (PHY_RATE_INFO_BASE+0x00000038)
+#define ADR_INFO15 (PHY_RATE_INFO_BASE+0x0000003c)
+#define ADR_INFO16 (PHY_RATE_INFO_BASE+0x00000040)
+#define ADR_INFO17 (PHY_RATE_INFO_BASE+0x00000044)
+#define ADR_INFO18 (PHY_RATE_INFO_BASE+0x00000048)
+#define ADR_INFO19 (PHY_RATE_INFO_BASE+0x0000004c)
+#define ADR_INFO20 (PHY_RATE_INFO_BASE+0x00000050)
+#define ADR_INFO21 (PHY_RATE_INFO_BASE+0x00000054)
+#define ADR_INFO22 (PHY_RATE_INFO_BASE+0x00000058)
+#define ADR_INFO23 (PHY_RATE_INFO_BASE+0x0000005c)
+#define ADR_INFO24 (PHY_RATE_INFO_BASE+0x00000060)
+#define ADR_INFO25 (PHY_RATE_INFO_BASE+0x00000064)
+#define ADR_INFO26 (PHY_RATE_INFO_BASE+0x00000068)
+#define ADR_INFO27 (PHY_RATE_INFO_BASE+0x0000006c)
+#define ADR_INFO28 (PHY_RATE_INFO_BASE+0x00000070)
+#define ADR_INFO29 (PHY_RATE_INFO_BASE+0x00000074)
+#define ADR_INFO30 (PHY_RATE_INFO_BASE+0x00000078)
+#define ADR_INFO31 (PHY_RATE_INFO_BASE+0x0000007c)
+#define ADR_INFO32 (PHY_RATE_INFO_BASE+0x00000080)
+#define ADR_INFO33 (PHY_RATE_INFO_BASE+0x00000084)
+#define ADR_INFO34 (PHY_RATE_INFO_BASE+0x00000088)
+#define ADR_INFO35 (PHY_RATE_INFO_BASE+0x0000008c)
+#define ADR_INFO36 (PHY_RATE_INFO_BASE+0x00000090)
+#define ADR_INFO37 (PHY_RATE_INFO_BASE+0x00000094)
+#define ADR_INFO38 (PHY_RATE_INFO_BASE+0x00000098)
+#define ADR_INFO_MASK (PHY_RATE_INFO_BASE+0x0000009c)
+#define ADR_INFO_RATE_OFFSET (PHY_RATE_INFO_BASE+0x000000a0)
+#define ADR_INFO_IDX_ADDR (PHY_RATE_INFO_BASE+0x000000a4)
+#define ADR_INFO_LEN_ADDR (PHY_RATE_INFO_BASE+0x000000a8)
+#define ADR_IC_TIME_TAG_0 (PHY_RATE_INFO_BASE+0x000000ac)
+#define ADR_IC_TIME_TAG_1 (PHY_RATE_INFO_BASE+0x000000b0)
+#define ADR_PACKET_ID_ALLOCATION_PRIORITY (PHY_RATE_INFO_BASE+0x000000b4)
+#define ADR_MAC_MODE (MAC_GLB_SET_BASE+0x00000000)
+#define ADR_ALL_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000004)
+#define ADR_ENG_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000008)
+#define ADR_CSR_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x0000000c)
+#define ADR_MAC_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000010)
+#define ADR_MAC_ENGINE_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000014)
+#define ADR_MAC_CSR_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000018)
+#define ADR_GLBLE_SET (MAC_GLB_SET_BASE+0x0000001c)
+#define ADR_REASON_TRAP0 (MAC_GLB_SET_BASE+0x00000020)
+#define ADR_REASON_TRAP1 (MAC_GLB_SET_BASE+0x00000024)
+#define ADR_BSSID_0 (MAC_GLB_SET_BASE+0x00000028)
+#define ADR_BSSID_1 (MAC_GLB_SET_BASE+0x0000002c)
+#define ADR_SCRT_STATE (MAC_GLB_SET_BASE+0x0000002c)
+#define ADR_STA_MAC_0 (MAC_GLB_SET_BASE+0x00000030)
+#define ADR_STA_MAC_1 (MAC_GLB_SET_BASE+0x00000034)
+#define ADR_SCRT_SET (MAC_GLB_SET_BASE+0x00000038)
+#define ADR_BTCX0 (BTCX_REG_BASE+0x00000000)
+#define ADR_BTCX1 (BTCX_REG_BASE+0x00000004)
+#define ADR_SWITCH_CTL (BTCX_REG_BASE+0x00000008)
+#define ADR_MIB_EN (MIB_REG_BASE+0x00000000)
+#define ADR_MTX_WSID0_SUCC (MIB_REG_BASE+0x00000118)
+#define ADR_MTX_WSID0_FRM (MIB_REG_BASE+0x00000128)
+#define ADR_MTX_WSID0_RETRY (MIB_REG_BASE+0x00000138)
+#define ADR_MTX_WSID0_TOTAL (MIB_REG_BASE+0x00000148)
+#define ADR_MTX_GROUP (MIB_REG_BASE+0x0000016c)
+#define ADR_MTX_FAIL (MIB_REG_BASE+0x00000170)
+#define ADR_MTX_RETRY (MIB_REG_BASE+0x00000174)
+#define ADR_MTX_MULTI_RETRY (MIB_REG_BASE+0x00000178)
+#define ADR_MTX_RTS_SUCCESS (MIB_REG_BASE+0x0000017c)
+#define ADR_MTX_RTS_FAIL (MIB_REG_BASE+0x00000180)
+#define ADR_MTX_ACK_FAIL (MIB_REG_BASE+0x00000184)
+#define ADR_MTX_FRM (MIB_REG_BASE+0x00000188)
+#define ADR_MTX_ACK_TX (MIB_REG_BASE+0x0000018c)
+#define ADR_MTX_CTS_TX (MIB_REG_BASE+0x00000190)
+#define ADR_MRX_DUP_FRM (MIB_REG_BASE+0x00000194)
+#define ADR_MRX_FRG_FRM (MIB_REG_BASE+0x00000198)
+#define ADR_MRX_GROUP_FRM (MIB_REG_BASE+0x0000019c)
+#define ADR_MRX_FCS_ERR (MIB_REG_BASE+0x000001a0)
+#define ADR_MRX_FCS_SUCC (MIB_REG_BASE+0x000001a4)
+#define ADR_MRX_MISS (MIB_REG_BASE+0x000001a8)
+#define ADR_MRX_ALC_FAIL (MIB_REG_BASE+0x000001ac)
+#define ADR_MRX_DAT_NTF (MIB_REG_BASE+0x000001b0)
+#define ADR_MRX_RTS_NTF (MIB_REG_BASE+0x000001b4)
+#define ADR_MRX_CTS_NTF (MIB_REG_BASE+0x000001b8)
+#define ADR_MRX_ACK_NTF (MIB_REG_BASE+0x000001bc)
+#define ADR_MRX_BA_NTF (MIB_REG_BASE+0x000001c0)
+#define ADR_MRX_DATA_NTF (MIB_REG_BASE+0x000001c4)
+#define ADR_MRX_MNG_NTF (MIB_REG_BASE+0x000001c8)
+#define ADR_MRX_DAT_CRC_NTF (MIB_REG_BASE+0x000001cc)
+#define ADR_MRX_BAR_NTF (MIB_REG_BASE+0x000001d0)
+#define ADR_MRX_MB_MISS (MIB_REG_BASE+0x000001d4)
+#define ADR_MRX_NIDLE_MISS (MIB_REG_BASE+0x000001d8)
+#define ADR_MRX_CSR_NTF (MIB_REG_BASE+0x000001dc)
+#define ADR_DBG_Q0_FRM_SUCCESS (MIB_REG_BASE+0x00000218)
+#define ADR_DBG_Q0_FRM_FAIL (MIB_REG_BASE+0x0000021c)
+#define ADR_DBG_Q0_ACK_SUCCESS (MIB_REG_BASE+0x00000220)
+#define ADR_DBG_Q0_ACK_FAIL (MIB_REG_BASE+0x00000224)
+#define ADR_DBG_Q1_FRM_SUCCESS (MIB_REG_BASE+0x00000268)
+#define ADR_DBG_Q1_FRM_FAIL (MIB_REG_BASE+0x0000026c)
+#define ADR_DBG_Q1_ACK_SUCCESS (MIB_REG_BASE+0x00000270)
+#define ADR_DBG_Q1_ACK_FAIL (MIB_REG_BASE+0x00000274)
+#define ADR_DBG_Q2_FRM_SUCCESS (MIB_REG_BASE+0x00000318)
+#define ADR_DBG_Q2_FRM_FAIL (MIB_REG_BASE+0x0000031c)
+#define ADR_DBG_Q2_ACK_SUCCESS (MIB_REG_BASE+0x00000320)
+#define ADR_DBG_Q2_ACK_FAIL (MIB_REG_BASE+0x00000324)
+#define ADR_DBG_Q3_FRM_SUCCESS (MIB_REG_BASE+0x00000368)
+#define ADR_DBG_Q3_FRM_FAIL (MIB_REG_BASE+0x0000036c)
+#define ADR_DBG_Q3_ACK_SUCCESS (MIB_REG_BASE+0x00000370)
+#define ADR_DBG_Q3_ACK_FAIL (MIB_REG_BASE+0x00000374)
+#define ADR_MIB_SCRT_TKIP0 (MIB_REG_BASE+0x00000418)
+#define ADR_MIB_SCRT_TKIP1 (MIB_REG_BASE+0x0000041c)
+#define ADR_MIB_SCRT_TKIP2 (MIB_REG_BASE+0x00000420)
+#define ADR_MIB_SCRT_CCMP0 (MIB_REG_BASE+0x00000424)
+#define ADR_MIB_SCRT_CCMP1 (MIB_REG_BASE+0x00000428)
+#define ADR_DBG_LEN_CRC_FAIL (MIB_REG_BASE+0x00000468)
+#define ADR_DBG_LEN_ALC_FAIL (MIB_REG_BASE+0x0000046c)
+#define ADR_DBG_AMPDU_PASS (MIB_REG_BASE+0x00000470)
+#define ADR_DBG_AMPDU_FAIL (MIB_REG_BASE+0x00000474)
+#define ADR_ID_ALC_FAIL1 (MIB_REG_BASE+0x00000478)
+#define ADR_ID_ALC_FAIL2 (MIB_REG_BASE+0x0000047c)
+#define ADR_CBR_HARD_WIRE_PIN_REGISTER (CBR_A_REG_BASE+0x00110000)
+#define ADR_CBR_MANUAL_ENABLE_REGISTER (CBR_A_REG_BASE+0x00110004)
+#define ADR_CBR_LDO_REGISTER (CBR_A_REG_BASE+0x00110008)
+#define ADR_CBR_ABB_REGISTER_1 (CBR_A_REG_BASE+0x0011000c)
+#define ADR_CBR_ABB_REGISTER_2 (CBR_A_REG_BASE+0x00110010)
+#define ADR_CBR_TX_FE_REGISTER (CBR_A_REG_BASE+0x00110014)
+#define ADR_CBR_RX_FE_REGISTER_1 (CBR_A_REG_BASE+0x00110018)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1 (CBR_A_REG_BASE+0x0011001c)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2 (CBR_A_REG_BASE+0x00110020)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3 (CBR_A_REG_BASE+0x00110024)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4 (CBR_A_REG_BASE+0x00110028)
+#define ADR_CBR_RX_FSM_REGISTER (CBR_A_REG_BASE+0x0011002c)
+#define ADR_CBR_RX_ADC_REGISTER (CBR_A_REG_BASE+0x00110030)
+#define ADR_CBR_TX_DAC_REGISTER (CBR_A_REG_BASE+0x00110034)
+#define ADR_CBR_SX_ENABLE_RGISTER (CBR_A_REG_BASE+0x00110038)
+#define ADR_CBR_SYN_RGISTER_1 (CBR_A_REG_BASE+0x0011003c)
+#define ADR_CBR_SYN_RGISTER_2 (CBR_A_REG_BASE+0x00110040)
+#define ADR_CBR_SYN_PFD_CHP (CBR_A_REG_BASE+0x00110044)
+#define ADR_CBR_SYN_VCO_LOBF (CBR_A_REG_BASE+0x00110048)
+#define ADR_CBR_SYN_DIV_SDM_XOSC (CBR_A_REG_BASE+0x0011004c)
+#define ADR_CBR_SYN_LCK1 (CBR_A_REG_BASE+0x00110050)
+#define ADR_CBR_SYN_LCK2 (CBR_A_REG_BASE+0x00110054)
+#define ADR_CBR_DPLL_VCO_REGISTER (CBR_A_REG_BASE+0x00110058)
+#define ADR_CBR_DPLL_CP_PFD_REGISTER (CBR_A_REG_BASE+0x0011005c)
+#define ADR_CBR_DPLL_DIVIDER_REGISTER (CBR_A_REG_BASE+0x00110060)
+#define ADR_CBR_DCOC_IDAC_REGISTER1 (CBR_A_REG_BASE+0x00110064)
+#define ADR_CBR_DCOC_IDAC_REGISTER2 (CBR_A_REG_BASE+0x00110068)
+#define ADR_CBR_DCOC_IDAC_REGISTER3 (CBR_A_REG_BASE+0x0011006c)
+#define ADR_CBR_DCOC_IDAC_REGISTER4 (CBR_A_REG_BASE+0x00110070)
+#define ADR_CBR_DCOC_IDAC_REGISTER5 (CBR_A_REG_BASE+0x00110074)
+#define ADR_CBR_DCOC_IDAC_REGISTER6 (CBR_A_REG_BASE+0x00110078)
+#define ADR_CBR_DCOC_IDAC_REGISTER7 (CBR_A_REG_BASE+0x0011007c)
+#define ADR_CBR_DCOC_IDAC_REGISTER8 (CBR_A_REG_BASE+0x00110080)
+#define ADR_CBR_RCAL_REGISTER (CBR_A_REG_BASE+0x00110084)
+#define ADR_CBR_MANUAL_REGISTER (CBR_A_REG_BASE+0x00110088)
+#define ADR_CBR_TRX_DUMMY_REGISTER (CBR_A_REG_BASE+0x0011008c)
+#define ADR_CBR_SX_DUMMY_REGISTER (CBR_A_REG_BASE+0x00110090)
+#define ADR_CBR_READ_ONLY_FLAGS_1 (CBR_A_REG_BASE+0x00110094)
+#define ADR_CBR_READ_ONLY_FLAGS_2 (CBR_A_REG_BASE+0x00110098)
+#define ADR_CBR_RG_PKT_GEN_0 (CBR_A_REG_BASE+0x00120080)
+#define ADR_CBR_RG_PKT_GEN_1 (CBR_A_REG_BASE+0x00120084)
+#define ADR_CBR_RG_PKT_GEN_2 (CBR_A_REG_BASE+0x00120088)
+#define ADR_CBR_RG_INTEGRATION (CBR_A_REG_BASE+0x00120090)
+#define ADR_CBR_RG_PKT_GEN_TXCNT (CBR_A_REG_BASE+0x00120094)
+#define ADR_CBR_PATTERN_GEN (CBR_A_REG_BASE+0x001203f8)
+#define ADR_MB_CPU_INT (MB_REG_BASE+0x00000004)
+#define ADR_CPU_ID_TB0 (MB_REG_BASE+0x00000008)
+#define ADR_CPU_ID_TB1 (MB_REG_BASE+0x0000000c)
+#define ADR_CH0_TRIG_1 (MB_REG_BASE+0x00000010)
+#define ADR_CH0_TRIG_0 (MB_REG_BASE+0x00000010)
+#define ADR_CH0_PRI_TRIG (MB_REG_BASE+0x00000014)
+#define ADR_MCU_STATUS (MB_REG_BASE+0x00000018)
+#define ADR_RD_IN_FFCNT1 (MB_REG_BASE+0x0000001c)
+#define ADR_RD_IN_FFCNT2 (MB_REG_BASE+0x00000020)
+#define ADR_RD_FFIN_FULL (MB_REG_BASE+0x00000024)
+#define ADR_MBOX_HALT_CFG (MB_REG_BASE+0x0000002c)
+#define ADR_MB_DBG_CFG1 (MB_REG_BASE+0x00000030)
+#define ADR_MB_DBG_CFG2 (MB_REG_BASE+0x00000034)
+#define ADR_MB_DBG_CFG3 (MB_REG_BASE+0x00000038)
+#define ADR_MB_DBG_CFG4 (MB_REG_BASE+0x0000003c)
+#define ADR_MB_OUT_QUEUE_CFG (MB_REG_BASE+0x00000040)
+#define ADR_MB_OUT_QUEUE_FLUSH (MB_REG_BASE+0x00000044)
+#define ADR_RD_FFOUT_CNT1 (MB_REG_BASE+0x00000048)
+#define ADR_RD_FFOUT_CNT2 (MB_REG_BASE+0x0000004c)
+#define ADR_RD_FFOUT_CNT3 (MB_REG_BASE+0x00000050)
+#define ADR_RD_FFOUT_FULL (MB_REG_BASE+0x00000054)
+#define ADR_MB_THRESHOLD6 (MB_REG_BASE+0x0000006c)
+#define ADR_MB_THRESHOLD7 (MB_REG_BASE+0x00000070)
+#define ADR_MB_THRESHOLD8 (MB_REG_BASE+0x00000074)
+#define ADR_MB_THRESHOLD9 (MB_REG_BASE+0x00000078)
+#define ADR_MB_THRESHOLD10 (MB_REG_BASE+0x0000007c)
+#define ADR_MB_TRASH_CFG (MB_REG_BASE+0x00000080)
+#define ADR_MB_IN_FF_FLUSH (MB_REG_BASE+0x00000084)
+#define ADR_CPU_ID_TB2 (MB_REG_BASE+0x00000088)
+#define ADR_CPU_ID_TB3 (MB_REG_BASE+0x0000008c)
+#define ADR_PHY_IQ_LOG_CFG0 (MB_REG_BASE+0x00000090)
+#define ADR_PHY_IQ_LOG_CFG1 (MB_REG_BASE+0x00000094)
+#define ADR_PHY_IQ_LOG_LEN (MB_REG_BASE+0x00000098)
+#define ADR_PHY_IQ_LOG_PTR (MB_REG_BASE+0x0000009c)
+#define ADR_WR_ALC (ID_MNG_REG_BASE+0x00000000)
+#define ADR_GETID (ID_MNG_REG_BASE+0x00000000)
+#define ADR_CH_STA_PRI (ID_MNG_REG_BASE+0x00000004)
+#define ADR_RD_ID0 (ID_MNG_REG_BASE+0x00000008)
+#define ADR_RD_ID1 (ID_MNG_REG_BASE+0x0000000c)
+#define ADR_IMD_CFG (ID_MNG_REG_BASE+0x00000010)
+#define ADR_IMD_STA (ID_MNG_REG_BASE+0x00000014)
+#define ADR_ALC_STA (ID_MNG_REG_BASE+0x00000018)
+#define ADR_TRX_ID_COUNT (ID_MNG_REG_BASE+0x0000001c)
+#define ADR_TRX_ID_THRESHOLD (ID_MNG_REG_BASE+0x00000020)
+#define ADR_TX_ID0 (ID_MNG_REG_BASE+0x00000024)
+#define ADR_TX_ID1 (ID_MNG_REG_BASE+0x00000028)
+#define ADR_RX_ID0 (ID_MNG_REG_BASE+0x0000002c)
+#define ADR_RX_ID1 (ID_MNG_REG_BASE+0x00000030)
+#define ADR_RTN_STA (ID_MNG_REG_BASE+0x00000034)
+#define ADR_ID_LEN_THREADSHOLD1 (ID_MNG_REG_BASE+0x00000038)
+#define ADR_ID_LEN_THREADSHOLD2 (ID_MNG_REG_BASE+0x0000003c)
+#define ADR_CH_ARB_PRI (ID_MNG_REG_BASE+0x00000040)
+#define ADR_TX_ID_REMAIN_STATUS (ID_MNG_REG_BASE+0x00000044)
+#define ADR_ID_INFO_STA (ID_MNG_REG_BASE+0x00000048)
+#define ADR_TX_LIMIT_INTR (ID_MNG_REG_BASE+0x0000004c)
+#define ADR_TX_ID_ALL_INFO (ID_MNG_REG_BASE+0x00000050)
+#define ADR_RD_ID2 (ID_MNG_REG_BASE+0x00000054)
+#define ADR_RD_ID3 (ID_MNG_REG_BASE+0x00000058)
+#define ADR_TX_ID2 (ID_MNG_REG_BASE+0x0000005c)
+#define ADR_TX_ID3 (ID_MNG_REG_BASE+0x00000060)
+#define ADR_RX_ID2 (ID_MNG_REG_BASE+0x00000064)
+#define ADR_RX_ID3 (ID_MNG_REG_BASE+0x00000068)
+#define ADR_TX_ID_ALL_INFO2 (ID_MNG_REG_BASE+0x0000006c)
+#define ADR_TX_ID_ALL_INFO_A (ID_MNG_REG_BASE+0x00000070)
+#define ADR_TX_ID_ALL_INFO_B (ID_MNG_REG_BASE+0x00000074)
+#define ADR_TX_ID_REMAIN_STATUS2 (ID_MNG_REG_BASE+0x00000078)
+#define ADR_ALC_ID_INFO (ID_MNG_REG_BASE+0x0000007c)
+#define ADR_ALC_ID_INF1 (ID_MNG_REG_BASE+0x00000080)
+#define ADR_PHY_EN_0 (CSR_PHY_BASE+0x00000000)
+#define ADR_PHY_EN_1 (CSR_PHY_BASE+0x00000004)
+#define ADR_SVN_VERSION_REG (CSR_PHY_BASE+0x00000008)
+#define ADR_PHY_PKT_GEN_0 (CSR_PHY_BASE+0x0000000c)
+#define ADR_PHY_PKT_GEN_1 (CSR_PHY_BASE+0x00000010)
+#define ADR_PHY_PKT_GEN_2 (CSR_PHY_BASE+0x00000014)
+#define ADR_PHY_PKT_GEN_3 (CSR_PHY_BASE+0x00000018)
+#define ADR_PHY_PKT_GEN_4 (CSR_PHY_BASE+0x0000001c)
+#define ADR_PHY_REG_00 (CSR_PHY_BASE+0x00000020)
+#define ADR_PHY_REG_01 (CSR_PHY_BASE+0x0000002c)
+#define ADR_PHY_REG_02_AGC (CSR_PHY_BASE+0x00000030)
+#define ADR_PHY_REG_03_AGC (CSR_PHY_BASE+0x00000034)
+#define ADR_PHY_REG_04_AGC (CSR_PHY_BASE+0x00000038)
+#define ADR_PHY_REG_05_AGC (CSR_PHY_BASE+0x0000003c)
+#define ADR_PHY_REG_06_11B_DAGC (CSR_PHY_BASE+0x00000040)
+#define ADR_PHY_REG_07_11B_DAGC (CSR_PHY_BASE+0x00000044)
+#define ADR_PHY_REG_08_11GN_DAGC (CSR_PHY_BASE+0x00000048)
+#define ADR_PHY_REG_09_11GN_DAGC (CSR_PHY_BASE+0x0000004c)
+#define ADR_PHY_READ_REG_00_DIG_PWR (CSR_PHY_BASE+0x00000050)
+#define ADR_PHY_READ_REG_01_RF_GAIN_PWR (CSR_PHY_BASE+0x00000054)
+#define ADR_PHY_READ_REG_02_RF_GAIN_PWR (CSR_PHY_BASE+0x00000058)
+#define ADR_PHY_READ_REG_03_RF_GAIN_PWR (CSR_PHY_BASE+0x0000005c)
+#define ADR_PHY_REG_10_TX_DES (CSR_PHY_BASE+0x00000060)
+#define ADR_PHY_REG_11_TX_DES (CSR_PHY_BASE+0x00000064)
+#define ADR_PHY_REG_12_TX_DES (CSR_PHY_BASE+0x00000068)
+#define ADR_PHY_REG_13_RX_DES (CSR_PHY_BASE+0x0000006c)
+#define ADR_PHY_REG_14_RX_DES (CSR_PHY_BASE+0x00000070)
+#define ADR_PHY_REG_15_RX_DES (CSR_PHY_BASE+0x00000074)
+#define ADR_PHY_REG_16_TX_DES_EXCP (CSR_PHY_BASE+0x00000078)
+#define ADR_PHY_REG_17_TX_DES_EXCP (CSR_PHY_BASE+0x0000007c)
+#define ADR_PHY_REG_18_RSSI_SNR (CSR_PHY_BASE+0x00000080)
+#define ADR_PHY_REG_19_DAC_MANUAL (CSR_PHY_BASE+0x00000084)
+#define ADR_PHY_REG_20_MRX_CNT (CSR_PHY_BASE+0x00000088)
+#define ADR_PHY_REG_21_TRX_RAMP (CSR_PHY_BASE+0x00000094)
+#define ADR_PHY_REG_22_TRX_RAMP (CSR_PHY_BASE+0x00000098)
+#define ADR_PHY_REG_23_ANT (CSR_PHY_BASE+0x0000009c)
+#define ADR_PHY_REG_24_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a0)
+#define ADR_PHY_REG_25_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a4)
+#define ADR_PHY_REG_26_MRX_LEN_CNT (CSR_PHY_BASE+0x000000a8)
+#define ADR_PHY_REG_27_MRX_LEN_CNT (CSR_PHY_BASE+0x000000ac)
+#define ADR_PHY_READ_REG_04 (CSR_PHY_BASE+0x000000b0)
+#define ADR_PHY_READ_REG_05 (CSR_PHY_BASE+0x000000b4)
+#define ADR_PHY_REG_28_BIST (CSR_PHY_BASE+0x000000b8)
+#define ADR_PHY_READ_REG_06_BIST (CSR_PHY_BASE+0x000000d8)
+#define ADR_PHY_READ_REG_07_BIST (CSR_PHY_BASE+0x000000f0)
+#define ADR_PHY_REG_29_MTRX_MAC (CSR_PHY_BASE+0x000000fc)
+#define ADR_PHY_READ_REG_08_MTRX_MAC (CSR_PHY_BASE+0x00000100)
+#define ADR_PHY_READ_REG_09_MTRX_MAC (CSR_PHY_BASE+0x00000104)
+#define ADR_PHY_REG_30_TX_UP_FIL (CSR_PHY_BASE+0x00000108)
+#define ADR_PHY_REG_31_TX_UP_FIL (CSR_PHY_BASE+0x0000010c)
+#define ADR_PHY_REG_32_TX_UP_FIL (CSR_PHY_BASE+0x00000110)
+#define ADR_PHY_READ_TBUS (CSR_PHY_BASE+0x000003fc)
+#define ADR_TX_11B_FIL_COEF_00 (CSR_PHY_BASE+0x00001000)
+#define ADR_TX_11B_FIL_COEF_01 (CSR_PHY_BASE+0x00001004)
+#define ADR_TX_11B_FIL_COEF_02 (CSR_PHY_BASE+0x00001008)
+#define ADR_TX_11B_FIL_COEF_03 (CSR_PHY_BASE+0x0000100c)
+#define ADR_TX_11B_FIL_COEF_04 (CSR_PHY_BASE+0x00001010)
+#define ADR_TX_11B_FIL_COEF_05 (CSR_PHY_BASE+0x00001014)
+#define ADR_TX_11B_FIL_COEF_06 (CSR_PHY_BASE+0x00001018)
+#define ADR_TX_11B_FIL_COEF_07 (CSR_PHY_BASE+0x0000101c)
+#define ADR_TX_11B_FIL_COEF_08 (CSR_PHY_BASE+0x00001020)
+#define ADR_TX_11B_FIL_COEF_09 (CSR_PHY_BASE+0x00001024)
+#define ADR_TX_11B_FIL_COEF_10 (CSR_PHY_BASE+0x00001028)
+#define ADR_TX_11B_FIL_COEF_11 (CSR_PHY_BASE+0x0000102c)
+#define ADR_TX_11B_FIL_COEF_12 (CSR_PHY_BASE+0x00001030)
+#define ADR_TX_11B_FIL_COEF_13 (CSR_PHY_BASE+0x00001034)
+#define ADR_TX_11B_FIL_COEF_14 (CSR_PHY_BASE+0x00001038)
+#define ADR_TX_11B_FIL_COEF_15 (CSR_PHY_BASE+0x0000103c)
+#define ADR_TX_11B_FIL_COEF_16 (CSR_PHY_BASE+0x00001040)
+#define ADR_TX_11B_FIL_COEF_17 (CSR_PHY_BASE+0x00001044)
+#define ADR_TX_11B_FIL_COEF_18 (CSR_PHY_BASE+0x00001048)
+#define ADR_TX_11B_FIL_COEF_19 (CSR_PHY_BASE+0x0000104c)
+#define ADR_TX_11B_FIL_COEF_20 (CSR_PHY_BASE+0x00001050)
+#define ADR_TX_11B_FIL_COEF_21 (CSR_PHY_BASE+0x00001054)
+#define ADR_TX_11B_FIL_COEF_22 (CSR_PHY_BASE+0x00001058)
+#define ADR_TX_11B_FIL_COEF_23 (CSR_PHY_BASE+0x0000105c)
+#define ADR_TX_11B_FIL_COEF_24 (CSR_PHY_BASE+0x00001060)
+#define ADR_TX_11B_FIL_COEF_25 (CSR_PHY_BASE+0x00001064)
+#define ADR_TX_11B_FIL_COEF_26 (CSR_PHY_BASE+0x00001068)
+#define ADR_TX_11B_FIL_COEF_27 (CSR_PHY_BASE+0x0000106c)
+#define ADR_TX_11B_FIL_COEF_28 (CSR_PHY_BASE+0x00001070)
+#define ADR_TX_11B_FIL_COEF_29 (CSR_PHY_BASE+0x00001074)
+#define ADR_TX_11B_FIL_COEF_30 (CSR_PHY_BASE+0x00001078)
+#define ADR_TX_11B_FIL_COEF_31 (CSR_PHY_BASE+0x0000107c)
+#define ADR_TX_11B_FIL_COEF_32 (CSR_PHY_BASE+0x00001080)
+#define ADR_TX_11B_FIL_COEF_33 (CSR_PHY_BASE+0x00001084)
+#define ADR_TX_11B_FIL_COEF_34 (CSR_PHY_BASE+0x00001088)
+#define ADR_TX_11B_FIL_COEF_35 (CSR_PHY_BASE+0x0000108c)
+#define ADR_TX_11B_FIL_COEF_36 (CSR_PHY_BASE+0x00001090)
+#define ADR_TX_11B_FIL_COEF_37 (CSR_PHY_BASE+0x00001094)
+#define ADR_TX_11B_FIL_COEF_38 (CSR_PHY_BASE+0x00001098)
+#define ADR_TX_11B_FIL_COEF_39 (CSR_PHY_BASE+0x0000109c)
+#define ADR_TX_11B_FIL_COEF_40 (CSR_PHY_BASE+0x000010a0)
+#define ADR_TX_11B_PLCP (CSR_PHY_BASE+0x000010a4)
+#define ADR_TX_11B_RAMP (CSR_PHY_BASE+0x000010b4)
+#define ADR_TX_11B_EN_CNT_RST_N (CSR_PHY_BASE+0x000010d4)
+#define ADR_TX_11B_EN_CNT (CSR_PHY_BASE+0x000010d8)
+#define ADR_TX_11B_PKT_GEN_CNT (CSR_PHY_BASE+0x00001c00)
+#define ADR_RX_11B_DES_DLY (CSR_PHY_BASE+0x00002000)
+#define ADR_RX_11B_CCA_0 (CSR_PHY_BASE+0x00002004)
+#define ADR_RX_11B_CCA_1 (CSR_PHY_BASE+0x00002008)
+#define ADR_RX_11B_TR_KP_KI_0 (CSR_PHY_BASE+0x0000200c)
+#define ADR_RX_11B_TR_KP_KI_1 (CSR_PHY_BASE+0x00002010)
+#define ADR_RX_11B_CE_CNT_THRESHOLD (CSR_PHY_BASE+0x00002014)
+#define ADR_RX_11B_CE_MU_0 (CSR_PHY_BASE+0x00002018)
+#define ADR_RX_11B_CE_MU_1 (CSR_PHY_BASE+0x0000201c)
+#define ADR_RX_11B_EQ_MU_0 (CSR_PHY_BASE+0x00002020)
+#define ADR_RX_11B_EQ_MU_1 (CSR_PHY_BASE+0x00002024)
+#define ADR_RX_11B_EQ_CR_KP_KI (CSR_PHY_BASE+0x00002028)
+#define ADR_RX_11B_LPF_RATE (CSR_PHY_BASE+0x0000202c)
+#define ADR_RX_11B_CIT_CNT_THRESHOLD (CSR_PHY_BASE+0x00002030)
+#define ADR_RX_11B_EQ_CH_MAIN_TAP (CSR_PHY_BASE+0x00002034)
+#define ADR_RX_11B_SEARCH_CNT_TH (CSR_PHY_BASE+0x0000209c)
+#define ADR_RX_11B_CCA_CONTROL (CSR_PHY_BASE+0x000020a0)
+#define ADR_RX_11B_FREQUENCY_OFFSET (CSR_PHY_BASE+0x000023d4)
+#define ADR_RX_11B_SNR_RSSI (CSR_PHY_BASE+0x000023d8)
+#define ADR_RX_11B_SFD_CRC_CNT (CSR_PHY_BASE+0x000023e4)
+#define ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT (CSR_PHY_BASE+0x000023e8)
+#define ADR_RX_11B_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000023ec)
+#define ADR_RX_11B_SFD_FILED_0 (CSR_PHY_BASE+0x000023f0)
+#define ADR_RX_11B_SFD_FIELD_1 (CSR_PHY_BASE+0x000023f4)
+#define ADR_RX_11B_PKT_STAT_EN (CSR_PHY_BASE+0x000023f8)
+#define ADR_RX_11B_SOFT_RST (CSR_PHY_BASE+0x000023fc)
+#define ADR_TX_11GN_RAMP (CSR_PHY_BASE+0x000030a4)
+#define ADR_TX_11GN_PLCP (CSR_PHY_BASE+0x000030b8)
+#define ADR_TX_11GN_PKT_GEN_CNT (CSR_PHY_BASE+0x00003c00)
+#define ADR_TX_11GN_PLCP_CRC_ERR_CNT (CSR_PHY_BASE+0x00003c08)
+#define ADR_RX_11GN_DES_DLY (CSR_PHY_BASE+0x00004000)
+#define ADR_RX_11GN_TR_0 (CSR_PHY_BASE+0x00004004)
+#define ADR_RX_11GN_TR_1 (CSR_PHY_BASE+0x00004008)
+#define ADR_RX_11GN_TR_2 (CSR_PHY_BASE+0x0000400c)
+#define ADR_RX_11GN_CCA_0 (CSR_PHY_BASE+0x00004010)
+#define ADR_RX_11GN_CCA_1 (CSR_PHY_BASE+0x00004014)
+#define ADR_RX_11GN_CCA_2 (CSR_PHY_BASE+0x00004018)
+#define ADR_RX_11GN_CCA_FFT_SCALE (CSR_PHY_BASE+0x0000401c)
+#define ADR_RX_11GN_SOFT_DEMAP_0 (CSR_PHY_BASE+0x00004020)
+#define ADR_RX_11GN_SOFT_DEMAP_1 (CSR_PHY_BASE+0x00004024)
+#define ADR_RX_11GN_SOFT_DEMAP_2 (CSR_PHY_BASE+0x00004028)
+#define ADR_RX_11GN_SOFT_DEMAP_3 (CSR_PHY_BASE+0x0000402c)
+#define ADR_RX_11GN_SOFT_DEMAP_4 (CSR_PHY_BASE+0x00004030)
+#define ADR_RX_11GN_SOFT_DEMAP_5 (CSR_PHY_BASE+0x00004034)
+#define ADR_RX_11GN_SYM_BOUND_0 (CSR_PHY_BASE+0x00004038)
+#define ADR_RX_11GN_SYM_BOUND_1 (CSR_PHY_BASE+0x0000409c)
+#define ADR_RX_11GN_CCA_PWR (CSR_PHY_BASE+0x000040c0)
+#define ADR_RX_11GN_CCA_CNT (CSR_PHY_BASE+0x000040c4)
+#define ADR_RX_11GN_CCA_ATCOR_RE_CHECK (CSR_PHY_BASE+0x000040c8)
+#define ADR_RX_11GN_VTB_TB (CSR_PHY_BASE+0x00004130)
+#define ADR_RX_11GN_ERR_UPDATE (CSR_PHY_BASE+0x00004164)
+#define ADR_RX_11GN_SHORT_GI (CSR_PHY_BASE+0x00004180)
+#define ADR_RX_11GN_CHANNEL_UPDATE (CSR_PHY_BASE+0x00004188)
+#define ADR_RX_11GN_PKT_FORMAT_0 (CSR_PHY_BASE+0x00004190)
+#define ADR_RX_11GN_PKT_FORMAT_1 (CSR_PHY_BASE+0x00004194)
+#define ADR_RX_11GN_TX_TIME (CSR_PHY_BASE+0x00004380)
+#define ADR_RX_11GN_STBC_TR_KP_KI (CSR_PHY_BASE+0x00004384)
+#define ADR_RX_11GN_BIST_0 (CSR_PHY_BASE+0x00004388)
+#define ADR_RX_11GN_BIST_1 (CSR_PHY_BASE+0x0000438c)
+#define ADR_RX_11GN_BIST_2 (CSR_PHY_BASE+0x000043c0)
+#define ADR_RX_11GN_BIST_3 (CSR_PHY_BASE+0x000043c4)
+#define ADR_RX_11GN_BIST_4 (CSR_PHY_BASE+0x000043c8)
+#define ADR_RX_11GN_BIST_5 (CSR_PHY_BASE+0x000043cc)
+#define ADR_RX_11GN_SPECTRUM_ANALYZER (CSR_PHY_BASE+0x000043d4)
+#define ADR_RX_11GN_READ_0 (CSR_PHY_BASE+0x000043d8)
+#define ADR_RX_11GN_FREQ_OFFSET (CSR_PHY_BASE+0x000043dc)
+#define ADR_RX_11GN_SIGNAL_FIELD_0 (CSR_PHY_BASE+0x000043e0)
+#define ADR_RX_11GN_SIGNAL_FIELD_1 (CSR_PHY_BASE+0x000043e4)
+#define ADR_RX_11GN_PKT_ERR_CNT (CSR_PHY_BASE+0x000043e8)
+#define ADR_RX_11GN_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000043ec)
+#define ADR_RX_11GN_SERVICE_LENGTH_FIELD (CSR_PHY_BASE+0x000043f0)
+#define ADR_RX_11GN_RATE (CSR_PHY_BASE+0x000043f4)
+#define ADR_RX_11GN_STAT_EN (CSR_PHY_BASE+0x000043f8)
+#define ADR_RX_11GN_SOFT_RST (CSR_PHY_BASE+0x000043fc)
+#define ADR_RF_CONTROL_0 (CSR_PHY_BASE+0x00007000)
+#define ADR_RF_CONTROL_1 (CSR_PHY_BASE+0x00007004)
+#define ADR_TX_IQ_CONTROL_0 (CSR_PHY_BASE+0x00007040)
+#define ADR_TX_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007044)
+#define ADR_TX_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007048)
+#define ADR_TX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x0000704c)
+#define ADR_RX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x00007050)
+#define ADR_RX_OBSERVATION_CIRCUIT_0 (CSR_PHY_BASE+0x00007058)
+#define ADR_RX_OBSERVATION_CIRCUIT_1 (CSR_PHY_BASE+0x0000705c)
+#define ADR_RX_OBSERVATION_CIRCUIT_2 (CSR_PHY_BASE+0x00007060)
+#define ADR_RX_OBSERVATION_CIRCUIT_3 (CSR_PHY_BASE+0x00007064)
+#define ADR_RF_IQ_CONTROL_0 (CSR_PHY_BASE+0x0000706c)
+#define ADR_RF_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007070)
+#define ADR_RF_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007074)
+#define ADR_RF_IQ_CONTROL_3 (CSR_PHY_BASE+0x00007078)
+#define ADR_DPD_CONTROL (CSR_PHY_BASE+0x0000711c)
+#define ADR_DPD_GAIN_TABLE_0 (CSR_PHY_BASE+0x00007120)
+#define ADR_DPD_GAIN_TABLE_1 (CSR_PHY_BASE+0x00007124)
+#define ADR_DPD_GAIN_TABLE_2 (CSR_PHY_BASE+0x00007128)
+#define ADR_DPD_GAIN_TABLE_3 (CSR_PHY_BASE+0x00007130)
+#define ADR_DPD_GAIN_TABLE_4 (CSR_PHY_BASE+0x00007134)
+#define ADR_DPD_GAIN_TABLE_5 (CSR_PHY_BASE+0x00007138)
+#define ADR_DPD_GAIN_TABLE_6 (CSR_PHY_BASE+0x0000713c)
+#define ADR_DPD_GAIN_TABLE_7 (CSR_PHY_BASE+0x00007140)
+#define ADR_DPD_GAIN_TABLE_8 (CSR_PHY_BASE+0x00007144)
+#define ADR_DPD_GAIN_TABLE_9 (CSR_PHY_BASE+0x00007148)
+#define ADR_DPD_GAIN_TABLE_A (CSR_PHY_BASE+0x0000714c)
+#define ADR_DPD_GAIN_TABLE_B (CSR_PHY_BASE+0x00007150)
+#define ADR_DPD_GAIN_TABLE_C (CSR_PHY_BASE+0x00007154)
+#define ADR_DPD_PH_TABLE_0 (CSR_PHY_BASE+0x00007170)
+#define ADR_DPD_PH_TABLE_1 (CSR_PHY_BASE+0x00007174)
+#define ADR_DPD_PH_TABLE_2 (CSR_PHY_BASE+0x00007178)
+#define ADR_DPD_PH_TABLE_3 (CSR_PHY_BASE+0x00007180)
+#define ADR_DPD_PH_TABLE_4 (CSR_PHY_BASE+0x00007184)
+#define ADR_DPD_PH_TABLE_5 (CSR_PHY_BASE+0x00007188)
+#define ADR_DPD_PH_TABLE_6 (CSR_PHY_BASE+0x0000718c)
+#define ADR_DPD_PH_TABLE_7 (CSR_PHY_BASE+0x00007190)
+#define ADR_DPD_PH_TABLE_8 (CSR_PHY_BASE+0x00007194)
+#define ADR_DPD_PH_TABLE_9 (CSR_PHY_BASE+0x00007198)
+#define ADR_DPD_PH_TABLE_A (CSR_PHY_BASE+0x0000719c)
+#define ADR_DPD_PH_TABLE_B (CSR_PHY_BASE+0x000071a0)
+#define ADR_DPD_PH_TABLE_C (CSR_PHY_BASE+0x000071a4)
+#define ADR_DPD_GAIN_ESTIMATION_0 (CSR_PHY_BASE+0x000071b0)
+#define ADR_DPD_GAIN_ESTIMATION_1 (CSR_PHY_BASE+0x000071b4)
+#define ADR_DPD_GAIN_ESTIMATION_2 (CSR_PHY_BASE+0x000071b8)
+#define ADR_TX_GAIN_FACTOR (CSR_PHY_BASE+0x000071bc)
+#define ADR_HARD_WIRE_PIN_REGISTER (CSR_RF_BASE+0x00000000)
+#define ADR_MANUAL_ENABLE_REGISTER (CSR_RF_BASE+0x00000004)
+#define ADR_LDO_REGISTER (CSR_RF_BASE+0x00000008)
+#define ADR_ABB_REGISTER_1 (CSR_RF_BASE+0x0000000c)
+#define ADR_ABB_REGISTER_2 (CSR_RF_BASE+0x00000010)
+#define ADR_TX_FE_REGISTER (CSR_RF_BASE+0x00000014)
+#define ADR_RX_FE_REGISTER_1 (CSR_RF_BASE+0x00000018)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_1 (CSR_RF_BASE+0x0000001c)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_2 (CSR_RF_BASE+0x00000020)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_3 (CSR_RF_BASE+0x00000024)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_4 (CSR_RF_BASE+0x00000028)
+#define ADR_RX_TX_FSM_REGISTER (CSR_RF_BASE+0x0000002c)
+#define ADR_RX_ADC_REGISTER (CSR_RF_BASE+0x00000030)
+#define ADR_TX_DAC_REGISTER (CSR_RF_BASE+0x00000034)
+#define ADR_SX_ENABLE_REGISTER (CSR_RF_BASE+0x00000038)
+#define ADR_SYN_REGISTER_1 (CSR_RF_BASE+0x0000003c)
+#define ADR_SYN_REGISTER_2 (CSR_RF_BASE+0x00000040)
+#define ADR_SYN_PFD_CHP (CSR_RF_BASE+0x00000044)
+#define ADR_SYN_VCO_LOBF (CSR_RF_BASE+0x00000048)
+#define ADR_SYN_DIV_SDM_XOSC (CSR_RF_BASE+0x0000004c)
+#define ADR_SYN_KVCO_XO_FINE_TUNE_CBANK (CSR_RF_BASE+0x00000050)
+#define ADR_SYN_LCK_VT (CSR_RF_BASE+0x00000054)
+#define ADR_DPLL_VCO_REGISTER (CSR_RF_BASE+0x00000058)
+#define ADR_DPLL_CP_PFD_REGISTER (CSR_RF_BASE+0x0000005c)
+#define ADR_DPLL_DIVIDER_REGISTER (CSR_RF_BASE+0x00000060)
+#define ADR_DCOC_IDAC_REGISTER1 (CSR_RF_BASE+0x00000064)
+#define ADR_DCOC_IDAC_REGISTER2 (CSR_RF_BASE+0x00000068)
+#define ADR_DCOC_IDAC_REGISTER3 (CSR_RF_BASE+0x0000006c)
+#define ADR_DCOC_IDAC_REGISTER4 (CSR_RF_BASE+0x00000070)
+#define ADR_DCOC_IDAC_REGISTER5 (CSR_RF_BASE+0x00000074)
+#define ADR_DCOC_IDAC_REGISTER6 (CSR_RF_BASE+0x00000078)
+#define ADR_DCOC_IDAC_REGISTER7 (CSR_RF_BASE+0x0000007c)
+#define ADR_DCOC_IDAC_REGISTER8 (CSR_RF_BASE+0x00000080)
+#define ADR_RCAL_REGISTER (CSR_RF_BASE+0x00000084)
+#define ADR_SX_LCK_BIN_REGISTERS_I (CSR_RF_BASE+0x00000088)
+#define ADR_TRX_DUMMY_REGISTER (CSR_RF_BASE+0x0000008c)
+#define ADR_SX_DUMMY_REGISTER (CSR_RF_BASE+0x00000090)
+#define ADR_READ_ONLY_FLAGS_1 (CSR_RF_BASE+0x00000094)
+#define ADR_READ_ONLY_FLAGS_2 (CSR_RF_BASE+0x00000098)
+#define ADR_DPLL_FB_DIVIDER_REGISTERS_I (CSR_RF_BASE+0x0000009c)
+#define ADR_DPLL_FB_DIVIDER_REGISTERS_II (CSR_RF_BASE+0x000000a0)
+#define ADR_SX_LCK_BIN_REGISTERS_II (CSR_RF_BASE+0x000000a4)
+#define ADR_RC_OSC_32K_CAL_REGISTERS (CSR_RF_BASE+0x000000a8)
+#define ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER (CSR_RF_BASE+0x000000ac)
+#define ADR_MMU_CTRL (MMU_REG_BASE+0x00000000)
+#define ADR_HS_CTRL (MMU_REG_BASE+0x00000004)
+#define ADR_CPU_POR0_7 (MMU_REG_BASE+0x00000008)
+#define ADR_CPU_POR8_F (MMU_REG_BASE+0x0000000c)
+#define ADR_REG_LEN_CTRL (MMU_REG_BASE+0x00000010)
+#define ADR_DMN_READ_BYPASS (MMU_REG_BASE+0x00000014)
+#define ADR_ALC_RLS_ABORT (MMU_REG_BASE+0x00000018)
+#define ADR_DEBUG_CTL (MMU_REG_BASE+0x00000020)
+#define ADR_DEBUG_OUT (MMU_REG_BASE+0x00000024)
+#define ADR_MMU_STATUS (MMU_REG_BASE+0x00000028)
+#define ADR_DMN_STATUS (MMU_REG_BASE+0x0000002c)
+#define ADR_TAG_STATUS (MMU_REG_BASE+0x00000030)
+#define ADR_DMN_MCU_STATUS (MMU_REG_BASE+0x00000034)
+#define ADR_MB_IDTBL_0_STATUS (MMU_REG_BASE+0x00000040)
+#define ADR_MB_IDTBL_1_STATUS (MMU_REG_BASE+0x00000044)
+#define ADR_MB_IDTBL_2_STATUS (MMU_REG_BASE+0x00000048)
+#define ADR_MB_IDTBL_3_STATUS (MMU_REG_BASE+0x0000004c)
+#define ADR_PKT_IDTBL_0_STATUS (MMU_REG_BASE+0x00000050)
+#define ADR_PKT_IDTBL_1_STATUS (MMU_REG_BASE+0x00000054)
+#define ADR_PKT_IDTBL_2_STATUS (MMU_REG_BASE+0x00000058)
+#define ADR_PKT_IDTBL_3_STATUS (MMU_REG_BASE+0x0000005c)
+#define ADR_DMN_IDTBL_0_STATUS (MMU_REG_BASE+0x00000060)
+#define ADR_DMN_IDTBL_1_STATUS (MMU_REG_BASE+0x00000064)
+#define ADR_DMN_IDTBL_2_STATUS (MMU_REG_BASE+0x00000068)
+#define ADR_DMN_IDTBL_3_STATUS (MMU_REG_BASE+0x0000006c)
+#define ADR_MB_NEQID_0_STATUS (MMU_REG_BASE+0x00000070)
+#define ADR_MB_NEQID_1_STATUS (MMU_REG_BASE+0x00000074)
+#define ADR_MB_NEQID_2_STATUS (MMU_REG_BASE+0x00000078)
+#define ADR_MB_NEQID_3_STATUS (MMU_REG_BASE+0x0000007c)
+#define ADR_PKT_NEQID_0_STATUS (MMU_REG_BASE+0x00000080)
+#define ADR_PKT_NEQID_1_STATUS (MMU_REG_BASE+0x00000084)
+#define ADR_PKT_NEQID_2_STATUS (MMU_REG_BASE+0x00000088)
+#define ADR_PKT_NEQID_3_STATUS (MMU_REG_BASE+0x0000008c)
+#define ADR_ALC_NOCHG_ID_STATUS (MMU_REG_BASE+0x00000090)
+#define ADR_TAG_SRAM0_F_STATUS_0 (MMU_REG_BASE+0x000000a0)
+#define ADR_TAG_SRAM0_F_STATUS_1 (MMU_REG_BASE+0x000000a4)
+#define ADR_TAG_SRAM0_F_STATUS_2 (MMU_REG_BASE+0x000000a8)
+#define ADR_TAG_SRAM0_F_STATUS_3 (MMU_REG_BASE+0x000000ac)
+#define ADR_TAG_SRAM0_F_STATUS_4 (MMU_REG_BASE+0x000000b0)
+#define ADR_TAG_SRAM0_F_STATUS_5 (MMU_REG_BASE+0x000000b4)
+#define ADR_TAG_SRAM0_F_STATUS_6 (MMU_REG_BASE+0x000000b8)
+#define ADR_TAG_SRAM0_F_STATUS_7 (MMU_REG_BASE+0x000000bc)
+#define GET_MCU_ENABLE (((REG32(ADR_BRG_SW_RST)) & 0x00000001 ) >> 0)
+#define GET_MAC_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000002 ) >> 1)
+#define GET_MCU_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000004 ) >> 2)
+#define GET_SDIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000008 ) >> 3)
+#define GET_SPI_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000010 ) >> 4)
+#define GET_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000020 ) >> 5)
+#define GET_DMA_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000040 ) >> 6)
+#define GET_WDT_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000080 ) >> 7)
+#define GET_I2C_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000100 ) >> 8)
+#define GET_INT_CTL_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000200 ) >> 9)
+#define GET_BTCX_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000400 ) >> 10)
+#define GET_GPIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000800 ) >> 11)
+#define GET_US0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00001000 ) >> 12)
+#define GET_US1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00002000 ) >> 13)
+#define GET_US2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00004000 ) >> 14)
+#define GET_US3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00008000 ) >> 15)
+#define GET_MS0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00010000 ) >> 16)
+#define GET_MS1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00020000 ) >> 17)
+#define GET_MS2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00040000 ) >> 18)
+#define GET_MS3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00080000 ) >> 19)
+#define GET_RF_BB_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00100000 ) >> 20)
+#define GET_SYS_ALL_RST (((REG32(ADR_BRG_SW_RST)) & 0x00200000 ) >> 21)
+#define GET_DAT_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00400000 ) >> 22)
+#define GET_I2C_MST_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00800000 ) >> 23)
+#define GET_RG_REBOOT (((REG32(ADR_BOOT)) & 0x00000001 ) >> 0)
+#define GET_TRAP_IMG_FLS (((REG32(ADR_BOOT)) & 0x00010000 ) >> 16)
+#define GET_TRAP_REBOOT (((REG32(ADR_BOOT)) & 0x00020000 ) >> 17)
+#define GET_TRAP_BOOT_FLS (((REG32(ADR_BOOT)) & 0x00040000 ) >> 18)
+#define GET_CHIP_ID_31_0 (((REG32(ADR_CHIP_ID_0)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_63_32 (((REG32(ADR_CHIP_ID_1)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_95_64 (((REG32(ADR_CHIP_ID_2)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_127_96 (((REG32(ADR_CHIP_ID_3)) & 0xffffffff ) >> 0)
+#define GET_CK_SEL_1_0 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000003 ) >> 0)
+#define GET_CK_SEL_2 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000004 ) >> 2)
+#define GET_SYS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_MAC_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MCU_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000004 ) >> 2)
+#define GET_SDIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_SPI_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_UART_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_DMA_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_WDT_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
+#define GET_I2C_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000100 ) >> 8)
+#define GET_INT_CTL_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
+#define GET_BTCX_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_GPIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_US0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_US1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_US2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_US3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_MS0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00010000 ) >> 16)
+#define GET_MS1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00020000 ) >> 17)
+#define GET_MS2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00040000 ) >> 18)
+#define GET_MS3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00080000 ) >> 19)
+#define GET_BIST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00100000 ) >> 20)
+#define GET_I2C_MST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00800000 ) >> 23)
+#define GET_BTCX_CSR_CLK_EN (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_MCU_DBG_SEL (((REG32(ADR_MCU_DBG_SEL)) & 0x0000003f ) >> 0)
+#define GET_MCU_STOP_NOGRANT (((REG32(ADR_MCU_DBG_SEL)) & 0x00000100 ) >> 8)
+#define GET_MCU_STOP_ANYTIME (((REG32(ADR_MCU_DBG_SEL)) & 0x00000200 ) >> 9)
+#define GET_MCU_DBG_DATA (((REG32(ADR_MCU_DBG_DATA)) & 0xffffffff ) >> 0)
+#define GET_AHB_SW_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000001 ) >> 0)
+#define GET_AHB_ERR_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000002 ) >> 1)
+#define GET_REG_AHB_DEBUG_MX (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000030 ) >> 4)
+#define GET_REG_PKT_W_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000100 ) >> 8)
+#define GET_REG_PKT_R_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000200 ) >> 9)
+#define GET_IQ_SRAM_SEL_0 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00001000 ) >> 12)
+#define GET_IQ_SRAM_SEL_1 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00002000 ) >> 13)
+#define GET_IQ_SRAM_SEL_2 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00004000 ) >> 14)
+#define GET_AHB_STATUS (((REG32(ADR_AHB_BRG_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_PARALLEL_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000001 ) >> 0)
+#define GET_MBRUN (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000010 ) >> 4)
+#define GET_SHIFT_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000100 ) >> 8)
+#define GET_MODE_REG_SI (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000200 ) >> 9)
+#define GET_SIMULATION_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000400 ) >> 10)
+#define GET_DBIST_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000800 ) >> 11)
+#define GET_MODE_REG_IN (((REG32(ADR_BIST_MODE_REG_IN)) & 0x001fffff ) >> 0)
+#define GET_MODE_REG_OUT_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x001fffff ) >> 0)
+#define GET_MODE_REG_SO_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x80000000 ) >> 31)
+#define GET_MONITOR_BUS_MCU_31_0 (((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0xffffffff ) >> 0)
+#define GET_MONITOR_BUS_MCU_33_32 (((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0x00000003 ) >> 0)
+#define GET_TB_ADR_SEL (((REG32(ADR_TB_ADR_SEL)) & 0x0000ffff ) >> 0)
+#define GET_TB_CS (((REG32(ADR_TB_ADR_SEL)) & 0x80000000 ) >> 31)
+#define GET_TB_RDATA (((REG32(ADR_TB_RDATA)) & 0xffffffff ) >> 0)
+#define GET_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000001 ) >> 0)
+#define GET_DATA_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000010 ) >> 4)
+#define GET_AHB_ILL_ADDR (((REG32(ADR_AHB_ILL_ADDR)) & 0xffffffff ) >> 0)
+#define GET_AHB_FEN_ADDR (((REG32(ADR_AHB_FEN_ADDR)) & 0xffffffff ) >> 0)
+#define GET_ILL_ADDR_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000001 ) >> 0)
+#define GET_FENCE_HIT_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000002 ) >> 1)
+#define GET_ILL_ADDR_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000010 ) >> 4)
+#define GET_FENCE_HIT_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000020 ) >> 5)
+#define GET_PWM_INI_VALUE_P_A (((REG32(ADR_PWM_A)) & 0x000000ff ) >> 0)
+#define GET_PWM_INI_VALUE_N_A (((REG32(ADR_PWM_A)) & 0x0000ff00 ) >> 8)
+#define GET_PWM_POST_SCALER_A (((REG32(ADR_PWM_A)) & 0x000f0000 ) >> 16)
+#define GET_PWM_ALWAYSON_A (((REG32(ADR_PWM_A)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_A (((REG32(ADR_PWM_A)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_A (((REG32(ADR_PWM_A)) & 0x80000000 ) >> 31)
+#define GET_PWM_INI_VALUE_P_B (((REG32(ADR_PWM_B)) & 0x000000ff ) >> 0)
+#define GET_PWM_INI_VALUE_N_B (((REG32(ADR_PWM_B)) & 0x0000ff00 ) >> 8)
+#define GET_PWM_POST_SCALER_B (((REG32(ADR_PWM_B)) & 0x000f0000 ) >> 16)
+#define GET_PWM_ALWAYSON_B (((REG32(ADR_PWM_B)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_B (((REG32(ADR_PWM_B)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_B (((REG32(ADR_PWM_B)) & 0x80000000 ) >> 31)
+#define GET_HBUSREQ_LOCK (((REG32(ADR_HBUSREQ_LOCK)) & 0x00001fff ) >> 0)
+#define GET_HBURST_LOCK (((REG32(ADR_HBURST_LOCK)) & 0x00001fff ) >> 0)
+#define GET_PRESCALER_USTIMER (((REG32(ADR_PRESCALER_USTIMER)) & 0x000001ff ) >> 0)
+#define GET_MODE_REG_IN_MMU (((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0x0000ffff ) >> 0)
+#define GET_MODE_REG_OUT_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x0000ffff ) >> 0)
+#define GET_MODE_REG_SO_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x80000000 ) >> 31)
+#define GET_MONITOR_BUS_MMU (((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0x0007ffff ) >> 0)
+#define GET_TEST_MODE0 (((REG32(ADR_TEST_MODE)) & 0x00000001 ) >> 0)
+#define GET_TEST_MODE1 (((REG32(ADR_TEST_MODE)) & 0x00000002 ) >> 1)
+#define GET_TEST_MODE2 (((REG32(ADR_TEST_MODE)) & 0x00000004 ) >> 2)
+#define GET_TEST_MODE3 (((REG32(ADR_TEST_MODE)) & 0x00000008 ) >> 3)
+#define GET_TEST_MODE4 (((REG32(ADR_TEST_MODE)) & 0x00000010 ) >> 4)
+#define GET_TEST_MODE_ALL (((REG32(ADR_TEST_MODE)) & 0x00000020 ) >> 5)
+#define GET_WDT_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000001 ) >> 0)
+#define GET_SD_HOST_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000002 ) >> 1)
+#define GET_ALLOW_SD_RESET (((REG32(ADR_SD_INIT_CFG)) & 0x00000001 ) >> 0)
+#define GET_UART_NRTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000001 ) >> 0)
+#define GET_UART_NCTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000002 ) >> 1)
+#define GET_TU0_TM_INIT_VALUE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU0_TM_MODE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU0_TM_INT_STS_DONE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU0_TM_INT_MASK (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU0_TM_CUR_VALUE (((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU1_TM_INIT_VALUE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU1_TM_MODE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU1_TM_INT_STS_DONE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU1_TM_INT_MASK (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU1_TM_CUR_VALUE (((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU2_TM_INIT_VALUE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU2_TM_MODE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU2_TM_INT_STS_DONE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU2_TM_INT_MASK (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU2_TM_CUR_VALUE (((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU3_TM_INIT_VALUE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU3_TM_MODE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU3_TM_INT_STS_DONE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU3_TM_INT_MASK (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU3_TM_CUR_VALUE (((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM0_TM_INIT_VALUE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM0_TM_MODE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM0_TM_INT_STS_DONE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM0_TM_INT_MASK (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM0_TM_CUR_VALUE (((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM1_TM_INIT_VALUE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM1_TM_MODE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM1_TM_INT_STS_DONE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM1_TM_INT_MASK (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM1_TM_CUR_VALUE (((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM2_TM_INIT_VALUE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM2_TM_MODE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM2_TM_INT_STS_DONE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM2_TM_INT_MASK (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM2_TM_CUR_VALUE (((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM3_TM_INIT_VALUE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM3_TM_MODE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM3_TM_INT_STS_DONE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM3_TM_INT_MASK (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM3_TM_CUR_VALUE (((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_MCU_WDT_TIME_CNT (((REG32(ADR_MCU_WDOG_REG)) & 0x0000ffff ) >> 0)
+#define GET_MCU_WDT_STATUS (((REG32(ADR_MCU_WDOG_REG)) & 0x00020000 ) >> 17)
+#define GET_MCU_WDOG_ENA (((REG32(ADR_MCU_WDOG_REG)) & 0x80000000 ) >> 31)
+#define GET_SYS_WDT_TIME_CNT (((REG32(ADR_SYS_WDOG_REG)) & 0x0000ffff ) >> 0)
+#define GET_SYS_WDT_STATUS (((REG32(ADR_SYS_WDOG_REG)) & 0x00020000 ) >> 17)
+#define GET_SYS_WDOG_ENA (((REG32(ADR_SYS_WDOG_REG)) & 0x80000000 ) >> 31)
+#define GET_XLNA_EN_O_OE (((REG32(ADR_PAD6)) & 0x00000001 ) >> 0)
+#define GET_XLNA_EN_O_PE (((REG32(ADR_PAD6)) & 0x00000002 ) >> 1)
+#define GET_PAD6_IE (((REG32(ADR_PAD6)) & 0x00000008 ) >> 3)
+#define GET_PAD6_SEL_I (((REG32(ADR_PAD6)) & 0x00000030 ) >> 4)
+#define GET_PAD6_OD (((REG32(ADR_PAD6)) & 0x00000100 ) >> 8)
+#define GET_PAD6_SEL_O (((REG32(ADR_PAD6)) & 0x00001000 ) >> 12)
+#define GET_XLNA_EN_O_C (((REG32(ADR_PAD6)) & 0x10000000 ) >> 28)
+#define GET_WIFI_TX_SW_O_OE (((REG32(ADR_PAD7)) & 0x00000001 ) >> 0)
+#define GET_WIFI_TX_SW_O_PE (((REG32(ADR_PAD7)) & 0x00000002 ) >> 1)
+#define GET_PAD7_IE (((REG32(ADR_PAD7)) & 0x00000008 ) >> 3)
+#define GET_PAD7_SEL_I (((REG32(ADR_PAD7)) & 0x00000030 ) >> 4)
+#define GET_PAD7_OD (((REG32(ADR_PAD7)) & 0x00000100 ) >> 8)
+#define GET_PAD7_SEL_O (((REG32(ADR_PAD7)) & 0x00001000 ) >> 12)
+#define GET_WIFI_TX_SW_O_C (((REG32(ADR_PAD7)) & 0x10000000 ) >> 28)
+#define GET_WIFI_RX_SW_O_OE (((REG32(ADR_PAD8)) & 0x00000001 ) >> 0)
+#define GET_WIFI_RX_SW_O_PE (((REG32(ADR_PAD8)) & 0x00000002 ) >> 1)
+#define GET_PAD8_IE (((REG32(ADR_PAD8)) & 0x00000008 ) >> 3)
+#define GET_PAD8_SEL_I (((REG32(ADR_PAD8)) & 0x00000030 ) >> 4)
+#define GET_PAD8_OD (((REG32(ADR_PAD8)) & 0x00000100 ) >> 8)
+#define GET_WIFI_RX_SW_O_C (((REG32(ADR_PAD8)) & 0x10000000 ) >> 28)
+#define GET_BT_SW_O_OE (((REG32(ADR_PAD9)) & 0x00000001 ) >> 0)
+#define GET_BT_SW_O_PE (((REG32(ADR_PAD9)) & 0x00000002 ) >> 1)
+#define GET_PAD9_IE (((REG32(ADR_PAD9)) & 0x00000008 ) >> 3)
+#define GET_PAD9_SEL_I (((REG32(ADR_PAD9)) & 0x00000030 ) >> 4)
+#define GET_PAD9_OD (((REG32(ADR_PAD9)) & 0x00000100 ) >> 8)
+#define GET_PAD9_SEL_O (((REG32(ADR_PAD9)) & 0x00001000 ) >> 12)
+#define GET_BT_SW_O_C (((REG32(ADR_PAD9)) & 0x10000000 ) >> 28)
+#define GET_XPA_EN_O_OE (((REG32(ADR_PAD11)) & 0x00000001 ) >> 0)
+#define GET_XPA_EN_O_PE (((REG32(ADR_PAD11)) & 0x00000002 ) >> 1)
+#define GET_PAD11_IE (((REG32(ADR_PAD11)) & 0x00000008 ) >> 3)
+#define GET_PAD11_SEL_I (((REG32(ADR_PAD11)) & 0x00000030 ) >> 4)
+#define GET_PAD11_OD (((REG32(ADR_PAD11)) & 0x00000100 ) >> 8)
+#define GET_PAD11_SEL_O (((REG32(ADR_PAD11)) & 0x00001000 ) >> 12)
+#define GET_XPA_EN_O_C (((REG32(ADR_PAD11)) & 0x10000000 ) >> 28)
+#define GET_PAD15_OE (((REG32(ADR_PAD15)) & 0x00000001 ) >> 0)
+#define GET_PAD15_PE (((REG32(ADR_PAD15)) & 0x00000002 ) >> 1)
+#define GET_PAD15_DS (((REG32(ADR_PAD15)) & 0x00000004 ) >> 2)
+#define GET_PAD15_IE (((REG32(ADR_PAD15)) & 0x00000008 ) >> 3)
+#define GET_PAD15_SEL_I (((REG32(ADR_PAD15)) & 0x00000030 ) >> 4)
+#define GET_PAD15_OD (((REG32(ADR_PAD15)) & 0x00000100 ) >> 8)
+#define GET_PAD15_SEL_O (((REG32(ADR_PAD15)) & 0x00001000 ) >> 12)
+#define GET_TEST_1_ID (((REG32(ADR_PAD15)) & 0x10000000 ) >> 28)
+#define GET_PAD16_OE (((REG32(ADR_PAD16)) & 0x00000001 ) >> 0)
+#define GET_PAD16_PE (((REG32(ADR_PAD16)) & 0x00000002 ) >> 1)
+#define GET_PAD16_DS (((REG32(ADR_PAD16)) & 0x00000004 ) >> 2)
+#define GET_PAD16_IE (((REG32(ADR_PAD16)) & 0x00000008 ) >> 3)
+#define GET_PAD16_SEL_I (((REG32(ADR_PAD16)) & 0x00000030 ) >> 4)
+#define GET_PAD16_OD (((REG32(ADR_PAD16)) & 0x00000100 ) >> 8)
+#define GET_PAD16_SEL_O (((REG32(ADR_PAD16)) & 0x00001000 ) >> 12)
+#define GET_TEST_2_ID (((REG32(ADR_PAD16)) & 0x10000000 ) >> 28)
+#define GET_PAD17_OE (((REG32(ADR_PAD17)) & 0x00000001 ) >> 0)
+#define GET_PAD17_PE (((REG32(ADR_PAD17)) & 0x00000002 ) >> 1)
+#define GET_PAD17_DS (((REG32(ADR_PAD17)) & 0x00000004 ) >> 2)
+#define GET_PAD17_IE (((REG32(ADR_PAD17)) & 0x00000008 ) >> 3)
+#define GET_PAD17_SEL_I (((REG32(ADR_PAD17)) & 0x00000030 ) >> 4)
+#define GET_PAD17_OD (((REG32(ADR_PAD17)) & 0x00000100 ) >> 8)
+#define GET_PAD17_SEL_O (((REG32(ADR_PAD17)) & 0x00001000 ) >> 12)
+#define GET_TEST_3_ID (((REG32(ADR_PAD17)) & 0x10000000 ) >> 28)
+#define GET_PAD18_OE (((REG32(ADR_PAD18)) & 0x00000001 ) >> 0)
+#define GET_PAD18_PE (((REG32(ADR_PAD18)) & 0x00000002 ) >> 1)
+#define GET_PAD18_DS (((REG32(ADR_PAD18)) & 0x00000004 ) >> 2)
+#define GET_PAD18_IE (((REG32(ADR_PAD18)) & 0x00000008 ) >> 3)
+#define GET_PAD18_SEL_I (((REG32(ADR_PAD18)) & 0x00000030 ) >> 4)
+#define GET_PAD18_OD (((REG32(ADR_PAD18)) & 0x00000100 ) >> 8)
+#define GET_PAD18_SEL_O (((REG32(ADR_PAD18)) & 0x00003000 ) >> 12)
+#define GET_TEST_4_ID (((REG32(ADR_PAD18)) & 0x10000000 ) >> 28)
+#define GET_PAD19_OE (((REG32(ADR_PAD19)) & 0x00000001 ) >> 0)
+#define GET_PAD19_PE (((REG32(ADR_PAD19)) & 0x00000002 ) >> 1)
+#define GET_PAD19_DS (((REG32(ADR_PAD19)) & 0x00000004 ) >> 2)
+#define GET_PAD19_IE (((REG32(ADR_PAD19)) & 0x00000008 ) >> 3)
+#define GET_PAD19_SEL_I (((REG32(ADR_PAD19)) & 0x00000030 ) >> 4)
+#define GET_PAD19_OD (((REG32(ADR_PAD19)) & 0x00000100 ) >> 8)
+#define GET_PAD19_SEL_O (((REG32(ADR_PAD19)) & 0x00007000 ) >> 12)
+#define GET_SHORT_TO_20_ID (((REG32(ADR_PAD19)) & 0x10000000 ) >> 28)
+#define GET_PAD20_OE (((REG32(ADR_PAD20)) & 0x00000001 ) >> 0)
+#define GET_PAD20_PE (((REG32(ADR_PAD20)) & 0x00000002 ) >> 1)
+#define GET_PAD20_DS (((REG32(ADR_PAD20)) & 0x00000004 ) >> 2)
+#define GET_PAD20_IE (((REG32(ADR_PAD20)) & 0x00000008 ) >> 3)
+#define GET_PAD20_SEL_I (((REG32(ADR_PAD20)) & 0x000000f0 ) >> 4)
+#define GET_PAD20_OD (((REG32(ADR_PAD20)) & 0x00000100 ) >> 8)
+#define GET_PAD20_SEL_O (((REG32(ADR_PAD20)) & 0x00003000 ) >> 12)
+#define GET_STRAP0 (((REG32(ADR_PAD20)) & 0x08000000 ) >> 27)
+#define GET_GPIO_TEST_1_ID (((REG32(ADR_PAD20)) & 0x10000000 ) >> 28)
+#define GET_PAD21_OE (((REG32(ADR_PAD21)) & 0x00000001 ) >> 0)
+#define GET_PAD21_PE (((REG32(ADR_PAD21)) & 0x00000002 ) >> 1)
+#define GET_PAD21_DS (((REG32(ADR_PAD21)) & 0x00000004 ) >> 2)
+#define GET_PAD21_IE (((REG32(ADR_PAD21)) & 0x00000008 ) >> 3)
+#define GET_PAD21_SEL_I (((REG32(ADR_PAD21)) & 0x00000070 ) >> 4)
+#define GET_PAD21_OD (((REG32(ADR_PAD21)) & 0x00000100 ) >> 8)
+#define GET_PAD21_SEL_O (((REG32(ADR_PAD21)) & 0x00003000 ) >> 12)
+#define GET_STRAP3 (((REG32(ADR_PAD21)) & 0x08000000 ) >> 27)
+#define GET_GPIO_TEST_2_ID (((REG32(ADR_PAD21)) & 0x10000000 ) >> 28)
+#define GET_PAD22_OE (((REG32(ADR_PAD22)) & 0x00000001 ) >> 0)
+#define GET_PAD22_PE (((REG32(ADR_PAD22)) & 0x00000002 ) >> 1)
+#define GET_PAD22_DS (((REG32(ADR_PAD22)) & 0x00000004 ) >> 2)
+#define GET_PAD22_IE (((REG32(ADR_PAD22)) & 0x00000008 ) >> 3)
+#define GET_PAD22_SEL_I (((REG32(ADR_PAD22)) & 0x00000070 ) >> 4)
+#define GET_PAD22_OD (((REG32(ADR_PAD22)) & 0x00000100 ) >> 8)
+#define GET_PAD22_SEL_O (((REG32(ADR_PAD22)) & 0x00007000 ) >> 12)
+#define GET_PAD22_SEL_OE (((REG32(ADR_PAD22)) & 0x00100000 ) >> 20)
+#define GET_GPIO_TEST_3_ID (((REG32(ADR_PAD22)) & 0x10000000 ) >> 28)
+#define GET_PAD24_OE (((REG32(ADR_PAD24)) & 0x00000001 ) >> 0)
+#define GET_PAD24_PE (((REG32(ADR_PAD24)) & 0x00000002 ) >> 1)
+#define GET_PAD24_DS (((REG32(ADR_PAD24)) & 0x00000004 ) >> 2)
+#define GET_PAD24_IE (((REG32(ADR_PAD24)) & 0x00000008 ) >> 3)
+#define GET_PAD24_SEL_I (((REG32(ADR_PAD24)) & 0x00000030 ) >> 4)
+#define GET_PAD24_OD (((REG32(ADR_PAD24)) & 0x00000100 ) >> 8)
+#define GET_PAD24_SEL_O (((REG32(ADR_PAD24)) & 0x00007000 ) >> 12)
+#define GET_GPIO_TEST_4_ID (((REG32(ADR_PAD24)) & 0x10000000 ) >> 28)
+#define GET_PAD25_OE (((REG32(ADR_PAD25)) & 0x00000001 ) >> 0)
+#define GET_PAD25_PE (((REG32(ADR_PAD25)) & 0x00000002 ) >> 1)
+#define GET_PAD25_DS (((REG32(ADR_PAD25)) & 0x00000004 ) >> 2)
+#define GET_PAD25_IE (((REG32(ADR_PAD25)) & 0x00000008 ) >> 3)
+#define GET_PAD25_SEL_I (((REG32(ADR_PAD25)) & 0x00000070 ) >> 4)
+#define GET_PAD25_OD (((REG32(ADR_PAD25)) & 0x00000100 ) >> 8)
+#define GET_PAD25_SEL_O (((REG32(ADR_PAD25)) & 0x00007000 ) >> 12)
+#define GET_PAD25_SEL_OE (((REG32(ADR_PAD25)) & 0x00100000 ) >> 20)
+#define GET_STRAP1 (((REG32(ADR_PAD25)) & 0x08000000 ) >> 27)
+#define GET_GPIO_1_ID (((REG32(ADR_PAD25)) & 0x10000000 ) >> 28)
+#define GET_PAD27_OE (((REG32(ADR_PAD27)) & 0x00000001 ) >> 0)
+#define GET_PAD27_PE (((REG32(ADR_PAD27)) & 0x00000002 ) >> 1)
+#define GET_PAD27_DS (((REG32(ADR_PAD27)) & 0x00000004 ) >> 2)
+#define GET_PAD27_IE (((REG32(ADR_PAD27)) & 0x00000008 ) >> 3)
+#define GET_PAD27_SEL_I (((REG32(ADR_PAD27)) & 0x00000070 ) >> 4)
+#define GET_PAD27_OD (((REG32(ADR_PAD27)) & 0x00000100 ) >> 8)
+#define GET_PAD27_SEL_O (((REG32(ADR_PAD27)) & 0x00007000 ) >> 12)
+#define GET_GPIO_2_ID (((REG32(ADR_PAD27)) & 0x10000000 ) >> 28)
+#define GET_PAD28_OE (((REG32(ADR_PAD28)) & 0x00000001 ) >> 0)
+#define GET_PAD28_PE (((REG32(ADR_PAD28)) & 0x00000002 ) >> 1)
+#define GET_PAD28_DS (((REG32(ADR_PAD28)) & 0x00000004 ) >> 2)
+#define GET_PAD28_IE (((REG32(ADR_PAD28)) & 0x00000008 ) >> 3)
+#define GET_PAD28_SEL_I (((REG32(ADR_PAD28)) & 0x00000070 ) >> 4)
+#define GET_PAD28_OD (((REG32(ADR_PAD28)) & 0x00000100 ) >> 8)
+#define GET_PAD28_SEL_O (((REG32(ADR_PAD28)) & 0x0000f000 ) >> 12)
+#define GET_PAD28_SEL_OE (((REG32(ADR_PAD28)) & 0x00100000 ) >> 20)
+#define GET_GPIO_3_ID (((REG32(ADR_PAD28)) & 0x10000000 ) >> 28)
+#define GET_PAD29_OE (((REG32(ADR_PAD29)) & 0x00000001 ) >> 0)
+#define GET_PAD29_PE (((REG32(ADR_PAD29)) & 0x00000002 ) >> 1)
+#define GET_PAD29_DS (((REG32(ADR_PAD29)) & 0x00000004 ) >> 2)
+#define GET_PAD29_IE (((REG32(ADR_PAD29)) & 0x00000008 ) >> 3)
+#define GET_PAD29_SEL_I (((REG32(ADR_PAD29)) & 0x00000070 ) >> 4)
+#define GET_PAD29_OD (((REG32(ADR_PAD29)) & 0x00000100 ) >> 8)
+#define GET_PAD29_SEL_O (((REG32(ADR_PAD29)) & 0x00007000 ) >> 12)
+#define GET_GPIO_TEST_5_ID (((REG32(ADR_PAD29)) & 0x10000000 ) >> 28)
+#define GET_PAD30_OE (((REG32(ADR_PAD30)) & 0x00000001 ) >> 0)
+#define GET_PAD30_PE (((REG32(ADR_PAD30)) & 0x00000002 ) >> 1)
+#define GET_PAD30_DS (((REG32(ADR_PAD30)) & 0x00000004 ) >> 2)
+#define GET_PAD30_IE (((REG32(ADR_PAD30)) & 0x00000008 ) >> 3)
+#define GET_PAD30_SEL_I (((REG32(ADR_PAD30)) & 0x00000030 ) >> 4)
+#define GET_PAD30_OD (((REG32(ADR_PAD30)) & 0x00000100 ) >> 8)
+#define GET_PAD30_SEL_O (((REG32(ADR_PAD30)) & 0x00003000 ) >> 12)
+#define GET_TEST_6_ID (((REG32(ADR_PAD30)) & 0x10000000 ) >> 28)
+#define GET_PAD31_OE (((REG32(ADR_PAD31)) & 0x00000001 ) >> 0)
+#define GET_PAD31_PE (((REG32(ADR_PAD31)) & 0x00000002 ) >> 1)
+#define GET_PAD31_DS (((REG32(ADR_PAD31)) & 0x00000004 ) >> 2)
+#define GET_PAD31_IE (((REG32(ADR_PAD31)) & 0x00000008 ) >> 3)
+#define GET_PAD31_SEL_I (((REG32(ADR_PAD31)) & 0x00000030 ) >> 4)
+#define GET_PAD31_OD (((REG32(ADR_PAD31)) & 0x00000100 ) >> 8)
+#define GET_PAD31_SEL_O (((REG32(ADR_PAD31)) & 0x00003000 ) >> 12)
+#define GET_TEST_7_ID (((REG32(ADR_PAD31)) & 0x10000000 ) >> 28)
+#define GET_PAD32_OE (((REG32(ADR_PAD32)) & 0x00000001 ) >> 0)
+#define GET_PAD32_PE (((REG32(ADR_PAD32)) & 0x00000002 ) >> 1)
+#define GET_PAD32_DS (((REG32(ADR_PAD32)) & 0x00000004 ) >> 2)
+#define GET_PAD32_IE (((REG32(ADR_PAD32)) & 0x00000008 ) >> 3)
+#define GET_PAD32_SEL_I (((REG32(ADR_PAD32)) & 0x00000030 ) >> 4)
+#define GET_PAD32_OD (((REG32(ADR_PAD32)) & 0x00000100 ) >> 8)
+#define GET_PAD32_SEL_O (((REG32(ADR_PAD32)) & 0x00003000 ) >> 12)
+#define GET_TEST_8_ID (((REG32(ADR_PAD32)) & 0x10000000 ) >> 28)
+#define GET_PAD33_OE (((REG32(ADR_PAD33)) & 0x00000001 ) >> 0)
+#define GET_PAD33_PE (((REG32(ADR_PAD33)) & 0x00000002 ) >> 1)
+#define GET_PAD33_DS (((REG32(ADR_PAD33)) & 0x00000004 ) >> 2)
+#define GET_PAD33_IE (((REG32(ADR_PAD33)) & 0x00000008 ) >> 3)
+#define GET_PAD33_SEL_I (((REG32(ADR_PAD33)) & 0x00000030 ) >> 4)
+#define GET_PAD33_OD (((REG32(ADR_PAD33)) & 0x00000100 ) >> 8)
+#define GET_PAD33_SEL_O (((REG32(ADR_PAD33)) & 0x00003000 ) >> 12)
+#define GET_TEST_9_ID (((REG32(ADR_PAD33)) & 0x10000000 ) >> 28)
+#define GET_PAD34_OE (((REG32(ADR_PAD34)) & 0x00000001 ) >> 0)
+#define GET_PAD34_PE (((REG32(ADR_PAD34)) & 0x00000002 ) >> 1)
+#define GET_PAD34_DS (((REG32(ADR_PAD34)) & 0x00000004 ) >> 2)
+#define GET_PAD34_IE (((REG32(ADR_PAD34)) & 0x00000008 ) >> 3)
+#define GET_PAD34_SEL_I (((REG32(ADR_PAD34)) & 0x00000030 ) >> 4)
+#define GET_PAD34_OD (((REG32(ADR_PAD34)) & 0x00000100 ) >> 8)
+#define GET_PAD34_SEL_O (((REG32(ADR_PAD34)) & 0x00003000 ) >> 12)
+#define GET_TEST_10_ID (((REG32(ADR_PAD34)) & 0x10000000 ) >> 28)
+#define GET_PAD42_OE (((REG32(ADR_PAD42)) & 0x00000001 ) >> 0)
+#define GET_PAD42_PE (((REG32(ADR_PAD42)) & 0x00000002 ) >> 1)
+#define GET_PAD42_DS (((REG32(ADR_PAD42)) & 0x00000004 ) >> 2)
+#define GET_PAD42_IE (((REG32(ADR_PAD42)) & 0x00000008 ) >> 3)
+#define GET_PAD42_SEL_I (((REG32(ADR_PAD42)) & 0x00000030 ) >> 4)
+#define GET_PAD42_OD (((REG32(ADR_PAD42)) & 0x00000100 ) >> 8)
+#define GET_PAD42_SEL_O (((REG32(ADR_PAD42)) & 0x00001000 ) >> 12)
+#define GET_TEST_11_ID (((REG32(ADR_PAD42)) & 0x10000000 ) >> 28)
+#define GET_PAD43_OE (((REG32(ADR_PAD43)) & 0x00000001 ) >> 0)
+#define GET_PAD43_PE (((REG32(ADR_PAD43)) & 0x00000002 ) >> 1)
+#define GET_PAD43_DS (((REG32(ADR_PAD43)) & 0x00000004 ) >> 2)
+#define GET_PAD43_IE (((REG32(ADR_PAD43)) & 0x00000008 ) >> 3)
+#define GET_PAD43_SEL_I (((REG32(ADR_PAD43)) & 0x00000030 ) >> 4)
+#define GET_PAD43_OD (((REG32(ADR_PAD43)) & 0x00000100 ) >> 8)
+#define GET_PAD43_SEL_O (((REG32(ADR_PAD43)) & 0x00001000 ) >> 12)
+#define GET_TEST_12_ID (((REG32(ADR_PAD43)) & 0x10000000 ) >> 28)
+#define GET_PAD44_OE (((REG32(ADR_PAD44)) & 0x00000001 ) >> 0)
+#define GET_PAD44_PE (((REG32(ADR_PAD44)) & 0x00000002 ) >> 1)
+#define GET_PAD44_DS (((REG32(ADR_PAD44)) & 0x00000004 ) >> 2)
+#define GET_PAD44_IE (((REG32(ADR_PAD44)) & 0x00000008 ) >> 3)
+#define GET_PAD44_SEL_I (((REG32(ADR_PAD44)) & 0x00000030 ) >> 4)
+#define GET_PAD44_OD (((REG32(ADR_PAD44)) & 0x00000100 ) >> 8)
+#define GET_PAD44_SEL_O (((REG32(ADR_PAD44)) & 0x00003000 ) >> 12)
+#define GET_TEST_13_ID (((REG32(ADR_PAD44)) & 0x10000000 ) >> 28)
+#define GET_PAD45_OE (((REG32(ADR_PAD45)) & 0x00000001 ) >> 0)
+#define GET_PAD45_PE (((REG32(ADR_PAD45)) & 0x00000002 ) >> 1)
+#define GET_PAD45_DS (((REG32(ADR_PAD45)) & 0x00000004 ) >> 2)
+#define GET_PAD45_IE (((REG32(ADR_PAD45)) & 0x00000008 ) >> 3)
+#define GET_PAD45_SEL_I (((REG32(ADR_PAD45)) & 0x00000030 ) >> 4)
+#define GET_PAD45_OD (((REG32(ADR_PAD45)) & 0x00000100 ) >> 8)
+#define GET_PAD45_SEL_O (((REG32(ADR_PAD45)) & 0x00003000 ) >> 12)
+#define GET_TEST_14_ID (((REG32(ADR_PAD45)) & 0x10000000 ) >> 28)
+#define GET_PAD46_OE (((REG32(ADR_PAD46)) & 0x00000001 ) >> 0)
+#define GET_PAD46_PE (((REG32(ADR_PAD46)) & 0x00000002 ) >> 1)
+#define GET_PAD46_DS (((REG32(ADR_PAD46)) & 0x00000004 ) >> 2)
+#define GET_PAD46_IE (((REG32(ADR_PAD46)) & 0x00000008 ) >> 3)
+#define GET_PAD46_SEL_I (((REG32(ADR_PAD46)) & 0x00000030 ) >> 4)
+#define GET_PAD46_OD (((REG32(ADR_PAD46)) & 0x00000100 ) >> 8)
+#define GET_PAD46_SEL_O (((REG32(ADR_PAD46)) & 0x00003000 ) >> 12)
+#define GET_TEST_15_ID (((REG32(ADR_PAD46)) & 0x10000000 ) >> 28)
+#define GET_PAD47_OE (((REG32(ADR_PAD47)) & 0x00000001 ) >> 0)
+#define GET_PAD47_PE (((REG32(ADR_PAD47)) & 0x00000002 ) >> 1)
+#define GET_PAD47_DS (((REG32(ADR_PAD47)) & 0x00000004 ) >> 2)
+#define GET_PAD47_SEL_I (((REG32(ADR_PAD47)) & 0x00000030 ) >> 4)
+#define GET_PAD47_OD (((REG32(ADR_PAD47)) & 0x00000100 ) >> 8)
+#define GET_PAD47_SEL_O (((REG32(ADR_PAD47)) & 0x00003000 ) >> 12)
+#define GET_PAD47_SEL_OE (((REG32(ADR_PAD47)) & 0x00100000 ) >> 20)
+#define GET_GPIO_9_ID (((REG32(ADR_PAD47)) & 0x10000000 ) >> 28)
+#define GET_PAD48_OE (((REG32(ADR_PAD48)) & 0x00000001 ) >> 0)
+#define GET_PAD48_PE (((REG32(ADR_PAD48)) & 0x00000002 ) >> 1)
+#define GET_PAD48_DS (((REG32(ADR_PAD48)) & 0x00000004 ) >> 2)
+#define GET_PAD48_IE (((REG32(ADR_PAD48)) & 0x00000008 ) >> 3)
+#define GET_PAD48_SEL_I (((REG32(ADR_PAD48)) & 0x00000070 ) >> 4)
+#define GET_PAD48_OD (((REG32(ADR_PAD48)) & 0x00000100 ) >> 8)
+#define GET_PAD48_PE_SEL (((REG32(ADR_PAD48)) & 0x00000800 ) >> 11)
+#define GET_PAD48_SEL_O (((REG32(ADR_PAD48)) & 0x00003000 ) >> 12)
+#define GET_PAD48_SEL_OE (((REG32(ADR_PAD48)) & 0x00100000 ) >> 20)
+#define GET_GPIO_10_ID (((REG32(ADR_PAD48)) & 0x10000000 ) >> 28)
+#define GET_PAD49_OE (((REG32(ADR_PAD49)) & 0x00000001 ) >> 0)
+#define GET_PAD49_PE (((REG32(ADR_PAD49)) & 0x00000002 ) >> 1)
+#define GET_PAD49_DS (((REG32(ADR_PAD49)) & 0x00000004 ) >> 2)
+#define GET_PAD49_IE (((REG32(ADR_PAD49)) & 0x00000008 ) >> 3)
+#define GET_PAD49_SEL_I (((REG32(ADR_PAD49)) & 0x00000070 ) >> 4)
+#define GET_PAD49_OD (((REG32(ADR_PAD49)) & 0x00000100 ) >> 8)
+#define GET_PAD49_SEL_O (((REG32(ADR_PAD49)) & 0x00003000 ) >> 12)
+#define GET_PAD49_SEL_OE (((REG32(ADR_PAD49)) & 0x00100000 ) >> 20)
+#define GET_GPIO_11_ID (((REG32(ADR_PAD49)) & 0x10000000 ) >> 28)
+#define GET_PAD50_OE (((REG32(ADR_PAD50)) & 0x00000001 ) >> 0)
+#define GET_PAD50_PE (((REG32(ADR_PAD50)) & 0x00000002 ) >> 1)
+#define GET_PAD50_DS (((REG32(ADR_PAD50)) & 0x00000004 ) >> 2)
+#define GET_PAD50_IE (((REG32(ADR_PAD50)) & 0x00000008 ) >> 3)
+#define GET_PAD50_SEL_I (((REG32(ADR_PAD50)) & 0x00000070 ) >> 4)
+#define GET_PAD50_OD (((REG32(ADR_PAD50)) & 0x00000100 ) >> 8)
+#define GET_PAD50_SEL_O (((REG32(ADR_PAD50)) & 0x00003000 ) >> 12)
+#define GET_PAD50_SEL_OE (((REG32(ADR_PAD50)) & 0x00100000 ) >> 20)
+#define GET_GPIO_12_ID (((REG32(ADR_PAD50)) & 0x10000000 ) >> 28)
+#define GET_PAD51_OE (((REG32(ADR_PAD51)) & 0x00000001 ) >> 0)
+#define GET_PAD51_PE (((REG32(ADR_PAD51)) & 0x00000002 ) >> 1)
+#define GET_PAD51_DS (((REG32(ADR_PAD51)) & 0x00000004 ) >> 2)
+#define GET_PAD51_IE (((REG32(ADR_PAD51)) & 0x00000008 ) >> 3)
+#define GET_PAD51_SEL_I (((REG32(ADR_PAD51)) & 0x00000030 ) >> 4)
+#define GET_PAD51_OD (((REG32(ADR_PAD51)) & 0x00000100 ) >> 8)
+#define GET_PAD51_SEL_O (((REG32(ADR_PAD51)) & 0x00001000 ) >> 12)
+#define GET_PAD51_SEL_OE (((REG32(ADR_PAD51)) & 0x00100000 ) >> 20)
+#define GET_GPIO_13_ID (((REG32(ADR_PAD51)) & 0x10000000 ) >> 28)
+#define GET_PAD52_OE (((REG32(ADR_PAD52)) & 0x00000001 ) >> 0)
+#define GET_PAD52_PE (((REG32(ADR_PAD52)) & 0x00000002 ) >> 1)
+#define GET_PAD52_DS (((REG32(ADR_PAD52)) & 0x00000004 ) >> 2)
+#define GET_PAD52_SEL_I (((REG32(ADR_PAD52)) & 0x00000030 ) >> 4)
+#define GET_PAD52_OD (((REG32(ADR_PAD52)) & 0x00000100 ) >> 8)
+#define GET_PAD52_SEL_O (((REG32(ADR_PAD52)) & 0x00001000 ) >> 12)
+#define GET_PAD52_SEL_OE (((REG32(ADR_PAD52)) & 0x00100000 ) >> 20)
+#define GET_GPIO_14_ID (((REG32(ADR_PAD52)) & 0x10000000 ) >> 28)
+#define GET_PAD53_OE (((REG32(ADR_PAD53)) & 0x00000001 ) >> 0)
+#define GET_PAD53_PE (((REG32(ADR_PAD53)) & 0x00000002 ) >> 1)
+#define GET_PAD53_DS (((REG32(ADR_PAD53)) & 0x00000004 ) >> 2)
+#define GET_PAD53_IE (((REG32(ADR_PAD53)) & 0x00000008 ) >> 3)
+#define GET_PAD53_SEL_I (((REG32(ADR_PAD53)) & 0x00000030 ) >> 4)
+#define GET_PAD53_OD (((REG32(ADR_PAD53)) & 0x00000100 ) >> 8)
+#define GET_PAD53_SEL_O (((REG32(ADR_PAD53)) & 0x00001000 ) >> 12)
+#define GET_JTAG_TMS_ID (((REG32(ADR_PAD53)) & 0x10000000 ) >> 28)
+#define GET_PAD54_OE (((REG32(ADR_PAD54)) & 0x00000001 ) >> 0)
+#define GET_PAD54_PE (((REG32(ADR_PAD54)) & 0x00000002 ) >> 1)
+#define GET_PAD54_DS (((REG32(ADR_PAD54)) & 0x00000004 ) >> 2)
+#define GET_PAD54_OD (((REG32(ADR_PAD54)) & 0x00000100 ) >> 8)
+#define GET_PAD54_SEL_O (((REG32(ADR_PAD54)) & 0x00003000 ) >> 12)
+#define GET_JTAG_TCK_ID (((REG32(ADR_PAD54)) & 0x10000000 ) >> 28)
+#define GET_PAD56_PE (((REG32(ADR_PAD56)) & 0x00000002 ) >> 1)
+#define GET_PAD56_DS (((REG32(ADR_PAD56)) & 0x00000004 ) >> 2)
+#define GET_PAD56_SEL_I (((REG32(ADR_PAD56)) & 0x00000010 ) >> 4)
+#define GET_PAD56_OD (((REG32(ADR_PAD56)) & 0x00000100 ) >> 8)
+#define GET_JTAG_TDI_ID (((REG32(ADR_PAD56)) & 0x10000000 ) >> 28)
+#define GET_PAD57_OE (((REG32(ADR_PAD57)) & 0x00000001 ) >> 0)
+#define GET_PAD57_PE (((REG32(ADR_PAD57)) & 0x00000002 ) >> 1)
+#define GET_PAD57_DS (((REG32(ADR_PAD57)) & 0x00000004 ) >> 2)
+#define GET_PAD57_IE (((REG32(ADR_PAD57)) & 0x00000008 ) >> 3)
+#define GET_PAD57_SEL_I (((REG32(ADR_PAD57)) & 0x00000030 ) >> 4)
+#define GET_PAD57_OD (((REG32(ADR_PAD57)) & 0x00000100 ) >> 8)
+#define GET_PAD57_SEL_O (((REG32(ADR_PAD57)) & 0x00003000 ) >> 12)
+#define GET_PAD57_SEL_OE (((REG32(ADR_PAD57)) & 0x00100000 ) >> 20)
+#define GET_JTAG_TDO_ID (((REG32(ADR_PAD57)) & 0x10000000 ) >> 28)
+#define GET_PAD58_OE (((REG32(ADR_PAD58)) & 0x00000001 ) >> 0)
+#define GET_PAD58_PE (((REG32(ADR_PAD58)) & 0x00000002 ) >> 1)
+#define GET_PAD58_DS (((REG32(ADR_PAD58)) & 0x00000004 ) >> 2)
+#define GET_PAD58_IE (((REG32(ADR_PAD58)) & 0x00000008 ) >> 3)
+#define GET_PAD58_SEL_I (((REG32(ADR_PAD58)) & 0x00000030 ) >> 4)
+#define GET_PAD58_OD (((REG32(ADR_PAD58)) & 0x00000100 ) >> 8)
+#define GET_PAD58_SEL_O (((REG32(ADR_PAD58)) & 0x00001000 ) >> 12)
+#define GET_TEST_16_ID (((REG32(ADR_PAD58)) & 0x10000000 ) >> 28)
+#define GET_PAD59_OE (((REG32(ADR_PAD59)) & 0x00000001 ) >> 0)
+#define GET_PAD59_PE (((REG32(ADR_PAD59)) & 0x00000002 ) >> 1)
+#define GET_PAD59_DS (((REG32(ADR_PAD59)) & 0x00000004 ) >> 2)
+#define GET_PAD59_IE (((REG32(ADR_PAD59)) & 0x00000008 ) >> 3)
+#define GET_PAD59_SEL_I (((REG32(ADR_PAD59)) & 0x00000030 ) >> 4)
+#define GET_PAD59_OD (((REG32(ADR_PAD59)) & 0x00000100 ) >> 8)
+#define GET_PAD59_SEL_O (((REG32(ADR_PAD59)) & 0x00001000 ) >> 12)
+#define GET_TEST_17_ID (((REG32(ADR_PAD59)) & 0x10000000 ) >> 28)
+#define GET_PAD60_OE (((REG32(ADR_PAD60)) & 0x00000001 ) >> 0)
+#define GET_PAD60_PE (((REG32(ADR_PAD60)) & 0x00000002 ) >> 1)
+#define GET_PAD60_DS (((REG32(ADR_PAD60)) & 0x00000004 ) >> 2)
+#define GET_PAD60_IE (((REG32(ADR_PAD60)) & 0x00000008 ) >> 3)
+#define GET_PAD60_SEL_I (((REG32(ADR_PAD60)) & 0x00000030 ) >> 4)
+#define GET_PAD60_OD (((REG32(ADR_PAD60)) & 0x00000100 ) >> 8)
+#define GET_PAD60_SEL_O (((REG32(ADR_PAD60)) & 0x00001000 ) >> 12)
+#define GET_TEST_18_ID (((REG32(ADR_PAD60)) & 0x10000000 ) >> 28)
+#define GET_PAD61_OE (((REG32(ADR_PAD61)) & 0x00000001 ) >> 0)
+#define GET_PAD61_PE (((REG32(ADR_PAD61)) & 0x00000002 ) >> 1)
+#define GET_PAD61_DS (((REG32(ADR_PAD61)) & 0x00000004 ) >> 2)
+#define GET_PAD61_IE (((REG32(ADR_PAD61)) & 0x00000008 ) >> 3)
+#define GET_PAD61_SEL_I (((REG32(ADR_PAD61)) & 0x00000010 ) >> 4)
+#define GET_PAD61_OD (((REG32(ADR_PAD61)) & 0x00000100 ) >> 8)
+#define GET_PAD61_SEL_O (((REG32(ADR_PAD61)) & 0x00003000 ) >> 12)
+#define GET_TEST_19_ID (((REG32(ADR_PAD61)) & 0x10000000 ) >> 28)
+#define GET_PAD62_OE (((REG32(ADR_PAD62)) & 0x00000001 ) >> 0)
+#define GET_PAD62_PE (((REG32(ADR_PAD62)) & 0x00000002 ) >> 1)
+#define GET_PAD62_DS (((REG32(ADR_PAD62)) & 0x00000004 ) >> 2)
+#define GET_PAD62_IE (((REG32(ADR_PAD62)) & 0x00000008 ) >> 3)
+#define GET_PAD62_SEL_I (((REG32(ADR_PAD62)) & 0x00000010 ) >> 4)
+#define GET_PAD62_OD (((REG32(ADR_PAD62)) & 0x00000100 ) >> 8)
+#define GET_PAD62_SEL_O (((REG32(ADR_PAD62)) & 0x00001000 ) >> 12)
+#define GET_TEST_20_ID (((REG32(ADR_PAD62)) & 0x10000000 ) >> 28)
+#define GET_PAD64_OE (((REG32(ADR_PAD64)) & 0x00000001 ) >> 0)
+#define GET_PAD64_PE (((REG32(ADR_PAD64)) & 0x00000002 ) >> 1)
+#define GET_PAD64_DS (((REG32(ADR_PAD64)) & 0x00000004 ) >> 2)
+#define GET_PAD64_IE (((REG32(ADR_PAD64)) & 0x00000008 ) >> 3)
+#define GET_PAD64_SEL_I (((REG32(ADR_PAD64)) & 0x00000070 ) >> 4)
+#define GET_PAD64_OD (((REG32(ADR_PAD64)) & 0x00000100 ) >> 8)
+#define GET_PAD64_SEL_O (((REG32(ADR_PAD64)) & 0x00003000 ) >> 12)
+#define GET_PAD64_SEL_OE (((REG32(ADR_PAD64)) & 0x00100000 ) >> 20)
+#define GET_GPIO_15_IP_ID (((REG32(ADR_PAD64)) & 0x10000000 ) >> 28)
+#define GET_PAD65_OE (((REG32(ADR_PAD65)) & 0x00000001 ) >> 0)
+#define GET_PAD65_PE (((REG32(ADR_PAD65)) & 0x00000002 ) >> 1)
+#define GET_PAD65_DS (((REG32(ADR_PAD65)) & 0x00000004 ) >> 2)
+#define GET_PAD65_IE (((REG32(ADR_PAD65)) & 0x00000008 ) >> 3)
+#define GET_PAD65_SEL_I (((REG32(ADR_PAD65)) & 0x00000070 ) >> 4)
+#define GET_PAD65_OD (((REG32(ADR_PAD65)) & 0x00000100 ) >> 8)
+#define GET_PAD65_SEL_O (((REG32(ADR_PAD65)) & 0x00001000 ) >> 12)
+#define GET_GPIO_TEST_7_IN_ID (((REG32(ADR_PAD65)) & 0x10000000 ) >> 28)
+#define GET_PAD66_OE (((REG32(ADR_PAD66)) & 0x00000001 ) >> 0)
+#define GET_PAD66_PE (((REG32(ADR_PAD66)) & 0x00000002 ) >> 1)
+#define GET_PAD66_DS (((REG32(ADR_PAD66)) & 0x00000004 ) >> 2)
+#define GET_PAD66_IE (((REG32(ADR_PAD66)) & 0x00000008 ) >> 3)
+#define GET_PAD66_SEL_I (((REG32(ADR_PAD66)) & 0x00000030 ) >> 4)
+#define GET_PAD66_OD (((REG32(ADR_PAD66)) & 0x00000100 ) >> 8)
+#define GET_PAD66_SEL_O (((REG32(ADR_PAD66)) & 0x00003000 ) >> 12)
+#define GET_GPIO_17_QP_ID (((REG32(ADR_PAD66)) & 0x10000000 ) >> 28)
+#define GET_PAD68_OE (((REG32(ADR_PAD68)) & 0x00000001 ) >> 0)
+#define GET_PAD68_PE (((REG32(ADR_PAD68)) & 0x00000002 ) >> 1)
+#define GET_PAD68_DS (((REG32(ADR_PAD68)) & 0x00000004 ) >> 2)
+#define GET_PAD68_IE (((REG32(ADR_PAD68)) & 0x00000008 ) >> 3)
+#define GET_PAD68_OD (((REG32(ADR_PAD68)) & 0x00000100 ) >> 8)
+#define GET_PAD68_SEL_O (((REG32(ADR_PAD68)) & 0x00001000 ) >> 12)
+#define GET_GPIO_19_ID (((REG32(ADR_PAD68)) & 0x10000000 ) >> 28)
+#define GET_PAD67_OE (((REG32(ADR_PAD67)) & 0x00000001 ) >> 0)
+#define GET_PAD67_PE (((REG32(ADR_PAD67)) & 0x00000002 ) >> 1)
+#define GET_PAD67_DS (((REG32(ADR_PAD67)) & 0x00000004 ) >> 2)
+#define GET_PAD67_IE (((REG32(ADR_PAD67)) & 0x00000008 ) >> 3)
+#define GET_PAD67_SEL_I (((REG32(ADR_PAD67)) & 0x00000070 ) >> 4)
+#define GET_PAD67_OD (((REG32(ADR_PAD67)) & 0x00000100 ) >> 8)
+#define GET_PAD67_SEL_O (((REG32(ADR_PAD67)) & 0x00003000 ) >> 12)
+#define GET_GPIO_TEST_8_QN_ID (((REG32(ADR_PAD67)) & 0x10000000 ) >> 28)
+#define GET_PAD69_OE (((REG32(ADR_PAD69)) & 0x00000001 ) >> 0)
+#define GET_PAD69_PE (((REG32(ADR_PAD69)) & 0x00000002 ) >> 1)
+#define GET_PAD69_DS (((REG32(ADR_PAD69)) & 0x00000004 ) >> 2)
+#define GET_PAD69_IE (((REG32(ADR_PAD69)) & 0x00000008 ) >> 3)
+#define GET_PAD69_SEL_I (((REG32(ADR_PAD69)) & 0x00000030 ) >> 4)
+#define GET_PAD69_OD (((REG32(ADR_PAD69)) & 0x00000100 ) >> 8)
+#define GET_PAD69_SEL_O (((REG32(ADR_PAD69)) & 0x00001000 ) >> 12)
+#define GET_STRAP2 (((REG32(ADR_PAD69)) & 0x08000000 ) >> 27)
+#define GET_GPIO_20_ID (((REG32(ADR_PAD69)) & 0x10000000 ) >> 28)
+#define GET_PAD70_OE (((REG32(ADR_PAD70)) & 0x00000001 ) >> 0)
+#define GET_PAD70_PE (((REG32(ADR_PAD70)) & 0x00000002 ) >> 1)
+#define GET_PAD70_DS (((REG32(ADR_PAD70)) & 0x00000004 ) >> 2)
+#define GET_PAD70_IE (((REG32(ADR_PAD70)) & 0x00000008 ) >> 3)
+#define GET_PAD70_SEL_I (((REG32(ADR_PAD70)) & 0x00000030 ) >> 4)
+#define GET_PAD70_OD (((REG32(ADR_PAD70)) & 0x00000100 ) >> 8)
+#define GET_PAD70_SEL_O (((REG32(ADR_PAD70)) & 0x00007000 ) >> 12)
+#define GET_GPIO_21_ID (((REG32(ADR_PAD70)) & 0x10000000 ) >> 28)
+#define GET_PAD231_OE (((REG32(ADR_PAD231)) & 0x00000001 ) >> 0)
+#define GET_PAD231_PE (((REG32(ADR_PAD231)) & 0x00000002 ) >> 1)
+#define GET_PAD231_DS (((REG32(ADR_PAD231)) & 0x00000004 ) >> 2)
+#define GET_PAD231_IE (((REG32(ADR_PAD231)) & 0x00000008 ) >> 3)
+#define GET_PAD231_OD (((REG32(ADR_PAD231)) & 0x00000100 ) >> 8)
+#define GET_PIN_40_OR_56_ID (((REG32(ADR_PAD231)) & 0x10000000 ) >> 28)
+#define GET_MP_PHY2RX_DATA__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000001 ) >> 0)
+#define GET_MP_PHY2RX_DATA__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000002 ) >> 1)
+#define GET_MP_TX_FF_RPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000004 ) >> 2)
+#define GET_MP_RX_FF_WPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000008 ) >> 3)
+#define GET_MP_RX_FF_WPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000010 ) >> 4)
+#define GET_MP_RX_FF_WPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000020 ) >> 5)
+#define GET_MP_PHY2RX_DATA__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000040 ) >> 6)
+#define GET_MP_PHY2RX_DATA__4_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000080 ) >> 7)
+#define GET_I2CM_SDA_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000300 ) >> 8)
+#define GET_CRYSTAL_OUT_REQ_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000400 ) >> 10)
+#define GET_MP_PHY2RX_DATA__5_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000800 ) >> 11)
+#define GET_MP_PHY2RX_DATA__3_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00001000 ) >> 12)
+#define GET_UART_RXD_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00006000 ) >> 13)
+#define GET_MP_PHY2RX_DATA__6_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00008000 ) >> 15)
+#define GET_DAT_UART_NCTS_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00010000 ) >> 16)
+#define GET_GPIO_LOG_STOP_SEL (((REG32(ADR_PIN_SEL_0)) & 0x000e0000 ) >> 17)
+#define GET_MP_TX_FF_RPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00100000 ) >> 20)
+#define GET_MP_PHY_RX_WRST_N_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00200000 ) >> 21)
+#define GET_EXT_32K_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00c00000 ) >> 22)
+#define GET_MP_PHY2RX_DATA__7_SEL (((REG32(ADR_PIN_SEL_0)) & 0x01000000 ) >> 24)
+#define GET_MP_TX_FF_RPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x02000000 ) >> 25)
+#define GET_PMUINT_WAKE_SEL (((REG32(ADR_PIN_SEL_0)) & 0x1c000000 ) >> 26)
+#define GET_I2CM_SCL_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x20000000 ) >> 29)
+#define GET_MP_MRX_RX_EN_SEL (((REG32(ADR_PIN_SEL_0)) & 0x40000000 ) >> 30)
+#define GET_DAT_UART_RXD_SEL_0 (((REG32(ADR_PIN_SEL_0)) & 0x80000000 ) >> 31)
+#define GET_DAT_UART_RXD_SEL_1 (((REG32(ADR_PIN_SEL_1)) & 0x00000001 ) >> 0)
+#define GET_SPI_DI_SEL (((REG32(ADR_PIN_SEL_1)) & 0x00000002 ) >> 1)
+#define GET_IO_PORT_REG (((REG32(ADR_IO_PORT_REG)) & 0x0001ffff ) >> 0)
+#define GET_MASK_RX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000001 ) >> 0)
+#define GET_MASK_TX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000002 ) >> 1)
+#define GET_MASK_SOC_SYSTEM_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000080 ) >> 7)
+#define GET_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000001 ) >> 0)
+#define GET_TX_COMPLETE_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000002 ) >> 1)
+#define GET_SOC_SYSTEM_INT_STATUS (((REG32(ADR_INT_STATUS_REG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000080 ) >> 7)
+#define GET_HOST_TRIGGERED_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000100 ) >> 8)
+#define GET_HOST_TRIGGERED_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000200 ) >> 9)
+#define GET_SOC_TRIGGER_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000400 ) >> 10)
+#define GET_SOC_TRIGGER_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000800 ) >> 11)
+#define GET_RDY_FOR_TX_RX (((REG32(ADR_FN1_STATUS_REG)) & 0x00000001 ) >> 0)
+#define GET_RDY_FOR_FW_DOWNLOAD (((REG32(ADR_FN1_STATUS_REG)) & 0x00000002 ) >> 1)
+#define GET_ILLEGAL_CMD_RESP_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000004 ) >> 2)
+#define GET_SDIO_TRX_DATA_SEQUENCE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000008 ) >> 3)
+#define GET_GPIO_INT_TRIGGER_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000010 ) >> 4)
+#define GET_TRIGGER_FUNCTION_SETTING (((REG32(ADR_FN1_STATUS_REG)) & 0x00000060 ) >> 5)
+#define GET_CMD52_ABORT_RESPONSE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000080 ) >> 7)
+#define GET_RX_PACKET_LENGTH (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x0000ffff ) >> 0)
+#define GET_CARD_FW_DL_STATUS (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x00ff0000 ) >> 16)
+#define GET_TX_RX_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x01000000 ) >> 24)
+#define GET_SDIO_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x02000000 ) >> 25)
+#define GET_CMD52_ABORT_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x10000000 ) >> 28)
+#define GET_CMD52_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x20000000 ) >> 29)
+#define GET_SDIO_PARTIAL_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x40000000 ) >> 30)
+#define GET_SDIO_ALL_RESE_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x80000000 ) >> 31)
+#define GET_RX_PACKET_LENGTH2 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x0000ffff ) >> 0)
+#define GET_RX_INT1 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00010000 ) >> 16)
+#define GET_TX_DONE (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00020000 ) >> 17)
+#define GET_HCI_TRX_FINISH (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00040000 ) >> 18)
+#define GET_ALLOCATE_STATUS (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00080000 ) >> 19)
+#define GET_HCI_INPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00f00000 ) >> 20)
+#define GET_HCI_OUTPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x1f000000 ) >> 24)
+#define GET_AHB_HANG4 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x20000000 ) >> 29)
+#define GET_HCI_IN_QUE_EMPTY (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x40000000 ) >> 30)
+#define GET_SYSTEM_INT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x80000000 ) >> 31)
+#define GET_CARD_RCA_REG (((REG32(ADR_CARD_RCA_REG)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_FIFO_WR_THLD_REG (((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_FIFO_WR_LIMIT_REG (((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_TX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_THLD_FOR_CMD53RD_REG (((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_RX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
+#define GET_START_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x000000ff ) >> 0)
+#define GET_END_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x0000ff00 ) >> 8)
+#define GET_SDIO_BYTE_MODE_BATCH_SIZE_REG (((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0x000000ff ) >> 0)
+#define GET_SDIO_LAST_CMD_INDEX_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x0000003f ) >> 0)
+#define GET_SDIO_LAST_CMD_CRC_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x00007f00 ) >> 8)
+#define GET_SDIO_LAST_CMD_ARG_REG (((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0xffffffff ) >> 0)
+#define GET_SDIO_BUS_STATE_REG (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000001f ) >> 0)
+#define GET_SDIO_BUSY_LONG_CNT (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_CARD_STATUS_REG (((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0xffffffff ) >> 0)
+#define GET_R5_RESPONSE_FLAG (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x000000ff ) >> 0)
+#define GET_RESP_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000100 ) >> 8)
+#define GET_DAT_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000200 ) >> 9)
+#define GET_MCU_TO_SDIO_INFO_MASK (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00010000 ) >> 16)
+#define GET_INT_THROUGH_PIN (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00020000 ) >> 17)
+#define GET_WRITE_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x000000ff ) >> 0)
+#define GET_WRITE_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x0000ff00 ) >> 8)
+#define GET_READ_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ff0000 ) >> 16)
+#define GET_READ_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff000000 ) >> 24)
+#define GET_FN1_DMA_START_ADDR_REG (((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0xffffffff ) >> 0)
+#define GET_SDIO_TO_MCU_INFO (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x000000ff ) >> 0)
+#define GET_SDIO_PARTIAL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000100 ) >> 8)
+#define GET_SDIO_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000200 ) >> 9)
+#define GET_PERI_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000400 ) >> 10)
+#define GET_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000800 ) >> 11)
+#define GET_AHB_BRIDGE_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00001000 ) >> 12)
+#define GET_IO_REG_PORT_REG (((REG32(ADR_IO_REG_PORT_REG)) & 0x0001ffff ) >> 0)
+#define GET_SDIO_FIFO_EMPTY_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_FIFO_FULL_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_CRC7_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_CRC16_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_RD_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x000001ff ) >> 0)
+#define GET_SDIO_WR_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x01ff0000 ) >> 16)
+#define GET_CMD52_RD_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x000f0000 ) >> 16)
+#define GET_CMD52_WR_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x00f00000 ) >> 20)
+#define GET_SDIO_FIFO_WR_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x000000ff ) >> 0)
+#define GET_SDIO_FIFO_RD_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x0000ff00 ) >> 8)
+#define GET_SDIO_READ_DATA_CTRL (((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0x00010000 ) >> 16)
+#define GET_TX_SIZE_BEFORE_SHIFT (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x000000ff ) >> 0)
+#define GET_TX_SIZE_SHIFT_BITS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00000700 ) >> 8)
+#define GET_SDIO_TX_ALLOC_STATE (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00001000 ) >> 12)
+#define GET_ALLOCATE_STATUS2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00010000 ) >> 16)
+#define GET_NO_ALLOCATE_SEND_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00020000 ) >> 17)
+#define GET_DOUBLE_ALLOCATE_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00040000 ) >> 18)
+#define GET_TX_DONE_STATUS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00080000 ) >> 19)
+#define GET_AHB_HANG2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00100000 ) >> 20)
+#define GET_HCI_TRX_FINISH2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00200000 ) >> 21)
+#define GET_INTR_RX (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00400000 ) >> 22)
+#define GET_HCI_INPUT_QUEUE_FULL (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00800000 ) >> 23)
+#define GET_ALLOCATESTATUS (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000001 ) >> 0)
+#define GET_HCI_TRX_FINISH3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000002 ) >> 1)
+#define GET_HCI_IN_QUE_EMPTY2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000004 ) >> 2)
+#define GET_MTX_MNG_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000008 ) >> 3)
+#define GET_EDCA0_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000010 ) >> 4)
+#define GET_EDCA1_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000020 ) >> 5)
+#define GET_EDCA2_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000040 ) >> 6)
+#define GET_EDCA3_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000080 ) >> 7)
+#define GET_TX_PAGE_REMAIN2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0000ff00 ) >> 8)
+#define GET_TX_ID_REMAIN3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x007f0000 ) >> 16)
+#define GET_HCI_OUTPUT_FF_CNT_0 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00800000 ) >> 23)
+#define GET_HCI_OUTPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0f000000 ) >> 24)
+#define GET_HCI_INPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0xf0000000 ) >> 28)
+#define GET_F1_BLOCK_SIZE_0_REG (((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0x00000fff ) >> 0)
+#define GET_START_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x000000ff ) >> 0)
+#define GET_COMMAND_COUNTER (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ff00 ) >> 8)
+#define GET_CMD_LOG_PART1 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff0000 ) >> 16)
+#define GET_CMD_LOG_PART2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff ) >> 0)
+#define GET_END_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000 ) >> 24)
+#define GET_RX_PACKET_LENGTH3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x0000ffff ) >> 0)
+#define GET_RX_INT3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_TX_ID_REMAIN2 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00fe0000 ) >> 17)
+#define GET_TX_PAGE_REMAIN3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff000000 ) >> 24)
+#define GET_CCCR_00H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x000000ff ) >> 0)
+#define GET_CCCR_02H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x00ff0000 ) >> 16)
+#define GET_CCCR_03H_REG (((REG32(ADR_CCCR_00H_REG)) & 0xff000000 ) >> 24)
+#define GET_CCCR_04H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000000ff ) >> 0)
+#define GET_CCCR_05H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x0000ff00 ) >> 8)
+#define GET_CCCR_06H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000f0000 ) >> 16)
+#define GET_CCCR_07H_REG (((REG32(ADR_CCCR_04H_REG)) & 0xff000000 ) >> 24)
+#define GET_SUPPORT_DIRECT_COMMAND_SDIO (((REG32(ADR_CCCR_08H_REG)) & 0x00000001 ) >> 0)
+#define GET_SUPPORT_MULTIPLE_BLOCK_TRANSFER (((REG32(ADR_CCCR_08H_REG)) & 0x00000002 ) >> 1)
+#define GET_SUPPORT_READ_WAIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000004 ) >> 2)
+#define GET_SUPPORT_BUS_CONTROL (((REG32(ADR_CCCR_08H_REG)) & 0x00000008 ) >> 3)
+#define GET_SUPPORT_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000010 ) >> 4)
+#define GET_ENABLE_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000020 ) >> 5)
+#define GET_LOW_SPEED_CARD (((REG32(ADR_CCCR_08H_REG)) & 0x00000040 ) >> 6)
+#define GET_LOW_SPEED_CARD_4BIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000080 ) >> 7)
+#define GET_COMMON_CIS_PONTER (((REG32(ADR_CCCR_08H_REG)) & 0x01ffff00 ) >> 8)
+#define GET_SUPPORT_HIGH_SPEED (((REG32(ADR_CCCR_13H_REG)) & 0x01000000 ) >> 24)
+#define GET_BSS (((REG32(ADR_CCCR_13H_REG)) & 0x0e000000 ) >> 25)
+#define GET_FBR_100H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000000f ) >> 0)
+#define GET_CSASUPPORT (((REG32(ADR_FBR_100H_REG)) & 0x00000040 ) >> 6)
+#define GET_ENABLECSA (((REG32(ADR_FBR_100H_REG)) & 0x00000080 ) >> 7)
+#define GET_FBR_101H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000ff00 ) >> 8)
+#define GET_FBR_109H_REG (((REG32(ADR_FBR_109H_REG)) & 0x01ffff00 ) >> 8)
+#define GET_F0_CIS_CONTENT_REG_31_0 (((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_63_32 (((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_95_64 (((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_127_96 (((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_159_128 (((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_191_160 (((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_223_192 (((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_255_224 (((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_287_256 (((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_319_288 (((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_351_320 (((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_383_352 (((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_415_384 (((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_447_416 (((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_479_448 (((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_511_480 (((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_31_0 (((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_63_32 (((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_95_64 (((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_127_96 (((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_159_128 (((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_191_160 (((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_223_192 (((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_255_224 (((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_287_256 (((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_319_288 (((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_351_320 (((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_383_352 (((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_415_384 (((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_447_416 (((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_479_448 (((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_511_480 (((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
+#define GET_SPI_MODE (((REG32(ADR_SPI_MODE)) & 0xffffffff ) >> 0)
+#define GET_RX_QUOTA (((REG32(ADR_RX_QUOTA)) & 0x0000ffff ) >> 0)
+#define GET_CONDI_NUM (((REG32(ADR_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
+#define GET_HOST_PATH (((REG32(ADR_HOST_PATH)) & 0x00000001 ) >> 0)
+#define GET_TX_SEG (((REG32(ADR_TX_SEG)) & 0xffffffff ) >> 0)
+#define GET_BRST_MODE (((REG32(ADR_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
+#define GET_CLK_WIDTH (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
+#define GET_CSN_INTER (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
+#define GET_BACK_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_FRONT_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
+#define GET_RX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000002 ) >> 1)
+#define GET_RX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000004 ) >> 2)
+#define GET_TX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000008 ) >> 3)
+#define GET_TX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000010 ) >> 4)
+#define GET_SPI_DOUBLE_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000020 ) >> 5)
+#define GET_SPI_TX_NO_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000040 ) >> 6)
+#define GET_RDATA_RDY (((REG32(ADR_SPI_STS)) & 0x00000080 ) >> 7)
+#define GET_SPI_ALLOC_STATUS (((REG32(ADR_SPI_STS)) & 0x00000100 ) >> 8)
+#define GET_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_SPI_STS)) & 0x00000200 ) >> 9)
+#define GET_RX_LEN (((REG32(ADR_SPI_STS)) & 0xffff0000 ) >> 16)
+#define GET_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
+#define GET_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
+#define GET_SPI_TX_ALLOC_SIZE (((REG32(ADR_TX_ALLOC)) & 0x000000ff ) >> 0)
+#define GET_RD_DAT_CNT (((REG32(ADR_DBG_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RD_STS_CNT (((REG32(ADR_DBG_CNT)) & 0xffff0000 ) >> 16)
+#define GET_JUDGE_CNT (((REG32(ADR_DBG_CNT2)) & 0x0000ffff ) >> 0)
+#define GET_RD_STS_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00010000 ) >> 16)
+#define GET_RD_DAT_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00020000 ) >> 17)
+#define GET_JUDGE_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00040000 ) >> 18)
+#define GET_TX_DONE_CNT (((REG32(ADR_DBG_CNT3)) & 0x0000ffff ) >> 0)
+#define GET_TX_DISCARD_CNT (((REG32(ADR_DBG_CNT3)) & 0xffff0000 ) >> 16)
+#define GET_TX_SET_CNT (((REG32(ADR_DBG_CNT4)) & 0x0000ffff ) >> 0)
+#define GET_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00010000 ) >> 16)
+#define GET_TX_DONE_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00020000 ) >> 17)
+#define GET_TX_SET_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00040000 ) >> 18)
+#define GET_DAT_MODE_OFF (((REG32(ADR_DBG_CNT4)) & 0x00080000 ) >> 19)
+#define GET_TX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x00700000 ) >> 20)
+#define GET_RX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x07000000 ) >> 24)
+#define GET_RX_RDY (((REG32(ADR_INT_TAG)) & 0x00000001 ) >> 0)
+#define GET_SDIO_SYS_INT (((REG32(ADR_INT_TAG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_IN (((REG32(ADR_INT_TAG)) & 0x00000080 ) >> 7)
+#define GET_SPI_FN1 (((REG32(ADR_INT_TAG)) & 0x00007f00 ) >> 8)
+#define GET_SPI_CLK_EN_INT (((REG32(ADR_INT_TAG)) & 0x00008000 ) >> 15)
+#define GET_SPI_HOST_MASK (((REG32(ADR_INT_TAG)) & 0x00ff0000 ) >> 16)
+#define GET_I2CM_INT_WDONE (((REG32(ADR_I2CM_EN)) & 0x00000001 ) >> 0)
+#define GET_I2CM_INT_RDONE (((REG32(ADR_I2CM_EN)) & 0x00000002 ) >> 1)
+#define GET_I2CM_IDLE (((REG32(ADR_I2CM_EN)) & 0x00000004 ) >> 2)
+#define GET_I2CM_INT_MISMATCH (((REG32(ADR_I2CM_EN)) & 0x00000008 ) >> 3)
+#define GET_I2CM_PSCL (((REG32(ADR_I2CM_EN)) & 0x00003ff0 ) >> 4)
+#define GET_I2CM_MANUAL_MODE (((REG32(ADR_I2CM_EN)) & 0x00010000 ) >> 16)
+#define GET_I2CM_INT_WDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00020000 ) >> 17)
+#define GET_I2CM_INT_RDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00040000 ) >> 18)
+#define GET_I2CM_DEV_A (((REG32(ADR_I2CM_DEV_A)) & 0x000003ff ) >> 0)
+#define GET_I2CM_DEV_A10B (((REG32(ADR_I2CM_DEV_A)) & 0x00004000 ) >> 14)
+#define GET_I2CM_RX (((REG32(ADR_I2CM_DEV_A)) & 0x00008000 ) >> 15)
+#define GET_I2CM_LEN (((REG32(ADR_I2CM_LEN)) & 0x0000ffff ) >> 0)
+#define GET_I2CM_T_LEFT (((REG32(ADR_I2CM_LEN)) & 0x00070000 ) >> 16)
+#define GET_I2CM_R_GET (((REG32(ADR_I2CM_LEN)) & 0x07000000 ) >> 24)
+#define GET_I2CM_WDAT (((REG32(ADR_I2CM_WDAT)) & 0xffffffff ) >> 0)
+#define GET_I2CM_RDAT (((REG32(ADR_I2CM_RDAT)) & 0xffffffff ) >> 0)
+#define GET_I2CM_SR_LEN (((REG32(ADR_I2CM_EN_2)) & 0x0000ffff ) >> 0)
+#define GET_I2CM_SR_RX (((REG32(ADR_I2CM_EN_2)) & 0x00010000 ) >> 16)
+#define GET_I2CM_REPEAT_START (((REG32(ADR_I2CM_EN_2)) & 0x00020000 ) >> 17)
+#define GET_UART_DATA (((REG32(ADR_UART_DATA)) & 0x000000ff ) >> 0)
+#define GET_DATA_RDY_IE (((REG32(ADR_UART_IER)) & 0x00000001 ) >> 0)
+#define GET_THR_EMPTY_IE (((REG32(ADR_UART_IER)) & 0x00000002 ) >> 1)
+#define GET_RX_LINESTS_IE (((REG32(ADR_UART_IER)) & 0x00000004 ) >> 2)
+#define GET_MDM_STS_IE (((REG32(ADR_UART_IER)) & 0x00000008 ) >> 3)
+#define GET_DMA_RXEND_IE (((REG32(ADR_UART_IER)) & 0x00000040 ) >> 6)
+#define GET_DMA_TXEND_IE (((REG32(ADR_UART_IER)) & 0x00000080 ) >> 7)
+#define GET_FIFO_EN (((REG32(ADR_UART_FCR)) & 0x00000001 ) >> 0)
+#define GET_RXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000002 ) >> 1)
+#define GET_TXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000004 ) >> 2)
+#define GET_DMA_MODE (((REG32(ADR_UART_FCR)) & 0x00000008 ) >> 3)
+#define GET_EN_AUTO_RTS (((REG32(ADR_UART_FCR)) & 0x00000010 ) >> 4)
+#define GET_EN_AUTO_CTS (((REG32(ADR_UART_FCR)) & 0x00000020 ) >> 5)
+#define GET_RXFIFO_TRGLVL (((REG32(ADR_UART_FCR)) & 0x000000c0 ) >> 6)
+#define GET_WORD_LEN (((REG32(ADR_UART_LCR)) & 0x00000003 ) >> 0)
+#define GET_STOP_BIT (((REG32(ADR_UART_LCR)) & 0x00000004 ) >> 2)
+#define GET_PARITY_EN (((REG32(ADR_UART_LCR)) & 0x00000008 ) >> 3)
+#define GET_EVEN_PARITY (((REG32(ADR_UART_LCR)) & 0x00000010 ) >> 4)
+#define GET_FORCE_PARITY (((REG32(ADR_UART_LCR)) & 0x00000020 ) >> 5)
+#define GET_SET_BREAK (((REG32(ADR_UART_LCR)) & 0x00000040 ) >> 6)
+#define GET_DLAB (((REG32(ADR_UART_LCR)) & 0x00000080 ) >> 7)
+#define GET_DTR (((REG32(ADR_UART_MCR)) & 0x00000001 ) >> 0)
+#define GET_RTS (((REG32(ADR_UART_MCR)) & 0x00000002 ) >> 1)
+#define GET_OUT_1 (((REG32(ADR_UART_MCR)) & 0x00000004 ) >> 2)
+#define GET_OUT_2 (((REG32(ADR_UART_MCR)) & 0x00000008 ) >> 3)
+#define GET_LOOP_BACK (((REG32(ADR_UART_MCR)) & 0x00000010 ) >> 4)
+#define GET_DATA_RDY (((REG32(ADR_UART_LSR)) & 0x00000001 ) >> 0)
+#define GET_OVERRUN_ERR (((REG32(ADR_UART_LSR)) & 0x00000002 ) >> 1)
+#define GET_PARITY_ERR (((REG32(ADR_UART_LSR)) & 0x00000004 ) >> 2)
+#define GET_FRAMING_ERR (((REG32(ADR_UART_LSR)) & 0x00000008 ) >> 3)
+#define GET_BREAK_INT (((REG32(ADR_UART_LSR)) & 0x00000010 ) >> 4)
+#define GET_THR_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000020 ) >> 5)
+#define GET_TX_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000040 ) >> 6)
+#define GET_FIFODATA_ERR (((REG32(ADR_UART_LSR)) & 0x00000080 ) >> 7)
+#define GET_DELTA_CTS (((REG32(ADR_UART_MSR)) & 0x00000001 ) >> 0)
+#define GET_DELTA_DSR (((REG32(ADR_UART_MSR)) & 0x00000002 ) >> 1)
+#define GET_TRAILEDGE_RI (((REG32(ADR_UART_MSR)) & 0x00000004 ) >> 2)
+#define GET_DELTA_CD (((REG32(ADR_UART_MSR)) & 0x00000008 ) >> 3)
+#define GET_CTS (((REG32(ADR_UART_MSR)) & 0x00000010 ) >> 4)
+#define GET_DSR (((REG32(ADR_UART_MSR)) & 0x00000020 ) >> 5)
+#define GET_RI (((REG32(ADR_UART_MSR)) & 0x00000040 ) >> 6)
+#define GET_CD (((REG32(ADR_UART_MSR)) & 0x00000080 ) >> 7)
+#define GET_BRDC_DIV (((REG32(ADR_UART_SPR)) & 0x0000ffff ) >> 0)
+#define GET_RTHR_L (((REG32(ADR_UART_RTHR)) & 0x0000000f ) >> 0)
+#define GET_RTHR_H (((REG32(ADR_UART_RTHR)) & 0x000000f0 ) >> 4)
+#define GET_INT_IDCODE (((REG32(ADR_UART_ISR)) & 0x0000000f ) >> 0)
+#define GET_FIFOS_ENABLED (((REG32(ADR_UART_ISR)) & 0x000000c0 ) >> 6)
+#define GET_DAT_UART_DATA (((REG32(ADR_DAT_UART_DATA)) & 0x000000ff ) >> 0)
+#define GET_DAT_DATA_RDY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000001 ) >> 0)
+#define GET_DAT_THR_EMPTY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000002 ) >> 1)
+#define GET_DAT_RX_LINESTS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000004 ) >> 2)
+#define GET_DAT_MDM_STS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000008 ) >> 3)
+#define GET_DAT_DMA_RXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000040 ) >> 6)
+#define GET_DAT_DMA_TXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000080 ) >> 7)
+#define GET_DAT_FIFO_EN (((REG32(ADR_DAT_UART_FCR)) & 0x00000001 ) >> 0)
+#define GET_DAT_RXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000002 ) >> 1)
+#define GET_DAT_TXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_DMA_MODE (((REG32(ADR_DAT_UART_FCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_EN_AUTO_RTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_EN_AUTO_CTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000020 ) >> 5)
+#define GET_DAT_RXFIFO_TRGLVL (((REG32(ADR_DAT_UART_FCR)) & 0x000000c0 ) >> 6)
+#define GET_DAT_WORD_LEN (((REG32(ADR_DAT_UART_LCR)) & 0x00000003 ) >> 0)
+#define GET_DAT_STOP_BIT (((REG32(ADR_DAT_UART_LCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_PARITY_EN (((REG32(ADR_DAT_UART_LCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_EVEN_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_FORCE_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000020 ) >> 5)
+#define GET_DAT_SET_BREAK (((REG32(ADR_DAT_UART_LCR)) & 0x00000040 ) >> 6)
+#define GET_DAT_DLAB (((REG32(ADR_DAT_UART_LCR)) & 0x00000080 ) >> 7)
+#define GET_DAT_DTR (((REG32(ADR_DAT_UART_MCR)) & 0x00000001 ) >> 0)
+#define GET_DAT_RTS (((REG32(ADR_DAT_UART_MCR)) & 0x00000002 ) >> 1)
+#define GET_DAT_OUT_1 (((REG32(ADR_DAT_UART_MCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_OUT_2 (((REG32(ADR_DAT_UART_MCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_LOOP_BACK (((REG32(ADR_DAT_UART_MCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_DATA_RDY (((REG32(ADR_DAT_UART_LSR)) & 0x00000001 ) >> 0)
+#define GET_DAT_OVERRUN_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000002 ) >> 1)
+#define GET_DAT_PARITY_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000004 ) >> 2)
+#define GET_DAT_FRAMING_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000008 ) >> 3)
+#define GET_DAT_BREAK_INT (((REG32(ADR_DAT_UART_LSR)) & 0x00000010 ) >> 4)
+#define GET_DAT_THR_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000020 ) >> 5)
+#define GET_DAT_TX_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000040 ) >> 6)
+#define GET_DAT_FIFODATA_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000080 ) >> 7)
+#define GET_DAT_DELTA_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000001 ) >> 0)
+#define GET_DAT_DELTA_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000002 ) >> 1)
+#define GET_DAT_TRAILEDGE_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000004 ) >> 2)
+#define GET_DAT_DELTA_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000008 ) >> 3)
+#define GET_DAT_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000010 ) >> 4)
+#define GET_DAT_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000020 ) >> 5)
+#define GET_DAT_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000040 ) >> 6)
+#define GET_DAT_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000080 ) >> 7)
+#define GET_DAT_BRDC_DIV (((REG32(ADR_DAT_UART_SPR)) & 0x0000ffff ) >> 0)
+#define GET_DAT_RTHR_L (((REG32(ADR_DAT_UART_RTHR)) & 0x0000000f ) >> 0)
+#define GET_DAT_RTHR_H (((REG32(ADR_DAT_UART_RTHR)) & 0x000000f0 ) >> 4)
+#define GET_DAT_INT_IDCODE (((REG32(ADR_DAT_UART_ISR)) & 0x0000000f ) >> 0)
+#define GET_DAT_FIFOS_ENABLED (((REG32(ADR_DAT_UART_ISR)) & 0x000000c0 ) >> 6)
+#define GET_MASK_TOP (((REG32(ADR_INT_MASK)) & 0xffffffff ) >> 0)
+#define GET_INT_MODE (((REG32(ADR_INT_MODE)) & 0xffffffff ) >> 0)
+#define GET_IRQ_PHY_0 (((REG32(ADR_INT_IRQ_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_PHY_1 (((REG32(ADR_INT_IRQ_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_SDIO (((REG32(ADR_INT_IRQ_STS)) & 0x00000004 ) >> 2)
+#define GET_IRQ_BEACON_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000010 ) >> 4)
+#define GET_IRQ_PRE_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000020 ) >> 5)
+#define GET_IRQ_EDCA0_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000040 ) >> 6)
+#define GET_IRQ_EDCA1_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000080 ) >> 7)
+#define GET_IRQ_EDCA2_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000100 ) >> 8)
+#define GET_IRQ_EDCA3_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000200 ) >> 9)
+#define GET_IRQ_EDCA4_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000400 ) >> 10)
+#define GET_IRQ_BEACON_DTIM (((REG32(ADR_INT_IRQ_STS)) & 0x00001000 ) >> 12)
+#define GET_IRQ_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00002000 ) >> 13)
+#define GET_IRQ_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00004000 ) >> 14)
+#define GET_IRQ_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00008000 ) >> 15)
+#define GET_IRQ_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00010000 ) >> 16)
+#define GET_IRQ_FENCE_HIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00020000 ) >> 17)
+#define GET_IRQ_ILL_ADDR_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00040000 ) >> 18)
+#define GET_IRQ_MBOX (((REG32(ADR_INT_IRQ_STS)) & 0x00080000 ) >> 19)
+#define GET_IRQ_US_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x00100000 ) >> 20)
+#define GET_IRQ_US_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x00200000 ) >> 21)
+#define GET_IRQ_US_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x00400000 ) >> 22)
+#define GET_IRQ_US_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x00800000 ) >> 23)
+#define GET_IRQ_MS_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x01000000 ) >> 24)
+#define GET_IRQ_MS_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_MS_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_MS_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x08000000 ) >> 27)
+#define GET_IRQ_TX_LIMIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x10000000 ) >> 28)
+#define GET_IRQ_DMA0 (((REG32(ADR_INT_IRQ_STS)) & 0x20000000 ) >> 29)
+#define GET_IRQ_CO_DMA (((REG32(ADR_INT_IRQ_STS)) & 0x40000000 ) >> 30)
+#define GET_IRQ_PERI_GROUP (((REG32(ADR_INT_IRQ_STS)) & 0x80000000 ) >> 31)
+#define GET_FIQ_STATUS (((REG32(ADR_INT_FIQ_STS)) & 0xffffffff ) >> 0)
+#define GET_IRQ_RAW (((REG32(ADR_INT_IRQ_RAW)) & 0xffffffff ) >> 0)
+#define GET_FIQ_RAW (((REG32(ADR_INT_FIQ_RAW)) & 0xffffffff ) >> 0)
+#define GET_INT_PERI_MASK (((REG32(ADR_INT_PERI_MASK)) & 0xffffffff ) >> 0)
+#define GET_PERI_RTC (((REG32(ADR_INT_PERI_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_UART0_TX (((REG32(ADR_INT_PERI_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_UART0_RX (((REG32(ADR_INT_PERI_STS)) & 0x00000004 ) >> 2)
+#define GET_PERI_GPI_2 (((REG32(ADR_INT_PERI_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_SPI_IPC (((REG32(ADR_INT_PERI_STS)) & 0x00000010 ) >> 4)
+#define GET_PERI_GPI_1_0 (((REG32(ADR_INT_PERI_STS)) & 0x00000060 ) >> 5)
+#define GET_SCRT_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000080 ) >> 7)
+#define GET_MMU_ALC_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000100 ) >> 8)
+#define GET_MMU_RLS_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000400 ) >> 10)
+#define GET_MBOX_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000800 ) >> 11)
+#define GET_MBOX_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00001000 ) >> 12)
+#define GET_MBOX_INT_3 (((REG32(ADR_INT_PERI_STS)) & 0x00002000 ) >> 13)
+#define GET_HCI_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00004000 ) >> 14)
+#define GET_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x00008000 ) >> 15)
+#define GET_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x00010000 ) >> 16)
+#define GET_ID_MNG_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00020000 ) >> 17)
+#define GET_DMN_NOHIT_INT (((REG32(ADR_INT_PERI_STS)) & 0x00040000 ) >> 18)
+#define GET_ID_THOLD_RX (((REG32(ADR_INT_PERI_STS)) & 0x00080000 ) >> 19)
+#define GET_ID_THOLD_TX (((REG32(ADR_INT_PERI_STS)) & 0x00100000 ) >> 20)
+#define GET_ID_DOUBLE_RLS (((REG32(ADR_INT_PERI_STS)) & 0x00200000 ) >> 21)
+#define GET_RX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00400000 ) >> 22)
+#define GET_TX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00800000 ) >> 23)
+#define GET_ALL_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x01000000 ) >> 24)
+#define GET_DMN_MCU_INT (((REG32(ADR_INT_PERI_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_DAT_UART_TX (((REG32(ADR_INT_PERI_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_DAT_UART_RX (((REG32(ADR_INT_PERI_STS)) & 0x08000000 ) >> 27)
+#define GET_DAT_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x10000000 ) >> 28)
+#define GET_DAT_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x20000000 ) >> 29)
+#define GET_ALR_ABT_NOCHG_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x40000000 ) >> 30)
+#define GET_TBLNEQ_MNGPKT_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x80000000 ) >> 31)
+#define GET_INTR_PERI_RAW (((REG32(ADR_INT_PERI_RAW)) & 0xffffffff ) >> 0)
+#define GET_INTR_GPI00_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x00000003 ) >> 0)
+#define GET_INTR_GPI01_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x0000000c ) >> 2)
+#define GET_SYS_RST_INT (((REG32(ADR_SYS_INT_FOR_HOST)) & 0x00000001 ) >> 0)
+#define GET_SPI_IPC_ADDR (((REG32(ADR_SPI_IPC)) & 0xffffffff ) >> 0)
+#define GET_SD_MASK_TOP (((REG32(ADR_SDIO_MASK)) & 0xffffffff ) >> 0)
+#define GET_IRQ_PHY_0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_PHY_1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_SDIO_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000004 ) >> 2)
+#define GET_IRQ_BEACON_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000010 ) >> 4)
+#define GET_IRQ_PRE_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000020 ) >> 5)
+#define GET_IRQ_EDCA0_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000040 ) >> 6)
+#define GET_IRQ_EDCA1_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000080 ) >> 7)
+#define GET_IRQ_EDCA2_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000100 ) >> 8)
+#define GET_IRQ_EDCA3_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000200 ) >> 9)
+#define GET_IRQ_EDCA4_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000400 ) >> 10)
+#define GET_IRQ_BEACON_DTIM_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00001000 ) >> 12)
+#define GET_IRQ_EDCA0_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00002000 ) >> 13)
+#define GET_IRQ_EDCA1_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00004000 ) >> 14)
+#define GET_IRQ_EDCA2_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00008000 ) >> 15)
+#define GET_IRQ_EDCA3_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00010000 ) >> 16)
+#define GET_IRQ_FENCE_HIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00020000 ) >> 17)
+#define GET_IRQ_ILL_ADDR_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00040000 ) >> 18)
+#define GET_IRQ_MBOX_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00080000 ) >> 19)
+#define GET_IRQ_US_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00100000 ) >> 20)
+#define GET_IRQ_US_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00200000 ) >> 21)
+#define GET_IRQ_US_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00400000 ) >> 22)
+#define GET_IRQ_US_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00800000 ) >> 23)
+#define GET_IRQ_MS_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x01000000 ) >> 24)
+#define GET_IRQ_MS_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_MS_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_MS_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x08000000 ) >> 27)
+#define GET_IRQ_TX_LIMIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x10000000 ) >> 28)
+#define GET_IRQ_DMA0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x20000000 ) >> 29)
+#define GET_IRQ_CO_DMA_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x40000000 ) >> 30)
+#define GET_IRQ_PERI_GROUP_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x80000000 ) >> 31)
+#define GET_INT_PERI_MASK_SD (((REG32(ADR_SD_PERI_MASK)) & 0xffffffff ) >> 0)
+#define GET_PERI_RTC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_UART0_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_UART0_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000004 ) >> 2)
+#define GET_PERI_GPI_SD_2 (((REG32(ADR_SD_PERI_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_SPI_IPC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000010 ) >> 4)
+#define GET_PERI_GPI_SD_1_0 (((REG32(ADR_SD_PERI_STS)) & 0x00000060 ) >> 5)
+#define GET_SCRT_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000080 ) >> 7)
+#define GET_MMU_ALC_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000100 ) >> 8)
+#define GET_MMU_RLS_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000400 ) >> 10)
+#define GET_MBOX_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000800 ) >> 11)
+#define GET_MBOX_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00001000 ) >> 12)
+#define GET_MBOX_INT_3_SD (((REG32(ADR_SD_PERI_STS)) & 0x00002000 ) >> 13)
+#define GET_HCI_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00004000 ) >> 14)
+#define GET_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00008000 ) >> 15)
+#define GET_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x00010000 ) >> 16)
+#define GET_ID_MNG_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00020000 ) >> 17)
+#define GET_DMN_NOHIT_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00040000 ) >> 18)
+#define GET_ID_THOLD_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00080000 ) >> 19)
+#define GET_ID_THOLD_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00100000 ) >> 20)
+#define GET_ID_DOUBLE_RLS_SD (((REG32(ADR_SD_PERI_STS)) & 0x00200000 ) >> 21)
+#define GET_RX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00400000 ) >> 22)
+#define GET_TX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00800000 ) >> 23)
+#define GET_ALL_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x01000000 ) >> 24)
+#define GET_DMN_MCU_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_DAT_UART_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_DAT_UART_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x08000000 ) >> 27)
+#define GET_DAT_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x10000000 ) >> 28)
+#define GET_DAT_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x20000000 ) >> 29)
+#define GET_ALR_ABT_NOCHG_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x40000000 ) >> 30)
+#define GET_TBLNEQ_MNGPKT_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x80000000 ) >> 31)
+#define GET_DBG_SPI_MODE (((REG32(ADR_DBG_SPI_MODE)) & 0xffffffff ) >> 0)
+#define GET_DBG_RX_QUOTA (((REG32(ADR_DBG_RX_QUOTA)) & 0x0000ffff ) >> 0)
+#define GET_DBG_CONDI_NUM (((REG32(ADR_DBG_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
+#define GET_DBG_HOST_PATH (((REG32(ADR_DBG_HOST_PATH)) & 0x00000001 ) >> 0)
+#define GET_DBG_TX_SEG (((REG32(ADR_DBG_TX_SEG)) & 0xffffffff ) >> 0)
+#define GET_DBG_BRST_MODE (((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
+#define GET_DBG_CLK_WIDTH (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
+#define GET_DBG_CSN_INTER (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
+#define GET_DBG_BACK_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_DBG_FRONT_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
+#define GET_DBG_RX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000002 ) >> 1)
+#define GET_DBG_RX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000004 ) >> 2)
+#define GET_DBG_TX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000008 ) >> 3)
+#define GET_DBG_TX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000010 ) >> 4)
+#define GET_DBG_SPI_DOUBLE_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000020 ) >> 5)
+#define GET_DBG_SPI_TX_NO_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000040 ) >> 6)
+#define GET_DBG_RDATA_RDY (((REG32(ADR_DBG_SPI_STS)) & 0x00000080 ) >> 7)
+#define GET_DBG_SPI_ALLOC_STATUS (((REG32(ADR_DBG_SPI_STS)) & 0x00000100 ) >> 8)
+#define GET_DBG_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_DBG_SPI_STS)) & 0x00000200 ) >> 9)
+#define GET_DBG_RX_LEN (((REG32(ADR_DBG_SPI_STS)) & 0xffff0000 ) >> 16)
+#define GET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
+#define GET_DBG_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
+#define GET_DBG_SPI_TX_ALLOC_SIZE (((REG32(ADR_DBG_TX_ALLOC)) & 0x000000ff ) >> 0)
+#define GET_DBG_RD_DAT_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff ) >> 0)
+#define GET_DBG_RD_STS_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000 ) >> 16)
+#define GET_DBG_JUDGE_CNT (((REG32(ADR_DBG_DBG_CNT2)) & 0x0000ffff ) >> 0)
+#define GET_DBG_RD_STS_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00010000 ) >> 16)
+#define GET_DBG_RD_DAT_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00020000 ) >> 17)
+#define GET_DBG_JUDGE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00040000 ) >> 18)
+#define GET_DBG_TX_DONE_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TX_DISCARD_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000 ) >> 16)
+#define GET_DBG_TX_SET_CNT (((REG32(ADR_DBG_DBG_CNT4)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00010000 ) >> 16)
+#define GET_DBG_TX_DONE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00020000 ) >> 17)
+#define GET_DBG_TX_SET_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00040000 ) >> 18)
+#define GET_DBG_DAT_MODE_OFF (((REG32(ADR_DBG_DBG_CNT4)) & 0x00080000 ) >> 19)
+#define GET_DBG_TX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x00700000 ) >> 20)
+#define GET_DBG_RX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x07000000 ) >> 24)
+#define GET_DBG_RX_RDY (((REG32(ADR_DBG_INT_TAG)) & 0x00000001 ) >> 0)
+#define GET_DBG_SDIO_SYS_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000004 ) >> 2)
+#define GET_DBG_EDCA0_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000008 ) >> 3)
+#define GET_DBG_EDCA1_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000010 ) >> 4)
+#define GET_DBG_EDCA2_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000020 ) >> 5)
+#define GET_DBG_EDCA3_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000040 ) >> 6)
+#define GET_DBG_TX_LIMIT_INT_IN (((REG32(ADR_DBG_INT_TAG)) & 0x00000080 ) >> 7)
+#define GET_DBG_SPI_FN1 (((REG32(ADR_DBG_INT_TAG)) & 0x00007f00 ) >> 8)
+#define GET_DBG_SPI_CLK_EN_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00008000 ) >> 15)
+#define GET_DBG_SPI_HOST_MASK (((REG32(ADR_DBG_INT_TAG)) & 0x00ff0000 ) >> 16)
+#define GET_BOOT_ADDR (((REG32(ADR_BOOT_ADDR)) & 0x00ffffff ) >> 0)
+#define GET_CHECK_SUM_FAIL (((REG32(ADR_BOOT_ADDR)) & 0x80000000 ) >> 31)
+#define GET_VERIFY_DATA (((REG32(ADR_VERIFY_DATA)) & 0xffffffff ) >> 0)
+#define GET_FLASH_ADDR (((REG32(ADR_FLASH_ADDR)) & 0x00ffffff ) >> 0)
+#define GET_FLASH_CMD_CLR (((REG32(ADR_FLASH_ADDR)) & 0x10000000 ) >> 28)
+#define GET_FLASH_DMA_CLR (((REG32(ADR_FLASH_ADDR)) & 0x20000000 ) >> 29)
+#define GET_DMA_EN (((REG32(ADR_FLASH_ADDR)) & 0x40000000 ) >> 30)
+#define GET_DMA_BUSY (((REG32(ADR_FLASH_ADDR)) & 0x80000000 ) >> 31)
+#define GET_SRAM_ADDR (((REG32(ADR_SRAM_ADDR)) & 0xffffffff ) >> 0)
+#define GET_FLASH_DMA_LEN (((REG32(ADR_LEN)) & 0xffffffff ) >> 0)
+#define GET_FLASH_FRONT_DLY (((REG32(ADR_SPI_PARAM)) & 0x0000ffff ) >> 0)
+#define GET_FLASH_BACK_DLY (((REG32(ADR_SPI_PARAM)) & 0xffff0000 ) >> 16)
+#define GET_FLASH_CLK_WIDTH (((REG32(ADR_SPI_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_SPI_BUSY (((REG32(ADR_SPI_PARAM2)) & 0x00010000 ) >> 16)
+#define GET_FLS_REMAP (((REG32(ADR_SPI_PARAM2)) & 0x00020000 ) >> 17)
+#define GET_PBUS_SWP (((REG32(ADR_SPI_PARAM2)) & 0x00040000 ) >> 18)
+#define GET_BIT_MODE1 (((REG32(ADR_SPI_PARAM2)) & 0x00080000 ) >> 19)
+#define GET_BIT_MODE2 (((REG32(ADR_SPI_PARAM2)) & 0x00100000 ) >> 20)
+#define GET_BIT_MODE4 (((REG32(ADR_SPI_PARAM2)) & 0x00200000 ) >> 21)
+#define GET_BOOT_CHECK_SUM (((REG32(ADR_CHECK_SUM_RESULT)) & 0xffffffff ) >> 0)
+#define GET_CHECK_SUM_TAG (((REG32(ADR_CHECK_SUM_IN_FILE)) & 0xffffffff ) >> 0)
+#define GET_CMD_LEN (((REG32(ADR_COMMAND_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CMD_ADDR (((REG32(ADR_COMMAND_ADDR)) & 0xffffffff ) >> 0)
+#define GET_DMA_ADR_SRC (((REG32(ADR_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
+#define GET_DMA_ADR_DST (((REG32(ADR_DMA_ADR_DST)) & 0xffffffff ) >> 0)
+#define GET_DMA_SRC_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000007 ) >> 0)
+#define GET_DMA_SRC_INC (((REG32(ADR_DMA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_DMA_DST_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000070 ) >> 4)
+#define GET_DMA_DST_INC (((REG32(ADR_DMA_CTRL)) & 0x00000080 ) >> 7)
+#define GET_DMA_FAST_FILL (((REG32(ADR_DMA_CTRL)) & 0x00000100 ) >> 8)
+#define GET_DMA_SDIO_KICK (((REG32(ADR_DMA_CTRL)) & 0x00001000 ) >> 12)
+#define GET_DMA_BADR_EN (((REG32(ADR_DMA_CTRL)) & 0x00002000 ) >> 13)
+#define GET_DMA_LEN (((REG32(ADR_DMA_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_DMA_INT_MASK (((REG32(ADR_DMA_INT)) & 0x00000001 ) >> 0)
+#define GET_DMA_STS (((REG32(ADR_DMA_INT)) & 0x00000100 ) >> 8)
+#define GET_DMA_FINISH (((REG32(ADR_DMA_INT)) & 0x80000000 ) >> 31)
+#define GET_DMA_CONST (((REG32(ADR_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
+#define GET_SLEEP_WAKE_CNT (((REG32(ADR_PMU_0)) & 0x00ffffff ) >> 0)
+#define GET_RG_DLDO_LEVEL (((REG32(ADR_PMU_0)) & 0x07000000 ) >> 24)
+#define GET_RG_DLDO_BOOST_IQ (((REG32(ADR_PMU_0)) & 0x08000000 ) >> 27)
+#define GET_RG_BUCK_LEVEL (((REG32(ADR_PMU_0)) & 0x70000000 ) >> 28)
+#define GET_RG_BUCK_VREF_SEL (((REG32(ADR_PMU_0)) & 0x80000000 ) >> 31)
+#define GET_RG_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_PMU_1)) & 0x000003ff ) >> 0)
+#define GET_RG_RTC_OSC_RES_SW (((REG32(ADR_PMU_1)) & 0x03ff0000 ) >> 16)
+#define GET_RTC_OSC_CAL_RES_RDY (((REG32(ADR_PMU_1)) & 0x80000000 ) >> 31)
+#define GET_RG_DCDC_MODE (((REG32(ADR_PMU_2)) & 0x00000001 ) >> 0)
+#define GET_RG_BUCK_EN_PSM (((REG32(ADR_PMU_2)) & 0x00000010 ) >> 4)
+#define GET_RG_BUCK_PSM_VTH (((REG32(ADR_PMU_2)) & 0x00000100 ) >> 8)
+#define GET_RG_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_PMU_2)) & 0x00001000 ) >> 12)
+#define GET_RG_RTC_RDY_DEGLITCH_TIMER (((REG32(ADR_PMU_2)) & 0x00006000 ) >> 13)
+#define GET_RTC_CAL_ENA (((REG32(ADR_PMU_2)) & 0x00010000 ) >> 16)
+#define GET_PMU_WAKE_TRIG_EVENT (((REG32(ADR_PMU_3)) & 0x00000003 ) >> 0)
+#define GET_DIGI_TOP_POR_MASK (((REG32(ADR_PMU_3)) & 0x00000010 ) >> 4)
+#define GET_PMU_ENTER_SLEEP_MODE (((REG32(ADR_PMU_3)) & 0x00000100 ) >> 8)
+#define GET_RG_RTC_DUMMIES (((REG32(ADR_PMU_3)) & 0xffff0000 ) >> 16)
+#define GET_RTC_EN (((REG32(ADR_RTC_1)) & 0x00000001 ) >> 0)
+#define GET_RTC_SRC (((REG32(ADR_RTC_1)) & 0x00000002 ) >> 1)
+#define GET_RTC_TICK_CNT (((REG32(ADR_RTC_1)) & 0x7fff0000 ) >> 16)
+#define GET_RTC_INT_SEC_MASK (((REG32(ADR_RTC_2)) & 0x00000001 ) >> 0)
+#define GET_RTC_INT_ALARM_MASK (((REG32(ADR_RTC_2)) & 0x00000002 ) >> 1)
+#define GET_RTC_INT_SEC (((REG32(ADR_RTC_2)) & 0x00010000 ) >> 16)
+#define GET_RTC_INT_ALARM (((REG32(ADR_RTC_2)) & 0x00020000 ) >> 17)
+#define GET_RTC_SEC_START_CNT (((REG32(ADR_RTC_3W)) & 0xffffffff ) >> 0)
+#define GET_RTC_SEC_CNT (((REG32(ADR_RTC_3R)) & 0xffffffff ) >> 0)
+#define GET_RTC_SEC_ALARM_VALUE (((REG32(ADR_RTC_4)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_ADR_SRC (((REG32(ADR_D2_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_ADR_DST (((REG32(ADR_D2_DMA_ADR_DST)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_SRC_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000007 ) >> 0)
+#define GET_D2_DMA_SRC_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_D2_DMA_DST_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000070 ) >> 4)
+#define GET_D2_DMA_DST_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000080 ) >> 7)
+#define GET_D2_DMA_FAST_FILL (((REG32(ADR_D2_DMA_CTRL)) & 0x00000100 ) >> 8)
+#define GET_D2_DMA_SDIO_KICK (((REG32(ADR_D2_DMA_CTRL)) & 0x00001000 ) >> 12)
+#define GET_D2_DMA_BADR_EN (((REG32(ADR_D2_DMA_CTRL)) & 0x00002000 ) >> 13)
+#define GET_D2_DMA_LEN (((REG32(ADR_D2_DMA_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_D2_DMA_INT_MASK (((REG32(ADR_D2_DMA_INT)) & 0x00000001 ) >> 0)
+#define GET_D2_DMA_STS (((REG32(ADR_D2_DMA_INT)) & 0x00000100 ) >> 8)
+#define GET_D2_DMA_FINISH (((REG32(ADR_D2_DMA_INT)) & 0x80000000 ) >> 31)
+#define GET_D2_DMA_CONST (((REG32(ADR_D2_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
+#define GET_TRAP_UNKNOWN_TYPE (((REG32(ADR_CONTROL)) & 0x00000001 ) >> 0)
+#define GET_TX_ON_DEMAND_ENA (((REG32(ADR_CONTROL)) & 0x00000002 ) >> 1)
+#define GET_RX_2_HOST (((REG32(ADR_CONTROL)) & 0x00000004 ) >> 2)
+#define GET_AUTO_SEQNO (((REG32(ADR_CONTROL)) & 0x00000008 ) >> 3)
+#define GET_BYPASSS_TX_PARSER_ENCAP (((REG32(ADR_CONTROL)) & 0x00000010 ) >> 4)
+#define GET_HDR_STRIP (((REG32(ADR_CONTROL)) & 0x00000020 ) >> 5)
+#define GET_ERP_PROTECT (((REG32(ADR_CONTROL)) & 0x000000c0 ) >> 6)
+#define GET_PRO_VER (((REG32(ADR_CONTROL)) & 0x00000300 ) >> 8)
+#define GET_TXQ_ID0 (((REG32(ADR_CONTROL)) & 0x00007000 ) >> 12)
+#define GET_TXQ_ID1 (((REG32(ADR_CONTROL)) & 0x00070000 ) >> 16)
+#define GET_TX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00100000 ) >> 20)
+#define GET_RX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00200000 ) >> 21)
+#define GET_RX_NULL_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00400000 ) >> 22)
+#define GET_RX_GET_TX_QUEUE_EN (((REG32(ADR_CONTROL)) & 0x02000000 ) >> 25)
+#define GET_HCI_INQ_SEL (((REG32(ADR_CONTROL)) & 0x04000000 ) >> 26)
+#define GET_TRX_DEBUG_CNT_ENA (((REG32(ADR_CONTROL)) & 0x10000000 ) >> 28)
+#define GET_WAKE_SOON_WITH_SCK (((REG32(ADR_SDIO_WAKE_MODE)) & 0x00000001 ) >> 0)
+#define GET_TX_FLOW_CTRL (((REG32(ADR_TX_FLOW_0)) & 0x0000ffff ) >> 0)
+#define GET_TX_FLOW_MGMT (((REG32(ADR_TX_FLOW_0)) & 0xffff0000 ) >> 16)
+#define GET_TX_FLOW_DATA (((REG32(ADR_TX_FLOW_1)) & 0xffffffff ) >> 0)
+#define GET_DOT11RTSTHRESHOLD (((REG32(ADR_THREASHOLD)) & 0xffff0000 ) >> 16)
+#define GET_TXF_ID (((REG32(ADR_TXFID_INCREASE)) & 0x0000003f ) >> 0)
+#define GET_SEQ_CTRL (((REG32(ADR_GLOBAL_SEQUENCE)) & 0x0000ffff ) >> 0)
+#define GET_TX_PBOFFSET (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x000000ff ) >> 0)
+#define GET_TX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x0000ff00 ) >> 8)
+#define GET_RX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ff0000 ) >> 16)
+#define GET_RX_LAST_PHY_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff000000 ) >> 24)
+#define GET_TX_INFO_CLEAR_SIZE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x0000003f ) >> 0)
+#define GET_TX_INFO_CLEAR_ENABLE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x00000100 ) >> 8)
+#define GET_TXTRAP_ETHTYPE1 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
+#define GET_TXTRAP_ETHTYPE0 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
+#define GET_RXTRAP_ETHTYPE1 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
+#define GET_RXTRAP_ETHTYPE0 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
+#define GET_TX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0xffffffff ) >> 0)
+#define GET_RX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0xffffffff ) >> 0)
+#define GET_HOST_CMD_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0x000000ff ) >> 0)
+#define GET_HOST_EVENT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0x000000ff ) >> 0)
+#define GET_TX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0x000000ff ) >> 0)
+#define GET_RX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0x000000ff ) >> 0)
+#define GET_TX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0x000000ff ) >> 0)
+#define GET_RX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0x000000ff ) >> 0)
+#define GET_HOST_TX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0x000000ff ) >> 0)
+#define GET_HOST_RX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0x000000ff ) >> 0)
+#define GET_HCI_STATE_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0xffffffff ) >> 0)
+#define GET_HCI_ST_TIMEOUT_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0xffffffff ) >> 0)
+#define GET_TX_ON_DEMAND_LENGTH (((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG1 (((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG2 (((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_TIME_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_TIME_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x0000ffff ) >> 0)
+#define GET_HCI_MB_MAX_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x00ff0000 ) >> 16)
+#define GET_HCI_TX_ALLOC_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x0000ffff ) >> 0)
+#define GET_HCI_PROC_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ff0000 ) >> 16)
+#define GET_SDIO_TRANS_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff000000 ) >> 24)
+#define GET_SDIO_TX_INVALID_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0xffffffff ) >> 0)
+#define GET_SDIO_TX_INVALID_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0x0000ffff ) >> 0)
+#define GET_CS_START_ADDR (((REG32(ADR_CS_START_ADDR)) & 0x0000ffff ) >> 0)
+#define GET_CS_PKT_ID (((REG32(ADR_CS_START_ADDR)) & 0x007f0000 ) >> 16)
+#define GET_ADD_LEN (((REG32(ADR_CS_ADD_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CS_ADDER_EN (((REG32(ADR_CS_CMD)) & 0x00000001 ) >> 0)
+#define GET_PSEUDO (((REG32(ADR_CS_CMD)) & 0x00000002 ) >> 1)
+#define GET_CALCULATE (((REG32(ADR_CS_INI_BUF)) & 0xffffffff ) >> 0)
+#define GET_L4_LEN (((REG32(ADR_CS_PSEUDO_BUF)) & 0x0000ffff ) >> 0)
+#define GET_L4_PROTOL (((REG32(ADR_CS_PSEUDO_BUF)) & 0x00ff0000 ) >> 16)
+#define GET_CHECK_SUM (((REG32(ADR_CS_CHECK_SUM)) & 0x0000ffff ) >> 0)
+#define GET_RAND_EN (((REG32(ADR_RAND_EN)) & 0x00000001 ) >> 0)
+#define GET_RAND_NUM (((REG32(ADR_RAND_NUM)) & 0xffffffff ) >> 0)
+#define GET_MUL_OP1 (((REG32(ADR_MUL_OP1)) & 0xffffffff ) >> 0)
+#define GET_MUL_OP2 (((REG32(ADR_MUL_OP2)) & 0xffffffff ) >> 0)
+#define GET_MUL_ANS0 (((REG32(ADR_MUL_ANS0)) & 0xffffffff ) >> 0)
+#define GET_MUL_ANS1 (((REG32(ADR_MUL_ANS1)) & 0xffffffff ) >> 0)
+#define GET_RD_ADDR (((REG32(ADR_DMA_RDATA)) & 0x0000ffff ) >> 0)
+#define GET_RD_ID (((REG32(ADR_DMA_RDATA)) & 0x007f0000 ) >> 16)
+#define GET_WR_ADDR (((REG32(ADR_DMA_WDATA)) & 0x0000ffff ) >> 0)
+#define GET_WR_ID (((REG32(ADR_DMA_WDATA)) & 0x007f0000 ) >> 16)
+#define GET_LEN (((REG32(ADR_DMA_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CLR (((REG32(ADR_DMA_CLR)) & 0x00000001 ) >> 0)
+#define GET_PHY_MODE (((REG32(ADR_NAV_DATA)) & 0x00000003 ) >> 0)
+#define GET_SHRT_PREAM (((REG32(ADR_NAV_DATA)) & 0x00000004 ) >> 2)
+#define GET_SHRT_GI (((REG32(ADR_NAV_DATA)) & 0x00000008 ) >> 3)
+#define GET_DATA_RATE (((REG32(ADR_NAV_DATA)) & 0x000007f0 ) >> 4)
+#define GET_MCS (((REG32(ADR_NAV_DATA)) & 0x00007000 ) >> 12)
+#define GET_FRAME_LEN (((REG32(ADR_NAV_DATA)) & 0xffff0000 ) >> 16)
+#define GET_DURATION (((REG32(ADR_CO_NAV)) & 0x0000ffff ) >> 0)
+#define GET_SHA_DST_ADDR (((REG32(ADR_SHA_DST_ADDR)) & 0xffffffff ) >> 0)
+#define GET_SHA_SRC_ADDR (((REG32(ADR_SHA_SRC_ADDR)) & 0xffffffff ) >> 0)
+#define GET_SHA_BUSY (((REG32(ADR_SHA_SETTING)) & 0x00000001 ) >> 0)
+#define GET_SHA_ENDIAN (((REG32(ADR_SHA_SETTING)) & 0x00000002 ) >> 1)
+#define GET_EFS_CLKFREQ (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00000fff ) >> 0)
+#define GET_LOW_ACTIVE (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00010000 ) >> 16)
+#define GET_EFS_CLKFREQ_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0ff00000 ) >> 20)
+#define GET_EFS_PRE_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf0000000 ) >> 28)
+#define GET_EFS_LDO_ON (((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff ) >> 0)
+#define GET_EFS_LDO_OFF (((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000 ) >> 16)
+#define GET_EFS_RDATA_0 (((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_0 (((REG32(ADR_EFUSE_WDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_1 (((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_1 (((REG32(ADR_EFUSE_WDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_2 (((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_2 (((REG32(ADR_EFUSE_WDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_3 (((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_3 (((REG32(ADR_EFUSE_WDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_4 (((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_4 (((REG32(ADR_EFUSE_WDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_5 (((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_5 (((REG32(ADR_EFUSE_WDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_6 (((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_6 (((REG32(ADR_EFUSE_WDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_7 (((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_7 (((REG32(ADR_EFUSE_WDATA_7)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RD0_EN (((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD1_EN (((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD2_EN (((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD3_EN (((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD4_EN (((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD5_EN (((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD6_EN (((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD7_EN (((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RBUSY (((REG32(ADR_EFUSE_SPI_BUSY)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RDATA_0 (((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_1 (((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_2 (((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_3 (((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_4 (((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_5 (((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_6 (((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_7 (((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0xffffffff ) >> 0)
+#define GET_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000001 ) >> 0)
+#define GET_FORCE_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000002 ) >> 1)
+#define GET_SMS4_DESCRY_EN (((REG32(ADR_SMS4_CFG1)) & 0x00000010 ) >> 4)
+#define GET_DEC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000001 ) >> 0)
+#define GET_DEC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000002 ) >> 1)
+#define GET_ENC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000004 ) >> 2)
+#define GET_ENC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000008 ) >> 3)
+#define GET_KEY_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000010 ) >> 4)
+#define GET_SMS4_CBC_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000001 ) >> 0)
+#define GET_SMS4_CFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000002 ) >> 1)
+#define GET_SMS4_OFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000004 ) >> 2)
+#define GET_SMS4_START_TRIG (((REG32(ADR_SMS4_TRIG)) & 0x00000001 ) >> 0)
+#define GET_SMS4_BUSY (((REG32(ADR_SMS4_STATUS1)) & 0x00000001 ) >> 0)
+#define GET_SMS4_DONE (((REG32(ADR_SMS4_STATUS2)) & 0x00000001 ) >> 0)
+#define GET_SMS4_DATAIN_0 (((REG32(ADR_SMS4_DATA_IN0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_1 (((REG32(ADR_SMS4_DATA_IN1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_2 (((REG32(ADR_SMS4_DATA_IN2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_3 (((REG32(ADR_SMS4_DATA_IN3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_0 (((REG32(ADR_SMS4_DATA_OUT0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_1 (((REG32(ADR_SMS4_DATA_OUT1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_2 (((REG32(ADR_SMS4_DATA_OUT2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_3 (((REG32(ADR_SMS4_DATA_OUT3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_0 (((REG32(ADR_SMS4_KEY_0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_1 (((REG32(ADR_SMS4_KEY_1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_2 (((REG32(ADR_SMS4_KEY_2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_3 (((REG32(ADR_SMS4_KEY_3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV0 (((REG32(ADR_SMS4_MODE_IV0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV1 (((REG32(ADR_SMS4_MODE_IV1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV2 (((REG32(ADR_SMS4_MODE_IV2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV3 (((REG32(ADR_SMS4_MODE_IV3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC0 (((REG32(ADR_SMS4_OFB_ENC0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC1 (((REG32(ADR_SMS4_OFB_ENC1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC2 (((REG32(ADR_SMS4_OFB_ENC2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC3 (((REG32(ADR_SMS4_OFB_ENC3)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB0_31_0 (((REG32(ADR_MRX_MCAST_TB0_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB0_47_32 (((REG32(ADR_MRX_MCAST_TB0_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK0_31_0 (((REG32(ADR_MRX_MCAST_MK0_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK0_47_32 (((REG32(ADR_MRX_MCAST_MK0_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_0 (((REG32(ADR_MRX_MCAST_CTRL0)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB1_31_0 (((REG32(ADR_MRX_MCAST_TB1_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB1_47_32 (((REG32(ADR_MRX_MCAST_TB1_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK1_31_0 (((REG32(ADR_MRX_MCAST_MK1_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK1_47_32 (((REG32(ADR_MRX_MCAST_MK1_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_1 (((REG32(ADR_MRX_MCAST_CTRL1)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB2_31_0 (((REG32(ADR_MRX_MCAST_TB2_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB2_47_32 (((REG32(ADR_MRX_MCAST_TB2_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK2_31_0 (((REG32(ADR_MRX_MCAST_MK2_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK2_47_32 (((REG32(ADR_MRX_MCAST_MK2_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_2 (((REG32(ADR_MRX_MCAST_CTRL2)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB3_31_0 (((REG32(ADR_MRX_MCAST_TB3_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB3_47_32 (((REG32(ADR_MRX_MCAST_TB3_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK3_31_0 (((REG32(ADR_MRX_MCAST_MK3_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK3_47_32 (((REG32(ADR_MRX_MCAST_MK3_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_3 (((REG32(ADR_MRX_MCAST_CTRL3)) & 0x00000003 ) >> 0)
+#define GET_MRX_PHY_INFO (((REG32(ADR_MRX_PHY_INFO)) & 0xffffffff ) >> 0)
+#define GET_DBG_BA_TYPE (((REG32(ADR_MRX_BA_DBG)) & 0x0000003f ) >> 0)
+#define GET_DBG_BA_SEQ (((REG32(ADR_MRX_BA_DBG)) & 0x000fff00 ) >> 8)
+#define GET_MRX_FLT_TB0 (((REG32(ADR_MRX_FLT_TB0)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB1 (((REG32(ADR_MRX_FLT_TB1)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB2 (((REG32(ADR_MRX_FLT_TB2)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB3 (((REG32(ADR_MRX_FLT_TB3)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB4 (((REG32(ADR_MRX_FLT_TB4)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB5 (((REG32(ADR_MRX_FLT_TB5)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB6 (((REG32(ADR_MRX_FLT_TB6)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB7 (((REG32(ADR_MRX_FLT_TB7)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB8 (((REG32(ADR_MRX_FLT_TB8)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB9 (((REG32(ADR_MRX_FLT_TB9)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB10 (((REG32(ADR_MRX_FLT_TB10)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB11 (((REG32(ADR_MRX_FLT_TB11)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB12 (((REG32(ADR_MRX_FLT_TB12)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB13 (((REG32(ADR_MRX_FLT_TB13)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB14 (((REG32(ADR_MRX_FLT_TB14)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB15 (((REG32(ADR_MRX_FLT_TB15)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_EN0 (((REG32(ADR_MRX_FLT_EN0)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN1 (((REG32(ADR_MRX_FLT_EN1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN2 (((REG32(ADR_MRX_FLT_EN2)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN3 (((REG32(ADR_MRX_FLT_EN3)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN4 (((REG32(ADR_MRX_FLT_EN4)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN5 (((REG32(ADR_MRX_FLT_EN5)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN6 (((REG32(ADR_MRX_FLT_EN6)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN7 (((REG32(ADR_MRX_FLT_EN7)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN8 (((REG32(ADR_MRX_FLT_EN8)) & 0x0000ffff ) >> 0)
+#define GET_MRX_LEN_FLT (((REG32(ADR_MRX_LEN_FLT)) & 0x0000ffff ) >> 0)
+#define GET_RX_FLOW_DATA (((REG32(ADR_RX_FLOW_DATA)) & 0xffffffff ) >> 0)
+#define GET_RX_FLOW_MNG (((REG32(ADR_RX_FLOW_MNG)) & 0x0000ffff ) >> 0)
+#define GET_RX_FLOW_CTRL (((REG32(ADR_RX_FLOW_CTRL)) & 0x0000ffff ) >> 0)
+#define GET_MRX_STP_EN (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x00000001 ) >> 0)
+#define GET_MRX_STP_OFST (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x0000ff00 ) >> 8)
+#define GET_DBG_FF_FULL (((REG32(ADR_DBG_FF_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_FF_FULL_CLR (((REG32(ADR_DBG_FF_FULL)) & 0x80000000 ) >> 31)
+#define GET_DBG_WFF_FULL (((REG32(ADR_DBG_WFF_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_WFF_FULL_CLR (((REG32(ADR_DBG_WFF_FULL)) & 0x80000000 ) >> 31)
+#define GET_DBG_MB_FULL (((REG32(ADR_DBG_MB_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_MB_FULL_CLR (((REG32(ADR_DBG_MB_FULL)) & 0x80000000 ) >> 31)
+#define GET_BA_CTRL (((REG32(ADR_BA_CTRL)) & 0x00000003 ) >> 0)
+#define GET_BA_DBG_EN (((REG32(ADR_BA_CTRL)) & 0x00000004 ) >> 2)
+#define GET_BA_AGRE_EN (((REG32(ADR_BA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_BA_TA_31_0 (((REG32(ADR_BA_TA_0)) & 0xffffffff ) >> 0)
+#define GET_BA_TA_47_32 (((REG32(ADR_BA_TA_1)) & 0x0000ffff ) >> 0)
+#define GET_BA_TID (((REG32(ADR_BA_TID)) & 0x0000000f ) >> 0)
+#define GET_BA_ST_SEQ (((REG32(ADR_BA_ST_SEQ)) & 0x00000fff ) >> 0)
+#define GET_BA_SB0 (((REG32(ADR_BA_SB0)) & 0xffffffff ) >> 0)
+#define GET_BA_SB1 (((REG32(ADR_BA_SB1)) & 0xffffffff ) >> 0)
+#define GET_MRX_WD (((REG32(ADR_MRX_WATCH_DOG)) & 0x0001ffff ) >> 0)
+#define GET_ACK_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000001 ) >> 0)
+#define GET_BA_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000002 ) >> 1)
+#define GET_ACK_GEN_DUR (((REG32(ADR_ACK_GEN_PARA)) & 0x0000ffff ) >> 0)
+#define GET_ACK_GEN_INFO (((REG32(ADR_ACK_GEN_PARA)) & 0x003f0000 ) >> 16)
+#define GET_ACK_GEN_RA_31_0 (((REG32(ADR_ACK_GEN_RA_0)) & 0xffffffff ) >> 0)
+#define GET_ACK_GEN_RA_47_32 (((REG32(ADR_ACK_GEN_RA_1)) & 0x0000ffff ) >> 0)
+#define GET_MIB_LEN_FAIL (((REG32(ADR_MIB_LEN_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_TRAP_HW_ID (((REG32(ADR_TRAP_HW_ID)) & 0x0000000f ) >> 0)
+#define GET_ID_IN_USE (((REG32(ADR_ID_IN_USE)) & 0x000000ff ) >> 0)
+#define GET_MRX_ERR (((REG32(ADR_MRX_ERR)) & 0xffffffff ) >> 0)
+#define GET_W0_T0_SEQ (((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T1_SEQ (((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T2_SEQ (((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T3_SEQ (((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T4_SEQ (((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T5_SEQ (((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T6_SEQ (((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T7_SEQ (((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T0_SEQ (((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T1_SEQ (((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T2_SEQ (((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T3_SEQ (((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T4_SEQ (((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T5_SEQ (((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T6_SEQ (((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T7_SEQ (((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_ADDR1A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000003 ) >> 0)
+#define GET_ADDR2A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x0000000c ) >> 2)
+#define GET_ADDR3A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000030 ) >> 4)
+#define GET_ADDR1B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x000000c0 ) >> 6)
+#define GET_ADDR2B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000300 ) >> 8)
+#define GET_ADDR3B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000c00 ) >> 10)
+#define GET_ADDR3C_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00003000 ) >> 12)
+#define GET_FRM_CTRL (((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0x0000003f ) >> 0)
+#define GET_CSR_PHY_INFO (((REG32(ADR_PHY_INFO)) & 0x00007fff ) >> 0)
+#define GET_AMPDU_SIG (((REG32(ADR_AMPDU_SIG)) & 0x000000ff ) >> 0)
+#define GET_MIB_AMPDU (((REG32(ADR_MIB_AMPDU)) & 0xffffffff ) >> 0)
+#define GET_LEN_FLT (((REG32(ADR_LEN_FLT)) & 0x0000ffff ) >> 0)
+#define GET_MIB_DELIMITER (((REG32(ADR_MIB_DELIMITER)) & 0x0000ffff ) >> 0)
+#define GET_MTX_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00010000 ) >> 16)
+#define GET_MTX_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00020000 ) >> 17)
+#define GET_MTX_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00040000 ) >> 18)
+#define GET_MTX_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00080000 ) >> 19)
+#define GET_MTX_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00100000 ) >> 20)
+#define GET_MTX_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00200000 ) >> 21)
+#define GET_MTX_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00400000 ) >> 22)
+#define GET_MTX_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00800000 ) >> 23)
+#define GET_MTX_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x01000000 ) >> 24)
+#define GET_MTX_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x02000000 ) >> 25)
+#define GET_MTX_EN_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00010000 ) >> 16)
+#define GET_MTX_EN_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00020000 ) >> 17)
+#define GET_MTX_EN_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00040000 ) >> 18)
+#define GET_MTX_EN_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00080000 ) >> 19)
+#define GET_MTX_EN_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00100000 ) >> 20)
+#define GET_MTX_EN_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00200000 ) >> 21)
+#define GET_MTX_EN_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00400000 ) >> 22)
+#define GET_MTX_EN_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00800000 ) >> 23)
+#define GET_MTX_EN_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x01000000 ) >> 24)
+#define GET_MTX_EN_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x02000000 ) >> 25)
+#define GET_MTX_MTX2PHY_SLOW (((REG32(ADR_MTX_MISC_EN)) & 0x00000001 ) >> 0)
+#define GET_MTX_M2M_SLOW_PRD (((REG32(ADR_MTX_MISC_EN)) & 0x0000000e ) >> 1)
+#define GET_MTX_AMPDU_CRC_AUTO (((REG32(ADR_MTX_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_MTX_FAST_RSP_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000040 ) >> 6)
+#define GET_MTX_RAW_DATA_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000080 ) >> 7)
+#define GET_MTX_ACK_DUR0 (((REG32(ADR_MTX_MISC_EN)) & 0x00000100 ) >> 8)
+#define GET_MTX_TSF_AUTO_BCN (((REG32(ADR_MTX_MISC_EN)) & 0x00000400 ) >> 10)
+#define GET_MTX_TSF_AUTO_MISC (((REG32(ADR_MTX_MISC_EN)) & 0x00000800 ) >> 11)
+#define GET_MTX_FORCE_CS_IDLE (((REG32(ADR_MTX_MISC_EN)) & 0x00001000 ) >> 12)
+#define GET_MTX_FORCE_BKF_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00002000 ) >> 13)
+#define GET_MTX_FORCE_DMA_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00004000 ) >> 14)
+#define GET_MTX_FORCE_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00008000 ) >> 15)
+#define GET_MTX_HALT_Q_MB (((REG32(ADR_MTX_MISC_EN)) & 0x003f0000 ) >> 16)
+#define GET_MTX_CTS_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00400000 ) >> 22)
+#define GET_MTX_AMPDU_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00800000 ) >> 23)
+#define GET_MTX_EDCCA_TOUT (((REG32(ADR_MTX_EDCCA_TOUT)) & 0x000003ff ) >> 0)
+#define GET_MTX_INT_BCN (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000002 ) >> 1)
+#define GET_MTX_INT_DTIM (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000008 ) >> 3)
+#define GET_MTX_EN_INT_BCN (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000002 ) >> 1)
+#define GET_MTX_EN_INT_DTIM (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000008 ) >> 3)
+#define GET_MTX_BCN_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000001 ) >> 0)
+#define GET_MTX_TIME_STAMP_AUTO_FILL (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000002 ) >> 1)
+#define GET_MTX_TSF_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000020 ) >> 5)
+#define GET_MTX_HALT_MNG_UNTIL_DTIM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000040 ) >> 6)
+#define GET_MTX_INT_DTIM_NUM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_AUTO_FLUSH_Q4 (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00010000 ) >> 16)
+#define GET_MTX_BCN_PKTID_CH_LOCK (((REG32(ADR_MTX_BCN_MISC)) & 0x00000001 ) >> 0)
+#define GET_MTX_BCN_CFG_VLD (((REG32(ADR_MTX_BCN_MISC)) & 0x00000006 ) >> 1)
+#define GET_MTX_AUTO_BCN_ONGOING (((REG32(ADR_MTX_BCN_MISC)) & 0x00000008 ) >> 3)
+#define GET_MTX_BCN_TIMER (((REG32(ADR_MTX_BCN_MISC)) & 0xffff0000 ) >> 16)
+#define GET_MTX_BCN_PERIOD (((REG32(ADR_MTX_BCN_PRD)) & 0x0000ffff ) >> 0)
+#define GET_MTX_DTIM_NUM (((REG32(ADR_MTX_BCN_PRD)) & 0xff000000 ) >> 24)
+#define GET_MTX_BCN_TSF_L (((REG32(ADR_MTX_BCN_TSF_L)) & 0xffffffff ) >> 0)
+#define GET_MTX_BCN_TSF_U (((REG32(ADR_MTX_BCN_TSF_U)) & 0xffffffff ) >> 0)
+#define GET_MTX_BCN_PKT_ID0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x0000007f ) >> 0)
+#define GET_MTX_DTIM_OFST0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x03ff0000 ) >> 16)
+#define GET_MTX_BCN_PKT_ID1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x0000007f ) >> 0)
+#define GET_MTX_DTIM_OFST1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x03ff0000 ) >> 16)
+#define GET_MTX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000001 ) >> 0)
+#define GET_MRX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000002 ) >> 1)
+#define GET_MTX_DMA_FSM (((REG32(ADR_MTX_STATUS)) & 0x0000001c ) >> 2)
+#define GET_CH_ST_FSM (((REG32(ADR_MTX_STATUS)) & 0x000000e0 ) >> 5)
+#define GET_MTX_GNT_LOCK (((REG32(ADR_MTX_STATUS)) & 0x00000100 ) >> 8)
+#define GET_MTX_DMA_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000200 ) >> 9)
+#define GET_MTX_Q_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000400 ) >> 10)
+#define GET_MTX_TX_EN (((REG32(ADR_MTX_STATUS)) & 0x00000800 ) >> 11)
+#define GET_MRX_RX_EN (((REG32(ADR_MTX_STATUS)) & 0x00001000 ) >> 12)
+#define GET_DBG_PRTC_PRD (((REG32(ADR_MTX_STATUS)) & 0x00002000 ) >> 13)
+#define GET_DBG_DMA_RDY (((REG32(ADR_MTX_STATUS)) & 0x00004000 ) >> 14)
+#define GET_DBG_WAIT_RSP (((REG32(ADR_MTX_STATUS)) & 0x00008000 ) >> 15)
+#define GET_DBG_CFRM_BUSY (((REG32(ADR_MTX_STATUS)) & 0x00010000 ) >> 16)
+#define GET_DBG_RST (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000001 ) >> 0)
+#define GET_DBG_MODE (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000002 ) >> 1)
+#define GET_MB_REQ_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff ) >> 0)
+#define GET_RX_EN_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000 ) >> 16)
+#define GET_RX_CS_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff ) >> 0)
+#define GET_TX_CCA_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000 ) >> 16)
+#define GET_Q_REQ_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA0_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000 ) >> 16)
+#define GET_MTX_DUR_RSP_TOUT_B (((REG32(ADR_MTX_DUR_TOUT)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_RSP_TOUT_G (((REG32(ADR_MTX_DUR_TOUT)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_RSP_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_BURST_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_SLOT (((REG32(ADR_MTX_DUR_IFS)) & 0x003f0000 ) >> 16)
+#define GET_MTX_DUR_RSP_EIFS (((REG32(ADR_MTX_DUR_IFS)) & 0xffc00000 ) >> 22)
+#define GET_MTX_DUR_RSP_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_BURST_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_SLOT_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003f0000 ) >> 16)
+#define GET_MTX_DUR_RSP_EIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc00000 ) >> 22)
+#define GET_CH_STA1_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA2_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000 ) >> 16)
+#define GET_MTX_NAV (((REG32(ADR_MTX_NAV)) & 0x0000ffff ) >> 0)
+#define GET_MTX_MIB_CNT0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x3fffffff ) >> 0)
+#define GET_MTX_MIB_EN0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x40000000 ) >> 30)
+#define GET_MTX_MIB_CNT1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x3fffffff ) >> 0)
+#define GET_MTX_MIB_EN1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x40000000 ) >> 30)
+#define GET_CH_STA3_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA4_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000 ) >> 16)
+#define GET_TXQ0_MTX_Q_PRE_LD (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ0_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ0_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ0_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ0_MTX_Q_RND_MODE (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ0_MTX_Q_AIFSN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ0_MTX_Q_ECWMIN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ0_MTX_Q_ECWMAX (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ0_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ0_MTX_Q_BKF_CNT (((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ0_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ0_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ0_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ0_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ0_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_PRE_LD (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ1_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ1_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ1_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ1_MTX_Q_RND_MODE (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ1_MTX_Q_AIFSN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ1_MTX_Q_ECWMIN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ1_MTX_Q_ECWMAX (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ1_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ1_MTX_Q_BKF_CNT (((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ1_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ1_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ1_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_PRE_LD (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ2_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ2_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ2_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ2_MTX_Q_RND_MODE (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ2_MTX_Q_AIFSN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ2_MTX_Q_ECWMIN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ2_MTX_Q_ECWMAX (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ2_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ2_MTX_Q_BKF_CNT (((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ2_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ2_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ2_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_PRE_LD (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ3_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ3_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ3_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ3_MTX_Q_RND_MODE (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ3_MTX_Q_AIFSN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ3_MTX_Q_ECWMIN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ3_MTX_Q_ECWMAX (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ3_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ3_MTX_Q_BKF_CNT (((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ3_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ3_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ3_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_PRE_LD (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ4_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ4_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ4_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ4_MTX_Q_RND_MODE (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ4_MTX_Q_AIFSN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ4_MTX_Q_ECWMIN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ4_MTX_Q_ECWMAX (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ4_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ4_MTX_Q_BKF_CNT (((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ4_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ4_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ4_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_VALID0 (((REG32(ADR_WSID0)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN0 (((REG32(ADR_WSID0)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE0 (((REG32(ADR_WSID0)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE0 (((REG32(ADR_WSID0)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC0_31_0 (((REG32(ADR_PEER_MAC0_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC0_47_32 (((REG32(ADR_PEER_MAC0_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_0_0 (((REG32(ADR_TX_ACK_POLICY_0_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_0 (((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_1 (((REG32(ADR_TX_ACK_POLICY_0_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_1 (((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_2 (((REG32(ADR_TX_ACK_POLICY_0_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_2 (((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_3 (((REG32(ADR_TX_ACK_POLICY_0_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_3 (((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_4 (((REG32(ADR_TX_ACK_POLICY_0_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_4 (((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_5 (((REG32(ADR_TX_ACK_POLICY_0_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_5 (((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_6 (((REG32(ADR_TX_ACK_POLICY_0_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_6 (((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_7 (((REG32(ADR_TX_ACK_POLICY_0_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_7 (((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0x00000fff ) >> 0)
+#define GET_VALID1 (((REG32(ADR_WSID1)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN1 (((REG32(ADR_WSID1)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE1 (((REG32(ADR_WSID1)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE1 (((REG32(ADR_WSID1)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC1_31_0 (((REG32(ADR_PEER_MAC1_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC1_47_32 (((REG32(ADR_PEER_MAC1_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_1_0 (((REG32(ADR_TX_ACK_POLICY_1_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_0 (((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_1 (((REG32(ADR_TX_ACK_POLICY_1_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_1 (((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_2 (((REG32(ADR_TX_ACK_POLICY_1_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_2 (((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_3 (((REG32(ADR_TX_ACK_POLICY_1_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_3 (((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_4 (((REG32(ADR_TX_ACK_POLICY_1_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_4 (((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_5 (((REG32(ADR_TX_ACK_POLICY_1_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_5 (((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_6 (((REG32(ADR_TX_ACK_POLICY_1_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_6 (((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_7 (((REG32(ADR_TX_ACK_POLICY_1_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_7 (((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0x00000fff ) >> 0)
+#define GET_INFO0 (((REG32(ADR_INFO0)) & 0xffffffff ) >> 0)
+#define GET_INFO1 (((REG32(ADR_INFO1)) & 0xffffffff ) >> 0)
+#define GET_INFO2 (((REG32(ADR_INFO2)) & 0xffffffff ) >> 0)
+#define GET_INFO3 (((REG32(ADR_INFO3)) & 0xffffffff ) >> 0)
+#define GET_INFO4 (((REG32(ADR_INFO4)) & 0xffffffff ) >> 0)
+#define GET_INFO5 (((REG32(ADR_INFO5)) & 0xffffffff ) >> 0)
+#define GET_INFO6 (((REG32(ADR_INFO6)) & 0xffffffff ) >> 0)
+#define GET_INFO7 (((REG32(ADR_INFO7)) & 0xffffffff ) >> 0)
+#define GET_INFO8 (((REG32(ADR_INFO8)) & 0xffffffff ) >> 0)
+#define GET_INFO9 (((REG32(ADR_INFO9)) & 0xffffffff ) >> 0)
+#define GET_INFO10 (((REG32(ADR_INFO10)) & 0xffffffff ) >> 0)
+#define GET_INFO11 (((REG32(ADR_INFO11)) & 0xffffffff ) >> 0)
+#define GET_INFO12 (((REG32(ADR_INFO12)) & 0xffffffff ) >> 0)
+#define GET_INFO13 (((REG32(ADR_INFO13)) & 0xffffffff ) >> 0)
+#define GET_INFO14 (((REG32(ADR_INFO14)) & 0xffffffff ) >> 0)
+#define GET_INFO15 (((REG32(ADR_INFO15)) & 0xffffffff ) >> 0)
+#define GET_INFO16 (((REG32(ADR_INFO16)) & 0xffffffff ) >> 0)
+#define GET_INFO17 (((REG32(ADR_INFO17)) & 0xffffffff ) >> 0)
+#define GET_INFO18 (((REG32(ADR_INFO18)) & 0xffffffff ) >> 0)
+#define GET_INFO19 (((REG32(ADR_INFO19)) & 0xffffffff ) >> 0)
+#define GET_INFO20 (((REG32(ADR_INFO20)) & 0xffffffff ) >> 0)
+#define GET_INFO21 (((REG32(ADR_INFO21)) & 0xffffffff ) >> 0)
+#define GET_INFO22 (((REG32(ADR_INFO22)) & 0xffffffff ) >> 0)
+#define GET_INFO23 (((REG32(ADR_INFO23)) & 0xffffffff ) >> 0)
+#define GET_INFO24 (((REG32(ADR_INFO24)) & 0xffffffff ) >> 0)
+#define GET_INFO25 (((REG32(ADR_INFO25)) & 0xffffffff ) >> 0)
+#define GET_INFO26 (((REG32(ADR_INFO26)) & 0xffffffff ) >> 0)
+#define GET_INFO27 (((REG32(ADR_INFO27)) & 0xffffffff ) >> 0)
+#define GET_INFO28 (((REG32(ADR_INFO28)) & 0xffffffff ) >> 0)
+#define GET_INFO29 (((REG32(ADR_INFO29)) & 0xffffffff ) >> 0)
+#define GET_INFO30 (((REG32(ADR_INFO30)) & 0xffffffff ) >> 0)
+#define GET_INFO31 (((REG32(ADR_INFO31)) & 0xffffffff ) >> 0)
+#define GET_INFO32 (((REG32(ADR_INFO32)) & 0xffffffff ) >> 0)
+#define GET_INFO33 (((REG32(ADR_INFO33)) & 0xffffffff ) >> 0)
+#define GET_INFO34 (((REG32(ADR_INFO34)) & 0xffffffff ) >> 0)
+#define GET_INFO35 (((REG32(ADR_INFO35)) & 0xffffffff ) >> 0)
+#define GET_INFO36 (((REG32(ADR_INFO36)) & 0xffffffff ) >> 0)
+#define GET_INFO37 (((REG32(ADR_INFO37)) & 0xffffffff ) >> 0)
+#define GET_INFO38 (((REG32(ADR_INFO38)) & 0xffffffff ) >> 0)
+#define GET_INFO_MASK (((REG32(ADR_INFO_MASK)) & 0xffffffff ) >> 0)
+#define GET_INFO_DEF_RATE (((REG32(ADR_INFO_RATE_OFFSET)) & 0x0000003f ) >> 0)
+#define GET_INFO_MRX_OFFSET (((REG32(ADR_INFO_RATE_OFFSET)) & 0x000f0000 ) >> 16)
+#define GET_BCAST_RATEUNKNOW (((REG32(ADR_INFO_RATE_OFFSET)) & 0x3f000000 ) >> 24)
+#define GET_INFO_IDX_TBL_ADDR (((REG32(ADR_INFO_IDX_ADDR)) & 0xffffffff ) >> 0)
+#define GET_INFO_LEN_TBL_ADDR (((REG32(ADR_INFO_LEN_ADDR)) & 0xffffffff ) >> 0)
+#define GET_IC_TAG_31_0 (((REG32(ADR_IC_TIME_TAG_0)) & 0xffffffff ) >> 0)
+#define GET_IC_TAG_63_32 (((REG32(ADR_IC_TIME_TAG_1)) & 0xffffffff ) >> 0)
+#define GET_CH1_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000003 ) >> 0)
+#define GET_CH2_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000300 ) >> 8)
+#define GET_CH3_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00030000 ) >> 16)
+#define GET_RG_MAC_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000001 ) >> 0)
+#define GET_RG_MAC_M2M (((REG32(ADR_MAC_MODE)) & 0x00000002 ) >> 1)
+#define GET_RG_PHY_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000004 ) >> 2)
+#define GET_RG_LPBK_RX_EN (((REG32(ADR_MAC_MODE)) & 0x00000008 ) >> 3)
+#define GET_EXT_MAC_MODE (((REG32(ADR_MAC_MODE)) & 0x00000010 ) >> 4)
+#define GET_EXT_PHY_MODE (((REG32(ADR_MAC_MODE)) & 0x00000020 ) >> 5)
+#define GET_ASIC_TAG (((REG32(ADR_MAC_MODE)) & 0xff000000 ) >> 24)
+#define GET_HCI_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_CHST_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_BCN_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MRX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_AMPDU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_MMU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
+#define GET_MBOX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00001000 ) >> 12)
+#define GET_SCRT_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
+#define GET_MIC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_CO_PROC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_CHST_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_BCN_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MRX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_AMPDU_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_ID_MNG_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_MBOX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
+#define GET_SCRT_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00010000 ) >> 16)
+#define GET_MIC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00020000 ) >> 17)
+#define GET_CO_PROC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE0_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_QUE1_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_QUE2_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MTX_QUE3_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_MTX_QUE4_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_MTX_QUE5_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
+#define GET_MRX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000400 ) >> 10)
+#define GET_AMPDU_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
+#define GET_SCRT_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
+#define GET_ID_MNG_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_MBOX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
+#define GET_HCI_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_MRX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_AMPDU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_MMU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
+#define GET_ID_MNG_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
+#define GET_MBOX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_SCRT_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_MIC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_MIB_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_HCI_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_MRX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_AMPDU_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_ID_MNG_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_MBOX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_SCRT_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_MIC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_CO_PROC_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MRX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_AMPDU_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_SCRT_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_ID_MNG_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_MBOX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_OP_MODE (((REG32(ADR_GLBLE_SET)) & 0x00000003 ) >> 0)
+#define GET_HT_MODE (((REG32(ADR_GLBLE_SET)) & 0x0000000c ) >> 2)
+#define GET_QOS_EN (((REG32(ADR_GLBLE_SET)) & 0x00000010 ) >> 4)
+#define GET_PB_OFFSET (((REG32(ADR_GLBLE_SET)) & 0x0000ff00 ) >> 8)
+#define GET_SNIFFER_MODE (((REG32(ADR_GLBLE_SET)) & 0x00010000 ) >> 16)
+#define GET_DUP_FLT (((REG32(ADR_GLBLE_SET)) & 0x00020000 ) >> 17)
+#define GET_TX_PKT_RSVD (((REG32(ADR_GLBLE_SET)) & 0x001c0000 ) >> 18)
+#define GET_AMPDU_SNIFFER (((REG32(ADR_GLBLE_SET)) & 0x00200000 ) >> 21)
+#define GET_REASON_TRAP0 (((REG32(ADR_REASON_TRAP0)) & 0xffffffff ) >> 0)
+#define GET_REASON_TRAP1 (((REG32(ADR_REASON_TRAP1)) & 0xffffffff ) >> 0)
+#define GET_BSSID_31_0 (((REG32(ADR_BSSID_0)) & 0xffffffff ) >> 0)
+#define GET_BSSID_47_32 (((REG32(ADR_BSSID_1)) & 0x0000ffff ) >> 0)
+#define GET_SCRT_STATE (((REG32(ADR_SCRT_STATE)) & 0x0000000f ) >> 0)
+#define GET_STA_MAC_31_0 (((REG32(ADR_STA_MAC_0)) & 0xffffffff ) >> 0)
+#define GET_STA_MAC_47_32 (((REG32(ADR_STA_MAC_1)) & 0x0000ffff ) >> 0)
+#define GET_PAIR_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000007 ) >> 0)
+#define GET_GRP_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000038 ) >> 3)
+#define GET_SCRT_PKT_ID (((REG32(ADR_SCRT_SET)) & 0x00001fc0 ) >> 6)
+#define GET_SCRT_RPLY_IGNORE (((REG32(ADR_SCRT_SET)) & 0x00010000 ) >> 16)
+#define GET_COEXIST_EN (((REG32(ADR_BTCX0)) & 0x00000001 ) >> 0)
+#define GET_WIRE_MODE (((REG32(ADR_BTCX0)) & 0x0000000e ) >> 1)
+#define GET_WL_RX_PRI (((REG32(ADR_BTCX0)) & 0x00000010 ) >> 4)
+#define GET_WL_TX_PRI (((REG32(ADR_BTCX0)) & 0x00000020 ) >> 5)
+#define GET_GURAN_USE_EN (((REG32(ADR_BTCX0)) & 0x00000100 ) >> 8)
+#define GET_GURAN_USE_CTRL (((REG32(ADR_BTCX0)) & 0x00000200 ) >> 9)
+#define GET_BEACON_TIMEOUT_EN (((REG32(ADR_BTCX0)) & 0x00000400 ) >> 10)
+#define GET_WLAN_ACT_POL (((REG32(ADR_BTCX0)) & 0x00000800 ) >> 11)
+#define GET_DUAL_ANT_EN (((REG32(ADR_BTCX0)) & 0x00001000 ) >> 12)
+#define GET_TRSW_PHY_POL (((REG32(ADR_BTCX0)) & 0x00010000 ) >> 16)
+#define GET_WIFI_TX_SW_POL (((REG32(ADR_BTCX0)) & 0x00020000 ) >> 17)
+#define GET_WIFI_RX_SW_POL (((REG32(ADR_BTCX0)) & 0x00040000 ) >> 18)
+#define GET_BT_SW_POL (((REG32(ADR_BTCX0)) & 0x00080000 ) >> 19)
+#define GET_BT_PRI_SMP_TIME (((REG32(ADR_BTCX1)) & 0x000000ff ) >> 0)
+#define GET_BT_STA_SMP_TIME (((REG32(ADR_BTCX1)) & 0x0000ff00 ) >> 8)
+#define GET_BEACON_TIMEOUT (((REG32(ADR_BTCX1)) & 0x00ff0000 ) >> 16)
+#define GET_WLAN_REMAIN_TIME (((REG32(ADR_BTCX1)) & 0xff000000 ) >> 24)
+#define GET_SW_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000001 ) >> 0)
+#define GET_SW_WL_TX (((REG32(ADR_SWITCH_CTL)) & 0x00000002 ) >> 1)
+#define GET_SW_WL_RX (((REG32(ADR_SWITCH_CTL)) & 0x00000004 ) >> 2)
+#define GET_SW_BT_TRX (((REG32(ADR_SWITCH_CTL)) & 0x00000008 ) >> 3)
+#define GET_BT_TXBAR_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000010 ) >> 4)
+#define GET_BT_TXBAR_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000020 ) >> 5)
+#define GET_BT_BUSY_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000100 ) >> 8)
+#define GET_BT_BUSY_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000200 ) >> 9)
+#define GET_G0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000004 ) >> 2)
+#define GET_G0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000008 ) >> 3)
+#define GET_G1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000010 ) >> 4)
+#define GET_G1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000020 ) >> 5)
+#define GET_Q0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000040 ) >> 6)
+#define GET_Q0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000080 ) >> 7)
+#define GET_Q1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000100 ) >> 8)
+#define GET_Q1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000200 ) >> 9)
+#define GET_Q2_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000400 ) >> 10)
+#define GET_Q2_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000800 ) >> 11)
+#define GET_Q3_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00001000 ) >> 12)
+#define GET_Q3_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00002000 ) >> 13)
+#define GET_SCRT_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00004000 ) >> 14)
+#define GET_SCRT_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00008000 ) >> 15)
+#define GET_MISC_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00010000 ) >> 16)
+#define GET_MISC_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00020000 ) >> 17)
+#define GET_MTX_WSID0_SUCC (((REG32(ADR_MTX_WSID0_SUCC)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_FRM (((REG32(ADR_MTX_WSID0_FRM)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_RETRY (((REG32(ADR_MTX_WSID0_RETRY)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_TOTAL (((REG32(ADR_MTX_WSID0_TOTAL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_GRP (((REG32(ADR_MTX_GROUP)) & 0x000fffff ) >> 0)
+#define GET_MTX_FAIL (((REG32(ADR_MTX_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RETRY (((REG32(ADR_MTX_RETRY)) & 0x000fffff ) >> 0)
+#define GET_MTX_MULTI_RETRY (((REG32(ADR_MTX_MULTI_RETRY)) & 0x000fffff ) >> 0)
+#define GET_MTX_RTS_SUCC (((REG32(ADR_MTX_RTS_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RTS_FAIL (((REG32(ADR_MTX_RTS_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_ACK_FAIL (((REG32(ADR_MTX_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_FRM (((REG32(ADR_MTX_FRM)) & 0x000fffff ) >> 0)
+#define GET_MTX_ACK_TX (((REG32(ADR_MTX_ACK_TX)) & 0x0000ffff ) >> 0)
+#define GET_MTX_CTS_TX (((REG32(ADR_MTX_CTS_TX)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DUP (((REG32(ADR_MRX_DUP_FRM)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FRG (((REG32(ADR_MRX_FRG_FRM)) & 0x000fffff ) >> 0)
+#define GET_MRX_GRP (((REG32(ADR_MRX_GROUP_FRM)) & 0x000fffff ) >> 0)
+#define GET_MRX_FCS_ERR (((REG32(ADR_MRX_FCS_ERR)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FCS_SUC (((REG32(ADR_MRX_FCS_SUCC)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MISS (((REG32(ADR_MRX_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_ALC_FAIL (((REG32(ADR_MRX_ALC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DAT_NTF (((REG32(ADR_MRX_DAT_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_RTS_NTF (((REG32(ADR_MRX_RTS_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_CTS_NTF (((REG32(ADR_MRX_CTS_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_ACK_NTF (((REG32(ADR_MRX_ACK_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_BA_NTF (((REG32(ADR_MRX_BA_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DATA_NTF (((REG32(ADR_MRX_DATA_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MNG_NTF (((REG32(ADR_MRX_MNG_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DAT_CRC_NTF (((REG32(ADR_MRX_DAT_CRC_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_BAR_NTF (((REG32(ADR_MRX_BAR_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MB_MISS (((REG32(ADR_MRX_MB_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_NIDLE_MISS (((REG32(ADR_MRX_NIDLE_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_CSR_NTF (((REG32(ADR_MRX_CSR_NTF)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_SUCC (((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_FAIL (((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_ACK_SUCC (((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_ACK_FAIL (((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_SUCC (((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_FAIL (((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_ACK_SUCC (((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_ACK_FAIL (((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_SUCC (((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_FAIL (((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_ACK_SUCC (((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_ACK_FAIL (((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_SUCC (((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_FAIL (((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_ACK_SUCC (((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_ACK_FAIL (((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_SCRT_TKIP_CERR (((REG32(ADR_MIB_SCRT_TKIP0)) & 0x000fffff ) >> 0)
+#define GET_SCRT_TKIP_MIC_ERR (((REG32(ADR_MIB_SCRT_TKIP1)) & 0x000fffff ) >> 0)
+#define GET_SCRT_TKIP_RPLY (((REG32(ADR_MIB_SCRT_TKIP2)) & 0x000fffff ) >> 0)
+#define GET_SCRT_CCMP_RPLY (((REG32(ADR_MIB_SCRT_CCMP0)) & 0x000fffff ) >> 0)
+#define GET_SCRT_CCMP_CERR (((REG32(ADR_MIB_SCRT_CCMP1)) & 0x000fffff ) >> 0)
+#define GET_DBG_LEN_CRC_FAIL (((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_LEN_ALC_FAIL (((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_AMPDU_PASS (((REG32(ADR_DBG_AMPDU_PASS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_AMPDU_FAIL (((REG32(ADR_DBG_AMPDU_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_RXID_ALC_CNT_FAIL (((REG32(ADR_ID_ALC_FAIL1)) & 0x0000ffff ) >> 0)
+#define GET_RXID_ALC_LEN_FAIL (((REG32(ADR_ID_ALC_FAIL2)) & 0x0000ffff ) >> 0)
+#define GET_CBR_RG_EN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_TX_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_TX_PA_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_TX_DAC_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_RX_AGC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_RX_GAIN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_RFG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_PGAG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_CBR_RG_MODE (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_EN_TX_TRSW (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_EN_SX (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_CBR_RG_EN_RX_LNA (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_CBR_RG_EN_RX_MIXER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_CBR_RG_EN_RX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_EN_RX_LOBUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_CBR_RG_EN_RX_TZ (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_EN_RX_FILTER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_EN_RX_HPF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_EN_RX_RSSI (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_EN_ADC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_CBR_RG_EN_TX_MOD (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_EN_TX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_CBR_RG_EN_TX_DIV2_BUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_CBR_RG_EN_TX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_CBR_RG_EN_RX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_CBR_RG_SEL_DPLL_CLK (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_EN_TX_DPD (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_TX_TSSI (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_EN_RX_IQCAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_EN_TX_DAC_CAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_EN_TX_SELF_MIXER (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_EN_TX_DAC_OUT (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_EN_LDO_RX_FE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_EN_LDO_ABB (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_EN_LDO_AFE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_EN_SX_CHPLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_EN_SX_LOBFLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_IREF_RX (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_DCDC_MODE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_LDO_LEVEL_RX_FE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_LDO_LEVEL_ABB (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000038 ) >> 3)
+#define GET_CBR_RG_LDO_LEVEL_AFE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
+#define GET_CBR_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
+#define GET_CBR_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_CBR_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_DP_LDO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
+#define GET_CBR_RG_TX_LDO_TX_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_CBR_RG_BUCK_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x38000000 ) >> 27)
+#define GET_CBR_RG_EN_RX_PADSW (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_RX_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_RX_ABBCFIX (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_RX_ABBCTUNE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
+#define GET_CBR_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_RX_ABB_N_MODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_RX_EN_LOOPA (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_RX_FILTERI1ST (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_RX_FILTERI2ND (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_FILTERI3RD (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_RX_FILTERI_COURSE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_RX_FILTERVCM (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
+#define GET_CBR_RG_RX_HPF3M (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_RX_HPF300K (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_RX_HPFI (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
+#define GET_CBR_RG_RX_HPF_FINALCORNER (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
+#define GET_CBR_RG_RX_HPF_SETTLE1_C (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_RX_HPF_SETTLE1_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_HPF_SETTLE2_C (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_RX_HPF_SETTLE2_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_RX_HPF_VCMCON2 (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_RX_HPF_VCMCON (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
+#define GET_CBR_RG_RX_OUTVCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
+#define GET_CBR_RG_RX_TZI (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_RX_TZ_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
+#define GET_CBR_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
+#define GET_CBR_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_RX_ADCRSSI_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
+#define GET_CBR_RG_RX_REC_LPFCORNER (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
+#define GET_CBR_RG_RSSI_CLOCK_GATING (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_TXPGA_CAPSW (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_TXPGA_MAIN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
+#define GET_CBR_RG_TXPGA_STEER (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
+#define GET_CBR_RG_TXMOD_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_TXLPF_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_PACELL_EN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_PABIAS_CTRL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
+#define GET_CBR_RG_PABIAS_AB (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_TX_DIV_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_CBR_RG_TX_LOBUF_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_RX_SQDC (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_RX_DIV2_CORE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_RX_LOBUF (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
+#define GET_CBR_RG_TX_DPDGM_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
+#define GET_CBR_RG_TX_DPD_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
+#define GET_CBR_RG_TX_TSSI_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_TX_TSSI_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_TX_TSSI_TESTMODE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_TX_TSSI_TEST (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
+#define GET_CBR_RG_RX_HG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_HG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_HG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_HG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_MG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_MG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_MG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_MG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_LG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_LG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_LG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_LG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_ULG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_ULG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_ULG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_HPF1_FAST_SET_X (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_HPF1_FAST_SET_Y (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_HPF1_FAST_SET_Z (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_HPF_T1A (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_HPF_T1B (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000060 ) >> 5)
+#define GET_CBR_RG_HPF_T1C (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000180 ) >> 7)
+#define GET_CBR_RG_RX_LNA_TRI_SEL (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_CBR_RG_RX_LNA_SETTLE (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00001800 ) >> 11)
+#define GET_CBR_RG_ADC_CLKSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_ADC_DIBIAS (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_ADC_DIVR (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_ADC_DVCMI (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_ADC_SAMSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_ADC_STNBY (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_ADC_TESTMODE (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_ADC_TSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_CBR_RG_ADC_VRSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_DICMP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_DIOP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_CBR_RG_DACI1ST (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_TX_DACLPF_ICOURSE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_TX_DACLPF_IFINE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_TX_DACLPF_VCM (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_TX_DAC_IBIAS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_CBR_RG_TX_DAC_OS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
+#define GET_CBR_RG_TX_DAC_RCAL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_TX_DAC_TSEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_CBR_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_TXLPF_BYPASS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_TXLPF_BOOSTI (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_EN_SX_R3 (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_SX_CH (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_EN_SX_CHP (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_EN_SX_DIVCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_EN_SX_VCOBF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_EN_SX_VCO (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_EN_SX_MOD (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_EN_SX_LCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_EN_SX_DITHER (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_EN_SX_DELCAL (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_EN_SX_PC_BYPASS (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_SX_VT_MON (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_EN_SX_VT_MON_DG (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_EN_SX_DIV (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_EN_SX_LPF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_RFCTRL_F (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x00ffffff ) >> 0)
+#define GET_CBR_RG_SX_SEL_CP (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_SEL_CS (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0000000 ) >> 28)
+#define GET_CBR_RG_SX_RFCTRL_CH (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000007ff ) >> 0)
+#define GET_CBR_RG_SX_SEL_C3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x00007800 ) >> 11)
+#define GET_CBR_RG_SX_SEL_RS (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000f8000 ) >> 15)
+#define GET_CBR_RG_SX_SEL_R3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x01f00000 ) >> 20)
+#define GET_CBR_RG_SX_SEL_ICHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
+#define GET_CBR_RG_SX_SEL_PCHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
+#define GET_CBR_RG_SX_SEL_CHP_REGOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
+#define GET_CBR_RG_SX_CHP_IOST_POL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_SX_CHP_IOST (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
+#define GET_CBR_RG_SX_PFDSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_SX_PFD_SET (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_SX_PFD_SET1 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
+#define GET_CBR_RG_SX_PFD_SET2 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_SX_VBNCAS_SEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
+#define GET_CBR_RG_SX_PFD_RST_H (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
+#define GET_CBR_RG_SX_PFD_TRUP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
+#define GET_CBR_RG_SX_PFD_TRDN (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
+#define GET_CBR_RG_SX_PFD_TRSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_SX_VCOBA_R (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_SX_VCORSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
+#define GET_CBR_RG_SX_VCOCUSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
+#define GET_CBR_RG_SX_RXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
+#define GET_CBR_RG_SX_TXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
+#define GET_CBR_RG_SX_VCOBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
+#define GET_CBR_RG_SX_DIVBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_GNDR_SEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
+#define GET_CBR_RG_SX_DITHER_WEIGHT (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_SX_MOD_ERRCMP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_SX_MOD_ORDER (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_SX_SDM_D1 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_SX_SDM_D2 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_SDM_PASS (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_SX_RST_H_DIV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_SX_SDM_EDGE (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_SX_XO_GM (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
+#define GET_CBR_RG_SX_REFBYTWO (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_SX_XO_SWCAP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0003c000 ) >> 14)
+#define GET_CBR_RG_SX_SDMLUT_INV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_SX_LCKEN (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
+#define GET_CBR_RG_SX_PREVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
+#define GET_CBR_RG_SX_PSCONTERVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_MOD_ERR_DELAY (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_SX_MODDB (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_SX_CV_CURVE_SEL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_SX_SEL_DELAY (((REG32(ADR_CBR_SYN_LCK1)) & 0x0000007c ) >> 2)
+#define GET_CBR_RG_SX_REF_CYCLE (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000780 ) >> 7)
+#define GET_CBR_RG_SX_VCOBY16 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_SX_VCOBY32 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_SX_PH (((REG32(ADR_CBR_SYN_LCK1)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_SX_PL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_VT_MON_MODE (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_SX_VT_TH_HI (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_SX_VT_TH_LO (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_SX_VT_SET (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_SX_VT_MON_TMR (((REG32(ADR_CBR_SYN_LCK2)) & 0x00007fc0 ) >> 6)
+#define GET_CBR_RG_IDEAL_CYCLE (((REG32(ADR_CBR_SYN_LCK2)) & 0x0fff8000 ) >> 15)
+#define GET_CBR_RG_EN_DP_VT_MON (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_DP_VT_TH_HI (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_DP_VT_TH_LO (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_DP_VT_MON_TMR (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00003fe0 ) >> 5)
+#define GET_CBR_RG_DP_CK320BY2 (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_DELCTRL (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x001f8000 ) >> 15)
+#define GET_CBR_RG_DP_OD_TEST (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_DP_BBPLL_BP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_DP_BBPLL_ICP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_DP_BBPLL_IDUAL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_DP_BBPLL_OD_TEST (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
+#define GET_CBR_RG_DP_BBPLL_PD (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_DP_BBPLL_TESTSEL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
+#define GET_CBR_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
+#define GET_CBR_RG_DP_RP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_DP_RHP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_DP_DR3 (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_CBR_RG_DP_DCP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_CBR_RG_DP_DCS (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x78000000 ) >> 27)
+#define GET_CBR_RG_DP_FBDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x00000fff ) >> 0)
+#define GET_CBR_RG_DP_FODIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003ff000 ) >> 12)
+#define GET_CBR_RG_DP_REFDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00000 ) >> 22)
+#define GET_CBR_RG_IDACAI_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_EN_RCAL (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_RCAL_SPD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_RCAL_TMR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
+#define GET_CBR_RG_RCAL_CODE_CWR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_RCAL_CODE_CWD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
+#define GET_CBR_RG_SX_SUB_SEL_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_SX_SUB_SEL_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x000000fe ) >> 1)
+#define GET_CBR_RG_DP_BBPLL_BS_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_DP_BBPLL_BS_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00007e00 ) >> 9)
+#define GET_CBR_RCAL_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
+#define GET_CBR_DA_LCK_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
+#define GET_CBR_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
+#define GET_CBR_DP_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000008 ) >> 3)
+#define GET_CBR_CH_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000010 ) >> 4)
+#define GET_CBR_DA_R_CODE_LUT (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
+#define GET_CBR_AD_SX_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
+#define GET_CBR_AD_DP_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
+#define GET_CBR_DA_R_CAL_CODE (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
+#define GET_CBR_DA_SX_SUB_SEL (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
+#define GET_CBR_DA_DP_BBPLL_BS (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0003f000 ) >> 12)
+#define GET_CBR_TX_EN (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000001 ) >> 0)
+#define GET_CBR_TX_CNT_RST (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000002 ) >> 1)
+#define GET_CBR_IFS_TIME (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000000fc ) >> 2)
+#define GET_CBR_LENGTH_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000fff00 ) >> 8)
+#define GET_CBR_TX_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xff000000 ) >> 24)
+#define GET_CBR_TC_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0x00ffffff ) >> 0)
+#define GET_CBR_PLCP_PSDU_DATA_MEM (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x000000ff ) >> 0)
+#define GET_CBR_PLCP_PSDU_PREAMBLE_SHORT (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00000100 ) >> 8)
+#define GET_CBR_PLCP_BYTE_LENGTH (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x001ffe00 ) >> 9)
+#define GET_CBR_PLCP_PSDU_RATE (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00600000 ) >> 21)
+#define GET_CBR_TAIL_TIME (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x1f800000 ) >> 23)
+#define GET_CBR_RG_O_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_I_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000002 ) >> 1)
+#define GET_CBR_SEL_ADCKP_INV (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_PAD_DS (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000008 ) >> 3)
+#define GET_CBR_SEL_ADCKP_MUX (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_PAD_DS_CLK (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000020 ) >> 5)
+#define GET_CBR_INTP_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000200 ) >> 9)
+#define GET_CBR_IQ_SWP (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_EXT_DA (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_DIS_DA_OFFSET (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00001000 ) >> 12)
+#define GET_CBR_DBG_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x000f0000 ) >> 16)
+#define GET_CBR_DBG_EN (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_PKT_GEN_TX_CNT (((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0xffffffff ) >> 0)
+#define GET_CBR_TP_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x0000001f ) >> 0)
+#define GET_CBR_IDEAL_IQ_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000020 ) >> 5)
+#define GET_CBR_DATA_OUT_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x000001c0 ) >> 6)
+#define GET_CBR_TWO_TONE_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000200 ) >> 9)
+#define GET_CBR_FREQ_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ff0000 ) >> 16)
+#define GET_CBR_IQ_SCALE (((REG32(ADR_CBR_PATTERN_GEN)) & 0xff000000 ) >> 24)
+#define GET_CPU_QUE_POP (((REG32(ADR_MB_CPU_INT)) & 0x00000001 ) >> 0)
+#define GET_CPU_INT (((REG32(ADR_MB_CPU_INT)) & 0x00000004 ) >> 2)
+#define GET_CPU_ID_TB0 (((REG32(ADR_CPU_ID_TB0)) & 0xffffffff ) >> 0)
+#define GET_CPU_ID_TB1 (((REG32(ADR_CPU_ID_TB1)) & 0xffffffff ) >> 0)
+#define GET_HW_PKTID (((REG32(ADR_CH0_TRIG_1)) & 0x000007ff ) >> 0)
+#define GET_CH0_INT_ADDR (((REG32(ADR_CH0_TRIG_0)) & 0xffffffff ) >> 0)
+#define GET_PRI_HW_PKTID (((REG32(ADR_CH0_PRI_TRIG)) & 0x000007ff ) >> 0)
+#define GET_CH0_FULL (((REG32(ADR_MCU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_FF0_EMPTY (((REG32(ADR_MCU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_RLS_BUSY (((REG32(ADR_MCU_STATUS)) & 0x00000200 ) >> 9)
+#define GET_RLS_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000400 ) >> 10)
+#define GET_RTN_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000800 ) >> 11)
+#define GET_RLS_COUNT (((REG32(ADR_MCU_STATUS)) & 0x00ff0000 ) >> 16)
+#define GET_RTN_COUNT (((REG32(ADR_MCU_STATUS)) & 0xff000000 ) >> 24)
+#define GET_FF0_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x0000001f ) >> 0)
+#define GET_FF1_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000001e0 ) >> 5)
+#define GET_FF3_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00003800 ) >> 11)
+#define GET_FF5_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000e0000 ) >> 17)
+#define GET_FF6_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00700000 ) >> 20)
+#define GET_FF7_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x03800000 ) >> 23)
+#define GET_FF8_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x1c000000 ) >> 26)
+#define GET_FF9_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0xe0000000 ) >> 29)
+#define GET_FF10_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000007 ) >> 0)
+#define GET_FF11_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000038 ) >> 3)
+#define GET_FF12_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000001c0 ) >> 6)
+#define GET_FF13_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000600 ) >> 9)
+#define GET_FF14_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00001800 ) >> 11)
+#define GET_FF15_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00006000 ) >> 13)
+#define GET_FF4_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000f8000 ) >> 15)
+#define GET_FF2_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00700000 ) >> 20)
+#define GET_CH1_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000002 ) >> 1)
+#define GET_CH2_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000004 ) >> 2)
+#define GET_CH3_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000008 ) >> 3)
+#define GET_CH4_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000010 ) >> 4)
+#define GET_CH5_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000020 ) >> 5)
+#define GET_CH6_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000040 ) >> 6)
+#define GET_CH7_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000080 ) >> 7)
+#define GET_CH8_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000100 ) >> 8)
+#define GET_CH9_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000200 ) >> 9)
+#define GET_CH10_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000400 ) >> 10)
+#define GET_CH11_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000800 ) >> 11)
+#define GET_CH12_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00001000 ) >> 12)
+#define GET_CH13_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00002000 ) >> 13)
+#define GET_CH14_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00004000 ) >> 14)
+#define GET_CH15_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00008000 ) >> 15)
+#define GET_HALT_CH0 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000001 ) >> 0)
+#define GET_HALT_CH1 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000002 ) >> 1)
+#define GET_HALT_CH2 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000004 ) >> 2)
+#define GET_HALT_CH3 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000008 ) >> 3)
+#define GET_HALT_CH4 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000010 ) >> 4)
+#define GET_HALT_CH5 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000020 ) >> 5)
+#define GET_HALT_CH6 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000040 ) >> 6)
+#define GET_HALT_CH7 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000080 ) >> 7)
+#define GET_HALT_CH8 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000100 ) >> 8)
+#define GET_HALT_CH9 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000200 ) >> 9)
+#define GET_HALT_CH10 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000400 ) >> 10)
+#define GET_HALT_CH11 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000800 ) >> 11)
+#define GET_HALT_CH12 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00001000 ) >> 12)
+#define GET_HALT_CH13 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00002000 ) >> 13)
+#define GET_HALT_CH14 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00004000 ) >> 14)
+#define GET_HALT_CH15 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00008000 ) >> 15)
+#define GET_STOP_MBOX (((REG32(ADR_MBOX_HALT_CFG)) & 0x00010000 ) >> 16)
+#define GET_MB_ERR_AUTO_HALT_EN (((REG32(ADR_MBOX_HALT_CFG)) & 0x00100000 ) >> 20)
+#define GET_MB_EXCEPT_CLR (((REG32(ADR_MBOX_HALT_CFG)) & 0x00200000 ) >> 21)
+#define GET_MB_EXCEPT_CASE (((REG32(ADR_MBOX_HALT_CFG)) & 0xff000000 ) >> 24)
+#define GET_MB_DBG_TIME_STEP (((REG32(ADR_MB_DBG_CFG1)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TYPE (((REG32(ADR_MB_DBG_CFG1)) & 0x00030000 ) >> 16)
+#define GET_MB_DBG_CLR (((REG32(ADR_MB_DBG_CFG1)) & 0x00040000 ) >> 18)
+#define GET_DBG_ALC_LOG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x00080000 ) >> 19)
+#define GET_MB_DBG_COUNTER_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x01000000 ) >> 24)
+#define GET_MB_DBG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x80000000 ) >> 31)
+#define GET_MB_DBG_RECORD_CNT (((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff ) >> 0)
+#define GET_MB_DBG_LENGTH (((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000 ) >> 16)
+#define GET_MB_DBG_CFG_ADDR (((REG32(ADR_MB_DBG_CFG3)) & 0xffffffff ) >> 0)
+#define GET_DBG_HWID0_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000001 ) >> 0)
+#define GET_DBG_HWID1_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000002 ) >> 1)
+#define GET_DBG_HWID2_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000004 ) >> 2)
+#define GET_DBG_HWID3_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000008 ) >> 3)
+#define GET_DBG_HWID4_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000010 ) >> 4)
+#define GET_DBG_HWID5_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000020 ) >> 5)
+#define GET_DBG_HWID6_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000040 ) >> 6)
+#define GET_DBG_HWID7_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000080 ) >> 7)
+#define GET_DBG_HWID8_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000100 ) >> 8)
+#define GET_DBG_HWID9_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000200 ) >> 9)
+#define GET_DBG_HWID10_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000400 ) >> 10)
+#define GET_DBG_HWID11_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000800 ) >> 11)
+#define GET_DBG_HWID12_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00001000 ) >> 12)
+#define GET_DBG_HWID13_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00002000 ) >> 13)
+#define GET_DBG_HWID14_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00004000 ) >> 14)
+#define GET_DBG_HWID15_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00008000 ) >> 15)
+#define GET_DBG_HWID0_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00010000 ) >> 16)
+#define GET_DBG_HWID1_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00020000 ) >> 17)
+#define GET_DBG_HWID2_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00040000 ) >> 18)
+#define GET_DBG_HWID3_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00080000 ) >> 19)
+#define GET_DBG_HWID4_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00100000 ) >> 20)
+#define GET_DBG_HWID5_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00200000 ) >> 21)
+#define GET_DBG_HWID6_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00400000 ) >> 22)
+#define GET_DBG_HWID7_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00800000 ) >> 23)
+#define GET_DBG_HWID8_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x01000000 ) >> 24)
+#define GET_DBG_HWID9_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x02000000 ) >> 25)
+#define GET_DBG_HWID10_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x04000000 ) >> 26)
+#define GET_DBG_HWID11_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x08000000 ) >> 27)
+#define GET_DBG_HWID12_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x10000000 ) >> 28)
+#define GET_DBG_HWID13_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x20000000 ) >> 29)
+#define GET_DBG_HWID14_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x40000000 ) >> 30)
+#define GET_DBG_HWID15_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x80000000 ) >> 31)
+#define GET_MB_OUT_QUEUE_EN (((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0x00000002 ) >> 1)
+#define GET_CH0_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000001 ) >> 0)
+#define GET_CH1_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000002 ) >> 1)
+#define GET_CH2_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000004 ) >> 2)
+#define GET_CH3_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000008 ) >> 3)
+#define GET_CH4_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000010 ) >> 4)
+#define GET_CH5_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000020 ) >> 5)
+#define GET_CH6_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000040 ) >> 6)
+#define GET_CH7_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000080 ) >> 7)
+#define GET_CH8_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000100 ) >> 8)
+#define GET_CH9_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000200 ) >> 9)
+#define GET_CH10_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000400 ) >> 10)
+#define GET_CH11_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000800 ) >> 11)
+#define GET_CH12_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00001000 ) >> 12)
+#define GET_CH13_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00002000 ) >> 13)
+#define GET_CH14_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00004000 ) >> 14)
+#define GET_CH15_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00008000 ) >> 15)
+#define GET_FFO0_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0000001f ) >> 0)
+#define GET_FFO1_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000003e0 ) >> 5)
+#define GET_FFO2_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00000c00 ) >> 10)
+#define GET_FFO3_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000f8000 ) >> 15)
+#define GET_FFO4_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00300000 ) >> 20)
+#define GET_FFO5_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0e000000 ) >> 25)
+#define GET_FFO6_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x0000000f ) >> 0)
+#define GET_FFO7_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000003e0 ) >> 5)
+#define GET_FFO8_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00007c00 ) >> 10)
+#define GET_FFO9_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000f8000 ) >> 15)
+#define GET_FFO10_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00f00000 ) >> 20)
+#define GET_FFO11_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x3e000000 ) >> 25)
+#define GET_FFO12_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000007 ) >> 0)
+#define GET_FFO13_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000060 ) >> 5)
+#define GET_FFO14_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000c00 ) >> 10)
+#define GET_FFO15_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x001f8000 ) >> 15)
+#define GET_CH0_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000001 ) >> 0)
+#define GET_CH1_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000002 ) >> 1)
+#define GET_CH2_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000004 ) >> 2)
+#define GET_CH3_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000008 ) >> 3)
+#define GET_CH4_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000010 ) >> 4)
+#define GET_CH5_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000020 ) >> 5)
+#define GET_CH6_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000040 ) >> 6)
+#define GET_CH7_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000080 ) >> 7)
+#define GET_CH8_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000100 ) >> 8)
+#define GET_CH9_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000200 ) >> 9)
+#define GET_CH10_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000400 ) >> 10)
+#define GET_CH11_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000800 ) >> 11)
+#define GET_CH12_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00001000 ) >> 12)
+#define GET_CH13_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00002000 ) >> 13)
+#define GET_CH14_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00004000 ) >> 14)
+#define GET_CH15_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00008000 ) >> 15)
+#define GET_CH0_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000001 ) >> 0)
+#define GET_CH1_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000002 ) >> 1)
+#define GET_CH2_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000004 ) >> 2)
+#define GET_CH3_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000008 ) >> 3)
+#define GET_CH4_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000010 ) >> 4)
+#define GET_CH5_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000020 ) >> 5)
+#define GET_CH6_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000040 ) >> 6)
+#define GET_CH7_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000080 ) >> 7)
+#define GET_CH8_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000100 ) >> 8)
+#define GET_CH9_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000200 ) >> 9)
+#define GET_CH10_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000400 ) >> 10)
+#define GET_CH11_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000800 ) >> 11)
+#define GET_CH12_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00001000 ) >> 12)
+#define GET_CH13_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00002000 ) >> 13)
+#define GET_CH14_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00004000 ) >> 14)
+#define GET_CH15_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00008000 ) >> 15)
+#define GET_MB_LOW_THOLD_EN (((REG32(ADR_MB_THRESHOLD6)) & 0x80000000 ) >> 31)
+#define GET_CH0_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x0000001f ) >> 0)
+#define GET_CH1_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x00001f00 ) >> 8)
+#define GET_CH2_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x001f0000 ) >> 16)
+#define GET_CH3_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x1f000000 ) >> 24)
+#define GET_CH4_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x0000001f ) >> 0)
+#define GET_CH5_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x00001f00 ) >> 8)
+#define GET_CH6_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x001f0000 ) >> 16)
+#define GET_CH7_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x1f000000 ) >> 24)
+#define GET_CH8_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x0000001f ) >> 0)
+#define GET_CH9_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x00001f00 ) >> 8)
+#define GET_CH10_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x001f0000 ) >> 16)
+#define GET_CH11_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x1f000000 ) >> 24)
+#define GET_CH12_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x0000001f ) >> 0)
+#define GET_CH13_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x00001f00 ) >> 8)
+#define GET_CH14_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x001f0000 ) >> 16)
+#define GET_CH15_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x1f000000 ) >> 24)
+#define GET_TRASH_TIMEOUT_EN (((REG32(ADR_MB_TRASH_CFG)) & 0x00000001 ) >> 0)
+#define GET_TRASH_CAN_INT (((REG32(ADR_MB_TRASH_CFG)) & 0x00000002 ) >> 1)
+#define GET_TRASH_INT_ID (((REG32(ADR_MB_TRASH_CFG)) & 0x000007f0 ) >> 4)
+#define GET_TRASH_TIMEOUT (((REG32(ADR_MB_TRASH_CFG)) & 0x03ff0000 ) >> 16)
+#define GET_CH0_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000001 ) >> 0)
+#define GET_CH1_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000002 ) >> 1)
+#define GET_CH2_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000004 ) >> 2)
+#define GET_CH3_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000008 ) >> 3)
+#define GET_CH4_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000010 ) >> 4)
+#define GET_CH5_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000020 ) >> 5)
+#define GET_CH6_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000040 ) >> 6)
+#define GET_CH7_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000080 ) >> 7)
+#define GET_CH8_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000100 ) >> 8)
+#define GET_CH9_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000200 ) >> 9)
+#define GET_CH10_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000400 ) >> 10)
+#define GET_CH11_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000800 ) >> 11)
+#define GET_CH12_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00001000 ) >> 12)
+#define GET_CH13_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00002000 ) >> 13)
+#define GET_CH14_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00004000 ) >> 14)
+#define GET_CPU_ID_TB2 (((REG32(ADR_CPU_ID_TB2)) & 0xffffffff ) >> 0)
+#define GET_CPU_ID_TB3 (((REG32(ADR_CPU_ID_TB3)) & 0xffffffff ) >> 0)
+#define GET_IQ_LOG_EN (((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0x00000001 ) >> 0)
+#define GET_IQ_LOG_STOP_MODE (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000001 ) >> 0)
+#define GET_GPIO_STOP_EN (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000010 ) >> 4)
+#define GET_GPIO_STOP_POL (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000020 ) >> 5)
+#define GET_IQ_LOG_TIMER (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffff0000 ) >> 16)
+#define GET_IQ_LOG_LEN (((REG32(ADR_PHY_IQ_LOG_LEN)) & 0x0000ffff ) >> 0)
+#define GET_IQ_LOG_TAIL_ADR (((REG32(ADR_PHY_IQ_LOG_PTR)) & 0x0000ffff ) >> 0)
+#define GET_ALC_LENG (((REG32(ADR_WR_ALC)) & 0x0003ffff ) >> 0)
+#define GET_CH0_DYN_PRI (((REG32(ADR_WR_ALC)) & 0x00300000 ) >> 20)
+#define GET_MCU_PKTID (((REG32(ADR_GETID)) & 0xffffffff ) >> 0)
+#define GET_CH0_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000003 ) >> 0)
+#define GET_CH1_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000030 ) >> 4)
+#define GET_CH2_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000300 ) >> 8)
+#define GET_CH3_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00003000 ) >> 12)
+#define GET_ID_TB0 (((REG32(ADR_RD_ID0)) & 0xffffffff ) >> 0)
+#define GET_ID_TB1 (((REG32(ADR_RD_ID1)) & 0xffffffff ) >> 0)
+#define GET_ID_MNG_HALT (((REG32(ADR_IMD_CFG)) & 0x00000010 ) >> 4)
+#define GET_ID_MNG_ERR_HALT_EN (((REG32(ADR_IMD_CFG)) & 0x00000020 ) >> 5)
+#define GET_ID_EXCEPT_FLG_CLR (((REG32(ADR_IMD_CFG)) & 0x00000040 ) >> 6)
+#define GET_ID_EXCEPT_FLG (((REG32(ADR_IMD_CFG)) & 0x00000080 ) >> 7)
+#define GET_ID_FULL (((REG32(ADR_IMD_STA)) & 0x00000001 ) >> 0)
+#define GET_ID_MNG_BUSY (((REG32(ADR_IMD_STA)) & 0x00000002 ) >> 1)
+#define GET_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000004 ) >> 2)
+#define GET_CH0_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000010 ) >> 4)
+#define GET_CH1_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000020 ) >> 5)
+#define GET_CH2_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000040 ) >> 6)
+#define GET_CH3_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000080 ) >> 7)
+#define GET_REQ_LOCK_INT_EN (((REG32(ADR_IMD_STA)) & 0x00000100 ) >> 8)
+#define GET_REQ_LOCK_INT (((REG32(ADR_IMD_STA)) & 0x00000200 ) >> 9)
+#define GET_MCU_ALC_READY (((REG32(ADR_ALC_STA)) & 0x00000001 ) >> 0)
+#define GET_ALC_FAIL (((REG32(ADR_ALC_STA)) & 0x00000002 ) >> 1)
+#define GET_ALC_BUSY (((REG32(ADR_ALC_STA)) & 0x00000004 ) >> 2)
+#define GET_CH0_NVLD (((REG32(ADR_ALC_STA)) & 0x00000010 ) >> 4)
+#define GET_CH1_NVLD (((REG32(ADR_ALC_STA)) & 0x00000020 ) >> 5)
+#define GET_CH2_NVLD (((REG32(ADR_ALC_STA)) & 0x00000040 ) >> 6)
+#define GET_CH3_NVLD (((REG32(ADR_ALC_STA)) & 0x00000080 ) >> 7)
+#define GET_ALC_INT_ID (((REG32(ADR_ALC_STA)) & 0x00007f00 ) >> 8)
+#define GET_ALC_TIMEOUT (((REG32(ADR_ALC_STA)) & 0x03ff0000 ) >> 16)
+#define GET_ALC_TIMEOUT_INT_EN (((REG32(ADR_ALC_STA)) & 0x40000000 ) >> 30)
+#define GET_ALC_TIMEOUT_INT (((REG32(ADR_ALC_STA)) & 0x80000000 ) >> 31)
+#define GET_TX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x000000ff ) >> 0)
+#define GET_RX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x0000ff00 ) >> 8)
+#define GET_TX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000000ff ) >> 0)
+#define GET_RX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x0000ff00 ) >> 8)
+#define GET_ID_THOLD_RX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00010000 ) >> 16)
+#define GET_RX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000e0000 ) >> 17)
+#define GET_ID_THOLD_TX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00100000 ) >> 20)
+#define GET_TX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00e00000 ) >> 21)
+#define GET_ID_THOLD_INT_EN (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x01000000 ) >> 24)
+#define GET_TX_ID_TB0 (((REG32(ADR_TX_ID0)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB1 (((REG32(ADR_TX_ID1)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB0 (((REG32(ADR_RX_ID0)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB1 (((REG32(ADR_RX_ID1)) & 0xffffffff ) >> 0)
+#define GET_DOUBLE_RLS_INT_EN (((REG32(ADR_RTN_STA)) & 0x00000001 ) >> 0)
+#define GET_ID_DOUBLE_RLS_INT (((REG32(ADR_RTN_STA)) & 0x00000002 ) >> 1)
+#define GET_DOUBLE_RLS_ID (((REG32(ADR_RTN_STA)) & 0x00007f00 ) >> 8)
+#define GET_ID_LEN_THOLD_INT_EN (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000001 ) >> 0)
+#define GET_ALL_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000002 ) >> 1)
+#define GET_TX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000004 ) >> 2)
+#define GET_RX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000008 ) >> 3)
+#define GET_ID_TX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00001ff0 ) >> 4)
+#define GET_ID_RX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x003fe000 ) >> 13)
+#define GET_ID_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x7fc00000 ) >> 22)
+#define GET_ALL_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x0003fe00 ) >> 9)
+#define GET_RX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x07fc0000 ) >> 18)
+#define GET_CH_ARB_EN (((REG32(ADR_CH_ARB_PRI)) & 0x00000001 ) >> 0)
+#define GET_CH_PRI1 (((REG32(ADR_CH_ARB_PRI)) & 0x00000030 ) >> 4)
+#define GET_CH_PRI2 (((REG32(ADR_CH_ARB_PRI)) & 0x00000300 ) >> 8)
+#define GET_CH_PRI3 (((REG32(ADR_CH_ARB_PRI)) & 0x00003000 ) >> 12)
+#define GET_CH_PRI4 (((REG32(ADR_CH_ARB_PRI)) & 0x00030000 ) >> 16)
+#define GET_TX_ID_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0000007f ) >> 0)
+#define GET_TX_PAGE_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0001ff00 ) >> 8)
+#define GET_ID_PAGE_MAX_SIZE (((REG32(ADR_ID_INFO_STA)) & 0x000001ff ) >> 0)
+#define GET_TX_PAGE_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x000001ff ) >> 0)
+#define GET_TX_COUNT_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x00ff0000 ) >> 16)
+#define GET_TX_LIMIT_INT (((REG32(ADR_TX_LIMIT_INTR)) & 0x40000000 ) >> 30)
+#define GET_TX_LIMIT_INT_EN (((REG32(ADR_TX_LIMIT_INTR)) & 0x80000000 ) >> 31)
+#define GET_TX_PAGE_USE_7_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x000000ff ) >> 0)
+#define GET_TX_ID_USE_5_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x00003f00 ) >> 8)
+#define GET_EDCA0_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x0003c000 ) >> 14)
+#define GET_EDCA1_FFO_CNT_3_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x003c0000 ) >> 18)
+#define GET_EDCA2_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x07c00000 ) >> 22)
+#define GET_EDCA3_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0xf8000000 ) >> 27)
+#define GET_ID_TB2 (((REG32(ADR_RD_ID2)) & 0xffffffff ) >> 0)
+#define GET_ID_TB3 (((REG32(ADR_RD_ID3)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB2 (((REG32(ADR_TX_ID2)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB3 (((REG32(ADR_TX_ID3)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB2 (((REG32(ADR_RX_ID2)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB3 (((REG32(ADR_RX_ID3)) & 0xffffffff ) >> 0)
+#define GET_TX_PAGE_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA4_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x001e0000 ) >> 17)
+#define GET_TX_PAGE_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA1_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x03e00000 ) >> 21)
+#define GET_EDCA4_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x3c000000 ) >> 26)
+#define GET_TX_PAGE_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA2_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x003e0000 ) >> 17)
+#define GET_EDCA3_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x07c00000 ) >> 22)
+#define GET_TX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x000001ff ) >> 0)
+#define GET_RX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x01ff0000 ) >> 16)
+#define GET_MAX_ALL_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x000000ff ) >> 0)
+#define GET_MAX_TX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x0000ff00 ) >> 8)
+#define GET_MAX_RX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x00ff0000 ) >> 16)
+#define GET_MAX_ALL_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x000001ff ) >> 0)
+#define GET_MAX_TX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x0003fe00 ) >> 9)
+#define GET_MAX_RX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x07fc0000 ) >> 18)
+#define GET_RG_PMDLBK (((REG32(ADR_PHY_EN_0)) & 0x00000001 ) >> 0)
+#define GET_RG_RDYACK_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000006 ) >> 1)
+#define GET_RG_ADEDGE_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000008 ) >> 3)
+#define GET_RG_SIGN_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000010 ) >> 4)
+#define GET_RG_IQ_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000020 ) >> 5)
+#define GET_RG_Q_INV (((REG32(ADR_PHY_EN_0)) & 0x00000040 ) >> 6)
+#define GET_RG_I_INV (((REG32(ADR_PHY_EN_0)) & 0x00000080 ) >> 7)
+#define GET_RG_BYPASS_ACI (((REG32(ADR_PHY_EN_0)) & 0x00000100 ) >> 8)
+#define GET_RG_LBK_ANA_PATH (((REG32(ADR_PHY_EN_0)) & 0x00000200 ) >> 9)
+#define GET_RG_SPECTRUM_LEAKY_FACTOR (((REG32(ADR_PHY_EN_0)) & 0x00000c00 ) >> 10)
+#define GET_RG_SPECTRUM_BW (((REG32(ADR_PHY_EN_0)) & 0x00003000 ) >> 12)
+#define GET_RG_SPECTRUM_FREQ_MANUAL (((REG32(ADR_PHY_EN_0)) & 0x00004000 ) >> 14)
+#define GET_RG_SPECTRUM_EN (((REG32(ADR_PHY_EN_0)) & 0x00008000 ) >> 15)
+#define GET_RG_TXPWRLVL_SET (((REG32(ADR_PHY_EN_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TXPWRLVL_SEL (((REG32(ADR_PHY_EN_0)) & 0x01000000 ) >> 24)
+#define GET_RG_RF_BB_CLK_SEL (((REG32(ADR_PHY_EN_0)) & 0x80000000 ) >> 31)
+#define GET_RG_PHY_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000001 ) >> 0)
+#define GET_RG_PHYRX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000002 ) >> 1)
+#define GET_RG_PHYTX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000004 ) >> 2)
+#define GET_RG_PHY11GN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000008 ) >> 3)
+#define GET_RG_PHY11B_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000010 ) >> 4)
+#define GET_RG_PHYRXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000020 ) >> 5)
+#define GET_RG_PHYTXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000040 ) >> 6)
+#define GET_RG_PHY11BGN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000100 ) >> 8)
+#define GET_RG_FORCE_11GN_EN (((REG32(ADR_PHY_EN_1)) & 0x00001000 ) >> 12)
+#define GET_RG_FORCE_11B_EN (((REG32(ADR_PHY_EN_1)) & 0x00002000 ) >> 13)
+#define GET_RG_FFT_MEM_CLK_EN_RX (((REG32(ADR_PHY_EN_1)) & 0x00004000 ) >> 14)
+#define GET_RG_FFT_MEM_CLK_EN_TX (((REG32(ADR_PHY_EN_1)) & 0x00008000 ) >> 15)
+#define GET_RG_PHY_IQ_TRIG_SEL (((REG32(ADR_PHY_EN_1)) & 0x000f0000 ) >> 16)
+#define GET_RG_SPECTRUM_FREQ (((REG32(ADR_PHY_EN_1)) & 0x3ff00000 ) >> 20)
+#define GET_SVN_VERSION (((REG32(ADR_SVN_VERSION_REG)) & 0xffffffff ) >> 0)
+#define GET_RG_LENGTH (((REG32(ADR_PHY_PKT_GEN_0)) & 0x0000ffff ) >> 0)
+#define GET_RG_PKT_MODE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00070000 ) >> 16)
+#define GET_RG_CH_BW (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00380000 ) >> 19)
+#define GET_RG_PRM (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00400000 ) >> 22)
+#define GET_RG_SHORTGI (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00800000 ) >> 23)
+#define GET_RG_RATE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_L_LENGTH (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00000fff ) >> 0)
+#define GET_RG_L_RATE (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00007000 ) >> 12)
+#define GET_RG_SERVICE (((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff0000 ) >> 16)
+#define GET_RG_SMOOTHING (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000001 ) >> 0)
+#define GET_RG_NO_SOUND (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000002 ) >> 1)
+#define GET_RG_AGGREGATE (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000004 ) >> 2)
+#define GET_RG_STBC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000018 ) >> 3)
+#define GET_RG_FEC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000020 ) >> 5)
+#define GET_RG_N_ESS (((REG32(ADR_PHY_PKT_GEN_2)) & 0x000000c0 ) >> 6)
+#define GET_RG_TXPWRLVL (((REG32(ADR_PHY_PKT_GEN_2)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TX_START (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000001 ) >> 0)
+#define GET_RG_IFS_TIME (((REG32(ADR_PHY_PKT_GEN_3)) & 0x000000fc ) >> 2)
+#define GET_RG_CONTINUOUS_DATA (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000100 ) >> 8)
+#define GET_RG_DATA_SEL (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000600 ) >> 9)
+#define GET_RG_TX_D (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_CNT_TARGET (((REG32(ADR_PHY_PKT_GEN_4)) & 0xffffffff ) >> 0)
+#define GET_RG_FFT_IFFT_MODE (((REG32(ADR_PHY_REG_00)) & 0x000000c0 ) >> 6)
+#define GET_RG_DAC_DBG_MODE (((REG32(ADR_PHY_REG_00)) & 0x00000100 ) >> 8)
+#define GET_RG_DAC_SGN_SWAP (((REG32(ADR_PHY_REG_00)) & 0x00000200 ) >> 9)
+#define GET_RG_TXD_SEL (((REG32(ADR_PHY_REG_00)) & 0x00000c00 ) >> 10)
+#define GET_RG_UP8X (((REG32(ADR_PHY_REG_00)) & 0x00ff0000 ) >> 16)
+#define GET_RG_IQ_DC_BYP (((REG32(ADR_PHY_REG_00)) & 0x01000000 ) >> 24)
+#define GET_RG_IQ_DC_LEAKY_FACTOR (((REG32(ADR_PHY_REG_00)) & 0x30000000 ) >> 28)
+#define GET_RG_DAC_DCEN (((REG32(ADR_PHY_REG_01)) & 0x00000001 ) >> 0)
+#define GET_RG_DAC_DCQ (((REG32(ADR_PHY_REG_01)) & 0x00003ff0 ) >> 4)
+#define GET_RG_DAC_DCI (((REG32(ADR_PHY_REG_01)) & 0x03ff0000 ) >> 16)
+#define GET_RG_PGA_REFDB_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0x0000007f ) >> 0)
+#define GET_RG_PGA_REFDB_TOP (((REG32(ADR_PHY_REG_02_AGC)) & 0x00007f00 ) >> 8)
+#define GET_RG_PGA_REF_UND (((REG32(ADR_PHY_REG_02_AGC)) & 0x03ff0000 ) >> 16)
+#define GET_RG_RF_REF_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0xf0000000 ) >> 28)
+#define GET_RG_PGAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_PGAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000010 ) >> 4)
+#define GET_RG_RFGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000060 ) >> 5)
+#define GET_RG_RFGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000080 ) >> 7)
+#define GET_RG_WAIT_T_RXAGC (((REG32(ADR_PHY_REG_03_AGC)) & 0x00003f00 ) >> 8)
+#define GET_RG_RXAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00004000 ) >> 14)
+#define GET_RG_RXAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00008000 ) >> 15)
+#define GET_RG_WAIT_T_FINAL (((REG32(ADR_PHY_REG_03_AGC)) & 0x003f0000 ) >> 16)
+#define GET_RG_WAIT_T (((REG32(ADR_PHY_REG_03_AGC)) & 0x3f000000 ) >> 24)
+#define GET_RG_ULG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_LG_PGA_UND_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000000f0 ) >> 4)
+#define GET_RG_LG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00000f00 ) >> 8)
+#define GET_RG_LG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000f000 ) >> 12)
+#define GET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000f0000 ) >> 16)
+#define GET_RG_HG_PGA_SAT2_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00f00000 ) >> 20)
+#define GET_RG_HG_PGA_SAT1_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0f000000 ) >> 24)
+#define GET_RG_HG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0xf0000000 ) >> 28)
+#define GET_RG_MG_PGA_JB_TH (((REG32(ADR_PHY_REG_05_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_MA_PGA_LOW_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x001f0000 ) >> 16)
+#define GET_RG_WR_RFGC_INIT_SET (((REG32(ADR_PHY_REG_05_AGC)) & 0x00600000 ) >> 21)
+#define GET_RG_WR_RFGC_INIT_EN (((REG32(ADR_PHY_REG_05_AGC)) & 0x00800000 ) >> 23)
+#define GET_RG_MA_PGA_HIGH_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x1f000000 ) >> 24)
+#define GET_RG_AGC_THRESHOLD (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x00003fff ) >> 0)
+#define GET_RG_ACI_POINT_CNT_LMT_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x007f0000 ) >> 16)
+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x03000000 ) >> 24)
+#define GET_RG_WR_ACI_GAIN_INI_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x000000ff ) >> 0)
+#define GET_RG_WR_ACI_GAIN_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_ACI_DAGC_SET_VALUE_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x007f0000 ) >> 16)
+#define GET_RG_WR_ACI_GAIN_OW_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x80000000 ) >> 31)
+#define GET_RG_ACI_POINT_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x000000ff ) >> 0)
+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00000300 ) >> 8)
+#define GET_RG_ACI_DAGC_DONE_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xff000000 ) >> 24)
+#define GET_RG_ACI_DAGC_SET_VALUE_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000007f ) >> 0)
+#define GET_RG_ACI_GAIN_INI_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_ACI_GAIN_OW_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x00ff0000 ) >> 16)
+#define GET_RG_ACI_GAIN_OW_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x80000000 ) >> 31)
+#define GET_RO_CCA_PWR_MA_11GN (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x0000007f ) >> 0)
+#define GET_RO_ED_STATE (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x00008000 ) >> 15)
+#define GET_RO_CCA_PWR_MA_11B (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x007f0000 ) >> 16)
+#define GET_RO_PGA_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RO_PGA_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RO_PGA_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RG_TX_DES_RATE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_DES_MODE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_DES_LEN_LO (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_LEN_UP (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_TX_DES_SRVC_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_TYPE (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_TX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000010 ) >> 4)
+#define GET_RG_TX_DES_RATE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000100 ) >> 8)
+#define GET_RG_TX_DES_MODE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00001000 ) >> 12)
+#define GET_RG_TX_DES_PWRLVL (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_SRVC_LO (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_RX_DES_RATE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x0000003f ) >> 0)
+#define GET_RG_RX_DES_MODE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x00003f00 ) >> 8)
+#define GET_RG_RX_DES_LEN_LO (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_LEN_UP (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RG_RX_DES_SRVC_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x0000003f ) >> 0)
+#define GET_RG_RX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x00003f00 ) >> 8)
+#define GET_RG_RX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_TYPE (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RG_RX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000001 ) >> 0)
+#define GET_RG_RX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000010 ) >> 4)
+#define GET_RG_RX_DES_RATE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000100 ) >> 8)
+#define GET_RG_RX_DES_MODE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00001000 ) >> 12)
+#define GET_RG_RX_DES_SNR (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x000f0000 ) >> 16)
+#define GET_RG_RX_DES_RCPI (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00f00000 ) >> 20)
+#define GET_RG_RX_DES_SRVC_LO (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RO_TX_DES_EXCP_RATE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x000000ff ) >> 0)
+#define GET_RO_TX_DES_EXCP_CH_BW_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x0000ff00 ) >> 8)
+#define GET_RO_TX_DES_EXCP_MODE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_DES_EXCP_RATE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x07000000 ) >> 24)
+#define GET_RG_TX_DES_EXCP_MODE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x70000000 ) >> 28)
+#define GET_RG_TX_DES_EXCP_CLR (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x80000000 ) >> 31)
+#define GET_RG_TX_DES_ACK_WIDTH (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_DES_ACK_PRD (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x0000000e ) >> 1)
+#define GET_RG_RX_DES_SNR_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_RCPI_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x3f000000 ) >> 24)
+#define GET_RG_TST_TBUS_SEL (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x0000000f ) >> 0)
+#define GET_RG_RSSI_OFFSET (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x00ff0000 ) >> 16)
+#define GET_RG_RSSI_INV (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x01000000 ) >> 24)
+#define GET_RG_TST_ADC_ON (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x40000000 ) >> 30)
+#define GET_RG_TST_EXT_GAIN (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x80000000 ) >> 31)
+#define GET_RG_DAC_Q_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x000003ff ) >> 0)
+#define GET_RG_DAC_I_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x003ff000 ) >> 12)
+#define GET_RG_DAC_EN_MAN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x10000000 ) >> 28)
+#define GET_RG_IQC_FFT_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x20000000 ) >> 29)
+#define GET_RG_DAC_MAN_Q_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x40000000 ) >> 30)
+#define GET_RG_DAC_MAN_I_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x80000000 ) >> 31)
+#define GET_RO_MRX_EN_CNT (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RG_MRX_EN_CNT_RST_N (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_PA_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_RFTX_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DAC_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_SW_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff000000 ) >> 24)
+#define GET_RG_PA_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_RFTX_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DAC_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_SW_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff000000 ) >> 24)
+#define GET_RG_ANT_SW_0 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000007 ) >> 0)
+#define GET_RG_ANT_SW_1 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000038 ) >> 3)
+#define GET_RG_MTX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MTX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MTX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MTX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MTX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MTX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MRX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MRX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MRX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MRX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MRX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MRX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RO_MTX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff ) >> 0)
+#define GET_RO_MTX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000 ) >> 16)
+#define GET_RO_MRX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff ) >> 0)
+#define GET_RO_MRX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000 ) >> 16)
+#define GET_RG_MODE_REG_IN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x0000ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x80000000 ) >> 31)
+#define GET_RO_MODE_REG_OUT_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x0000ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_16 (((REG32(ADR_PHY_READ_REG_07_BIST)) & 0x0007ffff ) >> 0)
+#define GET_RG_MRX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x000000ff ) >> 0)
+#define GET_RG_MRX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_MTX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ff0000 ) >> 16)
+#define GET_RG_MTX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff000000 ) >> 24)
+#define GET_RO_MTX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff ) >> 0)
+#define GET_RO_MTX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000 ) >> 16)
+#define GET_RO_MRX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff ) >> 0)
+#define GET_RO_MRX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000 ) >> 16)
+#define GET_RG_HB_COEF0 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RG_HB_COEF1 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
+#define GET_RG_HB_COEF2 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RG_HB_COEF3 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
+#define GET_RG_HB_COEF4 (((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RO_TBUS_O (((REG32(ADR_PHY_READ_TBUS)) & 0x000fffff ) >> 0)
+#define GET_RG_LPF4_00 (((REG32(ADR_TX_11B_FIL_COEF_00)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_01 (((REG32(ADR_TX_11B_FIL_COEF_01)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_02 (((REG32(ADR_TX_11B_FIL_COEF_02)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_03 (((REG32(ADR_TX_11B_FIL_COEF_03)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_04 (((REG32(ADR_TX_11B_FIL_COEF_04)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_05 (((REG32(ADR_TX_11B_FIL_COEF_05)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_06 (((REG32(ADR_TX_11B_FIL_COEF_06)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_07 (((REG32(ADR_TX_11B_FIL_COEF_07)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_08 (((REG32(ADR_TX_11B_FIL_COEF_08)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_09 (((REG32(ADR_TX_11B_FIL_COEF_09)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_10 (((REG32(ADR_TX_11B_FIL_COEF_10)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_11 (((REG32(ADR_TX_11B_FIL_COEF_11)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_12 (((REG32(ADR_TX_11B_FIL_COEF_12)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_13 (((REG32(ADR_TX_11B_FIL_COEF_13)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_14 (((REG32(ADR_TX_11B_FIL_COEF_14)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_15 (((REG32(ADR_TX_11B_FIL_COEF_15)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_16 (((REG32(ADR_TX_11B_FIL_COEF_16)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_17 (((REG32(ADR_TX_11B_FIL_COEF_17)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_18 (((REG32(ADR_TX_11B_FIL_COEF_18)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_19 (((REG32(ADR_TX_11B_FIL_COEF_19)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_20 (((REG32(ADR_TX_11B_FIL_COEF_20)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_21 (((REG32(ADR_TX_11B_FIL_COEF_21)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_22 (((REG32(ADR_TX_11B_FIL_COEF_22)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_23 (((REG32(ADR_TX_11B_FIL_COEF_23)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_24 (((REG32(ADR_TX_11B_FIL_COEF_24)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_25 (((REG32(ADR_TX_11B_FIL_COEF_25)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_26 (((REG32(ADR_TX_11B_FIL_COEF_26)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_27 (((REG32(ADR_TX_11B_FIL_COEF_27)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_28 (((REG32(ADR_TX_11B_FIL_COEF_28)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_29 (((REG32(ADR_TX_11B_FIL_COEF_29)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_30 (((REG32(ADR_TX_11B_FIL_COEF_30)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_31 (((REG32(ADR_TX_11B_FIL_COEF_31)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_32 (((REG32(ADR_TX_11B_FIL_COEF_32)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_33 (((REG32(ADR_TX_11B_FIL_COEF_33)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_34 (((REG32(ADR_TX_11B_FIL_COEF_34)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_35 (((REG32(ADR_TX_11B_FIL_COEF_35)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_36 (((REG32(ADR_TX_11B_FIL_COEF_36)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_37 (((REG32(ADR_TX_11B_FIL_COEF_37)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_38 (((REG32(ADR_TX_11B_FIL_COEF_38)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_39 (((REG32(ADR_TX_11B_FIL_COEF_39)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_40 (((REG32(ADR_TX_11B_FIL_COEF_40)) & 0x00001fff ) >> 0)
+#define GET_RG_BP_SMB (((REG32(ADR_TX_11B_PLCP)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SRVC (((REG32(ADR_TX_11B_PLCP)) & 0x00004000 ) >> 14)
+#define GET_RG_DES_SPD (((REG32(ADR_TX_11B_PLCP)) & 0x00030000 ) >> 16)
+#define GET_RG_BB_11B_RISE_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_11B_FALL_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_WR_TX_EN_CNT_RST_N (((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0x00000001 ) >> 0)
+#define GET_RO_TX_EN_CNT (((REG32(ADR_TX_11B_EN_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RO_TX_CNT (((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
+#define GET_RG_POS_DES_11B_L_EXT (((REG32(ADR_RX_11B_DES_DLY)) & 0x0000000f ) >> 0)
+#define GET_RG_PRE_DES_11B_DLY (((REG32(ADR_RX_11B_DES_DLY)) & 0x000000f0 ) >> 4)
+#define GET_RG_CNT_CCA_LMT (((REG32(ADR_RX_11B_CCA_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_BYPASS_DESCRAMBLER (((REG32(ADR_RX_11B_CCA_0)) & 0x20000000 ) >> 29)
+#define GET_RG_BYPASS_AGC (((REG32(ADR_RX_11B_CCA_0)) & 0x80000000 ) >> 31)
+#define GET_RG_CCA_BIT_CNT_LMT_RX (((REG32(ADR_RX_11B_CCA_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_CCA_SCALE_BF (((REG32(ADR_RX_11B_CCA_1)) & 0x007f0000 ) >> 16)
+#define GET_RG_PEAK_IDX_CNT_SEL (((REG32(ADR_RX_11B_CCA_1)) & 0x30000000 ) >> 28)
+#define GET_RG_TR_KI_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000007 ) >> 0)
+#define GET_RG_TR_KP_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000070 ) >> 4)
+#define GET_RG_TR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000700 ) >> 8)
+#define GET_RG_TR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00007000 ) >> 12)
+#define GET_RG_CR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00070000 ) >> 16)
+#define GET_RG_CR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00700000 ) >> 20)
+#define GET_RG_CHIP_CNT_SLICER (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000001f ) >> 0)
+#define GET_RG_CE_T4_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000ff00 ) >> 8)
+#define GET_RG_CE_T3_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ff0000 ) >> 16)
+#define GET_RG_CE_T2_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff000000 ) >> 24)
+#define GET_RG_CE_MU_T1 (((REG32(ADR_RX_11B_CE_MU_0)) & 0x00000007 ) >> 0)
+#define GET_RG_CE_DLY_SEL (((REG32(ADR_RX_11B_CE_MU_0)) & 0x003f0000 ) >> 16)
+#define GET_RG_CE_MU_T8 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000007 ) >> 0)
+#define GET_RG_CE_MU_T7 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000070 ) >> 4)
+#define GET_RG_CE_MU_T6 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000700 ) >> 8)
+#define GET_RG_CE_MU_T5 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00007000 ) >> 12)
+#define GET_RG_CE_MU_T4 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00070000 ) >> 16)
+#define GET_RG_CE_MU_T3 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00700000 ) >> 20)
+#define GET_RG_CE_MU_T2 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x07000000 ) >> 24)
+#define GET_RG_EQ_MU_FB_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x0000000f ) >> 0)
+#define GET_RG_EQ_MU_FF_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_MU_FB_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_EQ_MU_FF_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x00f00000 ) >> 20)
+#define GET_RG_EQ_MU_FB_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x0000000f ) >> 0)
+#define GET_RG_EQ_MU_FF_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_MU_FB_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000f0000 ) >> 16)
+#define GET_RG_EQ_MU_FF_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x00f00000 ) >> 20)
+#define GET_RG_EQ_KI_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00000700 ) >> 8)
+#define GET_RG_EQ_KP_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00007000 ) >> 12)
+#define GET_RG_EQ_KI_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00070000 ) >> 16)
+#define GET_RG_EQ_KP_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00700000 ) >> 20)
+#define GET_RG_TR_LPF_RATE (((REG32(ADR_RX_11B_LPF_RATE)) & 0x003fffff ) >> 0)
+#define GET_RG_CE_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x0000007f ) >> 0)
+#define GET_RG_CE_CH_MAIN_SET (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00000080 ) >> 7)
+#define GET_RG_TC_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00007f00 ) >> 8)
+#define GET_RG_CR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x007f0000 ) >> 16)
+#define GET_RG_TR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x7f000000 ) >> 24)
+#define GET_RG_EQ_MAIN_TAP_MAN (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x00000001 ) >> 0)
+#define GET_RG_EQ_MAIN_TAP_COEF (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x07ff0000 ) >> 16)
+#define GET_RG_PWRON_DLY_TH_11B (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x000000ff ) >> 0)
+#define GET_RG_SFD_BIT_CNT_LMT (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x00ff0000 ) >> 16)
+#define GET_RG_CCA_PWR_TH_RX (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x00007fff ) >> 0)
+#define GET_RG_CCA_PWR_CNT_TH (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x001f0000 ) >> 16)
+#define GET_B_FREQ_OS (((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0x000007ff ) >> 0)
+#define GET_B_SNR (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x0000007f ) >> 0)
+#define GET_B_RCPI (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x007f0000 ) >> 16)
+#define GET_CRC_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff ) >> 0)
+#define GET_SFD_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000 ) >> 16)
+#define GET_B_PACKET_ERR_CNT (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_PACKET_ERR (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x00010000 ) >> 16)
+#define GET_B_PACKET_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
+#define GET_B_CCA_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
+#define GET_B_LENGTH_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff ) >> 0)
+#define GET_SFD_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000 ) >> 16)
+#define GET_SIGNAL_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x000000ff ) >> 0)
+#define GET_B_SERVICE_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x0000ff00 ) >> 8)
+#define GET_CRC_CORRECT (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x00010000 ) >> 16)
+#define GET_DEBUG_SEL (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x0000000f ) >> 0)
+#define GET_RG_PACKET_STAT_EN_11B (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00100000 ) >> 20)
+#define GET_RG_BIT_REVERSE (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00200000 ) >> 21)
+#define GET_RX_PHY_11B_SOFT_RST_N (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000001 ) >> 0)
+#define GET_RG_CE_BYPASS_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_BYPASS_FBW_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000f00 ) >> 8)
+#define GET_RG_BB_11GN_RISE_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_11GN_FALL_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_HTCARR52_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x000003ff ) >> 0)
+#define GET_RG_HTCARR56_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x003ff000 ) >> 12)
+#define GET_RG_PACKET_STAT_EN (((REG32(ADR_TX_11GN_PLCP)) & 0x00800000 ) >> 23)
+#define GET_RG_SMB_DEF (((REG32(ADR_TX_11GN_PLCP)) & 0x7f000000 ) >> 24)
+#define GET_RG_CONTINUOUS_DATA_11GN (((REG32(ADR_TX_11GN_PLCP)) & 0x80000000 ) >> 31)
+#define GET_RO_TX_CNT_R (((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
+#define GET_RO_PACKET_ERR_CNT (((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RG_POS_DES_11GN_L_EXT (((REG32(ADR_RX_11GN_DES_DLY)) & 0x0000000f ) >> 0)
+#define GET_RG_PRE_DES_11GN_DLY (((REG32(ADR_RX_11GN_DES_DLY)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_KI_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_CNT_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TR_LPF_KI_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_TR_LPF_KP_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x00f00000 ) >> 20)
+#define GET_RG_TR_CNT_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0xff000000 ) >> 24)
+#define GET_RG_TR_LPF_KI_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_CNT_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TR_LPF_KI_G (((REG32(ADR_RX_11GN_TR_2)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G (((REG32(ADR_RX_11GN_TR_2)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_RATE_G (((REG32(ADR_RX_11GN_TR_2)) & 0x3fffff00 ) >> 8)
+#define GET_RG_CR_LPF_KI_G (((REG32(ADR_RX_11GN_CCA_0)) & 0x00000007 ) >> 0)
+#define GET_RG_SYM_BOUND_CNT (((REG32(ADR_RX_11GN_CCA_0)) & 0x00007f00 ) >> 8)
+#define GET_RG_XSCOR32_RATIO (((REG32(ADR_RX_11GN_CCA_0)) & 0x007f0000 ) >> 16)
+#define GET_RG_ATCOR64_CNT_LMT (((REG32(ADR_RX_11GN_CCA_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_ATCOR16_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_1)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_1)) & 0x007f0000 ) >> 16)
+#define GET_RG_ATCOR16_RATIO_SB (((REG32(ADR_RX_11GN_CCA_1)) & 0x7f000000 ) >> 24)
+#define GET_RG_XSCOR64_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_2)) & 0x007f0000 ) >> 16)
+#define GET_RG_XSCOR64_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_2)) & 0x7f000000 ) >> 24)
+#define GET_RG_RX_FFT_SCALE (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x000003ff ) >> 0)
+#define GET_RG_VITERBI_AB_SWAP (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x00010000 ) >> 16)
+#define GET_RG_ATCOR16_CNT_TH (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x0f000000 ) >> 24)
+#define GET_RG_NORMSQUARE_LOW_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_LOW_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_LOW_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_LOW_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_LOW_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_3 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_SNR_2 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_SNR_1 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_SNR_0 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0xff000000 ) >> 24)
+#define GET_RG_SNR_TH_64QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x0000007f ) >> 0)
+#define GET_RG_SNR_TH_16QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_CNT_PLUS_LMT2 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x0000007f ) >> 0)
+#define GET_RG_ATCOR16_CNT_PLUS_LMT1 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00007f00 ) >> 8)
+#define GET_RG_SYM_BOUND_METHOD (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00030000 ) >> 16)
+#define GET_RG_PWRON_DLY_TH_11GN (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x000000ff ) >> 0)
+#define GET_RG_SB_START_CNT (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x00007f00 ) >> 8)
+#define GET_RG_POW16_CNT_TH (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x000000f0 ) >> 4)
+#define GET_RG_POW16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x00000700 ) >> 8)
+#define GET_RG_POW16_TH_L (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x7f000000 ) >> 24)
+#define GET_RG_XSCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00000007 ) >> 0)
+#define GET_RG_XSCOR16_RATIO (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00070000 ) >> 16)
+#define GET_RG_ATCOR16_RATIO_CCD (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x7f000000 ) >> 24)
+#define GET_RG_ATCOR64_ACC_LMT (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x0000007f ) >> 0)
+#define GET_RG_ATCOR16_SHORT_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x00070000 ) >> 16)
+#define GET_RG_VITERBI_TB_BITS (((REG32(ADR_RX_11GN_VTB_TB)) & 0xff000000 ) >> 24)
+#define GET_RG_CR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x000000ff ) >> 0)
+#define GET_RG_TR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x00ff0000 ) >> 16)
+#define GET_RG_BYPASS_CPE_MA (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000010 ) >> 4)
+#define GET_RG_PILOT_BNDRY_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000700 ) >> 8)
+#define GET_RG_EQ_SHORT_GI_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00007000 ) >> 12)
+#define GET_RG_FFT_WDW_SHORT_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00070000 ) >> 16)
+#define GET_RG_CHSMTH_COEF (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00030000 ) >> 16)
+#define GET_RG_CHSMTH_EN (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00040000 ) >> 18)
+#define GET_RG_CHEST_DD_FACTOR (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x07000000 ) >> 24)
+#define GET_RG_CH_UPDATE (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x80000000 ) >> 31)
+#define GET_RG_FMT_DET_MM_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x000000ff ) >> 0)
+#define GET_RG_FMT_DET_GF_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DO_NOT_CHECK_L_RATE (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x02000000 ) >> 25)
+#define GET_RG_FMT_DET_LENGTH_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff ) >> 0)
+#define GET_RG_L_LENGTH_MAX (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000 ) >> 16)
+#define GET_RG_TX_TIME_EXT (((REG32(ADR_RX_11GN_TX_TIME)) & 0x000000ff ) >> 0)
+#define GET_RG_MAC_DES_SPACE (((REG32(ADR_RX_11GN_TX_TIME)) & 0x00f00000 ) >> 20)
+#define GET_RG_TR_LPF_STBC_GF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_STBC_GF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_STBC_MF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x00000f00 ) >> 8)
+#define GET_RG_TR_LPF_STBC_MF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000f000 ) >> 12)
+#define GET_RG_MODE_REG_IN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x0001ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x80000000 ) >> 31)
+#define GET_RG_MODE_REG_IN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x0000ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x80000000 ) >> 31)
+#define GET_RO_MODE_REG_OUT_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x0001ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_80 (((REG32(ADR_RX_11GN_BIST_3)) & 0x003fffff ) >> 0)
+#define GET_RO_MODE_REG_OUT_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x0000ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_64 (((REG32(ADR_RX_11GN_BIST_5)) & 0x0007ffff ) >> 0)
+#define GET_RO_SPECTRUM_DATA (((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0xffffffff ) >> 0)
+#define GET_GN_SNR (((REG32(ADR_RX_11GN_READ_0)) & 0x0000007f ) >> 0)
+#define GET_GN_NOISE_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x00007f00 ) >> 8)
+#define GET_GN_RCPI (((REG32(ADR_RX_11GN_READ_0)) & 0x007f0000 ) >> 16)
+#define GET_GN_SIGNAL_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x7f000000 ) >> 24)
+#define GET_RO_FREQ_OS_LTS (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x00007fff ) >> 0)
+#define GET_CSTATE (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x000f0000 ) >> 16)
+#define GET_SIGNAL_FIELD0 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0x00ffffff ) >> 0)
+#define GET_SIGNAL_FIELD1 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0x00ffffff ) >> 0)
+#define GET_GN_PACKET_ERR_CNT (((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_GN_PACKET_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
+#define GET_GN_CCA_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
+#define GET_GN_LENGTH_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff ) >> 0)
+#define GET_GN_SERVICE_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000 ) >> 16)
+#define GET_RO_HT_MCS_40M (((REG32(ADR_RX_11GN_RATE)) & 0x0000007f ) >> 0)
+#define GET_RO_L_RATE_40M (((REG32(ADR_RX_11GN_RATE)) & 0x00003f00 ) >> 8)
+#define GET_RG_DAGC_CNT_TH (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00000003 ) >> 0)
+#define GET_RG_PACKET_STAT_EN_11GN (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00100000 ) >> 20)
+#define GET_RX_PHY_11GN_SOFT_RST_N (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000001 ) >> 0)
+#define GET_RG_RIFS_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000002 ) >> 1)
+#define GET_RG_STBC_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000004 ) >> 2)
+#define GET_RG_COR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000008 ) >> 3)
+#define GET_RG_INI_PHASE (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000030 ) >> 4)
+#define GET_RG_HT_LTF_SEL_EQ (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000040 ) >> 6)
+#define GET_RG_HT_LTF_SEL_PILOT (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000080 ) >> 7)
+#define GET_RG_CCA_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000200 ) >> 9)
+#define GET_RG_CCA_XSCOR_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000400 ) >> 10)
+#define GET_RG_CCA_XSCOR_AVGPWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000800 ) >> 11)
+#define GET_RG_DEBUG_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x0000f000 ) >> 12)
+#define GET_RG_POST_CLK_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00010000 ) >> 16)
+#define GET_IQCAL_RF_TX_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000001 ) >> 0)
+#define GET_IQCAL_RF_TX_PA_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000002 ) >> 1)
+#define GET_IQCAL_RF_TX_DAC_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000004 ) >> 2)
+#define GET_IQCAL_RF_RX_AGC (((REG32(ADR_RF_CONTROL_0)) & 0x00000008 ) >> 3)
+#define GET_IQCAL_RF_PGAG (((REG32(ADR_RF_CONTROL_0)) & 0x00000f00 ) >> 8)
+#define GET_IQCAL_RF_RFG (((REG32(ADR_RF_CONTROL_0)) & 0x00003000 ) >> 12)
+#define GET_RG_TONEGEN_FREQ (((REG32(ADR_RF_CONTROL_0)) & 0x007f0000 ) >> 16)
+#define GET_RG_TONEGEN_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00800000 ) >> 23)
+#define GET_RG_TONEGEN_INIT_PH (((REG32(ADR_RF_CONTROL_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_TONEGEN2_FREQ (((REG32(ADR_RF_CONTROL_1)) & 0x0000007f ) >> 0)
+#define GET_RG_TONEGEN2_EN (((REG32(ADR_RF_CONTROL_1)) & 0x00000080 ) >> 7)
+#define GET_RG_TONEGEN2_SCALE (((REG32(ADR_RF_CONTROL_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TXIQ_CLP_THD_I (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x000003ff ) >> 0)
+#define GET_RG_TXIQ_CLP_THD_Q (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TX_I_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x000000ff ) >> 0)
+#define GET_RG_TX_Q_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TX_IQ_SWP (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00010000 ) >> 16)
+#define GET_RG_TX_SGN_OUT (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00020000 ) >> 17)
+#define GET_RG_TXIQ_EMU_IDX (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x003c0000 ) >> 18)
+#define GET_RG_TX_IQ_SRC (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x03000000 ) >> 24)
+#define GET_RG_TX_I_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x000003ff ) >> 0)
+#define GET_RG_TX_Q_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TX_IQ_THETA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_IQ_ALPHA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
+#define GET_RG_TXIQ_NOSHRINK (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
+#define GET_RG_TX_I_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_Q_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff000000 ) >> 24)
+#define GET_RG_RX_IQ_THETA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
+#define GET_RG_RX_IQ_ALPHA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
+#define GET_RG_RXIQ_NOSHRINK (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
+#define GET_RG_MA_DPTH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x0000000f ) >> 0)
+#define GET_RG_INTG_PH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x000003f0 ) >> 4)
+#define GET_RG_INTG_PRD (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00001c00 ) >> 10)
+#define GET_RG_INTG_MU (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00006000 ) >> 13)
+#define GET_RG_IQCAL_SPRM_SELQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00010000 ) >> 16)
+#define GET_RG_IQCAL_SPRM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00020000 ) >> 17)
+#define GET_RG_IQCAL_SPRM_FREQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IQCAL_IQCOL_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x01000000 ) >> 24)
+#define GET_RG_IQCAL_ALPHA_ESTM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x02000000 ) >> 25)
+#define GET_RG_IQCAL_DC_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x04000000 ) >> 26)
+#define GET_RG_PHEST_STBY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x08000000 ) >> 27)
+#define GET_RG_PHEST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x10000000 ) >> 28)
+#define GET_RG_GP_DIV_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x20000000 ) >> 29)
+#define GET_RG_DPD_GAIN_EST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x40000000 ) >> 30)
+#define GET_RG_IQCAL_MULT_OP0 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x000003ff ) >> 0)
+#define GET_RG_IQCAL_MULT_OP1 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x03ff0000 ) >> 16)
+#define GET_RO_IQCAL_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x000fffff ) >> 0)
+#define GET_RO_IQCAL_SPRM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00100000 ) >> 20)
+#define GET_RO_IQCAL_IQCOL_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00200000 ) >> 21)
+#define GET_RO_IQCAL_ALPHA_ESTM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00400000 ) >> 22)
+#define GET_RO_IQCAL_DC_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00800000 ) >> 23)
+#define GET_RO_IQCAL_MULT_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x01000000 ) >> 24)
+#define GET_RO_FFT_ENRG_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x02000000 ) >> 25)
+#define GET_RO_PHEST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x04000000 ) >> 26)
+#define GET_RO_GP_DIV_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x08000000 ) >> 27)
+#define GET_RO_GAIN_EST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x10000000 ) >> 28)
+#define GET_RO_AMP_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0x000001ff ) >> 0)
+#define GET_RG_RX_I_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x000000ff ) >> 0)
+#define GET_RG_RX_Q_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_RX_I_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_RX_Q_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff000000 ) >> 24)
+#define GET_RG_RX_IQ_SWP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000001 ) >> 0)
+#define GET_RG_RX_SGN_IN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000002 ) >> 1)
+#define GET_RG_RX_IQ_SRC (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x0000000c ) >> 2)
+#define GET_RG_ACI_GAIN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000ff0 ) >> 4)
+#define GET_RG_FFT_EN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00001000 ) >> 12)
+#define GET_RG_FFT_MOD (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00002000 ) >> 13)
+#define GET_RG_FFT_SCALE (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00ffc000 ) >> 14)
+#define GET_RG_FFT_ENRG_FREQ (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x3f000000 ) >> 24)
+#define GET_RG_FPGA_80M_PH_UP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x40000000 ) >> 30)
+#define GET_RG_FPGA_80M_PH_STP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x80000000 ) >> 31)
+#define GET_RG_ADC2LA_SEL (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000001 ) >> 0)
+#define GET_RG_ADC2LA_CLKPH (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000002 ) >> 1)
+#define GET_RG_RXIQ_EMU_IDX (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x0000000f ) >> 0)
+#define GET_RG_IQCAL_BP_ACI (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x00000010 ) >> 4)
+#define GET_RG_DPD_AM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000001 ) >> 0)
+#define GET_RG_DPD_PM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000002 ) >> 1)
+#define GET_RG_DPD_PM_AMSEL (((REG32(ADR_DPD_CONTROL)) & 0x00000004 ) >> 2)
+#define GET_RG_DPD_020_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_040_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_060_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_080_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_0C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_0E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_100_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_110_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_120_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_130_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_140_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_150_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_160_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_170_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_180_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_190_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1B0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_200_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_020_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_040_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_060_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_080_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0A0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_0C0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0D0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_0E0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0F0_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_100_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_110_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_120_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_130_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_140_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_150_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_160_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_170_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_180_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_190_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1A0_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1B0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1C0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1D0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1E0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1F0_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_200_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_GAIN_EST_Y0 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x000001ff ) >> 0)
+#define GET_RG_DPD_GAIN_EST_Y1 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x01ff0000 ) >> 16)
+#define GET_RG_DPD_LOOP_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_GAIN_EST_X0 (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x000001ff ) >> 0)
+#define GET_RO_DPD_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x03ff0000 ) >> 16)
+#define GET_TX_SCALE_11B (((REG32(ADR_TX_GAIN_FACTOR)) & 0x000000ff ) >> 0)
+#define GET_TX_SCALE_11B_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0x0000ff00 ) >> 8)
+#define GET_TX_SCALE_11G (((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ff0000 ) >> 16)
+#define GET_TX_SCALE_11G_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0xff000000 ) >> 24)
+#define GET_RG_EN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_TX_PA_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_TX_DAC_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_RX_AGC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_RX_GAIN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_RFG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_PGAG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_MODE (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_EN_TX_TRSW (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_SX (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_EN_RX_LNA (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_EN_RX_MIXER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_EN_RX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_EN_RX_LOBUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_EN_RX_TZ (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_EN_RX_FILTER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_EN_RX_HPF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_EN_RX_RSSI (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_EN_ADC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_EN_TX_MOD (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_EN_TX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_EN_TX_DIV2_BUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_EN_TX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_EN_RX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_SEL_DPLL_CLK (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_EN_CLK_960MBY13_UART (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_EN_TX_DPD (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_TX_TSSI (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_RX_IQCAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_TX_DAC_CAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_TX_SELF_MIXER (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_TX_DAC_OUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_EN_LDO_RX_FE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_LDO_ABB (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_EN_LDO_AFE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_EN_SX_CHPLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_EN_SX_LOBFLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_EN_IREF_RX (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_TX_DAC_VOUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SX_LCK_BIN (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_RTC_CAL_MODE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_EN_IQPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_EN_TESTPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_EN_TRXBF_BYPASS (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_LDO_LEVEL_RX_FE (((REG32(ADR_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_LDO_LEVEL_ABB (((REG32(ADR_LDO_REGISTER)) & 0x00000038 ) >> 3)
+#define GET_RG_LDO_LEVEL_AFE (((REG32(ADR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
+#define GET_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
+#define GET_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_RG_DP_LDO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
+#define GET_RG_TX_LDO_TX_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_EN_RX_PADSW (((REG32(ADR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_RX_TESTNODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
+#define GET_RG_RX_ABBCFIX (((REG32(ADR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
+#define GET_RG_RX_ABBCTUNE (((REG32(ADR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
+#define GET_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
+#define GET_RG_RX_ABB_N_MODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
+#define GET_RG_RX_EN_LOOPA (((REG32(ADR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
+#define GET_RG_RX_FILTERI1ST (((REG32(ADR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
+#define GET_RG_RX_FILTERI2ND (((REG32(ADR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_FILTERI3RD (((REG32(ADR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
+#define GET_RG_RX_FILTERI_COURSE (((REG32(ADR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
+#define GET_RG_RX_FILTERVCM (((REG32(ADR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
+#define GET_RG_RX_HPF3M (((REG32(ADR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
+#define GET_RG_RX_HPF300K (((REG32(ADR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
+#define GET_RG_RX_HPFI (((REG32(ADR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
+#define GET_RG_RX_HPF_FINALCORNER (((REG32(ADR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
+#define GET_RG_RX_HPF_SETTLE1_C (((REG32(ADR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
+#define GET_RG_RX_HPF_SETTLE1_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_HPF_SETTLE2_C (((REG32(ADR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
+#define GET_RG_RX_HPF_SETTLE2_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
+#define GET_RG_RX_HPF_VCMCON2 (((REG32(ADR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
+#define GET_RG_RX_HPF_VCMCON (((REG32(ADR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
+#define GET_RG_RX_OUTVCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
+#define GET_RG_RX_TZI (((REG32(ADR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
+#define GET_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
+#define GET_RG_RX_TZ_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
+#define GET_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
+#define GET_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
+#define GET_RG_RX_ADCRSSI_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
+#define GET_RG_RX_REC_LPFCORNER (((REG32(ADR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
+#define GET_RG_RSSI_CLOCK_GATING (((REG32(ADR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
+#define GET_RG_TXPGA_CAPSW (((REG32(ADR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TXPGA_MAIN (((REG32(ADR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
+#define GET_RG_TXPGA_STEER (((REG32(ADR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
+#define GET_RG_TXMOD_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TXLPF_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_PACELL_EN (((REG32(ADR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_RG_PABIAS_CTRL (((REG32(ADR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
+#define GET_RG_TX_DIV_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_TX_LOBUF_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_RX_SQDC (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
+#define GET_RG_RX_DIV2_CORE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
+#define GET_RG_RX_LOBUF (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
+#define GET_RG_TX_DPDGM_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
+#define GET_RG_TX_DPD_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
+#define GET_RG_TX_TSSI_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
+#define GET_RG_TX_TSSI_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
+#define GET_RG_TX_TSSI_TESTMODE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
+#define GET_RG_TX_TSSI_TEST (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
+#define GET_RG_PACASCODE_CTRL (((REG32(ADR_RX_FE_REGISTER_1)) & 0x07000000 ) >> 24)
+#define GET_RG_RX_HG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_HG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_HG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_HG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_MG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_MG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_MG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_MG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_LG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_LG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_LG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_LG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_ULG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_ULG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_ULG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
+#define GET_RG_HPF1_FAST_SET_X (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_HPF1_FAST_SET_Y (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_HPF1_FAST_SET_Z (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_HPF_T1A (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_HPF_T1B (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000060 ) >> 5)
+#define GET_RG_HPF_T1C (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000180 ) >> 7)
+#define GET_RG_RX_LNA_TRI_SEL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_RG_RX_LNA_SETTLE (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00001800 ) >> 11)
+#define GET_RG_TXGAIN_PHYCTRL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_TX_GAIN (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x003fc000 ) >> 14)
+#define GET_RG_TXGAIN_MANUAL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TX_GAIN_OFFSET (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_RG_ADC_CLKSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_ADC_DIBIAS (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_ADC_DIVR (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_ADC_DVCMI (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_ADC_SAMSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
+#define GET_RG_ADC_STNBY (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_ADC_TESTMODE (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_ADC_TSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_ADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_DICMP (((REG32(ADR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_DIOP (((REG32(ADR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_SARADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_EN_SAR_TEST (((REG32(ADR_RX_ADC_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_SARADC_THERMAL (((REG32(ADR_RX_ADC_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_SARADC_TSSI (((REG32(ADR_RX_ADC_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_CLK_SAR_SEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_EN_SARADC (((REG32(ADR_RX_ADC_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_DACI1ST (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TX_DACLPF_ICOURSE (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TX_DACLPF_IFINE (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_TX_DACLPF_VCM (((REG32(ADR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_TX_DAC_IBIAS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_RG_TX_DAC_OS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
+#define GET_RG_TX_DAC_RCAL (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TX_DAC_TSEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_TXLPF_BYPASS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_TXLPF_BOOSTI (((REG32(ADR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TX_DAC_IOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_RG_TX_DAC_QOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x78000000 ) >> 27)
+#define GET_RG_EN_SX_R3 (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_SX_CH (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_SX_CHP (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_SX_DIVCK (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_SX_VCOBF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_SX_VCO (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_EN_SX_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_SX_DITHER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_EN_SX_VT_MON (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_SX_VT_MON_DG (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_EN_SX_DIV (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SX_LPF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_DPL_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_DPL_MOD_ORDER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_SX_RFCTRL_F (((REG32(ADR_SYN_REGISTER_1)) & 0x00ffffff ) >> 0)
+#define GET_RG_SX_SEL_CP (((REG32(ADR_SYN_REGISTER_1)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_SEL_CS (((REG32(ADR_SYN_REGISTER_1)) & 0xf0000000 ) >> 28)
+#define GET_RG_SX_RFCTRL_CH (((REG32(ADR_SYN_REGISTER_2)) & 0x000007ff ) >> 0)
+#define GET_RG_SX_SEL_C3 (((REG32(ADR_SYN_REGISTER_2)) & 0x00007800 ) >> 11)
+#define GET_RG_SX_SEL_RS (((REG32(ADR_SYN_REGISTER_2)) & 0x000f8000 ) >> 15)
+#define GET_RG_SX_SEL_R3 (((REG32(ADR_SYN_REGISTER_2)) & 0x01f00000 ) >> 20)
+#define GET_RG_SX_SEL_ICHP (((REG32(ADR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
+#define GET_RG_SX_SEL_PCHP (((REG32(ADR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
+#define GET_RG_SX_SEL_CHP_REGOP (((REG32(ADR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
+#define GET_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
+#define GET_RG_SX_CHP_IOST_POL (((REG32(ADR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
+#define GET_RG_SX_CHP_IOST (((REG32(ADR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
+#define GET_RG_SX_PFDSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
+#define GET_RG_SX_PFD_SET (((REG32(ADR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
+#define GET_RG_SX_PFD_SET1 (((REG32(ADR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
+#define GET_RG_SX_PFD_SET2 (((REG32(ADR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
+#define GET_RG_SX_VBNCAS_SEL (((REG32(ADR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
+#define GET_RG_SX_PFD_RST_H (((REG32(ADR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
+#define GET_RG_SX_PFD_TRUP (((REG32(ADR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
+#define GET_RG_SX_PFD_TRDN (((REG32(ADR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
+#define GET_RG_SX_PFD_TRSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
+#define GET_RG_SX_VCOBA_R (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
+#define GET_RG_SX_VCORSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
+#define GET_RG_SX_VCOCUSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
+#define GET_RG_SX_RXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
+#define GET_RG_SX_TXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
+#define GET_RG_SX_VCOBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
+#define GET_RG_SX_DIVBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_GNDR_SEL (((REG32(ADR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
+#define GET_RG_SX_DITHER_WEIGHT (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
+#define GET_RG_SX_MOD_ORDER (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
+#define GET_RG_SX_RST_H_DIV (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
+#define GET_RG_SX_SDM_EDGE (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
+#define GET_RG_SX_XO_GM (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
+#define GET_RG_SX_REFBYTWO (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
+#define GET_RG_SX_LCKEN (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
+#define GET_RG_SX_PREVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
+#define GET_RG_SX_PSCONTERVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_PH (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00002000 ) >> 13)
+#define GET_RG_SX_PL (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00004000 ) >> 14)
+#define GET_RG_XOSC_CBANK_XO (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00078000 ) >> 15)
+#define GET_RG_XOSC_CBANK_XI (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00780000 ) >> 19)
+#define GET_RG_SX_VT_MON_MODE (((REG32(ADR_SYN_LCK_VT)) & 0x00000001 ) >> 0)
+#define GET_RG_SX_VT_TH_HI (((REG32(ADR_SYN_LCK_VT)) & 0x00000006 ) >> 1)
+#define GET_RG_SX_VT_TH_LO (((REG32(ADR_SYN_LCK_VT)) & 0x00000018 ) >> 3)
+#define GET_RG_SX_VT_SET (((REG32(ADR_SYN_LCK_VT)) & 0x00000020 ) >> 5)
+#define GET_RG_SX_VT_MON_TMR (((REG32(ADR_SYN_LCK_VT)) & 0x00007fc0 ) >> 6)
+#define GET_RG_EN_DP_VT_MON (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_DP_VT_TH_HI (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_DP_VT_TH_LO (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_DP_CK320BY2 (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_DP_OD_TEST (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_DP_BBPLL_BP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_DP_BBPLL_ICP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_DP_BBPLL_IDUAL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_DP_BBPLL_OD_TEST (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
+#define GET_RG_DP_BBPLL_PD (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_DP_BBPLL_TESTSEL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
+#define GET_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
+#define GET_RG_DP_RP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_RG_DP_RHP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_DP_BBPLL_SDM_EDGE (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_DP_FODIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x0007f000 ) >> 12)
+#define GET_RG_DP_REFDIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x1fc00000 ) >> 22)
+#define GET_RG_IDACAI_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
+#define GET_RG_DP_BBPLL_BS (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
+#define GET_RG_IDACAI_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
+#define GET_RG_EN_RCAL (((REG32(ADR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_RCAL_SPD (((REG32(ADR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_RCAL_TMR (((REG32(ADR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
+#define GET_RG_RCAL_CODE_CWR (((REG32(ADR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_RCAL_CODE_CWD (((REG32(ADR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
+#define GET_RG_SX_SUB_SEL_CWR (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00000001 ) >> 0)
+#define GET_RG_SX_SUB_SEL_CWD (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x000000fe ) >> 1)
+#define GET_RG_SX_LCK_BIN_OFFSET (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00078000 ) >> 15)
+#define GET_RG_SX_LCK_BIN_PRECISION (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00080000 ) >> 19)
+#define GET_RG_SX_LOCK_EN_N (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00100000 ) >> 20)
+#define GET_RG_SX_LOCK_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00200000 ) >> 21)
+#define GET_RG_SX_SUB_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00400000 ) >> 22)
+#define GET_RG_SX_SUB_SEL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x3f800000 ) >> 23)
+#define GET_RG_SX_MUX_SEL_VTH_BINL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x40000000 ) >> 30)
+#define GET_RG_TRX_DUMMMY (((REG32(ADR_TRX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
+#define GET_RG_SX_DUMMMY (((REG32(ADR_SX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
+#define GET_RCAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
+#define GET_LCK_BIN_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
+#define GET_VT_MON_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
+#define GET_DA_R_CODE_LUT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
+#define GET_AD_SX_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
+#define GET_AD_DP_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
+#define GET_RTC_CAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00008000 ) >> 15)
+#define GET_RG_SARADC_BIT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x003f0000 ) >> 16)
+#define GET_SAR_ADC_FSM_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00400000 ) >> 22)
+#define GET_AD_CIRCUIT_VERSION (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x07800000 ) >> 23)
+#define GET_DA_R_CAL_CODE (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
+#define GET_DA_SX_SUB_SEL (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
+#define GET_RG_DPL_RFCTRL_CH (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x000007ff ) >> 0)
+#define GET_RG_RSSIADC_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x00007800 ) >> 11)
+#define GET_RG_RX_ADC_I_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x007f8000 ) >> 15)
+#define GET_RG_RX_ADC_Q_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x7f800000 ) >> 23)
+#define GET_RG_DPL_RFCTRL_F (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0x00ffffff ) >> 0)
+#define GET_RG_SX_TARGET_CNT (((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0x00001fff ) >> 0)
+#define GET_RG_RTC_OFFSET (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000000ff ) >> 0)
+#define GET_RG_RTC_CAL_TARGET_COUNT (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000fff00 ) >> 8)
+#define GET_RG_RF_D_REG (((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0x0000ffff ) >> 0)
+#define GET_DIRECT_MODE (((REG32(ADR_MMU_CTRL)) & 0x00000001 ) >> 0)
+#define GET_TAG_INTERLEAVE_MD (((REG32(ADR_MMU_CTRL)) & 0x00000002 ) >> 1)
+#define GET_DIS_DEMAND (((REG32(ADR_MMU_CTRL)) & 0x00000004 ) >> 2)
+#define GET_SAME_ID_ALLOC_MD (((REG32(ADR_MMU_CTRL)) & 0x00000008 ) >> 3)
+#define GET_HS_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000010 ) >> 4)
+#define GET_SRAM_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000020 ) >> 5)
+#define GET_NOHIT_RPASS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000040 ) >> 6)
+#define GET_DMN_FLAG_CLR (((REG32(ADR_MMU_CTRL)) & 0x00000080 ) >> 7)
+#define GET_ERR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000100 ) >> 8)
+#define GET_ALR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000200 ) >> 9)
+#define GET_MCH_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000400 ) >> 10)
+#define GET_TAG_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000800 ) >> 11)
+#define GET_ABT_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00001000 ) >> 12)
+#define GET_MMU_VER (((REG32(ADR_MMU_CTRL)) & 0x0000e000 ) >> 13)
+#define GET_MMU_SHARE_MCU (((REG32(ADR_MMU_CTRL)) & 0x00ff0000 ) >> 16)
+#define GET_HS_WR (((REG32(ADR_HS_CTRL)) & 0x00000001 ) >> 0)
+#define GET_HS_FLAG (((REG32(ADR_HS_CTRL)) & 0x00000010 ) >> 4)
+#define GET_HS_ID (((REG32(ADR_HS_CTRL)) & 0x00007f00 ) >> 8)
+#define GET_HS_CHANNEL (((REG32(ADR_HS_CTRL)) & 0x000f0000 ) >> 16)
+#define GET_HS_PAGE (((REG32(ADR_HS_CTRL)) & 0x00f00000 ) >> 20)
+#define GET_HS_DATA (((REG32(ADR_HS_CTRL)) & 0xff000000 ) >> 24)
+#define GET_CPU_POR0 (((REG32(ADR_CPU_POR0_7)) & 0x0000000f ) >> 0)
+#define GET_CPU_POR1 (((REG32(ADR_CPU_POR0_7)) & 0x000000f0 ) >> 4)
+#define GET_CPU_POR2 (((REG32(ADR_CPU_POR0_7)) & 0x00000f00 ) >> 8)
+#define GET_CPU_POR3 (((REG32(ADR_CPU_POR0_7)) & 0x0000f000 ) >> 12)
+#define GET_CPU_POR4 (((REG32(ADR_CPU_POR0_7)) & 0x000f0000 ) >> 16)
+#define GET_CPU_POR5 (((REG32(ADR_CPU_POR0_7)) & 0x00f00000 ) >> 20)
+#define GET_CPU_POR6 (((REG32(ADR_CPU_POR0_7)) & 0x0f000000 ) >> 24)
+#define GET_CPU_POR7 (((REG32(ADR_CPU_POR0_7)) & 0xf0000000 ) >> 28)
+#define GET_CPU_POR8 (((REG32(ADR_CPU_POR8_F)) & 0x0000000f ) >> 0)
+#define GET_CPU_POR9 (((REG32(ADR_CPU_POR8_F)) & 0x000000f0 ) >> 4)
+#define GET_CPU_PORA (((REG32(ADR_CPU_POR8_F)) & 0x00000f00 ) >> 8)
+#define GET_CPU_PORB (((REG32(ADR_CPU_POR8_F)) & 0x0000f000 ) >> 12)
+#define GET_CPU_PORC (((REG32(ADR_CPU_POR8_F)) & 0x000f0000 ) >> 16)
+#define GET_CPU_PORD (((REG32(ADR_CPU_POR8_F)) & 0x00f00000 ) >> 20)
+#define GET_CPU_PORE (((REG32(ADR_CPU_POR8_F)) & 0x0f000000 ) >> 24)
+#define GET_CPU_PORF (((REG32(ADR_CPU_POR8_F)) & 0xf0000000 ) >> 28)
+#define GET_ACC_WR_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x0000003f ) >> 0)
+#define GET_ACC_RD_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x00003f00 ) >> 8)
+#define GET_REQ_NACK_CLR (((REG32(ADR_REG_LEN_CTRL)) & 0x00008000 ) >> 15)
+#define GET_NACK_FLAG_BUS (((REG32(ADR_REG_LEN_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_DMN_R_PASS (((REG32(ADR_DMN_READ_BYPASS)) & 0x0000ffff ) >> 0)
+#define GET_PARA_ALC_RLS (((REG32(ADR_DMN_READ_BYPASS)) & 0x00010000 ) >> 16)
+#define GET_REQ_PORNS_CHGEN (((REG32(ADR_DMN_READ_BYPASS)) & 0x01000000 ) >> 24)
+#define GET_ALC_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x0000007f ) >> 0)
+#define GET_ALC_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x00008000 ) >> 15)
+#define GET_RLS_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x007f0000 ) >> 16)
+#define GET_RLS_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x80000000 ) >> 31)
+#define GET_DEBUG_CTL (((REG32(ADR_DEBUG_CTL)) & 0x000000ff ) >> 0)
+#define GET_DEBUG_H16 (((REG32(ADR_DEBUG_CTL)) & 0x00000100 ) >> 8)
+#define GET_DEBUG_OUT (((REG32(ADR_DEBUG_OUT)) & 0xffffffff ) >> 0)
+#define GET_ALC_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_RLS_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_AL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00000700 ) >> 8)
+#define GET_RL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00007000 ) >> 12)
+#define GET_ALC_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x007f0000 ) >> 16)
+#define GET_RLS_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x7f000000 ) >> 24)
+#define GET_DMN_NOHIT_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000001 ) >> 0)
+#define GET_DMN_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000002 ) >> 1)
+#define GET_DMN_WR (((REG32(ADR_DMN_STATUS)) & 0x00000008 ) >> 3)
+#define GET_DMN_PORT (((REG32(ADR_DMN_STATUS)) & 0x000000f0 ) >> 4)
+#define GET_DMN_NHIT_ID (((REG32(ADR_DMN_STATUS)) & 0x00007f00 ) >> 8)
+#define GET_DMN_NHIT_ADDR (((REG32(ADR_DMN_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_TX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x000000ff ) >> 0)
+#define GET_RX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x0000ff00 ) >> 8)
+#define GET_AVA_TAG (((REG32(ADR_TAG_STATUS)) & 0x01ff0000 ) >> 16)
+#define GET_PKTBUF_FULL (((REG32(ADR_TAG_STATUS)) & 0x80000000 ) >> 31)
+#define GET_DMN_NOHIT_MCU (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_DMN_MCU_FLAG (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_DMN_MCU_WR (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000008 ) >> 3)
+#define GET_DMN_MCU_PORT (((REG32(ADR_DMN_MCU_STATUS)) & 0x000000f0 ) >> 4)
+#define GET_DMN_MCU_ID (((REG32(ADR_DMN_MCU_STATUS)) & 0x00007f00 ) >> 8)
+#define GET_DMN_MCU_ADDR (((REG32(ADR_DMN_MCU_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_MB_IDTBL_31_0 (((REG32(ADR_MB_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_63_32 (((REG32(ADR_MB_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_95_64 (((REG32(ADR_MB_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_127_96 (((REG32(ADR_MB_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_31_0 (((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_63_32 (((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_95_64 (((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_127_96 (((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_31_0 (((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_63_32 (((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_95_64 (((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_127_96 (((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_31_0 (((REG32(ADR_MB_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_63_32 (((REG32(ADR_MB_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_95_64 (((REG32(ADR_MB_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_127_96 (((REG32(ADR_MB_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_31_0 (((REG32(ADR_PKT_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_63_32 (((REG32(ADR_PKT_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_95_64 (((REG32(ADR_PKT_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_127_96 (((REG32(ADR_PKT_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_ALC_NOCHG_ID (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x0000007f ) >> 0)
+#define GET_ALC_NOCHG_INT (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00008000 ) >> 15)
+#define GET_NEQ_PKT_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00010000 ) >> 16)
+#define GET_NEQ_MB_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x01000000 ) >> 24)
+#define GET_SRAM_TAG_0 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_1 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_2 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_3 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_4 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_5 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_6 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_7 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_8 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_9 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_10 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_11 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_12 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_13 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_14 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_15 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000 ) >> 16)
+#define SET_MCU_ENABLE(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 0) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffe))
+#define SET_MAC_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 1) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffd))
+#define SET_MCU_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 2) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffb))
+#define SET_SDIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 3) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffff7))
+#define SET_SPI_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 4) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffef))
+#define SET_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 5) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffdf))
+#define SET_DMA_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 6) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffbf))
+#define SET_WDT_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 7) | ((REG32(ADR_BRG_SW_RST)) & 0xffffff7f))
+#define SET_I2C_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 8) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffeff))
+#define SET_INT_CTL_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 9) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffdff))
+#define SET_BTCX_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 10) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffbff))
+#define SET_GPIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 11) | ((REG32(ADR_BRG_SW_RST)) & 0xfffff7ff))
+#define SET_US0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 12) | ((REG32(ADR_BRG_SW_RST)) & 0xffffefff))
+#define SET_US1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 13) | ((REG32(ADR_BRG_SW_RST)) & 0xffffdfff))
+#define SET_US2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 14) | ((REG32(ADR_BRG_SW_RST)) & 0xffffbfff))
+#define SET_US3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 15) | ((REG32(ADR_BRG_SW_RST)) & 0xffff7fff))
+#define SET_MS0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 16) | ((REG32(ADR_BRG_SW_RST)) & 0xfffeffff))
+#define SET_MS1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 17) | ((REG32(ADR_BRG_SW_RST)) & 0xfffdffff))
+#define SET_MS2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 18) | ((REG32(ADR_BRG_SW_RST)) & 0xfffbffff))
+#define SET_MS3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 19) | ((REG32(ADR_BRG_SW_RST)) & 0xfff7ffff))
+#define SET_RF_BB_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 20) | ((REG32(ADR_BRG_SW_RST)) & 0xffefffff))
+#define SET_SYS_ALL_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 21) | ((REG32(ADR_BRG_SW_RST)) & 0xffdfffff))
+#define SET_DAT_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 22) | ((REG32(ADR_BRG_SW_RST)) & 0xffbfffff))
+#define SET_I2C_MST_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 23) | ((REG32(ADR_BRG_SW_RST)) & 0xff7fffff))
+#define SET_RG_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT)) & 0xfffffffe))
+#define SET_TRAP_IMG_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 16) | ((REG32(ADR_BOOT)) & 0xfffeffff))
+#define SET_TRAP_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 17) | ((REG32(ADR_BOOT)) & 0xfffdffff))
+#define SET_TRAP_BOOT_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 18) | ((REG32(ADR_BOOT)) & 0xfffbffff))
+#define SET_CHIP_ID_31_0(_VAL_) (REG32(ADR_CHIP_ID_0)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_0)) & 0x00000000))
+#define SET_CHIP_ID_63_32(_VAL_) (REG32(ADR_CHIP_ID_1)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_1)) & 0x00000000))
+#define SET_CHIP_ID_95_64(_VAL_) (REG32(ADR_CHIP_ID_2)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_2)) & 0x00000000))
+#define SET_CHIP_ID_127_96(_VAL_) (REG32(ADR_CHIP_ID_3)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_3)) & 0x00000000))
+#define SET_CK_SEL_1_0(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 0) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffc))
+#define SET_CK_SEL_2(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 2) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffb))
+#define SET_SYS_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_MAC_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MCU_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 2) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffb))
+#define SET_SDIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_SPI_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_UART_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_DMA_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_WDT_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffff7f))
+#define SET_I2C_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 8) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffeff))
+#define SET_INT_CTL_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffdff))
+#define SET_BTCX_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_GPIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_US0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_US1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_US2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_US3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_MS0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 16) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffeffff))
+#define SET_MS1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 17) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffdffff))
+#define SET_MS2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 18) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffbffff))
+#define SET_MS3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 19) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfff7ffff))
+#define SET_BIST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 20) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffefffff))
+#define SET_I2C_MST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 23) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xff7fffff))
+#define SET_BTCX_CSR_CLK_EN(_VAL_) (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_MCU_DBG_SEL(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_SEL)) & 0xffffffc0))
+#define SET_MCU_STOP_NOGRANT(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffeff))
+#define SET_MCU_STOP_ANYTIME(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffdff))
+#define SET_MCU_DBG_DATA(_VAL_) (REG32(ADR_MCU_DBG_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_DATA)) & 0x00000000))
+#define SET_AHB_SW_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffe))
+#define SET_AHB_ERR_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffd))
+#define SET_REG_AHB_DEBUG_MX(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffffcf))
+#define SET_REG_PKT_W_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffeff))
+#define SET_REG_PKT_R_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffdff))
+#define SET_IQ_SRAM_SEL_0(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffefff))
+#define SET_IQ_SRAM_SEL_1(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffdfff))
+#define SET_IQ_SRAM_SEL_2(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffbfff))
+#define SET_AHB_STATUS(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_AHB_BRG_STATUS)) & 0x0000ffff))
+#define SET_PARALLEL_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffffe))
+#define SET_MBRUN(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xffffffef))
+#define SET_SHIFT_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffeff))
+#define SET_MODE_REG_SI(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffdff))
+#define SET_SIMULATION_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffbff))
+#define SET_DBIST_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffff7ff))
+#define SET_MODE_REG_IN(_VAL_) (REG32(ADR_BIST_MODE_REG_IN)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN)) & 0xffe00000))
+#define SET_MODE_REG_OUT_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0xffe00000))
+#define SET_MODE_REG_SO_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0x7fffffff))
+#define SET_MONITOR_BUS_MCU_31_0(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0x00000000))
+#define SET_MONITOR_BUS_MCU_33_32(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0xfffffffc))
+#define SET_TB_ADR_SEL(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_TB_ADR_SEL)) & 0xffff0000))
+#define SET_TB_CS(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 31) | ((REG32(ADR_TB_ADR_SEL)) & 0x7fffffff))
+#define SET_TB_RDATA(_VAL_) (REG32(ADR_TB_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_TB_RDATA)) & 0x00000000))
+#define SET_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 0) | ((REG32(ADR_UART_W2B)) & 0xfffffffe))
+#define SET_DATA_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 4) | ((REG32(ADR_UART_W2B)) & 0xffffffef))
+#define SET_AHB_ILL_ADDR(_VAL_) (REG32(ADR_AHB_ILL_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILL_ADDR)) & 0x00000000))
+#define SET_AHB_FEN_ADDR(_VAL_) (REG32(ADR_AHB_FEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_FEN_ADDR)) & 0x00000000))
+#define SET_ILL_ADDR_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffe))
+#define SET_FENCE_HIT_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffd))
+#define SET_ILL_ADDR_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffef))
+#define SET_FENCE_HIT_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffdf))
+#define SET_PWM_INI_VALUE_P_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_A)) & 0xffffff00))
+#define SET_PWM_INI_VALUE_N_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_A)) & 0xffff00ff))
+#define SET_PWM_POST_SCALER_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_A)) & 0xfff0ffff))
+#define SET_PWM_ALWAYSON_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_A)) & 0xdfffffff))
+#define SET_PWM_INVERT_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_A)) & 0xbfffffff))
+#define SET_PWM_ENABLE_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_A)) & 0x7fffffff))
+#define SET_PWM_INI_VALUE_P_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_B)) & 0xffffff00))
+#define SET_PWM_INI_VALUE_N_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_B)) & 0xffff00ff))
+#define SET_PWM_POST_SCALER_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_B)) & 0xfff0ffff))
+#define SET_PWM_ALWAYSON_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_B)) & 0xdfffffff))
+#define SET_PWM_INVERT_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_B)) & 0xbfffffff))
+#define SET_PWM_ENABLE_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_B)) & 0x7fffffff))
+#define SET_HBUSREQ_LOCK(_VAL_) (REG32(ADR_HBUSREQ_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBUSREQ_LOCK)) & 0xffffe000))
+#define SET_HBURST_LOCK(_VAL_) (REG32(ADR_HBURST_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBURST_LOCK)) & 0xffffe000))
+#define SET_PRESCALER_USTIMER(_VAL_) (REG32(ADR_PRESCALER_USTIMER)) = (((_VAL_) << 0) | ((REG32(ADR_PRESCALER_USTIMER)) & 0xfffffe00))
+#define SET_MODE_REG_IN_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0xffff0000))
+#define SET_MODE_REG_OUT_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0xffff0000))
+#define SET_MODE_REG_SO_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x7fffffff))
+#define SET_MONITOR_BUS_MMU(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0xfff80000))
+#define SET_TEST_MODE0(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_TEST_MODE)) & 0xfffffffe))
+#define SET_TEST_MODE1(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_TEST_MODE)) & 0xfffffffd))
+#define SET_TEST_MODE2(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_TEST_MODE)) & 0xfffffffb))
+#define SET_TEST_MODE3(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_TEST_MODE)) & 0xfffffff7))
+#define SET_TEST_MODE4(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_TEST_MODE)) & 0xffffffef))
+#define SET_TEST_MODE_ALL(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_TEST_MODE)) & 0xffffffdf))
+#define SET_WDT_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffe))
+#define SET_SD_HOST_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffd))
+#define SET_ALLOW_SD_RESET(_VAL_) (REG32(ADR_SD_INIT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_SD_INIT_CFG)) & 0xfffffffe))
+#define SET_UART_NRTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffe))
+#define SET_UART_NCTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffd))
+#define SET_TU0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU0_TM_MODE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU0_TM_INT_MASK(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU1_TM_MODE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU1_TM_INT_MASK(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU2_TM_MODE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU2_TM_INT_MASK(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU3_TM_MODE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU3_TM_INT_MASK(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM0_TM_MODE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM0_TM_INT_MASK(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM1_TM_MODE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM1_TM_INT_MASK(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM2_TM_MODE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM2_TM_INT_MASK(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM3_TM_MODE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM3_TM_INT_MASK(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_MCU_WDT_TIME_CNT(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_WDOG_REG)) & 0xffff0000))
+#define SET_MCU_WDT_STATUS(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_MCU_WDOG_REG)) & 0xfffdffff))
+#define SET_MCU_WDOG_ENA(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_MCU_WDOG_REG)) & 0x7fffffff))
+#define SET_SYS_WDT_TIME_CNT(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_WDOG_REG)) & 0xffff0000))
+#define SET_SYS_WDT_STATUS(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYS_WDOG_REG)) & 0xfffdffff))
+#define SET_SYS_WDOG_ENA(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYS_WDOG_REG)) & 0x7fffffff))
+#define SET_XLNA_EN_O_OE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 0) | ((REG32(ADR_PAD6)) & 0xfffffffe))
+#define SET_XLNA_EN_O_PE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 1) | ((REG32(ADR_PAD6)) & 0xfffffffd))
+#define SET_PAD6_IE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 3) | ((REG32(ADR_PAD6)) & 0xfffffff7))
+#define SET_PAD6_SEL_I(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 4) | ((REG32(ADR_PAD6)) & 0xffffffcf))
+#define SET_PAD6_OD(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 8) | ((REG32(ADR_PAD6)) & 0xfffffeff))
+#define SET_PAD6_SEL_O(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 12) | ((REG32(ADR_PAD6)) & 0xffffefff))
+#define SET_XLNA_EN_O_C(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 28) | ((REG32(ADR_PAD6)) & 0xefffffff))
+#define SET_WIFI_TX_SW_O_OE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 0) | ((REG32(ADR_PAD7)) & 0xfffffffe))
+#define SET_WIFI_TX_SW_O_PE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 1) | ((REG32(ADR_PAD7)) & 0xfffffffd))
+#define SET_PAD7_IE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 3) | ((REG32(ADR_PAD7)) & 0xfffffff7))
+#define SET_PAD7_SEL_I(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 4) | ((REG32(ADR_PAD7)) & 0xffffffcf))
+#define SET_PAD7_OD(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 8) | ((REG32(ADR_PAD7)) & 0xfffffeff))
+#define SET_PAD7_SEL_O(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 12) | ((REG32(ADR_PAD7)) & 0xffffefff))
+#define SET_WIFI_TX_SW_O_C(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 28) | ((REG32(ADR_PAD7)) & 0xefffffff))
+#define SET_WIFI_RX_SW_O_OE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 0) | ((REG32(ADR_PAD8)) & 0xfffffffe))
+#define SET_WIFI_RX_SW_O_PE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 1) | ((REG32(ADR_PAD8)) & 0xfffffffd))
+#define SET_PAD8_IE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 3) | ((REG32(ADR_PAD8)) & 0xfffffff7))
+#define SET_PAD8_SEL_I(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 4) | ((REG32(ADR_PAD8)) & 0xffffffcf))
+#define SET_PAD8_OD(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 8) | ((REG32(ADR_PAD8)) & 0xfffffeff))
+#define SET_WIFI_RX_SW_O_C(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 28) | ((REG32(ADR_PAD8)) & 0xefffffff))
+#define SET_BT_SW_O_OE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 0) | ((REG32(ADR_PAD9)) & 0xfffffffe))
+#define SET_BT_SW_O_PE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 1) | ((REG32(ADR_PAD9)) & 0xfffffffd))
+#define SET_PAD9_IE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 3) | ((REG32(ADR_PAD9)) & 0xfffffff7))
+#define SET_PAD9_SEL_I(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 4) | ((REG32(ADR_PAD9)) & 0xffffffcf))
+#define SET_PAD9_OD(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 8) | ((REG32(ADR_PAD9)) & 0xfffffeff))
+#define SET_PAD9_SEL_O(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 12) | ((REG32(ADR_PAD9)) & 0xffffefff))
+#define SET_BT_SW_O_C(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 28) | ((REG32(ADR_PAD9)) & 0xefffffff))
+#define SET_XPA_EN_O_OE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 0) | ((REG32(ADR_PAD11)) & 0xfffffffe))
+#define SET_XPA_EN_O_PE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 1) | ((REG32(ADR_PAD11)) & 0xfffffffd))
+#define SET_PAD11_IE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 3) | ((REG32(ADR_PAD11)) & 0xfffffff7))
+#define SET_PAD11_SEL_I(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 4) | ((REG32(ADR_PAD11)) & 0xffffffcf))
+#define SET_PAD11_OD(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 8) | ((REG32(ADR_PAD11)) & 0xfffffeff))
+#define SET_PAD11_SEL_O(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 12) | ((REG32(ADR_PAD11)) & 0xffffefff))
+#define SET_XPA_EN_O_C(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 28) | ((REG32(ADR_PAD11)) & 0xefffffff))
+#define SET_PAD15_OE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 0) | ((REG32(ADR_PAD15)) & 0xfffffffe))
+#define SET_PAD15_PE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 1) | ((REG32(ADR_PAD15)) & 0xfffffffd))
+#define SET_PAD15_DS(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 2) | ((REG32(ADR_PAD15)) & 0xfffffffb))
+#define SET_PAD15_IE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 3) | ((REG32(ADR_PAD15)) & 0xfffffff7))
+#define SET_PAD15_SEL_I(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 4) | ((REG32(ADR_PAD15)) & 0xffffffcf))
+#define SET_PAD15_OD(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 8) | ((REG32(ADR_PAD15)) & 0xfffffeff))
+#define SET_PAD15_SEL_O(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 12) | ((REG32(ADR_PAD15)) & 0xffffefff))
+#define SET_TEST_1_ID(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 28) | ((REG32(ADR_PAD15)) & 0xefffffff))
+#define SET_PAD16_OE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 0) | ((REG32(ADR_PAD16)) & 0xfffffffe))
+#define SET_PAD16_PE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 1) | ((REG32(ADR_PAD16)) & 0xfffffffd))
+#define SET_PAD16_DS(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 2) | ((REG32(ADR_PAD16)) & 0xfffffffb))
+#define SET_PAD16_IE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 3) | ((REG32(ADR_PAD16)) & 0xfffffff7))
+#define SET_PAD16_SEL_I(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 4) | ((REG32(ADR_PAD16)) & 0xffffffcf))
+#define SET_PAD16_OD(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 8) | ((REG32(ADR_PAD16)) & 0xfffffeff))
+#define SET_PAD16_SEL_O(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 12) | ((REG32(ADR_PAD16)) & 0xffffefff))
+#define SET_TEST_2_ID(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 28) | ((REG32(ADR_PAD16)) & 0xefffffff))
+#define SET_PAD17_OE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 0) | ((REG32(ADR_PAD17)) & 0xfffffffe))
+#define SET_PAD17_PE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 1) | ((REG32(ADR_PAD17)) & 0xfffffffd))
+#define SET_PAD17_DS(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 2) | ((REG32(ADR_PAD17)) & 0xfffffffb))
+#define SET_PAD17_IE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 3) | ((REG32(ADR_PAD17)) & 0xfffffff7))
+#define SET_PAD17_SEL_I(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 4) | ((REG32(ADR_PAD17)) & 0xffffffcf))
+#define SET_PAD17_OD(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 8) | ((REG32(ADR_PAD17)) & 0xfffffeff))
+#define SET_PAD17_SEL_O(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 12) | ((REG32(ADR_PAD17)) & 0xffffefff))
+#define SET_TEST_3_ID(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 28) | ((REG32(ADR_PAD17)) & 0xefffffff))
+#define SET_PAD18_OE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 0) | ((REG32(ADR_PAD18)) & 0xfffffffe))
+#define SET_PAD18_PE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 1) | ((REG32(ADR_PAD18)) & 0xfffffffd))
+#define SET_PAD18_DS(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 2) | ((REG32(ADR_PAD18)) & 0xfffffffb))
+#define SET_PAD18_IE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 3) | ((REG32(ADR_PAD18)) & 0xfffffff7))
+#define SET_PAD18_SEL_I(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 4) | ((REG32(ADR_PAD18)) & 0xffffffcf))
+#define SET_PAD18_OD(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 8) | ((REG32(ADR_PAD18)) & 0xfffffeff))
+#define SET_PAD18_SEL_O(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 12) | ((REG32(ADR_PAD18)) & 0xffffcfff))
+#define SET_TEST_4_ID(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 28) | ((REG32(ADR_PAD18)) & 0xefffffff))
+#define SET_PAD19_OE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 0) | ((REG32(ADR_PAD19)) & 0xfffffffe))
+#define SET_PAD19_PE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 1) | ((REG32(ADR_PAD19)) & 0xfffffffd))
+#define SET_PAD19_DS(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 2) | ((REG32(ADR_PAD19)) & 0xfffffffb))
+#define SET_PAD19_IE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 3) | ((REG32(ADR_PAD19)) & 0xfffffff7))
+#define SET_PAD19_SEL_I(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 4) | ((REG32(ADR_PAD19)) & 0xffffffcf))
+#define SET_PAD19_OD(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 8) | ((REG32(ADR_PAD19)) & 0xfffffeff))
+#define SET_PAD19_SEL_O(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 12) | ((REG32(ADR_PAD19)) & 0xffff8fff))
+#define SET_SHORT_TO_20_ID(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 28) | ((REG32(ADR_PAD19)) & 0xefffffff))
+#define SET_PAD20_OE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 0) | ((REG32(ADR_PAD20)) & 0xfffffffe))
+#define SET_PAD20_PE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 1) | ((REG32(ADR_PAD20)) & 0xfffffffd))
+#define SET_PAD20_DS(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 2) | ((REG32(ADR_PAD20)) & 0xfffffffb))
+#define SET_PAD20_IE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 3) | ((REG32(ADR_PAD20)) & 0xfffffff7))
+#define SET_PAD20_SEL_I(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 4) | ((REG32(ADR_PAD20)) & 0xffffff0f))
+#define SET_PAD20_OD(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 8) | ((REG32(ADR_PAD20)) & 0xfffffeff))
+#define SET_PAD20_SEL_O(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 12) | ((REG32(ADR_PAD20)) & 0xffffcfff))
+#define SET_STRAP0(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 27) | ((REG32(ADR_PAD20)) & 0xf7ffffff))
+#define SET_GPIO_TEST_1_ID(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 28) | ((REG32(ADR_PAD20)) & 0xefffffff))
+#define SET_PAD21_OE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 0) | ((REG32(ADR_PAD21)) & 0xfffffffe))
+#define SET_PAD21_PE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 1) | ((REG32(ADR_PAD21)) & 0xfffffffd))
+#define SET_PAD21_DS(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 2) | ((REG32(ADR_PAD21)) & 0xfffffffb))
+#define SET_PAD21_IE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 3) | ((REG32(ADR_PAD21)) & 0xfffffff7))
+#define SET_PAD21_SEL_I(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 4) | ((REG32(ADR_PAD21)) & 0xffffff8f))
+#define SET_PAD21_OD(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 8) | ((REG32(ADR_PAD21)) & 0xfffffeff))
+#define SET_PAD21_SEL_O(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 12) | ((REG32(ADR_PAD21)) & 0xffffcfff))
+#define SET_STRAP3(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 27) | ((REG32(ADR_PAD21)) & 0xf7ffffff))
+#define SET_GPIO_TEST_2_ID(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 28) | ((REG32(ADR_PAD21)) & 0xefffffff))
+#define SET_PAD22_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 0) | ((REG32(ADR_PAD22)) & 0xfffffffe))
+#define SET_PAD22_PE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 1) | ((REG32(ADR_PAD22)) & 0xfffffffd))
+#define SET_PAD22_DS(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 2) | ((REG32(ADR_PAD22)) & 0xfffffffb))
+#define SET_PAD22_IE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 3) | ((REG32(ADR_PAD22)) & 0xfffffff7))
+#define SET_PAD22_SEL_I(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 4) | ((REG32(ADR_PAD22)) & 0xffffff8f))
+#define SET_PAD22_OD(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 8) | ((REG32(ADR_PAD22)) & 0xfffffeff))
+#define SET_PAD22_SEL_O(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 12) | ((REG32(ADR_PAD22)) & 0xffff8fff))
+#define SET_PAD22_SEL_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 20) | ((REG32(ADR_PAD22)) & 0xffefffff))
+#define SET_GPIO_TEST_3_ID(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 28) | ((REG32(ADR_PAD22)) & 0xefffffff))
+#define SET_PAD24_OE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 0) | ((REG32(ADR_PAD24)) & 0xfffffffe))
+#define SET_PAD24_PE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 1) | ((REG32(ADR_PAD24)) & 0xfffffffd))
+#define SET_PAD24_DS(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 2) | ((REG32(ADR_PAD24)) & 0xfffffffb))
+#define SET_PAD24_IE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 3) | ((REG32(ADR_PAD24)) & 0xfffffff7))
+#define SET_PAD24_SEL_I(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 4) | ((REG32(ADR_PAD24)) & 0xffffffcf))
+#define SET_PAD24_OD(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 8) | ((REG32(ADR_PAD24)) & 0xfffffeff))
+#define SET_PAD24_SEL_O(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 12) | ((REG32(ADR_PAD24)) & 0xffff8fff))
+#define SET_GPIO_TEST_4_ID(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 28) | ((REG32(ADR_PAD24)) & 0xefffffff))
+#define SET_PAD25_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 0) | ((REG32(ADR_PAD25)) & 0xfffffffe))
+#define SET_PAD25_PE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 1) | ((REG32(ADR_PAD25)) & 0xfffffffd))
+#define SET_PAD25_DS(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 2) | ((REG32(ADR_PAD25)) & 0xfffffffb))
+#define SET_PAD25_IE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 3) | ((REG32(ADR_PAD25)) & 0xfffffff7))
+#define SET_PAD25_SEL_I(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 4) | ((REG32(ADR_PAD25)) & 0xffffff8f))
+#define SET_PAD25_OD(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 8) | ((REG32(ADR_PAD25)) & 0xfffffeff))
+#define SET_PAD25_SEL_O(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 12) | ((REG32(ADR_PAD25)) & 0xffff8fff))
+#define SET_PAD25_SEL_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 20) | ((REG32(ADR_PAD25)) & 0xffefffff))
+#define SET_STRAP1(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 27) | ((REG32(ADR_PAD25)) & 0xf7ffffff))
+#define SET_GPIO_1_ID(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 28) | ((REG32(ADR_PAD25)) & 0xefffffff))
+#define SET_PAD27_OE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 0) | ((REG32(ADR_PAD27)) & 0xfffffffe))
+#define SET_PAD27_PE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 1) | ((REG32(ADR_PAD27)) & 0xfffffffd))
+#define SET_PAD27_DS(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 2) | ((REG32(ADR_PAD27)) & 0xfffffffb))
+#define SET_PAD27_IE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 3) | ((REG32(ADR_PAD27)) & 0xfffffff7))
+#define SET_PAD27_SEL_I(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 4) | ((REG32(ADR_PAD27)) & 0xffffff8f))
+#define SET_PAD27_OD(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 8) | ((REG32(ADR_PAD27)) & 0xfffffeff))
+#define SET_PAD27_SEL_O(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 12) | ((REG32(ADR_PAD27)) & 0xffff8fff))
+#define SET_GPIO_2_ID(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 28) | ((REG32(ADR_PAD27)) & 0xefffffff))
+#define SET_PAD28_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 0) | ((REG32(ADR_PAD28)) & 0xfffffffe))
+#define SET_PAD28_PE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 1) | ((REG32(ADR_PAD28)) & 0xfffffffd))
+#define SET_PAD28_DS(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 2) | ((REG32(ADR_PAD28)) & 0xfffffffb))
+#define SET_PAD28_IE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 3) | ((REG32(ADR_PAD28)) & 0xfffffff7))
+#define SET_PAD28_SEL_I(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 4) | ((REG32(ADR_PAD28)) & 0xffffff8f))
+#define SET_PAD28_OD(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 8) | ((REG32(ADR_PAD28)) & 0xfffffeff))
+#define SET_PAD28_SEL_O(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 12) | ((REG32(ADR_PAD28)) & 0xffff0fff))
+#define SET_PAD28_SEL_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 20) | ((REG32(ADR_PAD28)) & 0xffefffff))
+#define SET_GPIO_3_ID(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 28) | ((REG32(ADR_PAD28)) & 0xefffffff))
+#define SET_PAD29_OE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 0) | ((REG32(ADR_PAD29)) & 0xfffffffe))
+#define SET_PAD29_PE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 1) | ((REG32(ADR_PAD29)) & 0xfffffffd))
+#define SET_PAD29_DS(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 2) | ((REG32(ADR_PAD29)) & 0xfffffffb))
+#define SET_PAD29_IE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 3) | ((REG32(ADR_PAD29)) & 0xfffffff7))
+#define SET_PAD29_SEL_I(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 4) | ((REG32(ADR_PAD29)) & 0xffffff8f))
+#define SET_PAD29_OD(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 8) | ((REG32(ADR_PAD29)) & 0xfffffeff))
+#define SET_PAD29_SEL_O(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 12) | ((REG32(ADR_PAD29)) & 0xffff8fff))
+#define SET_GPIO_TEST_5_ID(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 28) | ((REG32(ADR_PAD29)) & 0xefffffff))
+#define SET_PAD30_OE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 0) | ((REG32(ADR_PAD30)) & 0xfffffffe))
+#define SET_PAD30_PE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 1) | ((REG32(ADR_PAD30)) & 0xfffffffd))
+#define SET_PAD30_DS(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 2) | ((REG32(ADR_PAD30)) & 0xfffffffb))
+#define SET_PAD30_IE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 3) | ((REG32(ADR_PAD30)) & 0xfffffff7))
+#define SET_PAD30_SEL_I(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 4) | ((REG32(ADR_PAD30)) & 0xffffffcf))
+#define SET_PAD30_OD(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 8) | ((REG32(ADR_PAD30)) & 0xfffffeff))
+#define SET_PAD30_SEL_O(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 12) | ((REG32(ADR_PAD30)) & 0xffffcfff))
+#define SET_TEST_6_ID(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 28) | ((REG32(ADR_PAD30)) & 0xefffffff))
+#define SET_PAD31_OE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 0) | ((REG32(ADR_PAD31)) & 0xfffffffe))
+#define SET_PAD31_PE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 1) | ((REG32(ADR_PAD31)) & 0xfffffffd))
+#define SET_PAD31_DS(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 2) | ((REG32(ADR_PAD31)) & 0xfffffffb))
+#define SET_PAD31_IE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 3) | ((REG32(ADR_PAD31)) & 0xfffffff7))
+#define SET_PAD31_SEL_I(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 4) | ((REG32(ADR_PAD31)) & 0xffffffcf))
+#define SET_PAD31_OD(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 8) | ((REG32(ADR_PAD31)) & 0xfffffeff))
+#define SET_PAD31_SEL_O(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 12) | ((REG32(ADR_PAD31)) & 0xffffcfff))
+#define SET_TEST_7_ID(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 28) | ((REG32(ADR_PAD31)) & 0xefffffff))
+#define SET_PAD32_OE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 0) | ((REG32(ADR_PAD32)) & 0xfffffffe))
+#define SET_PAD32_PE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 1) | ((REG32(ADR_PAD32)) & 0xfffffffd))
+#define SET_PAD32_DS(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 2) | ((REG32(ADR_PAD32)) & 0xfffffffb))
+#define SET_PAD32_IE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 3) | ((REG32(ADR_PAD32)) & 0xfffffff7))
+#define SET_PAD32_SEL_I(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 4) | ((REG32(ADR_PAD32)) & 0xffffffcf))
+#define SET_PAD32_OD(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 8) | ((REG32(ADR_PAD32)) & 0xfffffeff))
+#define SET_PAD32_SEL_O(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 12) | ((REG32(ADR_PAD32)) & 0xffffcfff))
+#define SET_TEST_8_ID(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 28) | ((REG32(ADR_PAD32)) & 0xefffffff))
+#define SET_PAD33_OE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 0) | ((REG32(ADR_PAD33)) & 0xfffffffe))
+#define SET_PAD33_PE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 1) | ((REG32(ADR_PAD33)) & 0xfffffffd))
+#define SET_PAD33_DS(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 2) | ((REG32(ADR_PAD33)) & 0xfffffffb))
+#define SET_PAD33_IE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 3) | ((REG32(ADR_PAD33)) & 0xfffffff7))
+#define SET_PAD33_SEL_I(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 4) | ((REG32(ADR_PAD33)) & 0xffffffcf))
+#define SET_PAD33_OD(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 8) | ((REG32(ADR_PAD33)) & 0xfffffeff))
+#define SET_PAD33_SEL_O(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 12) | ((REG32(ADR_PAD33)) & 0xffffcfff))
+#define SET_TEST_9_ID(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 28) | ((REG32(ADR_PAD33)) & 0xefffffff))
+#define SET_PAD34_OE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 0) | ((REG32(ADR_PAD34)) & 0xfffffffe))
+#define SET_PAD34_PE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 1) | ((REG32(ADR_PAD34)) & 0xfffffffd))
+#define SET_PAD34_DS(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 2) | ((REG32(ADR_PAD34)) & 0xfffffffb))
+#define SET_PAD34_IE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 3) | ((REG32(ADR_PAD34)) & 0xfffffff7))
+#define SET_PAD34_SEL_I(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 4) | ((REG32(ADR_PAD34)) & 0xffffffcf))
+#define SET_PAD34_OD(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 8) | ((REG32(ADR_PAD34)) & 0xfffffeff))
+#define SET_PAD34_SEL_O(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 12) | ((REG32(ADR_PAD34)) & 0xffffcfff))
+#define SET_TEST_10_ID(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 28) | ((REG32(ADR_PAD34)) & 0xefffffff))
+#define SET_PAD42_OE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 0) | ((REG32(ADR_PAD42)) & 0xfffffffe))
+#define SET_PAD42_PE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 1) | ((REG32(ADR_PAD42)) & 0xfffffffd))
+#define SET_PAD42_DS(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 2) | ((REG32(ADR_PAD42)) & 0xfffffffb))
+#define SET_PAD42_IE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 3) | ((REG32(ADR_PAD42)) & 0xfffffff7))
+#define SET_PAD42_SEL_I(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 4) | ((REG32(ADR_PAD42)) & 0xffffffcf))
+#define SET_PAD42_OD(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 8) | ((REG32(ADR_PAD42)) & 0xfffffeff))
+#define SET_PAD42_SEL_O(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 12) | ((REG32(ADR_PAD42)) & 0xffffefff))
+#define SET_TEST_11_ID(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 28) | ((REG32(ADR_PAD42)) & 0xefffffff))
+#define SET_PAD43_OE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 0) | ((REG32(ADR_PAD43)) & 0xfffffffe))
+#define SET_PAD43_PE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 1) | ((REG32(ADR_PAD43)) & 0xfffffffd))
+#define SET_PAD43_DS(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 2) | ((REG32(ADR_PAD43)) & 0xfffffffb))
+#define SET_PAD43_IE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 3) | ((REG32(ADR_PAD43)) & 0xfffffff7))
+#define SET_PAD43_SEL_I(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 4) | ((REG32(ADR_PAD43)) & 0xffffffcf))
+#define SET_PAD43_OD(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 8) | ((REG32(ADR_PAD43)) & 0xfffffeff))
+#define SET_PAD43_SEL_O(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 12) | ((REG32(ADR_PAD43)) & 0xffffefff))
+#define SET_TEST_12_ID(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 28) | ((REG32(ADR_PAD43)) & 0xefffffff))
+#define SET_PAD44_OE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 0) | ((REG32(ADR_PAD44)) & 0xfffffffe))
+#define SET_PAD44_PE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 1) | ((REG32(ADR_PAD44)) & 0xfffffffd))
+#define SET_PAD44_DS(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 2) | ((REG32(ADR_PAD44)) & 0xfffffffb))
+#define SET_PAD44_IE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 3) | ((REG32(ADR_PAD44)) & 0xfffffff7))
+#define SET_PAD44_SEL_I(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 4) | ((REG32(ADR_PAD44)) & 0xffffffcf))
+#define SET_PAD44_OD(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 8) | ((REG32(ADR_PAD44)) & 0xfffffeff))
+#define SET_PAD44_SEL_O(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 12) | ((REG32(ADR_PAD44)) & 0xffffcfff))
+#define SET_TEST_13_ID(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 28) | ((REG32(ADR_PAD44)) & 0xefffffff))
+#define SET_PAD45_OE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 0) | ((REG32(ADR_PAD45)) & 0xfffffffe))
+#define SET_PAD45_PE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 1) | ((REG32(ADR_PAD45)) & 0xfffffffd))
+#define SET_PAD45_DS(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 2) | ((REG32(ADR_PAD45)) & 0xfffffffb))
+#define SET_PAD45_IE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 3) | ((REG32(ADR_PAD45)) & 0xfffffff7))
+#define SET_PAD45_SEL_I(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 4) | ((REG32(ADR_PAD45)) & 0xffffffcf))
+#define SET_PAD45_OD(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 8) | ((REG32(ADR_PAD45)) & 0xfffffeff))
+#define SET_PAD45_SEL_O(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 12) | ((REG32(ADR_PAD45)) & 0xffffcfff))
+#define SET_TEST_14_ID(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 28) | ((REG32(ADR_PAD45)) & 0xefffffff))
+#define SET_PAD46_OE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 0) | ((REG32(ADR_PAD46)) & 0xfffffffe))
+#define SET_PAD46_PE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 1) | ((REG32(ADR_PAD46)) & 0xfffffffd))
+#define SET_PAD46_DS(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 2) | ((REG32(ADR_PAD46)) & 0xfffffffb))
+#define SET_PAD46_IE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 3) | ((REG32(ADR_PAD46)) & 0xfffffff7))
+#define SET_PAD46_SEL_I(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 4) | ((REG32(ADR_PAD46)) & 0xffffffcf))
+#define SET_PAD46_OD(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 8) | ((REG32(ADR_PAD46)) & 0xfffffeff))
+#define SET_PAD46_SEL_O(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 12) | ((REG32(ADR_PAD46)) & 0xffffcfff))
+#define SET_TEST_15_ID(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 28) | ((REG32(ADR_PAD46)) & 0xefffffff))
+#define SET_PAD47_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 0) | ((REG32(ADR_PAD47)) & 0xfffffffe))
+#define SET_PAD47_PE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 1) | ((REG32(ADR_PAD47)) & 0xfffffffd))
+#define SET_PAD47_DS(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 2) | ((REG32(ADR_PAD47)) & 0xfffffffb))
+#define SET_PAD47_SEL_I(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 4) | ((REG32(ADR_PAD47)) & 0xffffffcf))
+#define SET_PAD47_OD(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 8) | ((REG32(ADR_PAD47)) & 0xfffffeff))
+#define SET_PAD47_SEL_O(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 12) | ((REG32(ADR_PAD47)) & 0xffffcfff))
+#define SET_PAD47_SEL_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 20) | ((REG32(ADR_PAD47)) & 0xffefffff))
+#define SET_GPIO_9_ID(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 28) | ((REG32(ADR_PAD47)) & 0xefffffff))
+#define SET_PAD48_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 0) | ((REG32(ADR_PAD48)) & 0xfffffffe))
+#define SET_PAD48_PE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 1) | ((REG32(ADR_PAD48)) & 0xfffffffd))
+#define SET_PAD48_DS(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 2) | ((REG32(ADR_PAD48)) & 0xfffffffb))
+#define SET_PAD48_IE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 3) | ((REG32(ADR_PAD48)) & 0xfffffff7))
+#define SET_PAD48_SEL_I(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 4) | ((REG32(ADR_PAD48)) & 0xffffff8f))
+#define SET_PAD48_OD(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 8) | ((REG32(ADR_PAD48)) & 0xfffffeff))
+#define SET_PAD48_PE_SEL(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 11) | ((REG32(ADR_PAD48)) & 0xfffff7ff))
+#define SET_PAD48_SEL_O(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 12) | ((REG32(ADR_PAD48)) & 0xffffcfff))
+#define SET_PAD48_SEL_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 20) | ((REG32(ADR_PAD48)) & 0xffefffff))
+#define SET_GPIO_10_ID(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 28) | ((REG32(ADR_PAD48)) & 0xefffffff))
+#define SET_PAD49_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 0) | ((REG32(ADR_PAD49)) & 0xfffffffe))
+#define SET_PAD49_PE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 1) | ((REG32(ADR_PAD49)) & 0xfffffffd))
+#define SET_PAD49_DS(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 2) | ((REG32(ADR_PAD49)) & 0xfffffffb))
+#define SET_PAD49_IE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 3) | ((REG32(ADR_PAD49)) & 0xfffffff7))
+#define SET_PAD49_SEL_I(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 4) | ((REG32(ADR_PAD49)) & 0xffffff8f))
+#define SET_PAD49_OD(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 8) | ((REG32(ADR_PAD49)) & 0xfffffeff))
+#define SET_PAD49_SEL_O(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 12) | ((REG32(ADR_PAD49)) & 0xffffcfff))
+#define SET_PAD49_SEL_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 20) | ((REG32(ADR_PAD49)) & 0xffefffff))
+#define SET_GPIO_11_ID(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 28) | ((REG32(ADR_PAD49)) & 0xefffffff))
+#define SET_PAD50_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 0) | ((REG32(ADR_PAD50)) & 0xfffffffe))
+#define SET_PAD50_PE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 1) | ((REG32(ADR_PAD50)) & 0xfffffffd))
+#define SET_PAD50_DS(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 2) | ((REG32(ADR_PAD50)) & 0xfffffffb))
+#define SET_PAD50_IE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 3) | ((REG32(ADR_PAD50)) & 0xfffffff7))
+#define SET_PAD50_SEL_I(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 4) | ((REG32(ADR_PAD50)) & 0xffffff8f))
+#define SET_PAD50_OD(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 8) | ((REG32(ADR_PAD50)) & 0xfffffeff))
+#define SET_PAD50_SEL_O(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 12) | ((REG32(ADR_PAD50)) & 0xffffcfff))
+#define SET_PAD50_SEL_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 20) | ((REG32(ADR_PAD50)) & 0xffefffff))
+#define SET_GPIO_12_ID(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 28) | ((REG32(ADR_PAD50)) & 0xefffffff))
+#define SET_PAD51_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 0) | ((REG32(ADR_PAD51)) & 0xfffffffe))
+#define SET_PAD51_PE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 1) | ((REG32(ADR_PAD51)) & 0xfffffffd))
+#define SET_PAD51_DS(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 2) | ((REG32(ADR_PAD51)) & 0xfffffffb))
+#define SET_PAD51_IE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 3) | ((REG32(ADR_PAD51)) & 0xfffffff7))
+#define SET_PAD51_SEL_I(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 4) | ((REG32(ADR_PAD51)) & 0xffffffcf))
+#define SET_PAD51_OD(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 8) | ((REG32(ADR_PAD51)) & 0xfffffeff))
+#define SET_PAD51_SEL_O(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 12) | ((REG32(ADR_PAD51)) & 0xffffefff))
+#define SET_PAD51_SEL_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 20) | ((REG32(ADR_PAD51)) & 0xffefffff))
+#define SET_GPIO_13_ID(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 28) | ((REG32(ADR_PAD51)) & 0xefffffff))
+#define SET_PAD52_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 0) | ((REG32(ADR_PAD52)) & 0xfffffffe))
+#define SET_PAD52_PE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 1) | ((REG32(ADR_PAD52)) & 0xfffffffd))
+#define SET_PAD52_DS(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 2) | ((REG32(ADR_PAD52)) & 0xfffffffb))
+#define SET_PAD52_SEL_I(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 4) | ((REG32(ADR_PAD52)) & 0xffffffcf))
+#define SET_PAD52_OD(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 8) | ((REG32(ADR_PAD52)) & 0xfffffeff))
+#define SET_PAD52_SEL_O(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 12) | ((REG32(ADR_PAD52)) & 0xffffefff))
+#define SET_PAD52_SEL_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 20) | ((REG32(ADR_PAD52)) & 0xffefffff))
+#define SET_GPIO_14_ID(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 28) | ((REG32(ADR_PAD52)) & 0xefffffff))
+#define SET_PAD53_OE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 0) | ((REG32(ADR_PAD53)) & 0xfffffffe))
+#define SET_PAD53_PE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 1) | ((REG32(ADR_PAD53)) & 0xfffffffd))
+#define SET_PAD53_DS(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 2) | ((REG32(ADR_PAD53)) & 0xfffffffb))
+#define SET_PAD53_IE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 3) | ((REG32(ADR_PAD53)) & 0xfffffff7))
+#define SET_PAD53_SEL_I(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 4) | ((REG32(ADR_PAD53)) & 0xffffffcf))
+#define SET_PAD53_OD(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 8) | ((REG32(ADR_PAD53)) & 0xfffffeff))
+#define SET_PAD53_SEL_O(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 12) | ((REG32(ADR_PAD53)) & 0xffffefff))
+#define SET_JTAG_TMS_ID(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 28) | ((REG32(ADR_PAD53)) & 0xefffffff))
+#define SET_PAD54_OE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 0) | ((REG32(ADR_PAD54)) & 0xfffffffe))
+#define SET_PAD54_PE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 1) | ((REG32(ADR_PAD54)) & 0xfffffffd))
+#define SET_PAD54_DS(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 2) | ((REG32(ADR_PAD54)) & 0xfffffffb))
+#define SET_PAD54_OD(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 8) | ((REG32(ADR_PAD54)) & 0xfffffeff))
+#define SET_PAD54_SEL_O(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 12) | ((REG32(ADR_PAD54)) & 0xffffcfff))
+#define SET_JTAG_TCK_ID(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 28) | ((REG32(ADR_PAD54)) & 0xefffffff))
+#define SET_PAD56_PE(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 1) | ((REG32(ADR_PAD56)) & 0xfffffffd))
+#define SET_PAD56_DS(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 2) | ((REG32(ADR_PAD56)) & 0xfffffffb))
+#define SET_PAD56_SEL_I(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 4) | ((REG32(ADR_PAD56)) & 0xffffffef))
+#define SET_PAD56_OD(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 8) | ((REG32(ADR_PAD56)) & 0xfffffeff))
+#define SET_JTAG_TDI_ID(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 28) | ((REG32(ADR_PAD56)) & 0xefffffff))
+#define SET_PAD57_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 0) | ((REG32(ADR_PAD57)) & 0xfffffffe))
+#define SET_PAD57_PE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 1) | ((REG32(ADR_PAD57)) & 0xfffffffd))
+#define SET_PAD57_DS(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 2) | ((REG32(ADR_PAD57)) & 0xfffffffb))
+#define SET_PAD57_IE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 3) | ((REG32(ADR_PAD57)) & 0xfffffff7))
+#define SET_PAD57_SEL_I(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 4) | ((REG32(ADR_PAD57)) & 0xffffffcf))
+#define SET_PAD57_OD(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 8) | ((REG32(ADR_PAD57)) & 0xfffffeff))
+#define SET_PAD57_SEL_O(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 12) | ((REG32(ADR_PAD57)) & 0xffffcfff))
+#define SET_PAD57_SEL_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 20) | ((REG32(ADR_PAD57)) & 0xffefffff))
+#define SET_JTAG_TDO_ID(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 28) | ((REG32(ADR_PAD57)) & 0xefffffff))
+#define SET_PAD58_OE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 0) | ((REG32(ADR_PAD58)) & 0xfffffffe))
+#define SET_PAD58_PE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 1) | ((REG32(ADR_PAD58)) & 0xfffffffd))
+#define SET_PAD58_DS(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 2) | ((REG32(ADR_PAD58)) & 0xfffffffb))
+#define SET_PAD58_IE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 3) | ((REG32(ADR_PAD58)) & 0xfffffff7))
+#define SET_PAD58_SEL_I(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 4) | ((REG32(ADR_PAD58)) & 0xffffffcf))
+#define SET_PAD58_OD(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 8) | ((REG32(ADR_PAD58)) & 0xfffffeff))
+#define SET_PAD58_SEL_O(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 12) | ((REG32(ADR_PAD58)) & 0xffffefff))
+#define SET_TEST_16_ID(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 28) | ((REG32(ADR_PAD58)) & 0xefffffff))
+#define SET_PAD59_OE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 0) | ((REG32(ADR_PAD59)) & 0xfffffffe))
+#define SET_PAD59_PE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 1) | ((REG32(ADR_PAD59)) & 0xfffffffd))
+#define SET_PAD59_DS(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 2) | ((REG32(ADR_PAD59)) & 0xfffffffb))
+#define SET_PAD59_IE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 3) | ((REG32(ADR_PAD59)) & 0xfffffff7))
+#define SET_PAD59_SEL_I(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 4) | ((REG32(ADR_PAD59)) & 0xffffffcf))
+#define SET_PAD59_OD(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 8) | ((REG32(ADR_PAD59)) & 0xfffffeff))
+#define SET_PAD59_SEL_O(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 12) | ((REG32(ADR_PAD59)) & 0xffffefff))
+#define SET_TEST_17_ID(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 28) | ((REG32(ADR_PAD59)) & 0xefffffff))
+#define SET_PAD60_OE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 0) | ((REG32(ADR_PAD60)) & 0xfffffffe))
+#define SET_PAD60_PE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 1) | ((REG32(ADR_PAD60)) & 0xfffffffd))
+#define SET_PAD60_DS(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 2) | ((REG32(ADR_PAD60)) & 0xfffffffb))
+#define SET_PAD60_IE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 3) | ((REG32(ADR_PAD60)) & 0xfffffff7))
+#define SET_PAD60_SEL_I(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 4) | ((REG32(ADR_PAD60)) & 0xffffffcf))
+#define SET_PAD60_OD(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 8) | ((REG32(ADR_PAD60)) & 0xfffffeff))
+#define SET_PAD60_SEL_O(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 12) | ((REG32(ADR_PAD60)) & 0xffffefff))
+#define SET_TEST_18_ID(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 28) | ((REG32(ADR_PAD60)) & 0xefffffff))
+#define SET_PAD61_OE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 0) | ((REG32(ADR_PAD61)) & 0xfffffffe))
+#define SET_PAD61_PE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 1) | ((REG32(ADR_PAD61)) & 0xfffffffd))
+#define SET_PAD61_DS(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 2) | ((REG32(ADR_PAD61)) & 0xfffffffb))
+#define SET_PAD61_IE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 3) | ((REG32(ADR_PAD61)) & 0xfffffff7))
+#define SET_PAD61_SEL_I(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 4) | ((REG32(ADR_PAD61)) & 0xffffffef))
+#define SET_PAD61_OD(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 8) | ((REG32(ADR_PAD61)) & 0xfffffeff))
+#define SET_PAD61_SEL_O(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 12) | ((REG32(ADR_PAD61)) & 0xffffcfff))
+#define SET_TEST_19_ID(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 28) | ((REG32(ADR_PAD61)) & 0xefffffff))
+#define SET_PAD62_OE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 0) | ((REG32(ADR_PAD62)) & 0xfffffffe))
+#define SET_PAD62_PE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 1) | ((REG32(ADR_PAD62)) & 0xfffffffd))
+#define SET_PAD62_DS(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 2) | ((REG32(ADR_PAD62)) & 0xfffffffb))
+#define SET_PAD62_IE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 3) | ((REG32(ADR_PAD62)) & 0xfffffff7))
+#define SET_PAD62_SEL_I(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 4) | ((REG32(ADR_PAD62)) & 0xffffffef))
+#define SET_PAD62_OD(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 8) | ((REG32(ADR_PAD62)) & 0xfffffeff))
+#define SET_PAD62_SEL_O(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 12) | ((REG32(ADR_PAD62)) & 0xffffefff))
+#define SET_TEST_20_ID(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 28) | ((REG32(ADR_PAD62)) & 0xefffffff))
+#define SET_PAD64_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 0) | ((REG32(ADR_PAD64)) & 0xfffffffe))
+#define SET_PAD64_PE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 1) | ((REG32(ADR_PAD64)) & 0xfffffffd))
+#define SET_PAD64_DS(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 2) | ((REG32(ADR_PAD64)) & 0xfffffffb))
+#define SET_PAD64_IE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 3) | ((REG32(ADR_PAD64)) & 0xfffffff7))
+#define SET_PAD64_SEL_I(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 4) | ((REG32(ADR_PAD64)) & 0xffffff8f))
+#define SET_PAD64_OD(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 8) | ((REG32(ADR_PAD64)) & 0xfffffeff))
+#define SET_PAD64_SEL_O(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 12) | ((REG32(ADR_PAD64)) & 0xffffcfff))
+#define SET_PAD64_SEL_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 20) | ((REG32(ADR_PAD64)) & 0xffefffff))
+#define SET_GPIO_15_IP_ID(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 28) | ((REG32(ADR_PAD64)) & 0xefffffff))
+#define SET_PAD65_OE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 0) | ((REG32(ADR_PAD65)) & 0xfffffffe))
+#define SET_PAD65_PE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 1) | ((REG32(ADR_PAD65)) & 0xfffffffd))
+#define SET_PAD65_DS(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 2) | ((REG32(ADR_PAD65)) & 0xfffffffb))
+#define SET_PAD65_IE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 3) | ((REG32(ADR_PAD65)) & 0xfffffff7))
+#define SET_PAD65_SEL_I(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 4) | ((REG32(ADR_PAD65)) & 0xffffff8f))
+#define SET_PAD65_OD(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 8) | ((REG32(ADR_PAD65)) & 0xfffffeff))
+#define SET_PAD65_SEL_O(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 12) | ((REG32(ADR_PAD65)) & 0xffffefff))
+#define SET_GPIO_TEST_7_IN_ID(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 28) | ((REG32(ADR_PAD65)) & 0xefffffff))
+#define SET_PAD66_OE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 0) | ((REG32(ADR_PAD66)) & 0xfffffffe))
+#define SET_PAD66_PE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 1) | ((REG32(ADR_PAD66)) & 0xfffffffd))
+#define SET_PAD66_DS(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 2) | ((REG32(ADR_PAD66)) & 0xfffffffb))
+#define SET_PAD66_IE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 3) | ((REG32(ADR_PAD66)) & 0xfffffff7))
+#define SET_PAD66_SEL_I(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 4) | ((REG32(ADR_PAD66)) & 0xffffffcf))
+#define SET_PAD66_OD(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 8) | ((REG32(ADR_PAD66)) & 0xfffffeff))
+#define SET_PAD66_SEL_O(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 12) | ((REG32(ADR_PAD66)) & 0xffffcfff))
+#define SET_GPIO_17_QP_ID(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 28) | ((REG32(ADR_PAD66)) & 0xefffffff))
+#define SET_PAD68_OE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 0) | ((REG32(ADR_PAD68)) & 0xfffffffe))
+#define SET_PAD68_PE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 1) | ((REG32(ADR_PAD68)) & 0xfffffffd))
+#define SET_PAD68_DS(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 2) | ((REG32(ADR_PAD68)) & 0xfffffffb))
+#define SET_PAD68_IE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 3) | ((REG32(ADR_PAD68)) & 0xfffffff7))
+#define SET_PAD68_OD(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 8) | ((REG32(ADR_PAD68)) & 0xfffffeff))
+#define SET_PAD68_SEL_O(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 12) | ((REG32(ADR_PAD68)) & 0xffffefff))
+#define SET_GPIO_19_ID(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 28) | ((REG32(ADR_PAD68)) & 0xefffffff))
+#define SET_PAD67_OE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 0) | ((REG32(ADR_PAD67)) & 0xfffffffe))
+#define SET_PAD67_PE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 1) | ((REG32(ADR_PAD67)) & 0xfffffffd))
+#define SET_PAD67_DS(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 2) | ((REG32(ADR_PAD67)) & 0xfffffffb))
+#define SET_PAD67_IE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 3) | ((REG32(ADR_PAD67)) & 0xfffffff7))
+#define SET_PAD67_SEL_I(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 4) | ((REG32(ADR_PAD67)) & 0xffffff8f))
+#define SET_PAD67_OD(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 8) | ((REG32(ADR_PAD67)) & 0xfffffeff))
+#define SET_PAD67_SEL_O(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 12) | ((REG32(ADR_PAD67)) & 0xffffcfff))
+#define SET_GPIO_TEST_8_QN_ID(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 28) | ((REG32(ADR_PAD67)) & 0xefffffff))
+#define SET_PAD69_OE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 0) | ((REG32(ADR_PAD69)) & 0xfffffffe))
+#define SET_PAD69_PE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 1) | ((REG32(ADR_PAD69)) & 0xfffffffd))
+#define SET_PAD69_DS(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 2) | ((REG32(ADR_PAD69)) & 0xfffffffb))
+#define SET_PAD69_IE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 3) | ((REG32(ADR_PAD69)) & 0xfffffff7))
+#define SET_PAD69_SEL_I(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 4) | ((REG32(ADR_PAD69)) & 0xffffffcf))
+#define SET_PAD69_OD(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 8) | ((REG32(ADR_PAD69)) & 0xfffffeff))
+#define SET_PAD69_SEL_O(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 12) | ((REG32(ADR_PAD69)) & 0xffffefff))
+#define SET_STRAP2(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 27) | ((REG32(ADR_PAD69)) & 0xf7ffffff))
+#define SET_GPIO_20_ID(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 28) | ((REG32(ADR_PAD69)) & 0xefffffff))
+#define SET_PAD70_OE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 0) | ((REG32(ADR_PAD70)) & 0xfffffffe))
+#define SET_PAD70_PE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 1) | ((REG32(ADR_PAD70)) & 0xfffffffd))
+#define SET_PAD70_DS(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 2) | ((REG32(ADR_PAD70)) & 0xfffffffb))
+#define SET_PAD70_IE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 3) | ((REG32(ADR_PAD70)) & 0xfffffff7))
+#define SET_PAD70_SEL_I(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 4) | ((REG32(ADR_PAD70)) & 0xffffffcf))
+#define SET_PAD70_OD(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 8) | ((REG32(ADR_PAD70)) & 0xfffffeff))
+#define SET_PAD70_SEL_O(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 12) | ((REG32(ADR_PAD70)) & 0xffff8fff))
+#define SET_GPIO_21_ID(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 28) | ((REG32(ADR_PAD70)) & 0xefffffff))
+#define SET_PAD231_OE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 0) | ((REG32(ADR_PAD231)) & 0xfffffffe))
+#define SET_PAD231_PE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 1) | ((REG32(ADR_PAD231)) & 0xfffffffd))
+#define SET_PAD231_DS(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 2) | ((REG32(ADR_PAD231)) & 0xfffffffb))
+#define SET_PAD231_IE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 3) | ((REG32(ADR_PAD231)) & 0xfffffff7))
+#define SET_PAD231_OD(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 8) | ((REG32(ADR_PAD231)) & 0xfffffeff))
+#define SET_PIN_40_OR_56_ID(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 28) | ((REG32(ADR_PAD231)) & 0xefffffff))
+#define SET_MP_PHY2RX_DATA__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffe))
+#define SET_MP_PHY2RX_DATA__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffd))
+#define SET_MP_TX_FF_RPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 2) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffb))
+#define SET_MP_RX_FF_WPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 3) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffff7))
+#define SET_MP_RX_FF_WPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 4) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffef))
+#define SET_MP_RX_FF_WPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 5) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffdf))
+#define SET_MP_PHY2RX_DATA__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 6) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffbf))
+#define SET_MP_PHY2RX_DATA__4_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 7) | ((REG32(ADR_PIN_SEL_0)) & 0xffffff7f))
+#define SET_I2CM_SDA_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 8) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffcff))
+#define SET_CRYSTAL_OUT_REQ_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 10) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffbff))
+#define SET_MP_PHY2RX_DATA__5_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 11) | ((REG32(ADR_PIN_SEL_0)) & 0xfffff7ff))
+#define SET_MP_PHY2RX_DATA__3_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 12) | ((REG32(ADR_PIN_SEL_0)) & 0xffffefff))
+#define SET_UART_RXD_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 13) | ((REG32(ADR_PIN_SEL_0)) & 0xffff9fff))
+#define SET_MP_PHY2RX_DATA__6_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 15) | ((REG32(ADR_PIN_SEL_0)) & 0xffff7fff))
+#define SET_DAT_UART_NCTS_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 16) | ((REG32(ADR_PIN_SEL_0)) & 0xfffeffff))
+#define SET_GPIO_LOG_STOP_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 17) | ((REG32(ADR_PIN_SEL_0)) & 0xfff1ffff))
+#define SET_MP_TX_FF_RPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 20) | ((REG32(ADR_PIN_SEL_0)) & 0xffefffff))
+#define SET_MP_PHY_RX_WRST_N_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 21) | ((REG32(ADR_PIN_SEL_0)) & 0xffdfffff))
+#define SET_EXT_32K_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 22) | ((REG32(ADR_PIN_SEL_0)) & 0xff3fffff))
+#define SET_MP_PHY2RX_DATA__7_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 24) | ((REG32(ADR_PIN_SEL_0)) & 0xfeffffff))
+#define SET_MP_TX_FF_RPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 25) | ((REG32(ADR_PIN_SEL_0)) & 0xfdffffff))
+#define SET_PMUINT_WAKE_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 26) | ((REG32(ADR_PIN_SEL_0)) & 0xe3ffffff))
+#define SET_I2CM_SCL_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 29) | ((REG32(ADR_PIN_SEL_0)) & 0xdfffffff))
+#define SET_MP_MRX_RX_EN_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 30) | ((REG32(ADR_PIN_SEL_0)) & 0xbfffffff))
+#define SET_DAT_UART_RXD_SEL_0(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 31) | ((REG32(ADR_PIN_SEL_0)) & 0x7fffffff))
+#define SET_DAT_UART_RXD_SEL_1(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffe))
+#define SET_SPI_DI_SEL(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffd))
+#define SET_IO_PORT_REG(_VAL_) (REG32(ADR_IO_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_PORT_REG)) & 0xfffe0000))
+#define SET_MASK_RX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffe))
+#define SET_MASK_TX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffd))
+#define SET_MASK_SOC_SYSTEM_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffb))
+#define SET_EDCA0_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffff7))
+#define SET_EDCA1_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffef))
+#define SET_EDCA2_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffdf))
+#define SET_EDCA3_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_MASK_REG)) & 0xffffff7f))
+#define SET_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffe))
+#define SET_TX_COMPLETE_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffd))
+#define SET_SOC_SYSTEM_INT_STATUS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffb))
+#define SET_EDCA0_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffff7))
+#define SET_EDCA1_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffef))
+#define SET_EDCA2_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffdf))
+#define SET_EDCA3_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffff7f))
+#define SET_HOST_TRIGGERED_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffeff))
+#define SET_HOST_TRIGGERED_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 9) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffdff))
+#define SET_SOC_TRIGGER_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 10) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffbff))
+#define SET_SOC_TRIGGER_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 11) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffff7ff))
+#define SET_RDY_FOR_TX_RX(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffe))
+#define SET_RDY_FOR_FW_DOWNLOAD(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffd))
+#define SET_ILLEGAL_CMD_RESP_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffb))
+#define SET_SDIO_TRX_DATA_SEQUENCE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffff7))
+#define SET_GPIO_INT_TRIGGER_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffffef))
+#define SET_TRIGGER_FUNCTION_SETTING(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff9f))
+#define SET_CMD52_ABORT_RESPONSE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff7f))
+#define SET_RX_PACKET_LENGTH(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xffff0000))
+#define SET_CARD_FW_DL_STATUS(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 16) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xff00ffff))
+#define SET_TX_RX_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 24) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfeffffff))
+#define SET_SDIO_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 25) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfdffffff))
+#define SET_CMD52_ABORT_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 28) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xefffffff))
+#define SET_CMD52_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 29) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xdfffffff))
+#define SET_SDIO_PARTIAL_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 30) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xbfffffff))
+#define SET_SDIO_ALL_RESE_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 31) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x7fffffff))
+#define SET_RX_PACKET_LENGTH2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xffff0000))
+#define SET_RX_INT1(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffeffff))
+#define SET_TX_DONE(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffdffff))
+#define SET_HCI_TRX_FINISH(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffbffff))
+#define SET_ALLOCATE_STATUS(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfff7ffff))
+#define SET_HCI_INPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xff0fffff))
+#define SET_HCI_OUTPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xe0ffffff))
+#define SET_AHB_HANG4(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 29) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xdfffffff))
+#define SET_HCI_IN_QUE_EMPTY(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 30) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xbfffffff))
+#define SET_SYSTEM_INT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x7fffffff))
+#define SET_CARD_RCA_REG(_VAL_) (REG32(ADR_CARD_RCA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_RCA_REG)) & 0xffff0000))
+#define SET_SDIO_FIFO_WR_THLD_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0xfffffe00))
+#define SET_SDIO_FIFO_WR_LIMIT_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0xfffffe00))
+#define SET_SDIO_TX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
+#define SET_SDIO_THLD_FOR_CMD53RD_REG(_VAL_) (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0xfffffe00))
+#define SET_SDIO_RX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
+#define SET_START_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffffff00))
+#define SET_END_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffff00ff))
+#define SET_SDIO_BYTE_MODE_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0xffffff00))
+#define SET_SDIO_LAST_CMD_INDEX_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffffffc0))
+#define SET_SDIO_LAST_CMD_CRC_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffff80ff))
+#define SET_SDIO_LAST_CMD_ARG_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0x00000000))
+#define SET_SDIO_BUS_STATE_REG(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffffffe0))
+#define SET_SDIO_BUSY_LONG_CNT(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000ffff))
+#define SET_SDIO_CARD_STATUS_REG(_VAL_) (REG32(ADR_SDIO_CARD_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0x00000000))
+#define SET_R5_RESPONSE_FLAG(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 0) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xffffff00))
+#define SET_RESP_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 8) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffeff))
+#define SET_DAT_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 9) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffdff))
+#define SET_MCU_TO_SDIO_INFO_MASK(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 16) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffeffff))
+#define SET_INT_THROUGH_PIN(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 17) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffdffff))
+#define SET_WRITE_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffffff00))
+#define SET_WRITE_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 8) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffff00ff))
+#define SET_READ_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff00ffff))
+#define SET_READ_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 24) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ffffff))
+#define SET_FN1_DMA_START_ADDR_REG(_VAL_) (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0x00000000))
+#define SET_SDIO_TO_MCU_INFO(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffff00))
+#define SET_SDIO_PARTIAL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffeff))
+#define SET_SDIO_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffdff))
+#define SET_PERI_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffbff))
+#define SET_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffff7ff))
+#define SET_AHB_BRIDGE_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffefff))
+#define SET_IO_REG_PORT_REG(_VAL_) (REG32(ADR_IO_REG_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_REG_PORT_REG)) & 0xfffe0000))
+#define SET_SDIO_FIFO_EMPTY_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000))
+#define SET_SDIO_FIFO_FULL_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff))
+#define SET_SDIO_CRC7_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000))
+#define SET_SDIO_CRC16_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff))
+#define SET_SDIO_RD_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfffffe00))
+#define SET_SDIO_WR_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfe00ffff))
+#define SET_CMD52_RD_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xfff0ffff))
+#define SET_CMD52_WR_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 20) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xff0fffff))
+#define SET_SDIO_FIFO_WR_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffffff00))
+#define SET_SDIO_FIFO_RD_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffff00ff))
+#define SET_SDIO_READ_DATA_CTRL(_VAL_) (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0xfffeffff))
+#define SET_TX_SIZE_BEFORE_SHIFT(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffff00))
+#define SET_TX_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffff8ff))
+#define SET_SDIO_TX_ALLOC_STATE(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffefff))
+#define SET_ALLOCATE_STATUS2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffeffff))
+#define SET_NO_ALLOCATE_SEND_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffdffff))
+#define SET_DOUBLE_ALLOCATE_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffbffff))
+#define SET_TX_DONE_STATUS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfff7ffff))
+#define SET_AHB_HANG2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffefffff))
+#define SET_HCI_TRX_FINISH2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffdfffff))
+#define SET_INTR_RX(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffbfffff))
+#define SET_HCI_INPUT_QUEUE_FULL(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xff7fffff))
+#define SET_ALLOCATESTATUS(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffe))
+#define SET_HCI_TRX_FINISH3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffd))
+#define SET_HCI_IN_QUE_EMPTY2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffb))
+#define SET_MTX_MNG_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffff7))
+#define SET_EDCA0_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffef))
+#define SET_EDCA1_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffdf))
+#define SET_EDCA2_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffbf))
+#define SET_EDCA3_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffff7f))
+#define SET_TX_PAGE_REMAIN2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffff00ff))
+#define SET_TX_ID_REMAIN3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff80ffff))
+#define SET_HCI_OUTPUT_FF_CNT_0(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff7fffff))
+#define SET_HCI_OUTPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xf0ffffff))
+#define SET_HCI_INPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_TX_INFORM)) & 0x0fffffff))
+#define SET_F1_BLOCK_SIZE_0_REG(_VAL_) (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (((_VAL_) << 0) | ((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0xfffff000))
+#define SET_START_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffffff00))
+#define SET_COMMAND_COUNTER(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff00ff))
+#define SET_CMD_LOG_PART1(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ffff))
+#define SET_CMD_LOG_PART2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000))
+#define SET_END_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff))
+#define SET_RX_PACKET_LENGTH3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xffff0000))
+#define SET_RX_INT3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xfffeffff))
+#define SET_TX_ID_REMAIN2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff01ffff))
+#define SET_TX_PAGE_REMAIN3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00ffffff))
+#define SET_CCCR_00H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_00H_REG)) & 0xffffff00))
+#define SET_CCCR_02H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_00H_REG)) & 0xff00ffff))
+#define SET_CCCR_03H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_00H_REG)) & 0x00ffffff))
+#define SET_CCCR_04H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_04H_REG)) & 0xffffff00))
+#define SET_CCCR_05H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_04H_REG)) & 0xffff00ff))
+#define SET_CCCR_06H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_04H_REG)) & 0xfff0ffff))
+#define SET_CCCR_07H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_04H_REG)) & 0x00ffffff))
+#define SET_SUPPORT_DIRECT_COMMAND_SDIO(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffe))
+#define SET_SUPPORT_MULTIPLE_BLOCK_TRANSFER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 1) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffd))
+#define SET_SUPPORT_READ_WAIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 2) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffb))
+#define SET_SUPPORT_BUS_CONTROL(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 3) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffff7))
+#define SET_SUPPORT_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 4) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffef))
+#define SET_ENABLE_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 5) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffdf))
+#define SET_LOW_SPEED_CARD(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffbf))
+#define SET_LOW_SPEED_CARD_4BIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffff7f))
+#define SET_COMMON_CIS_PONTER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_08H_REG)) & 0xfe0000ff))
+#define SET_SUPPORT_HIGH_SPEED(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_13H_REG)) & 0xfeffffff))
+#define SET_BSS(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 25) | ((REG32(ADR_CCCR_13H_REG)) & 0xf1ffffff))
+#define SET_FBR_100H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FBR_100H_REG)) & 0xfffffff0))
+#define SET_CSASUPPORT(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_FBR_100H_REG)) & 0xffffffbf))
+#define SET_ENABLECSA(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FBR_100H_REG)) & 0xffffff7f))
+#define SET_FBR_101H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_100H_REG)) & 0xffff00ff))
+#define SET_FBR_109H_REG(_VAL_) (REG32(ADR_FBR_109H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_109H_REG)) & 0xfe0000ff))
+#define SET_F0_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0x00000000))
+#define SET_SPI_MODE(_VAL_) (REG32(ADR_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_MODE)) & 0x00000000))
+#define SET_RX_QUOTA(_VAL_) (REG32(ADR_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_QUOTA)) & 0xffff0000))
+#define SET_CONDI_NUM(_VAL_) (REG32(ADR_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_CONDITION_NUMBER)) & 0xffffff00))
+#define SET_HOST_PATH(_VAL_) (REG32(ADR_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_HOST_PATH)) & 0xfffffffe))
+#define SET_TX_SEG(_VAL_) (REG32(ADR_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEG)) & 0x00000000))
+#define SET_BRST_MODE(_VAL_) (REG32(ADR_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_BURST_MODE)) & 0xfffffffe))
+#define SET_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000))
+#define SET_CSN_INTER(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
+#define SET_BACK_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000))
+#define SET_FRONT_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
+#define SET_RX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SPI_STS)) & 0xfffffffd))
+#define SET_RX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SPI_STS)) & 0xfffffffb))
+#define SET_TX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SPI_STS)) & 0xfffffff7))
+#define SET_TX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SPI_STS)) & 0xffffffef))
+#define SET_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SPI_STS)) & 0xffffffdf))
+#define SET_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SPI_STS)) & 0xffffffbf))
+#define SET_RDATA_RDY(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SPI_STS)) & 0xffffff7f))
+#define SET_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SPI_STS)) & 0xfffffeff))
+#define SET_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SPI_STS)) & 0xfffffdff))
+#define SET_RX_LEN(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_STS)) & 0x0000ffff))
+#define SET_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffff8))
+#define SET_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffeff))
+#define SET_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC)) & 0xffffff00))
+#define SET_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT)) & 0xffff0000))
+#define SET_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT)) & 0x0000ffff))
+#define SET_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT2)) & 0xffff0000))
+#define SET_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT2)) & 0xfffeffff))
+#define SET_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT2)) & 0xfffdffff))
+#define SET_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT2)) & 0xfffbffff))
+#define SET_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT3)) & 0xffff0000))
+#define SET_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT3)) & 0x0000ffff))
+#define SET_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT4)) & 0xffff0000))
+#define SET_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT4)) & 0xfffeffff))
+#define SET_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT4)) & 0xfffdffff))
+#define SET_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT4)) & 0xfffbffff))
+#define SET_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_CNT4)) & 0xfff7ffff))
+#define SET_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_CNT4)) & 0xff8fffff))
+#define SET_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_CNT4)) & 0xf8ffffff))
+#define SET_RX_RDY(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_TAG)) & 0xfffffffe))
+#define SET_SDIO_SYS_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_TAG)) & 0xfffffffb))
+#define SET_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_TAG)) & 0xfffffff7))
+#define SET_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_TAG)) & 0xffffffef))
+#define SET_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_TAG)) & 0xffffffdf))
+#define SET_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_TAG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_TAG)) & 0xffffff7f))
+#define SET_SPI_FN1(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_TAG)) & 0xffff80ff))
+#define SET_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_INT_TAG)) & 0xffff7fff))
+#define SET_SPI_HOST_MASK(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_INT_TAG)) & 0xff00ffff))
+#define SET_I2CM_INT_WDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN)) & 0xfffffffe))
+#define SET_I2CM_INT_RDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 1) | ((REG32(ADR_I2CM_EN)) & 0xfffffffd))
+#define SET_I2CM_IDLE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 2) | ((REG32(ADR_I2CM_EN)) & 0xfffffffb))
+#define SET_I2CM_INT_MISMATCH(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 3) | ((REG32(ADR_I2CM_EN)) & 0xfffffff7))
+#define SET_I2CM_PSCL(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 4) | ((REG32(ADR_I2CM_EN)) & 0xffffc00f))
+#define SET_I2CM_MANUAL_MODE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN)) & 0xfffeffff))
+#define SET_I2CM_INT_WDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN)) & 0xfffdffff))
+#define SET_I2CM_INT_RDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 18) | ((REG32(ADR_I2CM_EN)) & 0xfffbffff))
+#define SET_I2CM_DEV_A(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_DEV_A)) & 0xfffffc00))
+#define SET_I2CM_DEV_A10B(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 14) | ((REG32(ADR_I2CM_DEV_A)) & 0xffffbfff))
+#define SET_I2CM_RX(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 15) | ((REG32(ADR_I2CM_DEV_A)) & 0xffff7fff))
+#define SET_I2CM_LEN(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_LEN)) & 0xffff0000))
+#define SET_I2CM_T_LEFT(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_LEN)) & 0xfff8ffff))
+#define SET_I2CM_R_GET(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 24) | ((REG32(ADR_I2CM_LEN)) & 0xf8ffffff))
+#define SET_I2CM_WDAT(_VAL_) (REG32(ADR_I2CM_WDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_WDAT)) & 0x00000000))
+#define SET_I2CM_RDAT(_VAL_) (REG32(ADR_I2CM_RDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_RDAT)) & 0x00000000))
+#define SET_I2CM_SR_LEN(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN_2)) & 0xffff0000))
+#define SET_I2CM_SR_RX(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN_2)) & 0xfffeffff))
+#define SET_I2CM_REPEAT_START(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN_2)) & 0xfffdffff))
+#define SET_UART_DATA(_VAL_) (REG32(ADR_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_UART_DATA)) & 0xffffff00))
+#define SET_DATA_RDY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_UART_IER)) & 0xfffffffe))
+#define SET_THR_EMPTY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_UART_IER)) & 0xfffffffd))
+#define SET_RX_LINESTS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_UART_IER)) & 0xfffffffb))
+#define SET_MDM_STS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_UART_IER)) & 0xfffffff7))
+#define SET_DMA_RXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_UART_IER)) & 0xffffffbf))
+#define SET_DMA_TXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_UART_IER)) & 0xffffff7f))
+#define SET_FIFO_EN(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_FCR)) & 0xfffffffe))
+#define SET_RXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_FCR)) & 0xfffffffd))
+#define SET_TXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_FCR)) & 0xfffffffb))
+#define SET_DMA_MODE(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_FCR)) & 0xfffffff7))
+#define SET_EN_AUTO_RTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_FCR)) & 0xffffffef))
+#define SET_EN_AUTO_CTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_FCR)) & 0xffffffdf))
+#define SET_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_FCR)) & 0xffffff3f))
+#define SET_WORD_LEN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LCR)) & 0xfffffffc))
+#define SET_STOP_BIT(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LCR)) & 0xfffffffb))
+#define SET_PARITY_EN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LCR)) & 0xfffffff7))
+#define SET_EVEN_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LCR)) & 0xffffffef))
+#define SET_FORCE_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LCR)) & 0xffffffdf))
+#define SET_SET_BREAK(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LCR)) & 0xffffffbf))
+#define SET_DLAB(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LCR)) & 0xffffff7f))
+#define SET_DTR(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MCR)) & 0xfffffffe))
+#define SET_RTS(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MCR)) & 0xfffffffd))
+#define SET_OUT_1(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MCR)) & 0xfffffffb))
+#define SET_OUT_2(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MCR)) & 0xfffffff7))
+#define SET_LOOP_BACK(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MCR)) & 0xffffffef))
+#define SET_DATA_RDY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LSR)) & 0xfffffffe))
+#define SET_OVERRUN_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_LSR)) & 0xfffffffd))
+#define SET_PARITY_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LSR)) & 0xfffffffb))
+#define SET_FRAMING_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LSR)) & 0xfffffff7))
+#define SET_BREAK_INT(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LSR)) & 0xffffffef))
+#define SET_THR_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LSR)) & 0xffffffdf))
+#define SET_TX_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LSR)) & 0xffffffbf))
+#define SET_FIFODATA_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LSR)) & 0xffffff7f))
+#define SET_DELTA_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MSR)) & 0xfffffffe))
+#define SET_DELTA_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MSR)) & 0xfffffffd))
+#define SET_TRAILEDGE_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MSR)) & 0xfffffffb))
+#define SET_DELTA_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MSR)) & 0xfffffff7))
+#define SET_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MSR)) & 0xffffffef))
+#define SET_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_MSR)) & 0xffffffdf))
+#define SET_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_MSR)) & 0xffffffbf))
+#define SET_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_MSR)) & 0xffffff7f))
+#define SET_BRDC_DIV(_VAL_) (REG32(ADR_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_SPR)) & 0xffff0000))
+#define SET_RTHR_L(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_RTHR)) & 0xfffffff0))
+#define SET_RTHR_H(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_RTHR)) & 0xffffff0f))
+#define SET_INT_IDCODE(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_ISR)) & 0xfffffff0))
+#define SET_FIFOS_ENABLED(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_ISR)) & 0xffffff3f))
+#define SET_DAT_UART_DATA(_VAL_) (REG32(ADR_DAT_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_DATA)) & 0xffffff00))
+#define SET_DAT_DATA_RDY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffe))
+#define SET_DAT_THR_EMPTY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffd))
+#define SET_DAT_RX_LINESTS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffb))
+#define SET_DAT_MDM_STS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffff7))
+#define SET_DAT_DMA_RXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_IER)) & 0xffffffbf))
+#define SET_DAT_DMA_TXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_IER)) & 0xffffff7f))
+#define SET_DAT_FIFO_EN(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffe))
+#define SET_DAT_RXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffd))
+#define SET_DAT_TXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffb))
+#define SET_DAT_DMA_MODE(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffff7))
+#define SET_DAT_EN_AUTO_RTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffef))
+#define SET_DAT_EN_AUTO_CTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffdf))
+#define SET_DAT_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffff3f))
+#define SET_DAT_WORD_LEN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffc))
+#define SET_DAT_STOP_BIT(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffb))
+#define SET_DAT_PARITY_EN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffff7))
+#define SET_DAT_EVEN_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffef))
+#define SET_DAT_FORCE_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffdf))
+#define SET_DAT_SET_BREAK(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffbf))
+#define SET_DAT_DLAB(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffff7f))
+#define SET_DAT_DTR(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffe))
+#define SET_DAT_RTS(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffd))
+#define SET_DAT_OUT_1(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffb))
+#define SET_DAT_OUT_2(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffff7))
+#define SET_DAT_LOOP_BACK(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MCR)) & 0xffffffef))
+#define SET_DAT_DATA_RDY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffe))
+#define SET_DAT_OVERRUN_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffd))
+#define SET_DAT_PARITY_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffb))
+#define SET_DAT_FRAMING_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffff7))
+#define SET_DAT_BREAK_INT(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffef))
+#define SET_DAT_THR_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffdf))
+#define SET_DAT_TX_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffbf))
+#define SET_DAT_FIFODATA_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffff7f))
+#define SET_DAT_DELTA_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffe))
+#define SET_DAT_DELTA_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffd))
+#define SET_DAT_TRAILEDGE_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffb))
+#define SET_DAT_DELTA_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffff7))
+#define SET_DAT_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffef))
+#define SET_DAT_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffdf))
+#define SET_DAT_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffbf))
+#define SET_DAT_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffff7f))
+#define SET_DAT_BRDC_DIV(_VAL_) (REG32(ADR_DAT_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_SPR)) & 0xffff0000))
+#define SET_DAT_RTHR_L(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_RTHR)) & 0xfffffff0))
+#define SET_DAT_RTHR_H(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_RTHR)) & 0xffffff0f))
+#define SET_DAT_INT_IDCODE(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_ISR)) & 0xfffffff0))
+#define SET_DAT_FIFOS_ENABLED(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_ISR)) & 0xffffff3f))
+#define SET_MASK_TOP(_VAL_) (REG32(ADR_INT_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK)) & 0x00000000))
+#define SET_INT_MODE(_VAL_) (REG32(ADR_INT_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MODE)) & 0x00000000))
+#define SET_IRQ_PHY_0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffe))
+#define SET_IRQ_PHY_1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffd))
+#define SET_IRQ_SDIO(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffb))
+#define SET_IRQ_BEACON_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffff7))
+#define SET_IRQ_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffef))
+#define SET_IRQ_PRE_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffdf))
+#define SET_IRQ_EDCA0_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffbf))
+#define SET_IRQ_EDCA1_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffff7f))
+#define SET_IRQ_EDCA2_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffeff))
+#define SET_IRQ_EDCA3_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffdff))
+#define SET_IRQ_EDCA4_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffbff))
+#define SET_IRQ_BEACON_DTIM(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffefff))
+#define SET_IRQ_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffdfff))
+#define SET_IRQ_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffbfff))
+#define SET_IRQ_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_IRQ_STS)) & 0xffff7fff))
+#define SET_IRQ_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffeffff))
+#define SET_IRQ_FENCE_HIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffdffff))
+#define SET_IRQ_ILL_ADDR_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffbffff))
+#define SET_IRQ_MBOX(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_IRQ_STS)) & 0xfff7ffff))
+#define SET_IRQ_US_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_IRQ_STS)) & 0xffefffff))
+#define SET_IRQ_US_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_IRQ_STS)) & 0xffdfffff))
+#define SET_IRQ_US_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_IRQ_STS)) & 0xffbfffff))
+#define SET_IRQ_US_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_IRQ_STS)) & 0xff7fffff))
+#define SET_IRQ_MS_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_IRQ_STS)) & 0xfeffffff))
+#define SET_IRQ_MS_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_IRQ_STS)) & 0xfdffffff))
+#define SET_IRQ_MS_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_IRQ_STS)) & 0xfbffffff))
+#define SET_IRQ_MS_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_IRQ_STS)) & 0xf7ffffff))
+#define SET_IRQ_TX_LIMIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_IRQ_STS)) & 0xefffffff))
+#define SET_IRQ_DMA0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_IRQ_STS)) & 0xdfffffff))
+#define SET_IRQ_CO_DMA(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_IRQ_STS)) & 0xbfffffff))
+#define SET_IRQ_PERI_GROUP(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_IRQ_STS)) & 0x7fffffff))
+#define SET_FIQ_STATUS(_VAL_) (REG32(ADR_INT_FIQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_STS)) & 0x00000000))
+#define SET_IRQ_RAW(_VAL_) (REG32(ADR_INT_IRQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_RAW)) & 0x00000000))
+#define SET_FIQ_RAW(_VAL_) (REG32(ADR_INT_FIQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_RAW)) & 0x00000000))
+#define SET_INT_PERI_MASK(_VAL_) (REG32(ADR_INT_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_MASK)) & 0x00000000))
+#define SET_PERI_RTC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffe))
+#define SET_IRQ_UART0_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffd))
+#define SET_IRQ_UART0_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffb))
+#define SET_PERI_GPI_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffff7))
+#define SET_IRQ_SPI_IPC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_PERI_STS)) & 0xffffffef))
+#define SET_PERI_GPI_1_0(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff9f))
+#define SET_SCRT_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff7f))
+#define SET_MMU_ALC_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffeff))
+#define SET_MMU_RLS_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffdff))
+#define SET_ID_MNG_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffbff))
+#define SET_MBOX_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_INT_PERI_STS)) & 0xfffff7ff))
+#define SET_MBOX_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_PERI_STS)) & 0xffffefff))
+#define SET_MBOX_INT_3(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_PERI_STS)) & 0xffffdfff))
+#define SET_HCI_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_PERI_STS)) & 0xffffbfff))
+#define SET_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_PERI_STS)) & 0xffff7fff))
+#define SET_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_PERI_STS)) & 0xfffeffff))
+#define SET_ID_MNG_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_PERI_STS)) & 0xfffdffff))
+#define SET_DMN_NOHIT_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_PERI_STS)) & 0xfffbffff))
+#define SET_ID_THOLD_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_PERI_STS)) & 0xfff7ffff))
+#define SET_ID_THOLD_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_PERI_STS)) & 0xffefffff))
+#define SET_ID_DOUBLE_RLS(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_PERI_STS)) & 0xffdfffff))
+#define SET_RX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_PERI_STS)) & 0xffbfffff))
+#define SET_TX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_PERI_STS)) & 0xff7fffff))
+#define SET_ALL_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_PERI_STS)) & 0xfeffffff))
+#define SET_DMN_MCU_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_PERI_STS)) & 0xfdffffff))
+#define SET_IRQ_DAT_UART_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_PERI_STS)) & 0xfbffffff))
+#define SET_IRQ_DAT_UART_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_PERI_STS)) & 0xf7ffffff))
+#define SET_DAT_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_PERI_STS)) & 0xefffffff))
+#define SET_DAT_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_PERI_STS)) & 0xdfffffff))
+#define SET_ALR_ABT_NOCHG_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_PERI_STS)) & 0xbfffffff))
+#define SET_TBLNEQ_MNGPKT_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_PERI_STS)) & 0x7fffffff))
+#define SET_INTR_PERI_RAW(_VAL_) (REG32(ADR_INT_PERI_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_RAW)) & 0x00000000))
+#define SET_INTR_GPI00_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffffc))
+#define SET_INTR_GPI01_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffff3))
+#define SET_SYS_RST_INT(_VAL_) (REG32(ADR_SYS_INT_FOR_HOST)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_INT_FOR_HOST)) & 0xfffffffe))
+#define SET_SPI_IPC_ADDR(_VAL_) (REG32(ADR_SPI_IPC)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_IPC)) & 0x00000000))
+#define SET_SD_MASK_TOP(_VAL_) (REG32(ADR_SDIO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_MASK)) & 0x00000000))
+#define SET_IRQ_PHY_0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffe))
+#define SET_IRQ_PHY_1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffd))
+#define SET_IRQ_SDIO_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffb))
+#define SET_IRQ_BEACON_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffff7))
+#define SET_IRQ_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffef))
+#define SET_IRQ_PRE_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffdf))
+#define SET_IRQ_EDCA0_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffbf))
+#define SET_IRQ_EDCA1_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffff7f))
+#define SET_IRQ_EDCA2_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffeff))
+#define SET_IRQ_EDCA3_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffdff))
+#define SET_IRQ_EDCA4_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffbff))
+#define SET_IRQ_BEACON_DTIM_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffefff))
+#define SET_IRQ_EDCA0_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffdfff))
+#define SET_IRQ_EDCA1_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffbfff))
+#define SET_IRQ_EDCA2_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffff7fff))
+#define SET_IRQ_EDCA3_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffeffff))
+#define SET_IRQ_FENCE_HIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffdffff))
+#define SET_IRQ_ILL_ADDR_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffbffff))
+#define SET_IRQ_MBOX_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfff7ffff))
+#define SET_IRQ_US_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffefffff))
+#define SET_IRQ_US_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffdfffff))
+#define SET_IRQ_US_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffbfffff))
+#define SET_IRQ_US_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xff7fffff))
+#define SET_IRQ_MS_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfeffffff))
+#define SET_IRQ_MS_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfdffffff))
+#define SET_IRQ_MS_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfbffffff))
+#define SET_IRQ_MS_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xf7ffffff))
+#define SET_IRQ_TX_LIMIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xefffffff))
+#define SET_IRQ_DMA0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xdfffffff))
+#define SET_IRQ_CO_DMA_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xbfffffff))
+#define SET_IRQ_PERI_GROUP_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SDIO_IRQ_STS)) & 0x7fffffff))
+#define SET_INT_PERI_MASK_SD(_VAL_) (REG32(ADR_SD_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_MASK)) & 0x00000000))
+#define SET_PERI_RTC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffe))
+#define SET_IRQ_UART0_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffd))
+#define SET_IRQ_UART0_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffb))
+#define SET_PERI_GPI_SD_2(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffff7))
+#define SET_IRQ_SPI_IPC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SD_PERI_STS)) & 0xffffffef))
+#define SET_PERI_GPI_SD_1_0(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff9f))
+#define SET_SCRT_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff7f))
+#define SET_MMU_ALC_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffeff))
+#define SET_MMU_RLS_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffdff))
+#define SET_ID_MNG_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffbff))
+#define SET_MBOX_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_SD_PERI_STS)) & 0xfffff7ff))
+#define SET_MBOX_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SD_PERI_STS)) & 0xffffefff))
+#define SET_MBOX_INT_3_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SD_PERI_STS)) & 0xffffdfff))
+#define SET_HCI_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SD_PERI_STS)) & 0xffffbfff))
+#define SET_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SD_PERI_STS)) & 0xffff7fff))
+#define SET_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SD_PERI_STS)) & 0xfffeffff))
+#define SET_ID_MNG_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SD_PERI_STS)) & 0xfffdffff))
+#define SET_DMN_NOHIT_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SD_PERI_STS)) & 0xfffbffff))
+#define SET_ID_THOLD_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SD_PERI_STS)) & 0xfff7ffff))
+#define SET_ID_THOLD_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SD_PERI_STS)) & 0xffefffff))
+#define SET_ID_DOUBLE_RLS_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SD_PERI_STS)) & 0xffdfffff))
+#define SET_RX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SD_PERI_STS)) & 0xffbfffff))
+#define SET_TX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SD_PERI_STS)) & 0xff7fffff))
+#define SET_ALL_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SD_PERI_STS)) & 0xfeffffff))
+#define SET_DMN_MCU_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SD_PERI_STS)) & 0xfdffffff))
+#define SET_IRQ_DAT_UART_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SD_PERI_STS)) & 0xfbffffff))
+#define SET_IRQ_DAT_UART_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SD_PERI_STS)) & 0xf7ffffff))
+#define SET_DAT_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SD_PERI_STS)) & 0xefffffff))
+#define SET_DAT_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SD_PERI_STS)) & 0xdfffffff))
+#define SET_ALR_ABT_NOCHG_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SD_PERI_STS)) & 0xbfffffff))
+#define SET_TBLNEQ_MNGPKT_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SD_PERI_STS)) & 0x7fffffff))
+#define SET_DBG_SPI_MODE(_VAL_) (REG32(ADR_DBG_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_MODE)) & 0x00000000))
+#define SET_DBG_RX_QUOTA(_VAL_) (REG32(ADR_DBG_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_RX_QUOTA)) & 0xffff0000))
+#define SET_DBG_CONDI_NUM(_VAL_) (REG32(ADR_DBG_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CONDITION_NUMBER)) & 0xffffff00))
+#define SET_DBG_HOST_PATH(_VAL_) (REG32(ADR_DBG_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_HOST_PATH)) & 0xfffffffe))
+#define SET_DBG_TX_SEG(_VAL_) (REG32(ADR_DBG_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_SEG)) & 0x00000000))
+#define SET_DBG_BRST_MODE(_VAL_) (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0xfffffffe))
+#define SET_DBG_CLK_WIDTH(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000))
+#define SET_DBG_CSN_INTER(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
+#define SET_DBG_BACK_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000))
+#define SET_DBG_FRONT_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
+#define SET_DBG_RX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffd))
+#define SET_DBG_RX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffb))
+#define SET_DBG_TX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffff7))
+#define SET_DBG_TX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffef))
+#define SET_DBG_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffdf))
+#define SET_DBG_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffbf))
+#define SET_DBG_RDATA_RDY(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffff7f))
+#define SET_DBG_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffeff))
+#define SET_DBG_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffdff))
+#define SET_DBG_RX_LEN(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_STS)) & 0x0000ffff))
+#define SET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffff8))
+#define SET_DBG_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffeff))
+#define SET_DBG_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_DBG_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC)) & 0xffffff00))
+#define SET_DBG_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000))
+#define SET_DBG_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff))
+#define SET_DBG_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xffff0000))
+#define SET_DBG_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffeffff))
+#define SET_DBG_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffdffff))
+#define SET_DBG_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffbffff))
+#define SET_DBG_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000))
+#define SET_DBG_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff))
+#define SET_DBG_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xffff0000))
+#define SET_DBG_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffeffff))
+#define SET_DBG_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffdffff))
+#define SET_DBG_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffbffff))
+#define SET_DBG_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfff7ffff))
+#define SET_DBG_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xff8fffff))
+#define SET_DBG_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xf8ffffff))
+#define SET_DBG_RX_RDY(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffe))
+#define SET_DBG_SDIO_SYS_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffb))
+#define SET_DBG_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffff7))
+#define SET_DBG_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffef))
+#define SET_DBG_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffdf))
+#define SET_DBG_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffbf))
+#define SET_DBG_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffff7f))
+#define SET_DBG_SPI_FN1(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff80ff))
+#define SET_DBG_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff7fff))
+#define SET_DBG_SPI_HOST_MASK(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_INT_TAG)) & 0xff00ffff))
+#define SET_BOOT_ADDR(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_ADDR)) & 0xff000000))
+#define SET_CHECK_SUM_FAIL(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_BOOT_ADDR)) & 0x7fffffff))
+#define SET_VERIFY_DATA(_VAL_) (REG32(ADR_VERIFY_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_VERIFY_DATA)) & 0x00000000))
+#define SET_FLASH_ADDR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_FLASH_ADDR)) & 0xff000000))
+#define SET_FLASH_CMD_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 28) | ((REG32(ADR_FLASH_ADDR)) & 0xefffffff))
+#define SET_FLASH_DMA_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 29) | ((REG32(ADR_FLASH_ADDR)) & 0xdfffffff))
+#define SET_DMA_EN(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 30) | ((REG32(ADR_FLASH_ADDR)) & 0xbfffffff))
+#define SET_DMA_BUSY(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_FLASH_ADDR)) & 0x7fffffff))
+#define SET_SRAM_ADDR(_VAL_) (REG32(ADR_SRAM_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SRAM_ADDR)) & 0x00000000))
+#define SET_FLASH_DMA_LEN(_VAL_) (REG32(ADR_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_LEN)) & 0x00000000))
+#define SET_FLASH_FRONT_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM)) & 0xffff0000))
+#define SET_FLASH_BACK_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM)) & 0x0000ffff))
+#define SET_FLASH_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM2)) & 0xffff0000))
+#define SET_SPI_BUSY(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM2)) & 0xfffeffff))
+#define SET_FLS_REMAP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 17) | ((REG32(ADR_SPI_PARAM2)) & 0xfffdffff))
+#define SET_PBUS_SWP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 18) | ((REG32(ADR_SPI_PARAM2)) & 0xfffbffff))
+#define SET_BIT_MODE1(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 19) | ((REG32(ADR_SPI_PARAM2)) & 0xfff7ffff))
+#define SET_BIT_MODE2(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 20) | ((REG32(ADR_SPI_PARAM2)) & 0xffefffff))
+#define SET_BIT_MODE4(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 21) | ((REG32(ADR_SPI_PARAM2)) & 0xffdfffff))
+#define SET_BOOT_CHECK_SUM(_VAL_) (REG32(ADR_CHECK_SUM_RESULT)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_RESULT)) & 0x00000000))
+#define SET_CHECK_SUM_TAG(_VAL_) (REG32(ADR_CHECK_SUM_IN_FILE)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_IN_FILE)) & 0x00000000))
+#define SET_CMD_LEN(_VAL_) (REG32(ADR_COMMAND_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_LEN)) & 0xffff0000))
+#define SET_CMD_ADDR(_VAL_) (REG32(ADR_COMMAND_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_ADDR)) & 0x00000000))
+#define SET_DMA_ADR_SRC(_VAL_) (REG32(ADR_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_SRC)) & 0x00000000))
+#define SET_DMA_ADR_DST(_VAL_) (REG32(ADR_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_DST)) & 0x00000000))
+#define SET_DMA_SRC_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff8))
+#define SET_DMA_SRC_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff7))
+#define SET_DMA_DST_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_DMA_CTRL)) & 0xffffff8f))
+#define SET_DMA_DST_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_DMA_CTRL)) & 0xffffff7f))
+#define SET_DMA_FAST_FILL(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_CTRL)) & 0xfffffeff))
+#define SET_DMA_SDIO_KICK(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_DMA_CTRL)) & 0xffffefff))
+#define SET_DMA_BADR_EN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_DMA_CTRL)) & 0xffffdfff))
+#define SET_DMA_LEN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_CTRL)) & 0x0000ffff))
+#define SET_DMA_INT_MASK(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_INT)) & 0xfffffffe))
+#define SET_DMA_STS(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_INT)) & 0xfffffeff))
+#define SET_DMA_FINISH(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_DMA_INT)) & 0x7fffffff))
+#define SET_DMA_CONST(_VAL_) (REG32(ADR_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_FILL_CONST)) & 0x00000000))
+#define SET_SLEEP_WAKE_CNT(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_0)) & 0xff000000))
+#define SET_RG_DLDO_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 24) | ((REG32(ADR_PMU_0)) & 0xf8ffffff))
+#define SET_RG_DLDO_BOOST_IQ(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 27) | ((REG32(ADR_PMU_0)) & 0xf7ffffff))
+#define SET_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 28) | ((REG32(ADR_PMU_0)) & 0x8fffffff))
+#define SET_RG_BUCK_VREF_SEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_0)) & 0x7fffffff))
+#define SET_RG_RTC_OSC_RES_SW_MANUAL(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_1)) & 0xfffffc00))
+#define SET_RG_RTC_OSC_RES_SW(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_1)) & 0xfc00ffff))
+#define SET_RTC_OSC_CAL_RES_RDY(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_1)) & 0x7fffffff))
+#define SET_RG_DCDC_MODE(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_2)) & 0xfffffffe))
+#define SET_RG_BUCK_EN_PSM(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_2)) & 0xffffffef))
+#define SET_RG_BUCK_PSM_VTH(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_2)) & 0xfffffeff))
+#define SET_RG_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 12) | ((REG32(ADR_PMU_2)) & 0xffffefff))
+#define SET_RG_RTC_RDY_DEGLITCH_TIMER(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 13) | ((REG32(ADR_PMU_2)) & 0xffff9fff))
+#define SET_RTC_CAL_ENA(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_2)) & 0xfffeffff))
+#define SET_PMU_WAKE_TRIG_EVENT(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_3)) & 0xfffffffc))
+#define SET_DIGI_TOP_POR_MASK(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_3)) & 0xffffffef))
+#define SET_PMU_ENTER_SLEEP_MODE(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_3)) & 0xfffffeff))
+#define SET_RG_RTC_DUMMIES(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_3)) & 0x0000ffff))
+#define SET_RTC_EN(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_1)) & 0xfffffffe))
+#define SET_RTC_SRC(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_1)) & 0xfffffffd))
+#define SET_RTC_TICK_CNT(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_1)) & 0x8000ffff))
+#define SET_RTC_INT_SEC_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_2)) & 0xfffffffe))
+#define SET_RTC_INT_ALARM_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_2)) & 0xfffffffd))
+#define SET_RTC_INT_SEC(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_2)) & 0xfffeffff))
+#define SET_RTC_INT_ALARM(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 17) | ((REG32(ADR_RTC_2)) & 0xfffdffff))
+#define SET_RTC_SEC_START_CNT(_VAL_) (REG32(ADR_RTC_3W)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3W)) & 0x00000000))
+#define SET_RTC_SEC_CNT(_VAL_) (REG32(ADR_RTC_3R)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3R)) & 0x00000000))
+#define SET_RTC_SEC_ALARM_VALUE(_VAL_) (REG32(ADR_RTC_4)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_4)) & 0x00000000))
+#define SET_D2_DMA_ADR_SRC(_VAL_) (REG32(ADR_D2_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_SRC)) & 0x00000000))
+#define SET_D2_DMA_ADR_DST(_VAL_) (REG32(ADR_D2_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_DST)) & 0x00000000))
+#define SET_D2_DMA_SRC_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff8))
+#define SET_D2_DMA_SRC_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff7))
+#define SET_D2_DMA_DST_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff8f))
+#define SET_D2_DMA_DST_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff7f))
+#define SET_D2_DMA_FAST_FILL(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffeff))
+#define SET_D2_DMA_SDIO_KICK(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffefff))
+#define SET_D2_DMA_BADR_EN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffdfff))
+#define SET_D2_DMA_LEN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_D2_DMA_CTRL)) & 0x0000ffff))
+#define SET_D2_DMA_INT_MASK(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffffe))
+#define SET_D2_DMA_STS(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffeff))
+#define SET_D2_DMA_FINISH(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_D2_DMA_INT)) & 0x7fffffff))
+#define SET_D2_DMA_CONST(_VAL_) (REG32(ADR_D2_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_FILL_CONST)) & 0x00000000))
+#define SET_TRAP_UNKNOWN_TYPE(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_CONTROL)) & 0xfffffffe))
+#define SET_TX_ON_DEMAND_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_CONTROL)) & 0xfffffffd))
+#define SET_RX_2_HOST(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_CONTROL)) & 0xfffffffb))
+#define SET_AUTO_SEQNO(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 3) | ((REG32(ADR_CONTROL)) & 0xfffffff7))
+#define SET_BYPASSS_TX_PARSER_ENCAP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 4) | ((REG32(ADR_CONTROL)) & 0xffffffef))
+#define SET_HDR_STRIP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 5) | ((REG32(ADR_CONTROL)) & 0xffffffdf))
+#define SET_ERP_PROTECT(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 6) | ((REG32(ADR_CONTROL)) & 0xffffff3f))
+#define SET_PRO_VER(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_CONTROL)) & 0xfffffcff))
+#define SET_TXQ_ID0(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 12) | ((REG32(ADR_CONTROL)) & 0xffff8fff))
+#define SET_TXQ_ID1(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_CONTROL)) & 0xfff8ffff))
+#define SET_TX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 20) | ((REG32(ADR_CONTROL)) & 0xffefffff))
+#define SET_RX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 21) | ((REG32(ADR_CONTROL)) & 0xffdfffff))
+#define SET_RX_NULL_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 22) | ((REG32(ADR_CONTROL)) & 0xffbfffff))
+#define SET_RX_GET_TX_QUEUE_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 25) | ((REG32(ADR_CONTROL)) & 0xfdffffff))
+#define SET_HCI_INQ_SEL(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 26) | ((REG32(ADR_CONTROL)) & 0xfbffffff))
+#define SET_TRX_DEBUG_CNT_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 28) | ((REG32(ADR_CONTROL)) & 0xefffffff))
+#define SET_WAKE_SOON_WITH_SCK(_VAL_) (REG32(ADR_SDIO_WAKE_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_WAKE_MODE)) & 0xfffffffe))
+#define SET_TX_FLOW_CTRL(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_0)) & 0xffff0000))
+#define SET_TX_FLOW_MGMT(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FLOW_0)) & 0x0000ffff))
+#define SET_TX_FLOW_DATA(_VAL_) (REG32(ADR_TX_FLOW_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_1)) & 0x00000000))
+#define SET_DOT11RTSTHRESHOLD(_VAL_) (REG32(ADR_THREASHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_THREASHOLD)) & 0x0000ffff))
+#define SET_TXF_ID(_VAL_) (REG32(ADR_TXFID_INCREASE)) = (((_VAL_) << 0) | ((REG32(ADR_TXFID_INCREASE)) & 0xffffffc0))
+#define SET_SEQ_CTRL(_VAL_) (REG32(ADR_GLOBAL_SEQUENCE)) = (((_VAL_) << 0) | ((REG32(ADR_GLOBAL_SEQUENCE)) & 0xffff0000))
+#define SET_TX_PBOFFSET(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffffff00))
+#define SET_TX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffff00ff))
+#define SET_RX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff00ffff))
+#define SET_RX_LAST_PHY_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ffffff))
+#define SET_TX_INFO_CLEAR_SIZE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xffffffc0))
+#define SET_TX_INFO_CLEAR_ENABLE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xfffffeff))
+#define SET_TXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000))
+#define SET_TXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff))
+#define SET_RXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000))
+#define SET_RXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff))
+#define SET_TX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_0)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0x00000000))
+#define SET_RX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_1)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0x00000000))
+#define SET_HOST_CMD_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_2)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0xffffff00))
+#define SET_HOST_EVENT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_3)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0xffffff00))
+#define SET_TX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_4)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0xffffff00))
+#define SET_RX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_5)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0xffffff00))
+#define SET_TX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_6)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0xffffff00))
+#define SET_RX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_7)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0xffffff00))
+#define SET_HOST_TX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0xffffff00))
+#define SET_HOST_RX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0xffffff00))
+#define SET_HCI_STATE_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0x00000000))
+#define SET_HCI_ST_TIMEOUT_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0x00000000))
+#define SET_TX_ON_DEMAND_LENGTH(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0x00000000))
+#define SET_HCI_MONITOR_REG1(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0x00000000))
+#define SET_HCI_MONITOR_REG2(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_TIME_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_TIME_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xffff0000))
+#define SET_HCI_MB_MAX_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xff00ffff))
+#define SET_HCI_TX_ALLOC_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xffff0000))
+#define SET_HCI_PROC_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff00ffff))
+#define SET_SDIO_TRANS_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ffffff))
+#define SET_SDIO_TX_INVALID_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0x00000000))
+#define SET_SDIO_TX_INVALID_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0xffff0000))
+#define SET_CS_START_ADDR(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_CS_START_ADDR)) & 0xffff0000))
+#define SET_CS_PKT_ID(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 16) | ((REG32(ADR_CS_START_ADDR)) & 0xff80ffff))
+#define SET_ADD_LEN(_VAL_) (REG32(ADR_CS_ADD_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_CS_ADD_LEN)) & 0xffff0000))
+#define SET_CS_ADDER_EN(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CMD)) & 0xfffffffe))
+#define SET_PSEUDO(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 1) | ((REG32(ADR_CS_CMD)) & 0xfffffffd))
+#define SET_CALCULATE(_VAL_) (REG32(ADR_CS_INI_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_INI_BUF)) & 0x00000000))
+#define SET_L4_LEN(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xffff0000))
+#define SET_L4_PROTOL(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 16) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xff00ffff))
+#define SET_CHECK_SUM(_VAL_) (REG32(ADR_CS_CHECK_SUM)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CHECK_SUM)) & 0xffff0000))
+#define SET_RAND_EN(_VAL_) (REG32(ADR_RAND_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_EN)) & 0xfffffffe))
+#define SET_RAND_NUM(_VAL_) (REG32(ADR_RAND_NUM)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_NUM)) & 0x00000000))
+#define SET_MUL_OP1(_VAL_) (REG32(ADR_MUL_OP1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP1)) & 0x00000000))
+#define SET_MUL_OP2(_VAL_) (REG32(ADR_MUL_OP2)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP2)) & 0x00000000))
+#define SET_MUL_ANS0(_VAL_) (REG32(ADR_MUL_ANS0)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS0)) & 0x00000000))
+#define SET_MUL_ANS1(_VAL_) (REG32(ADR_MUL_ANS1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS1)) & 0x00000000))
+#define SET_RD_ADDR(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_RDATA)) & 0xffff0000))
+#define SET_RD_ID(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_RDATA)) & 0xff80ffff))
+#define SET_WR_ADDR(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_WDATA)) & 0xffff0000))
+#define SET_WR_ID(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_WDATA)) & 0xff80ffff))
+#define SET_LEN(_VAL_) (REG32(ADR_DMA_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_LEN)) & 0xffff0000))
+#define SET_CLR(_VAL_) (REG32(ADR_DMA_CLR)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CLR)) & 0xfffffffe))
+#define SET_PHY_MODE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_NAV_DATA)) & 0xfffffffc))
+#define SET_SHRT_PREAM(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 2) | ((REG32(ADR_NAV_DATA)) & 0xfffffffb))
+#define SET_SHRT_GI(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 3) | ((REG32(ADR_NAV_DATA)) & 0xfffffff7))
+#define SET_DATA_RATE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 4) | ((REG32(ADR_NAV_DATA)) & 0xfffff80f))
+#define SET_MCS(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 12) | ((REG32(ADR_NAV_DATA)) & 0xffff8fff))
+#define SET_FRAME_LEN(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 16) | ((REG32(ADR_NAV_DATA)) & 0x0000ffff))
+#define SET_DURATION(_VAL_) (REG32(ADR_CO_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_CO_NAV)) & 0xffff0000))
+#define SET_SHA_DST_ADDR(_VAL_) (REG32(ADR_SHA_DST_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_DST_ADDR)) & 0x00000000))
+#define SET_SHA_SRC_ADDR(_VAL_) (REG32(ADR_SHA_SRC_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SRC_ADDR)) & 0x00000000))
+#define SET_SHA_BUSY(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffe))
+#define SET_SHA_ENDIAN(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 1) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffd))
+#define SET_EFS_CLKFREQ(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffff000))
+#define SET_LOW_ACTIVE(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffeffff))
+#define SET_EFS_CLKFREQ_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 20) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf00fffff))
+#define SET_EFS_PRE_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 28) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0fffffff))
+#define SET_EFS_LDO_ON(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000))
+#define SET_EFS_LDO_OFF(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff))
+#define SET_EFS_RDATA_0(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0x00000000))
+#define SET_EFS_WDATA_0(_VAL_) (REG32(ADR_EFUSE_WDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_0)) & 0x00000000))
+#define SET_EFS_RDATA_1(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0x00000000))
+#define SET_EFS_WDATA_1(_VAL_) (REG32(ADR_EFUSE_WDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_1)) & 0x00000000))
+#define SET_EFS_RDATA_2(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0x00000000))
+#define SET_EFS_WDATA_2(_VAL_) (REG32(ADR_EFUSE_WDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_2)) & 0x00000000))
+#define SET_EFS_RDATA_3(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0x00000000))
+#define SET_EFS_WDATA_3(_VAL_) (REG32(ADR_EFUSE_WDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_3)) & 0x00000000))
+#define SET_EFS_RDATA_4(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0x00000000))
+#define SET_EFS_WDATA_4(_VAL_) (REG32(ADR_EFUSE_WDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_4)) & 0x00000000))
+#define SET_EFS_RDATA_5(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0x00000000))
+#define SET_EFS_WDATA_5(_VAL_) (REG32(ADR_EFUSE_WDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_5)) & 0x00000000))
+#define SET_EFS_RDATA_6(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0x00000000))
+#define SET_EFS_WDATA_6(_VAL_) (REG32(ADR_EFUSE_WDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_6)) & 0x00000000))
+#define SET_EFS_RDATA_7(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0x00000000))
+#define SET_EFS_WDATA_7(_VAL_) (REG32(ADR_EFUSE_WDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_7)) & 0x00000000))
+#define SET_EFS_SPI_RD0_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD0_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD1_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD1_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD2_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD2_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD3_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD3_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD4_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD4_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD5_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD5_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD6_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD6_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD7_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD7_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RBUSY(_VAL_) (REG32(ADR_EFUSE_SPI_BUSY)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_BUSY)) & 0xfffffffe))
+#define SET_EFS_SPI_RDATA_0(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_1(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_2(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_3(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_4(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_5(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_6(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_7(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0x00000000))
+#define SET_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffe))
+#define SET_FORCE_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffd))
+#define SET_SMS4_DESCRY_EN(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG1)) & 0xffffffef))
+#define SET_DEC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffe))
+#define SET_DEC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffd))
+#define SET_ENC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffb))
+#define SET_ENC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 3) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffff7))
+#define SET_KEY_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG2)) & 0xffffffef))
+#define SET_SMS4_CBC_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffe))
+#define SET_SMS4_CFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffd))
+#define SET_SMS4_OFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffb))
+#define SET_SMS4_START_TRIG(_VAL_) (REG32(ADR_SMS4_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_TRIG)) & 0xfffffffe))
+#define SET_SMS4_BUSY(_VAL_) (REG32(ADR_SMS4_STATUS1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS1)) & 0xfffffffe))
+#define SET_SMS4_DONE(_VAL_) (REG32(ADR_SMS4_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS2)) & 0xfffffffe))
+#define SET_SMS4_DATAIN_0(_VAL_) (REG32(ADR_SMS4_DATA_IN0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN0)) & 0x00000000))
+#define SET_SMS4_DATAIN_1(_VAL_) (REG32(ADR_SMS4_DATA_IN1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN1)) & 0x00000000))
+#define SET_SMS4_DATAIN_2(_VAL_) (REG32(ADR_SMS4_DATA_IN2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN2)) & 0x00000000))
+#define SET_SMS4_DATAIN_3(_VAL_) (REG32(ADR_SMS4_DATA_IN3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN3)) & 0x00000000))
+#define SET_SMS4_DATAOUT_0(_VAL_) (REG32(ADR_SMS4_DATA_OUT0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT0)) & 0x00000000))
+#define SET_SMS4_DATAOUT_1(_VAL_) (REG32(ADR_SMS4_DATA_OUT1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT1)) & 0x00000000))
+#define SET_SMS4_DATAOUT_2(_VAL_) (REG32(ADR_SMS4_DATA_OUT2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT2)) & 0x00000000))
+#define SET_SMS4_DATAOUT_3(_VAL_) (REG32(ADR_SMS4_DATA_OUT3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT3)) & 0x00000000))
+#define SET_SMS4_KEY_0(_VAL_) (REG32(ADR_SMS4_KEY_0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_0)) & 0x00000000))
+#define SET_SMS4_KEY_1(_VAL_) (REG32(ADR_SMS4_KEY_1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_1)) & 0x00000000))
+#define SET_SMS4_KEY_2(_VAL_) (REG32(ADR_SMS4_KEY_2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_2)) & 0x00000000))
+#define SET_SMS4_KEY_3(_VAL_) (REG32(ADR_SMS4_KEY_3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_3)) & 0x00000000))
+#define SET_SMS4_MODE_IV0(_VAL_) (REG32(ADR_SMS4_MODE_IV0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV0)) & 0x00000000))
+#define SET_SMS4_MODE_IV1(_VAL_) (REG32(ADR_SMS4_MODE_IV1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV1)) & 0x00000000))
+#define SET_SMS4_MODE_IV2(_VAL_) (REG32(ADR_SMS4_MODE_IV2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV2)) & 0x00000000))
+#define SET_SMS4_MODE_IV3(_VAL_) (REG32(ADR_SMS4_MODE_IV3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV3)) & 0x00000000))
+#define SET_SMS4_OFB_ENC0(_VAL_) (REG32(ADR_SMS4_OFB_ENC0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC0)) & 0x00000000))
+#define SET_SMS4_OFB_ENC1(_VAL_) (REG32(ADR_SMS4_OFB_ENC1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC1)) & 0x00000000))
+#define SET_SMS4_OFB_ENC2(_VAL_) (REG32(ADR_SMS4_OFB_ENC2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC2)) & 0x00000000))
+#define SET_SMS4_OFB_ENC3(_VAL_) (REG32(ADR_SMS4_OFB_ENC3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC3)) & 0x00000000))
+#define SET_MRX_MCAST_TB0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_0(_VAL_) (REG32(ADR_MRX_MCAST_CTRL0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL0)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_1(_VAL_) (REG32(ADR_MRX_MCAST_CTRL1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL1)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_2(_VAL_) (REG32(ADR_MRX_MCAST_CTRL2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL2)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_3(_VAL_) (REG32(ADR_MRX_MCAST_CTRL3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL3)) & 0xfffffffc))
+#define SET_MRX_PHY_INFO(_VAL_) (REG32(ADR_MRX_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_PHY_INFO)) & 0x00000000))
+#define SET_DBG_BA_TYPE(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_DBG)) & 0xffffffc0))
+#define SET_DBG_BA_SEQ(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 8) | ((REG32(ADR_MRX_BA_DBG)) & 0xfff000ff))
+#define SET_MRX_FLT_TB0(_VAL_) (REG32(ADR_MRX_FLT_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB0)) & 0xffff8000))
+#define SET_MRX_FLT_TB1(_VAL_) (REG32(ADR_MRX_FLT_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB1)) & 0xffff8000))
+#define SET_MRX_FLT_TB2(_VAL_) (REG32(ADR_MRX_FLT_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB2)) & 0xffff8000))
+#define SET_MRX_FLT_TB3(_VAL_) (REG32(ADR_MRX_FLT_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB3)) & 0xffff8000))
+#define SET_MRX_FLT_TB4(_VAL_) (REG32(ADR_MRX_FLT_TB4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB4)) & 0xffff8000))
+#define SET_MRX_FLT_TB5(_VAL_) (REG32(ADR_MRX_FLT_TB5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB5)) & 0xffff8000))
+#define SET_MRX_FLT_TB6(_VAL_) (REG32(ADR_MRX_FLT_TB6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB6)) & 0xffff8000))
+#define SET_MRX_FLT_TB7(_VAL_) (REG32(ADR_MRX_FLT_TB7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB7)) & 0xffff8000))
+#define SET_MRX_FLT_TB8(_VAL_) (REG32(ADR_MRX_FLT_TB8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB8)) & 0xffff8000))
+#define SET_MRX_FLT_TB9(_VAL_) (REG32(ADR_MRX_FLT_TB9)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB9)) & 0xffff8000))
+#define SET_MRX_FLT_TB10(_VAL_) (REG32(ADR_MRX_FLT_TB10)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB10)) & 0xffff8000))
+#define SET_MRX_FLT_TB11(_VAL_) (REG32(ADR_MRX_FLT_TB11)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB11)) & 0xffff8000))
+#define SET_MRX_FLT_TB12(_VAL_) (REG32(ADR_MRX_FLT_TB12)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB12)) & 0xffff8000))
+#define SET_MRX_FLT_TB13(_VAL_) (REG32(ADR_MRX_FLT_TB13)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB13)) & 0xffff8000))
+#define SET_MRX_FLT_TB14(_VAL_) (REG32(ADR_MRX_FLT_TB14)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB14)) & 0xffff8000))
+#define SET_MRX_FLT_TB15(_VAL_) (REG32(ADR_MRX_FLT_TB15)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB15)) & 0xffff8000))
+#define SET_MRX_FLT_EN0(_VAL_) (REG32(ADR_MRX_FLT_EN0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN0)) & 0xffff0000))
+#define SET_MRX_FLT_EN1(_VAL_) (REG32(ADR_MRX_FLT_EN1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN1)) & 0xffff0000))
+#define SET_MRX_FLT_EN2(_VAL_) (REG32(ADR_MRX_FLT_EN2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN2)) & 0xffff0000))
+#define SET_MRX_FLT_EN3(_VAL_) (REG32(ADR_MRX_FLT_EN3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN3)) & 0xffff0000))
+#define SET_MRX_FLT_EN4(_VAL_) (REG32(ADR_MRX_FLT_EN4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN4)) & 0xffff0000))
+#define SET_MRX_FLT_EN5(_VAL_) (REG32(ADR_MRX_FLT_EN5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN5)) & 0xffff0000))
+#define SET_MRX_FLT_EN6(_VAL_) (REG32(ADR_MRX_FLT_EN6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN6)) & 0xffff0000))
+#define SET_MRX_FLT_EN7(_VAL_) (REG32(ADR_MRX_FLT_EN7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN7)) & 0xffff0000))
+#define SET_MRX_FLT_EN8(_VAL_) (REG32(ADR_MRX_FLT_EN8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN8)) & 0xffff0000))
+#define SET_MRX_LEN_FLT(_VAL_) (REG32(ADR_MRX_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_LEN_FLT)) & 0xffff0000))
+#define SET_RX_FLOW_DATA(_VAL_) (REG32(ADR_RX_FLOW_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_DATA)) & 0x00000000))
+#define SET_RX_FLOW_MNG(_VAL_) (REG32(ADR_RX_FLOW_MNG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_MNG)) & 0xffff0000))
+#define SET_RX_FLOW_CTRL(_VAL_) (REG32(ADR_RX_FLOW_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_CTRL)) & 0xffff0000))
+#define SET_MRX_STP_EN(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xfffffffe))
+#define SET_MRX_STP_OFST(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xffff00ff))
+#define SET_DBG_FF_FULL(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_FF_FULL)) & 0xffff0000))
+#define SET_DBG_FF_FULL_CLR(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_FF_FULL)) & 0x7fffffff))
+#define SET_DBG_WFF_FULL(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_WFF_FULL)) & 0xffff0000))
+#define SET_DBG_WFF_FULL_CLR(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_WFF_FULL)) & 0x7fffffff))
+#define SET_DBG_MB_FULL(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_MB_FULL)) & 0xffff0000))
+#define SET_DBG_MB_FULL_CLR(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_MB_FULL)) & 0x7fffffff))
+#define SET_BA_CTRL(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BA_CTRL)) & 0xfffffffc))
+#define SET_BA_DBG_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_BA_CTRL)) & 0xfffffffb))
+#define SET_BA_AGRE_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_BA_CTRL)) & 0xfffffff7))
+#define SET_BA_TA_31_0(_VAL_) (REG32(ADR_BA_TA_0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_0)) & 0x00000000))
+#define SET_BA_TA_47_32(_VAL_) (REG32(ADR_BA_TA_1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_1)) & 0xffff0000))
+#define SET_BA_TID(_VAL_) (REG32(ADR_BA_TID)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TID)) & 0xfffffff0))
+#define SET_BA_ST_SEQ(_VAL_) (REG32(ADR_BA_ST_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_BA_ST_SEQ)) & 0xfffff000))
+#define SET_BA_SB0(_VAL_) (REG32(ADR_BA_SB0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB0)) & 0x00000000))
+#define SET_BA_SB1(_VAL_) (REG32(ADR_BA_SB1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB1)) & 0x00000000))
+#define SET_MRX_WD(_VAL_) (REG32(ADR_MRX_WATCH_DOG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_WATCH_DOG)) & 0xfffe0000))
+#define SET_ACK_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffe))
+#define SET_BA_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 1) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffd))
+#define SET_ACK_GEN_DUR(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffff0000))
+#define SET_ACK_GEN_INFO(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 16) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffc0ffff))
+#define SET_ACK_GEN_RA_31_0(_VAL_) (REG32(ADR_ACK_GEN_RA_0)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_0)) & 0x00000000))
+#define SET_ACK_GEN_RA_47_32(_VAL_) (REG32(ADR_ACK_GEN_RA_1)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_1)) & 0xffff0000))
+#define SET_MIB_LEN_FAIL(_VAL_) (REG32(ADR_MIB_LEN_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_LEN_FAIL)) & 0xffff0000))
+#define SET_TRAP_HW_ID(_VAL_) (REG32(ADR_TRAP_HW_ID)) = (((_VAL_) << 0) | ((REG32(ADR_TRAP_HW_ID)) & 0xfffffff0))
+#define SET_ID_IN_USE(_VAL_) (REG32(ADR_ID_IN_USE)) = (((_VAL_) << 0) | ((REG32(ADR_ID_IN_USE)) & 0xffffff00))
+#define SET_MRX_ERR(_VAL_) (REG32(ADR_MRX_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ERR)) & 0x00000000))
+#define SET_W0_T0_SEQ(_VAL_) (REG32(ADR_WSID0_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T1_SEQ(_VAL_) (REG32(ADR_WSID0_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T2_SEQ(_VAL_) (REG32(ADR_WSID0_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T3_SEQ(_VAL_) (REG32(ADR_WSID0_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T4_SEQ(_VAL_) (REG32(ADR_WSID0_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T5_SEQ(_VAL_) (REG32(ADR_WSID0_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T6_SEQ(_VAL_) (REG32(ADR_WSID0_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T7_SEQ(_VAL_) (REG32(ADR_WSID0_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T0_SEQ(_VAL_) (REG32(ADR_WSID1_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T1_SEQ(_VAL_) (REG32(ADR_WSID1_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T2_SEQ(_VAL_) (REG32(ADR_WSID1_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T3_SEQ(_VAL_) (REG32(ADR_WSID1_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T4_SEQ(_VAL_) (REG32(ADR_WSID1_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T5_SEQ(_VAL_) (REG32(ADR_WSID1_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T6_SEQ(_VAL_) (REG32(ADR_WSID1_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T7_SEQ(_VAL_) (REG32(ADR_WSID1_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0xffff0000))
+#define SET_ADDR1A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffffc))
+#define SET_ADDR2A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 2) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffff3))
+#define SET_ADDR3A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 4) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffffcf))
+#define SET_ADDR1B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 6) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffff3f))
+#define SET_ADDR2B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffcff))
+#define SET_ADDR3B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 10) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffff3ff))
+#define SET_ADDR3C_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 12) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffcfff))
+#define SET_FRM_CTRL(_VAL_) (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (((_VAL_) << 0) | ((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0xffffffc0))
+#define SET_CSR_PHY_INFO(_VAL_) (REG32(ADR_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_INFO)) & 0xffff8000))
+#define SET_AMPDU_SIG(_VAL_) (REG32(ADR_AMPDU_SIG)) = (((_VAL_) << 0) | ((REG32(ADR_AMPDU_SIG)) & 0xffffff00))
+#define SET_MIB_AMPDU(_VAL_) (REG32(ADR_MIB_AMPDU)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_AMPDU)) & 0x00000000))
+#define SET_LEN_FLT(_VAL_) (REG32(ADR_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_LEN_FLT)) & 0xffff0000))
+#define SET_MIB_DELIMITER(_VAL_) (REG32(ADR_MIB_DELIMITER)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_DELIMITER)) & 0xffff0000))
+#define SET_MTX_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_STS)) & 0xfffeffff))
+#define SET_MTX_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_STS)) & 0xfffdffff))
+#define SET_MTX_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_STS)) & 0xfffbffff))
+#define SET_MTX_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_STS)) & 0xfff7ffff))
+#define SET_MTX_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_STS)) & 0xffefffff))
+#define SET_MTX_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_STS)) & 0xffdfffff))
+#define SET_MTX_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_STS)) & 0xffbfffff))
+#define SET_MTX_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_STS)) & 0xff7fffff))
+#define SET_MTX_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_STS)) & 0xfeffffff))
+#define SET_MTX_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_STS)) & 0xfdffffff))
+#define SET_MTX_EN_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_EN)) & 0xfffeffff))
+#define SET_MTX_EN_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_EN)) & 0xfffdffff))
+#define SET_MTX_EN_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_EN)) & 0xfffbffff))
+#define SET_MTX_EN_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_EN)) & 0xfff7ffff))
+#define SET_MTX_EN_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_EN)) & 0xffefffff))
+#define SET_MTX_EN_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_EN)) & 0xffdfffff))
+#define SET_MTX_EN_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_EN)) & 0xffbfffff))
+#define SET_MTX_EN_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_EN)) & 0xff7fffff))
+#define SET_MTX_EN_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_EN)) & 0xfeffffff))
+#define SET_MTX_EN_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_EN)) & 0xfdffffff))
+#define SET_MTX_MTX2PHY_SLOW(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffffe))
+#define SET_MTX_M2M_SLOW_PRD(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffff1))
+#define SET_MTX_AMPDU_CRC_AUTO(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffdf))
+#define SET_MTX_FAST_RSP_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffbf))
+#define SET_MTX_RAW_DATA_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffff7f))
+#define SET_MTX_ACK_DUR0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffeff))
+#define SET_MTX_TSF_AUTO_BCN(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffbff))
+#define SET_MTX_TSF_AUTO_MISC(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffff7ff))
+#define SET_MTX_FORCE_CS_IDLE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffefff))
+#define SET_MTX_FORCE_BKF_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffdfff))
+#define SET_MTX_FORCE_DMA_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffbfff))
+#define SET_MTX_FORCE_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_MISC_EN)) & 0xffff7fff))
+#define SET_MTX_HALT_Q_MB(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_MISC_EN)) & 0xffc0ffff))
+#define SET_MTX_CTS_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_MISC_EN)) & 0xffbfffff))
+#define SET_MTX_AMPDU_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_MISC_EN)) & 0xff7fffff))
+#define SET_MTX_EDCCA_TOUT(_VAL_) (REG32(ADR_MTX_EDCCA_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_EDCCA_TOUT)) & 0xfffffc00))
+#define SET_MTX_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffffd))
+#define SET_MTX_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffff7))
+#define SET_MTX_EN_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffffd))
+#define SET_MTX_EN_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffff7))
+#define SET_MTX_BCN_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffe))
+#define SET_MTX_TIME_STAMP_AUTO_FILL(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffd))
+#define SET_MTX_TSF_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffdf))
+#define SET_MTX_HALT_MNG_UNTIL_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffbf))
+#define SET_MTX_INT_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffff00ff))
+#define SET_MTX_AUTO_FLUSH_Q4(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffeffff))
+#define SET_MTX_BCN_PKTID_CH_LOCK(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffffe))
+#define SET_MTX_BCN_CFG_VLD(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff9))
+#define SET_MTX_AUTO_BCN_ONGOING(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff7))
+#define SET_MTX_BCN_TIMER(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_MISC)) & 0x0000ffff))
+#define SET_MTX_BCN_PERIOD(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_PRD)) & 0xffff0000))
+#define SET_MTX_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_BCN_PRD)) & 0x00ffffff))
+#define SET_MTX_BCN_TSF_L(_VAL_) (REG32(ADR_MTX_BCN_TSF_L)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_L)) & 0x00000000))
+#define SET_MTX_BCN_TSF_U(_VAL_) (REG32(ADR_MTX_BCN_TSF_U)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_U)) & 0x00000000))
+#define SET_MTX_BCN_PKT_ID0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xffffff80))
+#define SET_MTX_DTIM_OFST0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xfc00ffff))
+#define SET_MTX_BCN_PKT_ID1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xffffff80))
+#define SET_MTX_DTIM_OFST1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xfc00ffff))
+#define SET_MTX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffe))
+#define SET_MRX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffd))
+#define SET_MTX_DMA_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 2) | ((REG32(ADR_MTX_STATUS)) & 0xffffffe3))
+#define SET_CH_ST_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_STATUS)) & 0xffffff1f))
+#define SET_MTX_GNT_LOCK(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_STATUS)) & 0xfffffeff))
+#define SET_MTX_DMA_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MTX_STATUS)) & 0xfffffdff))
+#define SET_MTX_Q_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_STATUS)) & 0xfffffbff))
+#define SET_MTX_TX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_STATUS)) & 0xfffff7ff))
+#define SET_MRX_RX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_STATUS)) & 0xffffefff))
+#define SET_DBG_PRTC_PRD(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_STATUS)) & 0xffffdfff))
+#define SET_DBG_DMA_RDY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_STATUS)) & 0xffffbfff))
+#define SET_DBG_WAIT_RSP(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_STATUS)) & 0xffff7fff))
+#define SET_DBG_CFRM_BUSY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_STATUS)) & 0xfffeffff))
+#define SET_DBG_RST(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffe))
+#define SET_DBG_MODE(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffd))
+#define SET_MB_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000))
+#define SET_RX_EN_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff))
+#define SET_RX_CS_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000))
+#define SET_TX_CCA_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff))
+#define SET_Q_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000))
+#define SET_CH_STA0_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff))
+#define SET_MTX_DUR_RSP_TOUT_B(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffffff00))
+#define SET_MTX_DUR_RSP_TOUT_G(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffff00ff))
+#define SET_MTX_DUR_RSP_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffffff00))
+#define SET_MTX_DUR_BURST_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffff00ff))
+#define SET_MTX_DUR_SLOT(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffc0ffff))
+#define SET_MTX_DUR_RSP_EIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_IFS)) & 0x003fffff))
+#define SET_MTX_DUR_RSP_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffffff00))
+#define SET_MTX_DUR_BURST_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffff00ff))
+#define SET_MTX_DUR_SLOT_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc0ffff))
+#define SET_MTX_DUR_RSP_EIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003fffff))
+#define SET_CH_STA1_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000))
+#define SET_CH_STA2_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff))
+#define SET_MTX_NAV(_VAL_) (REG32(ADR_MTX_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_NAV)) & 0xffff0000))
+#define SET_MTX_MIB_CNT0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xc0000000))
+#define SET_MTX_MIB_EN0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xbfffffff))
+#define SET_MTX_MIB_CNT1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xc0000000))
+#define SET_MTX_MIB_EN1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xbfffffff))
+#define SET_CH_STA3_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000))
+#define SET_CH_STA4_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff))
+#define SET_TXQ0_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ0_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ0_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ0_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ0_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ0_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ0_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ0_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ0_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ0_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ0_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ0_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ0_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ0_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ0_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ1_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ1_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ1_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ1_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ1_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ1_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ1_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ1_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ1_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ1_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ1_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ1_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ2_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ2_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ2_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ2_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ2_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ2_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ2_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ2_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ2_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ2_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ2_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ2_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ3_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ3_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ3_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ3_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ3_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ3_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ3_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ3_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ3_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ3_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ3_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ3_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ4_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ4_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ4_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ4_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ4_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ4_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ4_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ4_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ4_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ4_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ4_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ4_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_VALID0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0)) & 0xfffffffe))
+#define SET_PEER_QOS_EN0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 1) | ((REG32(ADR_WSID0)) & 0xfffffffd))
+#define SET_PEER_OP_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 2) | ((REG32(ADR_WSID0)) & 0xfffffff3))
+#define SET_PEER_HT_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 4) | ((REG32(ADR_WSID0)) & 0xffffffcf))
+#define SET_PEER_MAC0_31_0(_VAL_) (REG32(ADR_PEER_MAC0_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_0)) & 0x00000000))
+#define SET_PEER_MAC0_47_32(_VAL_) (REG32(ADR_PEER_MAC0_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_1)) & 0xffff0000))
+#define SET_TX_ACK_POLICY_0_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_0)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_1)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_2)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_3)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_4)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_5)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_6)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_7)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0xfffff000))
+#define SET_VALID1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1)) & 0xfffffffe))
+#define SET_PEER_QOS_EN1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 1) | ((REG32(ADR_WSID1)) & 0xfffffffd))
+#define SET_PEER_OP_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 2) | ((REG32(ADR_WSID1)) & 0xfffffff3))
+#define SET_PEER_HT_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 4) | ((REG32(ADR_WSID1)) & 0xffffffcf))
+#define SET_PEER_MAC1_31_0(_VAL_) (REG32(ADR_PEER_MAC1_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_0)) & 0x00000000))
+#define SET_PEER_MAC1_47_32(_VAL_) (REG32(ADR_PEER_MAC1_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_1)) & 0xffff0000))
+#define SET_TX_ACK_POLICY_1_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_0)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_1)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_2)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_3)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_4)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_5)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_6)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_7)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0xfffff000))
+#define SET_INFO0(_VAL_) (REG32(ADR_INFO0)) = (((_VAL_) << 0) | ((REG32(ADR_INFO0)) & 0x00000000))
+#define SET_INFO1(_VAL_) (REG32(ADR_INFO1)) = (((_VAL_) << 0) | ((REG32(ADR_INFO1)) & 0x00000000))
+#define SET_INFO2(_VAL_) (REG32(ADR_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_INFO2)) & 0x00000000))
+#define SET_INFO3(_VAL_) (REG32(ADR_INFO3)) = (((_VAL_) << 0) | ((REG32(ADR_INFO3)) & 0x00000000))
+#define SET_INFO4(_VAL_) (REG32(ADR_INFO4)) = (((_VAL_) << 0) | ((REG32(ADR_INFO4)) & 0x00000000))
+#define SET_INFO5(_VAL_) (REG32(ADR_INFO5)) = (((_VAL_) << 0) | ((REG32(ADR_INFO5)) & 0x00000000))
+#define SET_INFO6(_VAL_) (REG32(ADR_INFO6)) = (((_VAL_) << 0) | ((REG32(ADR_INFO6)) & 0x00000000))
+#define SET_INFO7(_VAL_) (REG32(ADR_INFO7)) = (((_VAL_) << 0) | ((REG32(ADR_INFO7)) & 0x00000000))
+#define SET_INFO8(_VAL_) (REG32(ADR_INFO8)) = (((_VAL_) << 0) | ((REG32(ADR_INFO8)) & 0x00000000))
+#define SET_INFO9(_VAL_) (REG32(ADR_INFO9)) = (((_VAL_) << 0) | ((REG32(ADR_INFO9)) & 0x00000000))
+#define SET_INFO10(_VAL_) (REG32(ADR_INFO10)) = (((_VAL_) << 0) | ((REG32(ADR_INFO10)) & 0x00000000))
+#define SET_INFO11(_VAL_) (REG32(ADR_INFO11)) = (((_VAL_) << 0) | ((REG32(ADR_INFO11)) & 0x00000000))
+#define SET_INFO12(_VAL_) (REG32(ADR_INFO12)) = (((_VAL_) << 0) | ((REG32(ADR_INFO12)) & 0x00000000))
+#define SET_INFO13(_VAL_) (REG32(ADR_INFO13)) = (((_VAL_) << 0) | ((REG32(ADR_INFO13)) & 0x00000000))
+#define SET_INFO14(_VAL_) (REG32(ADR_INFO14)) = (((_VAL_) << 0) | ((REG32(ADR_INFO14)) & 0x00000000))
+#define SET_INFO15(_VAL_) (REG32(ADR_INFO15)) = (((_VAL_) << 0) | ((REG32(ADR_INFO15)) & 0x00000000))
+#define SET_INFO16(_VAL_) (REG32(ADR_INFO16)) = (((_VAL_) << 0) | ((REG32(ADR_INFO16)) & 0x00000000))
+#define SET_INFO17(_VAL_) (REG32(ADR_INFO17)) = (((_VAL_) << 0) | ((REG32(ADR_INFO17)) & 0x00000000))
+#define SET_INFO18(_VAL_) (REG32(ADR_INFO18)) = (((_VAL_) << 0) | ((REG32(ADR_INFO18)) & 0x00000000))
+#define SET_INFO19(_VAL_) (REG32(ADR_INFO19)) = (((_VAL_) << 0) | ((REG32(ADR_INFO19)) & 0x00000000))
+#define SET_INFO20(_VAL_) (REG32(ADR_INFO20)) = (((_VAL_) << 0) | ((REG32(ADR_INFO20)) & 0x00000000))
+#define SET_INFO21(_VAL_) (REG32(ADR_INFO21)) = (((_VAL_) << 0) | ((REG32(ADR_INFO21)) & 0x00000000))
+#define SET_INFO22(_VAL_) (REG32(ADR_INFO22)) = (((_VAL_) << 0) | ((REG32(ADR_INFO22)) & 0x00000000))
+#define SET_INFO23(_VAL_) (REG32(ADR_INFO23)) = (((_VAL_) << 0) | ((REG32(ADR_INFO23)) & 0x00000000))
+#define SET_INFO24(_VAL_) (REG32(ADR_INFO24)) = (((_VAL_) << 0) | ((REG32(ADR_INFO24)) & 0x00000000))
+#define SET_INFO25(_VAL_) (REG32(ADR_INFO25)) = (((_VAL_) << 0) | ((REG32(ADR_INFO25)) & 0x00000000))
+#define SET_INFO26(_VAL_) (REG32(ADR_INFO26)) = (((_VAL_) << 0) | ((REG32(ADR_INFO26)) & 0x00000000))
+#define SET_INFO27(_VAL_) (REG32(ADR_INFO27)) = (((_VAL_) << 0) | ((REG32(ADR_INFO27)) & 0x00000000))
+#define SET_INFO28(_VAL_) (REG32(ADR_INFO28)) = (((_VAL_) << 0) | ((REG32(ADR_INFO28)) & 0x00000000))
+#define SET_INFO29(_VAL_) (REG32(ADR_INFO29)) = (((_VAL_) << 0) | ((REG32(ADR_INFO29)) & 0x00000000))
+#define SET_INFO30(_VAL_) (REG32(ADR_INFO30)) = (((_VAL_) << 0) | ((REG32(ADR_INFO30)) & 0x00000000))
+#define SET_INFO31(_VAL_) (REG32(ADR_INFO31)) = (((_VAL_) << 0) | ((REG32(ADR_INFO31)) & 0x00000000))
+#define SET_INFO32(_VAL_) (REG32(ADR_INFO32)) = (((_VAL_) << 0) | ((REG32(ADR_INFO32)) & 0x00000000))
+#define SET_INFO33(_VAL_) (REG32(ADR_INFO33)) = (((_VAL_) << 0) | ((REG32(ADR_INFO33)) & 0x00000000))
+#define SET_INFO34(_VAL_) (REG32(ADR_INFO34)) = (((_VAL_) << 0) | ((REG32(ADR_INFO34)) & 0x00000000))
+#define SET_INFO35(_VAL_) (REG32(ADR_INFO35)) = (((_VAL_) << 0) | ((REG32(ADR_INFO35)) & 0x00000000))
+#define SET_INFO36(_VAL_) (REG32(ADR_INFO36)) = (((_VAL_) << 0) | ((REG32(ADR_INFO36)) & 0x00000000))
+#define SET_INFO37(_VAL_) (REG32(ADR_INFO37)) = (((_VAL_) << 0) | ((REG32(ADR_INFO37)) & 0x00000000))
+#define SET_INFO38(_VAL_) (REG32(ADR_INFO38)) = (((_VAL_) << 0) | ((REG32(ADR_INFO38)) & 0x00000000))
+#define SET_INFO_MASK(_VAL_) (REG32(ADR_INFO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_MASK)) & 0x00000000))
+#define SET_INFO_DEF_RATE(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xffffffc0))
+#define SET_INFO_MRX_OFFSET(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xfff0ffff))
+#define SET_BCAST_RATEUNKNOW(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 24) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xc0ffffff))
+#define SET_INFO_IDX_TBL_ADDR(_VAL_) (REG32(ADR_INFO_IDX_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_IDX_ADDR)) & 0x00000000))
+#define SET_INFO_LEN_TBL_ADDR(_VAL_) (REG32(ADR_INFO_LEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_LEN_ADDR)) & 0x00000000))
+#define SET_IC_TAG_31_0(_VAL_) (REG32(ADR_IC_TIME_TAG_0)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_0)) & 0x00000000))
+#define SET_IC_TAG_63_32(_VAL_) (REG32(ADR_IC_TIME_TAG_1)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_1)) & 0x00000000))
+#define SET_CH1_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffffc))
+#define SET_CH2_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 8) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffcff))
+#define SET_CH3_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 16) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffcffff))
+#define SET_RG_MAC_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_MODE)) & 0xfffffffe))
+#define SET_RG_MAC_M2M(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_MODE)) & 0xfffffffd))
+#define SET_RG_PHY_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_MAC_MODE)) & 0xfffffffb))
+#define SET_RG_LPBK_RX_EN(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_MODE)) & 0xfffffff7))
+#define SET_EXT_MAC_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_MODE)) & 0xffffffef))
+#define SET_EXT_PHY_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_MODE)) & 0xffffffdf))
+#define SET_ASIC_TAG(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 24) | ((REG32(ADR_MAC_MODE)) & 0x00ffffff))
+#define SET_HCI_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffe))
+#define SET_CO_PROC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_CHST_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_BCN_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MRX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_AMPDU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_MMU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffdff))
+#define SET_ID_MNG_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffff7ff))
+#define SET_MBOX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffefff))
+#define SET_SCRT_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffdfff))
+#define SET_MIC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_CO_PROC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_CHST_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_BCN_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MRX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_AMPDU_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_ID_MNG_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_MBOX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffff7fff))
+#define SET_SCRT_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 16) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffeffff))
+#define SET_MIC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 17) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffdffff))
+#define SET_CO_PROC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE0_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_QUE1_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_QUE2_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MTX_QUE3_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_MTX_QUE4_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_MTX_QUE5_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffdff))
+#define SET_MRX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffbff))
+#define SET_AMPDU_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffff7ff))
+#define SET_SCRT_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffdfff))
+#define SET_ID_MNG_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_MBOX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffff7fff))
+#define SET_HCI_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_CO_PROC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MTX_MISC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_MTX_QUE_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_MRX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_AMPDU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_MMU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffff7f))
+#define SET_ID_MNG_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffdff))
+#define SET_MBOX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_SCRT_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_MIC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_MIB_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_HCI_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_CO_PROC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MTX_MISC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_MTX_QUE_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_MRX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_AMPDU_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_ID_MNG_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_MBOX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_SCRT_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_MIC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_CO_PROC_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MRX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_AMPDU_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_SCRT_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_ID_MNG_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_MBOX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_OP_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 0) | ((REG32(ADR_GLBLE_SET)) & 0xfffffffc))
+#define SET_HT_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 2) | ((REG32(ADR_GLBLE_SET)) & 0xfffffff3))
+#define SET_QOS_EN(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 4) | ((REG32(ADR_GLBLE_SET)) & 0xffffffef))
+#define SET_PB_OFFSET(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 8) | ((REG32(ADR_GLBLE_SET)) & 0xffff00ff))
+#define SET_SNIFFER_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 16) | ((REG32(ADR_GLBLE_SET)) & 0xfffeffff))
+#define SET_DUP_FLT(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 17) | ((REG32(ADR_GLBLE_SET)) & 0xfffdffff))
+#define SET_TX_PKT_RSVD(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 18) | ((REG32(ADR_GLBLE_SET)) & 0xffe3ffff))
+#define SET_AMPDU_SNIFFER(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 21) | ((REG32(ADR_GLBLE_SET)) & 0xffdfffff))
+#define SET_REASON_TRAP0(_VAL_) (REG32(ADR_REASON_TRAP0)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP0)) & 0x00000000))
+#define SET_REASON_TRAP1(_VAL_) (REG32(ADR_REASON_TRAP1)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP1)) & 0x00000000))
+#define SET_BSSID_31_0(_VAL_) (REG32(ADR_BSSID_0)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_0)) & 0x00000000))
+#define SET_BSSID_47_32(_VAL_) (REG32(ADR_BSSID_1)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_1)) & 0xffff0000))
+#define SET_SCRT_STATE(_VAL_) (REG32(ADR_SCRT_STATE)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_STATE)) & 0xfffffff0))
+#define SET_STA_MAC_31_0(_VAL_) (REG32(ADR_STA_MAC_0)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_0)) & 0x00000000))
+#define SET_STA_MAC_47_32(_VAL_) (REG32(ADR_STA_MAC_1)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_1)) & 0xffff0000))
+#define SET_PAIR_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_SET)) & 0xfffffff8))
+#define SET_GRP_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 3) | ((REG32(ADR_SCRT_SET)) & 0xffffffc7))
+#define SET_SCRT_PKT_ID(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 6) | ((REG32(ADR_SCRT_SET)) & 0xffffe03f))
+#define SET_SCRT_RPLY_IGNORE(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 16) | ((REG32(ADR_SCRT_SET)) & 0xfffeffff))
+#define SET_COEXIST_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX0)) & 0xfffffffe))
+#define SET_WIRE_MODE(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 1) | ((REG32(ADR_BTCX0)) & 0xfffffff1))
+#define SET_WL_RX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 4) | ((REG32(ADR_BTCX0)) & 0xffffffef))
+#define SET_WL_TX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 5) | ((REG32(ADR_BTCX0)) & 0xffffffdf))
+#define SET_GURAN_USE_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX0)) & 0xfffffeff))
+#define SET_GURAN_USE_CTRL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 9) | ((REG32(ADR_BTCX0)) & 0xfffffdff))
+#define SET_BEACON_TIMEOUT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 10) | ((REG32(ADR_BTCX0)) & 0xfffffbff))
+#define SET_WLAN_ACT_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 11) | ((REG32(ADR_BTCX0)) & 0xfffff7ff))
+#define SET_DUAL_ANT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 12) | ((REG32(ADR_BTCX0)) & 0xffffefff))
+#define SET_TRSW_PHY_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX0)) & 0xfffeffff))
+#define SET_WIFI_TX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 17) | ((REG32(ADR_BTCX0)) & 0xfffdffff))
+#define SET_WIFI_RX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 18) | ((REG32(ADR_BTCX0)) & 0xfffbffff))
+#define SET_BT_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 19) | ((REG32(ADR_BTCX0)) & 0xfff7ffff))
+#define SET_BT_PRI_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX1)) & 0xffffff00))
+#define SET_BT_STA_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX1)) & 0xffff00ff))
+#define SET_BEACON_TIMEOUT(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX1)) & 0xff00ffff))
+#define SET_WLAN_REMAIN_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 24) | ((REG32(ADR_BTCX1)) & 0x00ffffff))
+#define SET_SW_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffe))
+#define SET_SW_WL_TX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 1) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffd))
+#define SET_SW_WL_RX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 2) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffb))
+#define SET_SW_BT_TRX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 3) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffff7))
+#define SET_BT_TXBAR_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 4) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffef))
+#define SET_BT_TXBAR_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 5) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffdf))
+#define SET_BT_BUSY_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffeff))
+#define SET_BT_BUSY_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 9) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffdff))
+#define SET_G0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 2) | ((REG32(ADR_MIB_EN)) & 0xfffffffb))
+#define SET_G0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 3) | ((REG32(ADR_MIB_EN)) & 0xfffffff7))
+#define SET_G1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 4) | ((REG32(ADR_MIB_EN)) & 0xffffffef))
+#define SET_G1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MIB_EN)) & 0xffffffdf))
+#define SET_Q0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MIB_EN)) & 0xffffffbf))
+#define SET_Q0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MIB_EN)) & 0xffffff7f))
+#define SET_Q1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MIB_EN)) & 0xfffffeff))
+#define SET_Q1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 9) | ((REG32(ADR_MIB_EN)) & 0xfffffdff))
+#define SET_Q2_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MIB_EN)) & 0xfffffbff))
+#define SET_Q2_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MIB_EN)) & 0xfffff7ff))
+#define SET_Q3_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MIB_EN)) & 0xffffefff))
+#define SET_Q3_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MIB_EN)) & 0xffffdfff))
+#define SET_SCRT_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MIB_EN)) & 0xffffbfff))
+#define SET_SCRT_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MIB_EN)) & 0xffff7fff))
+#define SET_MISC_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MIB_EN)) & 0xfffeffff))
+#define SET_MISC_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MIB_EN)) & 0xfffdffff))
+#define SET_MTX_WSID0_SUCC(_VAL_) (REG32(ADR_MTX_WSID0_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_SUCC)) & 0xffff0000))
+#define SET_MTX_WSID0_FRM(_VAL_) (REG32(ADR_MTX_WSID0_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_FRM)) & 0xffff0000))
+#define SET_MTX_WSID0_RETRY(_VAL_) (REG32(ADR_MTX_WSID0_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_RETRY)) & 0xffff0000))
+#define SET_MTX_WSID0_TOTAL(_VAL_) (REG32(ADR_MTX_WSID0_TOTAL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_TOTAL)) & 0xffff0000))
+#define SET_MTX_GRP(_VAL_) (REG32(ADR_MTX_GROUP)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_GROUP)) & 0xfff00000))
+#define SET_MTX_FAIL(_VAL_) (REG32(ADR_MTX_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FAIL)) & 0xffff0000))
+#define SET_MTX_RETRY(_VAL_) (REG32(ADR_MTX_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RETRY)) & 0xfff00000))
+#define SET_MTX_MULTI_RETRY(_VAL_) (REG32(ADR_MTX_MULTI_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MULTI_RETRY)) & 0xfff00000))
+#define SET_MTX_RTS_SUCC(_VAL_) (REG32(ADR_MTX_RTS_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_SUCCESS)) & 0xffff0000))
+#define SET_MTX_RTS_FAIL(_VAL_) (REG32(ADR_MTX_RTS_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_FAIL)) & 0xffff0000))
+#define SET_MTX_ACK_FAIL(_VAL_) (REG32(ADR_MTX_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_FAIL)) & 0xffff0000))
+#define SET_MTX_FRM(_VAL_) (REG32(ADR_MTX_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FRM)) & 0xfff00000))
+#define SET_MTX_ACK_TX(_VAL_) (REG32(ADR_MTX_ACK_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_TX)) & 0xffff0000))
+#define SET_MTX_CTS_TX(_VAL_) (REG32(ADR_MTX_CTS_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_CTS_TX)) & 0xffff0000))
+#define SET_MRX_DUP(_VAL_) (REG32(ADR_MRX_DUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DUP_FRM)) & 0xffff0000))
+#define SET_MRX_FRG(_VAL_) (REG32(ADR_MRX_FRG_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FRG_FRM)) & 0xfff00000))
+#define SET_MRX_GRP(_VAL_) (REG32(ADR_MRX_GROUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_GROUP_FRM)) & 0xfff00000))
+#define SET_MRX_FCS_ERR(_VAL_) (REG32(ADR_MRX_FCS_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_ERR)) & 0xffff0000))
+#define SET_MRX_FCS_SUC(_VAL_) (REG32(ADR_MRX_FCS_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_SUCC)) & 0xffff0000))
+#define SET_MRX_MISS(_VAL_) (REG32(ADR_MRX_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MISS)) & 0xffff0000))
+#define SET_MRX_ALC_FAIL(_VAL_) (REG32(ADR_MRX_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ALC_FAIL)) & 0xffff0000))
+#define SET_MRX_DAT_NTF(_VAL_) (REG32(ADR_MRX_DAT_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_NTF)) & 0xffff0000))
+#define SET_MRX_RTS_NTF(_VAL_) (REG32(ADR_MRX_RTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_RTS_NTF)) & 0xffff0000))
+#define SET_MRX_CTS_NTF(_VAL_) (REG32(ADR_MRX_CTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CTS_NTF)) & 0xffff0000))
+#define SET_MRX_ACK_NTF(_VAL_) (REG32(ADR_MRX_ACK_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ACK_NTF)) & 0xffff0000))
+#define SET_MRX_BA_NTF(_VAL_) (REG32(ADR_MRX_BA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_NTF)) & 0xffff0000))
+#define SET_MRX_DATA_NTF(_VAL_) (REG32(ADR_MRX_DATA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DATA_NTF)) & 0xffff0000))
+#define SET_MRX_MNG_NTF(_VAL_) (REG32(ADR_MRX_MNG_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MNG_NTF)) & 0xffff0000))
+#define SET_MRX_DAT_CRC_NTF(_VAL_) (REG32(ADR_MRX_DAT_CRC_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_CRC_NTF)) & 0xffff0000))
+#define SET_MRX_BAR_NTF(_VAL_) (REG32(ADR_MRX_BAR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BAR_NTF)) & 0xffff0000))
+#define SET_MRX_MB_MISS(_VAL_) (REG32(ADR_MRX_MB_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MB_MISS)) & 0xffff0000))
+#define SET_MRX_NIDLE_MISS(_VAL_) (REG32(ADR_MRX_NIDLE_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_NIDLE_MISS)) & 0xffff0000))
+#define SET_MRX_CSR_NTF(_VAL_) (REG32(ADR_MRX_CSR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CSR_NTF)) & 0xffff0000))
+#define SET_DBG_Q0_SUCC(_VAL_) (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q0_FAIL(_VAL_) (REG32(ADR_DBG_Q0_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q0_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q0_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q0_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q1_SUCC(_VAL_) (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q1_FAIL(_VAL_) (REG32(ADR_DBG_Q1_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q1_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q1_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q1_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q2_SUCC(_VAL_) (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q2_FAIL(_VAL_) (REG32(ADR_DBG_Q2_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q2_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q2_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q2_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q3_SUCC(_VAL_) (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q3_FAIL(_VAL_) (REG32(ADR_DBG_Q3_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q3_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q3_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q3_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0xffff0000))
+#define SET_SCRT_TKIP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP0)) & 0xfff00000))
+#define SET_SCRT_TKIP_MIC_ERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP1)) & 0xfff00000))
+#define SET_SCRT_TKIP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_TKIP2)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP2)) & 0xfff00000))
+#define SET_SCRT_CCMP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_CCMP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP0)) & 0xfff00000))
+#define SET_SCRT_CCMP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_CCMP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP1)) & 0xfff00000))
+#define SET_DBG_LEN_CRC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_CRC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0xffff0000))
+#define SET_DBG_LEN_ALC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0xffff0000))
+#define SET_DBG_AMPDU_PASS(_VAL_) (REG32(ADR_DBG_AMPDU_PASS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_PASS)) & 0xffff0000))
+#define SET_DBG_AMPDU_FAIL(_VAL_) (REG32(ADR_DBG_AMPDU_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_FAIL)) & 0xffff0000))
+#define SET_RXID_ALC_CNT_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL1)) & 0xffff0000))
+#define SET_RXID_ALC_LEN_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL2)) & 0xffff0000))
+#define SET_CBR_RG_EN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_TX_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_TX_PA_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_TX_DAC_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_RX_AGC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
+#define SET_CBR_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_RFG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
+#define SET_CBR_RG_PGAG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
+#define SET_CBR_RG_MODE(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
+#define SET_CBR_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_EN_SX(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
+#define SET_CBR_RG_EN_RX_LNA(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
+#define SET_CBR_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
+#define SET_CBR_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
+#define SET_CBR_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
+#define SET_CBR_RG_EN_RX_TZ(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
+#define SET_CBR_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_EN_RX_HPF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
+#define SET_CBR_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
+#define SET_CBR_RG_EN_ADC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
+#define SET_CBR_RG_EN_TX_MOD(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
+#define SET_CBR_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
+#define SET_CBR_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
+#define SET_CBR_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
+#define SET_CBR_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
+#define SET_CBR_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
+#define SET_CBR_RG_EN_TX_DPD(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_CBR_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_CBR_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
+#define SET_CBR_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_EN_IREF_RX(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_DCDC_MODE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffefff))
+#define SET_CBR_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffff8))
+#define SET_CBR_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffffffc7))
+#define SET_CBR_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffe3f))
+#define SET_CBR_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffff1ff))
+#define SET_CBR_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffff8fff))
+#define SET_CBR_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffc7fff))
+#define SET_CBR_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffe3ffff))
+#define SET_CBR_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xff1fffff))
+#define SET_CBR_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xf8ffffff))
+#define SET_CBR_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xc7ffffff))
+#define SET_CBR_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffe))
+#define SET_CBR_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffd))
+#define SET_CBR_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffb))
+#define SET_CBR_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffe07))
+#define SET_CBR_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffdff))
+#define SET_CBR_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffbff))
+#define SET_CBR_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffff7ff))
+#define SET_CBR_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffffcfff))
+#define SET_CBR_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffff3fff))
+#define SET_CBR_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffcffff))
+#define SET_CBR_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfff3ffff))
+#define SET_CBR_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffcfffff))
+#define SET_CBR_RG_RX_HPF3M(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffbfffff))
+#define SET_CBR_RG_RX_HPF300K(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xff7fffff))
+#define SET_CBR_RG_RX_HPFI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfcffffff))
+#define SET_CBR_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xf3ffffff))
+#define SET_CBR_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xcfffffff))
+#define SET_CBR_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffffc))
+#define SET_CBR_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffff3))
+#define SET_CBR_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffffcf))
+#define SET_CBR_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffff3f))
+#define SET_CBR_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffcff))
+#define SET_CBR_RG_RX_OUTVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffff3ff))
+#define SET_CBR_RG_RX_TZI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffcfff))
+#define SET_CBR_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffbfff))
+#define SET_CBR_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffe7fff))
+#define SET_CBR_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfff1ffff))
+#define SET_CBR_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffefffff))
+#define SET_CBR_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xff9fffff))
+#define SET_CBR_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfe7fffff))
+#define SET_CBR_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfdffffff))
+#define SET_CBR_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffffffc))
+#define SET_CBR_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffff03))
+#define SET_CBR_RG_TXPGA_STEER(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffc0ff))
+#define SET_CBR_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffff3fff))
+#define SET_CBR_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffcffff))
+#define SET_CBR_RG_PACELL_EN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffe3ffff))
+#define SET_CBR_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfe1fffff))
+#define SET_CBR_RG_PABIAS_AB(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfdffffff))
+#define SET_CBR_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xf3ffffff))
+#define SET_CBR_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xcfffffff))
+#define SET_CBR_RG_RX_SQDC(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffffff8))
+#define SET_CBR_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffffe7))
+#define SET_CBR_RG_RX_LOBUF(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffff9f))
+#define SET_CBR_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffff87f))
+#define SET_CBR_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffff87ff))
+#define SET_CBR_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffc7fff))
+#define SET_CBR_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffe3ffff))
+#define SET_CBR_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffdfffff))
+#define SET_CBR_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xff3fffff))
+#define SET_CBR_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
+#define SET_CBR_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
+#define SET_CBR_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
+#define SET_CBR_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
+#define SET_CBR_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
+#define SET_CBR_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
+#define SET_CBR_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
+#define SET_CBR_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
+#define SET_CBR_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
+#define SET_CBR_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
+#define SET_CBR_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
+#define SET_CBR_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
+#define SET_CBR_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
+#define SET_CBR_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_HPF_T1A(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_HPF_T1B(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffff9f))
+#define SET_CBR_RG_HPF_T1C(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffe7f))
+#define SET_CBR_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffff9ff))
+#define SET_CBR_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffe7ff))
+#define SET_CBR_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_ADC_DIVR(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_ADC_DVCMI(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffffffcf))
+#define SET_CBR_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffc3f))
+#define SET_CBR_RG_ADC_STNBY(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_ADC_TSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffff0fff))
+#define SET_CBR_RG_ADC_VRSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffcffff))
+#define SET_CBR_RG_DICMP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfff3ffff))
+#define SET_CBR_RG_DIOP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffcfffff))
+#define SET_CBR_RG_DACI1ST(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffffc))
+#define SET_CBR_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffff3))
+#define SET_CBR_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffffcf))
+#define SET_CBR_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffff3f))
+#define SET_CBR_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffff9ff))
+#define SET_CBR_RG_TX_DAC_OS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffc7ff))
+#define SET_CBR_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffff3fff))
+#define SET_CBR_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfff0ffff))
+#define SET_CBR_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffefffff))
+#define SET_CBR_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffbfffff))
+#define SET_CBR_RG_EN_SX_R3(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_EN_SX_CH(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_EN_SX_CHP(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffef))
+#define SET_CBR_RG_EN_SX_VCO(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_EN_SX_MOD(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffbf))
+#define SET_CBR_RG_EN_SX_LCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffff7f))
+#define SET_CBR_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_EN_SX_DELCAL(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_EN_SX_PC_BYPASS(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffefff))
+#define SET_CBR_RG_EN_SX_DIV(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffdfff))
+#define SET_CBR_RG_EN_SX_LPF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xff000000))
+#define SET_CBR_RG_SX_SEL_CP(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_SEL_CS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0fffffff))
+#define SET_CBR_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfffff800))
+#define SET_CBR_RG_SX_SEL_C3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xffff87ff))
+#define SET_CBR_RG_SX_SEL_RS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfff07fff))
+#define SET_CBR_RG_SX_SEL_R3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfe0fffff))
+#define SET_CBR_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffffe0))
+#define SET_CBR_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffffc1f))
+#define SET_CBR_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffc3ff))
+#define SET_CBR_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffc3fff))
+#define SET_CBR_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffbffff))
+#define SET_CBR_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffc7ffff))
+#define SET_CBR_RG_SX_PFDSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffbfffff))
+#define SET_CBR_RG_SX_PFD_SET(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xff7fffff))
+#define SET_CBR_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfeffffff))
+#define SET_CBR_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfdffffff))
+#define SET_CBR_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfbffffff))
+#define SET_CBR_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xf7ffffff))
+#define SET_CBR_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xefffffff))
+#define SET_CBR_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xdfffffff))
+#define SET_CBR_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xbfffffff))
+#define SET_CBR_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffffff8))
+#define SET_CBR_RG_SX_VCORSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffffff07))
+#define SET_CBR_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffff0ff))
+#define SET_CBR_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffff0fff))
+#define SET_CBR_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfff0ffff))
+#define SET_CBR_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xff0fffff))
+#define SET_CBR_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0fffffff))
+#define SET_CBR_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
+#define SET_CBR_RG_SX_MOD_ERRCMP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffff3))
+#define SET_CBR_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
+#define SET_CBR_RG_SX_SDM_D1(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffbf))
+#define SET_CBR_RG_SX_SDM_D2(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffff7f))
+#define SET_CBR_RG_SDM_PASS(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffeff))
+#define SET_CBR_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
+#define SET_CBR_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
+#define SET_CBR_RG_SX_XO_GM(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
+#define SET_CBR_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
+#define SET_CBR_RG_SX_XO_SWCAP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffc3fff))
+#define SET_CBR_RG_SX_SDMLUT_INV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffbffff))
+#define SET_CBR_RG_SX_LCKEN(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
+#define SET_CBR_RG_SX_PREVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
+#define SET_CBR_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_MOD_ERR_DELAY(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xcfffffff))
+#define SET_CBR_RG_SX_MODDB(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xbfffffff))
+#define SET_CBR_RG_SX_CV_CURVE_SEL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffffffc))
+#define SET_CBR_RG_SX_SEL_DELAY(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffff83))
+#define SET_CBR_RG_SX_REF_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff87f))
+#define SET_CBR_RG_SX_VCOBY16(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff7ff))
+#define SET_CBR_RG_SX_VCOBY32(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffefff))
+#define SET_CBR_RG_SX_PH(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffdfff))
+#define SET_CBR_RG_SX_PL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffbfff))
+#define SET_CBR_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffffe))
+#define SET_CBR_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffff9))
+#define SET_CBR_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffe7))
+#define SET_CBR_RG_SX_VT_SET(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffdf))
+#define SET_CBR_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffff803f))
+#define SET_CBR_RG_IDEAL_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xf0007fff))
+#define SET_CBR_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_DP_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffc01f))
+#define SET_CBR_RG_DP_CK320BY2(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_SX_DELCTRL(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffe07fff))
+#define SET_CBR_RG_DP_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
+#define SET_CBR_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
+#define SET_CBR_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
+#define SET_CBR_RG_DP_RP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
+#define SET_CBR_RG_DP_RHP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
+#define SET_CBR_RG_DP_DR3(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xff8fffff))
+#define SET_CBR_RG_DP_DCP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xf87fffff))
+#define SET_CBR_RG_DP_DCS(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x87ffffff))
+#define SET_CBR_RG_DP_FBDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xfffff000))
+#define SET_CBR_RG_DP_FODIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00fff))
+#define SET_CBR_RG_DP_REFDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003fffff))
+#define SET_CBR_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
+#define SET_CBR_RG_EN_RCAL(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_RCAL_SPD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_RCAL_TMR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffe03))
+#define SET_CBR_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xffff83ff))
+#define SET_CBR_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffffff01))
+#define SET_CBR_RG_DP_BBPLL_BS_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_DP_BBPLL_BS_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffff81ff))
+#define SET_CBR_RCAL_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
+#define SET_CBR_DA_LCK_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
+#define SET_CBR_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
+#define SET_CBR_DP_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffff7))
+#define SET_CBR_CH_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffffef))
+#define SET_CBR_DA_R_CODE_LUT(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
+#define SET_CBR_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
+#define SET_CBR_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
+#define SET_CBR_DA_R_CAL_CODE(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
+#define SET_CBR_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
+#define SET_CBR_DA_DP_BBPLL_BS(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffc0fff))
+#define SET_CBR_TX_EN(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffe))
+#define SET_CBR_TX_CNT_RST(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffd))
+#define SET_CBR_IFS_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xffffff03))
+#define SET_CBR_LENGTH_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfff000ff))
+#define SET_CBR_TX_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00ffffff))
+#define SET_CBR_TC_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0xff000000))
+#define SET_CBR_PLCP_PSDU_DATA_MEM(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffffff00))
+#define SET_CBR_PLCP_PSDU_PREAMBLE_SHORT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xfffffeff))
+#define SET_CBR_PLCP_BYTE_LENGTH(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffe001ff))
+#define SET_CBR_PLCP_PSDU_RATE(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xff9fffff))
+#define SET_CBR_TAIL_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xe07fffff))
+#define SET_CBR_RG_O_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffe))
+#define SET_CBR_RG_I_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffd))
+#define SET_CBR_SEL_ADCKP_INV(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffb))
+#define SET_CBR_RG_PAD_DS(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffff7))
+#define SET_CBR_SEL_ADCKP_MUX(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffef))
+#define SET_CBR_RG_PAD_DS_CLK(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffdf))
+#define SET_CBR_INTP_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffdff))
+#define SET_CBR_IQ_SWP(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffbff))
+#define SET_CBR_RG_EN_EXT_DA(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffff7ff))
+#define SET_CBR_RG_DIS_DA_OFFSET(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffefff))
+#define SET_CBR_DBG_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfff0ffff))
+#define SET_CBR_DBG_EN(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffefffff))
+#define SET_CBR_RG_PKT_GEN_TX_CNT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0x00000000))
+#define SET_CBR_TP_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffe0))
+#define SET_CBR_IDEAL_IQ_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffdf))
+#define SET_CBR_DATA_OUT_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffe3f))
+#define SET_CBR_TWO_TONE_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffdff))
+#define SET_CBR_FREQ_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xff00ffff))
+#define SET_CBR_IQ_SCALE(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ffffff))
+#define SET_CPU_QUE_POP(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 0) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffe))
+#define SET_CPU_INT(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 2) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffb))
+#define SET_CPU_ID_TB0(_VAL_) (REG32(ADR_CPU_ID_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB0)) & 0x00000000))
+#define SET_CPU_ID_TB1(_VAL_) (REG32(ADR_CPU_ID_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB1)) & 0x00000000))
+#define SET_HW_PKTID(_VAL_) (REG32(ADR_CH0_TRIG_1)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_1)) & 0xfffff800))
+#define SET_CH0_INT_ADDR(_VAL_) (REG32(ADR_CH0_TRIG_0)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_0)) & 0x00000000))
+#define SET_PRI_HW_PKTID(_VAL_) (REG32(ADR_CH0_PRI_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_PRI_TRIG)) & 0xfffff800))
+#define SET_CH0_FULL(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffe))
+#define SET_FF0_EMPTY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffd))
+#define SET_RLS_BUSY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_STATUS)) & 0xfffffdff))
+#define SET_RLS_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MCU_STATUS)) & 0xfffffbff))
+#define SET_RTN_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MCU_STATUS)) & 0xfffff7ff))
+#define SET_RLS_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MCU_STATUS)) & 0xff00ffff))
+#define SET_RTN_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MCU_STATUS)) & 0x00ffffff))
+#define SET_FF0_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffffe0))
+#define SET_FF1_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfffffe1f))
+#define SET_FF3_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffc7ff))
+#define SET_FF5_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 17) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfff1ffff))
+#define SET_FF6_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xff8fffff))
+#define SET_FF7_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 23) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfc7fffff))
+#define SET_FF8_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 26) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xe3ffffff))
+#define SET_FF9_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 29) | ((REG32(ADR_RD_IN_FFCNT1)) & 0x1fffffff))
+#define SET_FF10_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffff8))
+#define SET_FF11_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 3) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffffc7))
+#define SET_FF12_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 6) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffe3f))
+#define SET_FF13_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 9) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffff9ff))
+#define SET_FF14_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffe7ff))
+#define SET_FF15_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 13) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffff9fff))
+#define SET_FF4_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfff07fff))
+#define SET_FF2_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xff8fffff))
+#define SET_CH1_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffd))
+#define SET_CH2_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffb))
+#define SET_CH3_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffff7))
+#define SET_CH4_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffef))
+#define SET_CH5_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffdf))
+#define SET_CH6_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffbf))
+#define SET_CH7_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffff7f))
+#define SET_CH8_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffeff))
+#define SET_CH9_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffdff))
+#define SET_CH10_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffbff))
+#define SET_CH11_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffff7ff))
+#define SET_CH12_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffefff))
+#define SET_CH13_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffdfff))
+#define SET_CH14_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffbfff))
+#define SET_CH15_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffff7fff))
+#define SET_HALT_CH0(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffe))
+#define SET_HALT_CH1(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffd))
+#define SET_HALT_CH2(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffb))
+#define SET_HALT_CH3(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 3) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffff7))
+#define SET_HALT_CH4(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffef))
+#define SET_HALT_CH5(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffdf))
+#define SET_HALT_CH6(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffbf))
+#define SET_HALT_CH7(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffff7f))
+#define SET_HALT_CH8(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffeff))
+#define SET_HALT_CH9(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 9) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffdff))
+#define SET_HALT_CH10(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 10) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffbff))
+#define SET_HALT_CH11(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 11) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffff7ff))
+#define SET_HALT_CH12(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 12) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffefff))
+#define SET_HALT_CH13(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 13) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffdfff))
+#define SET_HALT_CH14(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 14) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffbfff))
+#define SET_HALT_CH15(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 15) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffff7fff))
+#define SET_STOP_MBOX(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffeffff))
+#define SET_MB_ERR_AUTO_HALT_EN(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 20) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffefffff))
+#define SET_MB_EXCEPT_CLR(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 21) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffdfffff))
+#define SET_MB_EXCEPT_CASE(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 24) | ((REG32(ADR_MBOX_HALT_CFG)) & 0x00ffffff))
+#define SET_MB_DBG_TIME_STEP(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG1)) & 0xffff0000))
+#define SET_DBG_TYPE(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffcffff))
+#define SET_MB_DBG_CLR(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffbffff))
+#define SET_DBG_ALC_LOG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfff7ffff))
+#define SET_MB_DBG_COUNTER_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfeffffff))
+#define SET_MB_DBG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG1)) & 0x7fffffff))
+#define SET_MB_DBG_RECORD_CNT(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000))
+#define SET_MB_DBG_LENGTH(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff))
+#define SET_MB_DBG_CFG_ADDR(_VAL_) (REG32(ADR_MB_DBG_CFG3)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG3)) & 0x00000000))
+#define SET_DBG_HWID0_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffe))
+#define SET_DBG_HWID1_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 1) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffd))
+#define SET_DBG_HWID2_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 2) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffb))
+#define SET_DBG_HWID3_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 3) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffff7))
+#define SET_DBG_HWID4_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 4) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffef))
+#define SET_DBG_HWID5_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 5) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffdf))
+#define SET_DBG_HWID6_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 6) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffbf))
+#define SET_DBG_HWID7_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 7) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffff7f))
+#define SET_DBG_HWID8_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 8) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffeff))
+#define SET_DBG_HWID9_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 9) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffdff))
+#define SET_DBG_HWID10_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 10) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffbff))
+#define SET_DBG_HWID11_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 11) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffff7ff))
+#define SET_DBG_HWID12_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 12) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffefff))
+#define SET_DBG_HWID13_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 13) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffdfff))
+#define SET_DBG_HWID14_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 14) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffbfff))
+#define SET_DBG_HWID15_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 15) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffff7fff))
+#define SET_DBG_HWID0_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffeffff))
+#define SET_DBG_HWID1_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 17) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffdffff))
+#define SET_DBG_HWID2_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffbffff))
+#define SET_DBG_HWID3_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfff7ffff))
+#define SET_DBG_HWID4_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 20) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffefffff))
+#define SET_DBG_HWID5_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 21) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffdfffff))
+#define SET_DBG_HWID6_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 22) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffbfffff))
+#define SET_DBG_HWID7_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 23) | ((REG32(ADR_MB_DBG_CFG4)) & 0xff7fffff))
+#define SET_DBG_HWID8_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfeffffff))
+#define SET_DBG_HWID9_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 25) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfdffffff))
+#define SET_DBG_HWID10_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 26) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfbffffff))
+#define SET_DBG_HWID11_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 27) | ((REG32(ADR_MB_DBG_CFG4)) & 0xf7ffffff))
+#define SET_DBG_HWID12_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 28) | ((REG32(ADR_MB_DBG_CFG4)) & 0xefffffff))
+#define SET_DBG_HWID13_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 29) | ((REG32(ADR_MB_DBG_CFG4)) & 0xdfffffff))
+#define SET_DBG_HWID14_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 30) | ((REG32(ADR_MB_DBG_CFG4)) & 0xbfffffff))
+#define SET_DBG_HWID15_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG4)) & 0x7fffffff))
+#define SET_MB_OUT_QUEUE_EN(_VAL_) (REG32(ADR_MB_OUT_QUEUE_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0xfffffffd))
+#define SET_CH0_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffe))
+#define SET_CH1_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffd))
+#define SET_CH2_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffb))
+#define SET_CH3_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffff7))
+#define SET_CH4_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffef))
+#define SET_CH5_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffdf))
+#define SET_CH6_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffbf))
+#define SET_CH7_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffff7f))
+#define SET_CH8_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffeff))
+#define SET_CH9_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffdff))
+#define SET_CH10_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffbff))
+#define SET_CH11_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffff7ff))
+#define SET_CH12_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffefff))
+#define SET_CH13_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffdfff))
+#define SET_CH14_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffbfff))
+#define SET_CH15_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 15) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffff7fff))
+#define SET_FFO0_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffffffe0))
+#define SET_FFO1_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffffc1f))
+#define SET_FFO2_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffff3ff))
+#define SET_FFO3_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfff07fff))
+#define SET_FFO4_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffcfffff))
+#define SET_FFO5_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xf1ffffff))
+#define SET_FFO6_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffff0))
+#define SET_FFO7_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffc1f))
+#define SET_FFO8_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xffff83ff))
+#define SET_FFO9_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfff07fff))
+#define SET_FFO10_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xff0fffff))
+#define SET_FFO11_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xc1ffffff))
+#define SET_FFO12_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffffff8))
+#define SET_FFO13_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffffff9f))
+#define SET_FFO14_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffff3ff))
+#define SET_FFO15_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffe07fff))
+#define SET_CH0_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffe))
+#define SET_CH1_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffd))
+#define SET_CH2_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffb))
+#define SET_CH3_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffff7))
+#define SET_CH4_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffef))
+#define SET_CH5_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffdf))
+#define SET_CH6_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffbf))
+#define SET_CH7_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffff7f))
+#define SET_CH8_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffeff))
+#define SET_CH9_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffdff))
+#define SET_CH10_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffbff))
+#define SET_CH11_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffff7ff))
+#define SET_CH12_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffefff))
+#define SET_CH13_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffdfff))
+#define SET_CH14_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffbfff))
+#define SET_CH15_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffff7fff))
+#define SET_CH0_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffe))
+#define SET_CH1_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 1) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffd))
+#define SET_CH2_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 2) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffb))
+#define SET_CH3_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 3) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffff7))
+#define SET_CH4_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 4) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffef))
+#define SET_CH5_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 5) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffdf))
+#define SET_CH6_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 6) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffbf))
+#define SET_CH7_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 7) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffff7f))
+#define SET_CH8_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffeff))
+#define SET_CH9_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 9) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffdff))
+#define SET_CH10_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 10) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffbff))
+#define SET_CH11_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 11) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffff7ff))
+#define SET_CH12_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 12) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffefff))
+#define SET_CH13_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 13) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffdfff))
+#define SET_CH14_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 14) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffbfff))
+#define SET_CH15_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 15) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffff7fff))
+#define SET_MB_LOW_THOLD_EN(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 31) | ((REG32(ADR_MB_THRESHOLD6)) & 0x7fffffff))
+#define SET_CH0_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffffe0))
+#define SET_CH1_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffe0ff))
+#define SET_CH2_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffe0ffff))
+#define SET_CH3_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD7)) & 0xe0ffffff))
+#define SET_CH4_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffffe0))
+#define SET_CH5_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffe0ff))
+#define SET_CH6_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffe0ffff))
+#define SET_CH7_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD8)) & 0xe0ffffff))
+#define SET_CH8_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffffe0))
+#define SET_CH9_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffe0ff))
+#define SET_CH10_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffe0ffff))
+#define SET_CH11_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD9)) & 0xe0ffffff))
+#define SET_CH12_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffffe0))
+#define SET_CH13_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffe0ff))
+#define SET_CH14_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffe0ffff))
+#define SET_CH15_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD10)) & 0xe0ffffff))
+#define SET_TRASH_TIMEOUT_EN(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffe))
+#define SET_TRASH_CAN_INT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffd))
+#define SET_TRASH_INT_ID(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffff80f))
+#define SET_TRASH_TIMEOUT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfc00ffff))
+#define SET_CH0_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffe))
+#define SET_CH1_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffd))
+#define SET_CH2_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffb))
+#define SET_CH3_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffff7))
+#define SET_CH4_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffef))
+#define SET_CH5_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffdf))
+#define SET_CH6_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffbf))
+#define SET_CH7_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffff7f))
+#define SET_CH8_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffeff))
+#define SET_CH9_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffdff))
+#define SET_CH10_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffbff))
+#define SET_CH11_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffff7ff))
+#define SET_CH12_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffefff))
+#define SET_CH13_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffdfff))
+#define SET_CH14_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffbfff))
+#define SET_CPU_ID_TB2(_VAL_) (REG32(ADR_CPU_ID_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB2)) & 0x00000000))
+#define SET_CPU_ID_TB3(_VAL_) (REG32(ADR_CPU_ID_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB3)) & 0x00000000))
+#define SET_IQ_LOG_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0xfffffffe))
+#define SET_IQ_LOG_STOP_MODE(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xfffffffe))
+#define SET_GPIO_STOP_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffef))
+#define SET_GPIO_STOP_POL(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffdf))
+#define SET_IQ_LOG_TIMER(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x0000ffff))
+#define SET_IQ_LOG_LEN(_VAL_) (REG32(ADR_PHY_IQ_LOG_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_LEN)) & 0xffff0000))
+#define SET_IQ_LOG_TAIL_ADR(_VAL_) (REG32(ADR_PHY_IQ_LOG_PTR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_PTR)) & 0xffff0000))
+#define SET_ALC_LENG(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 0) | ((REG32(ADR_WR_ALC)) & 0xfffc0000))
+#define SET_CH0_DYN_PRI(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 20) | ((REG32(ADR_WR_ALC)) & 0xffcfffff))
+#define SET_MCU_PKTID(_VAL_) (REG32(ADR_GETID)) = (((_VAL_) << 0) | ((REG32(ADR_GETID)) & 0x00000000))
+#define SET_CH0_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffffc))
+#define SET_CH1_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_STA_PRI)) & 0xffffffcf))
+#define SET_CH2_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffcff))
+#define SET_CH3_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_STA_PRI)) & 0xffffcfff))
+#define SET_ID_TB0(_VAL_) (REG32(ADR_RD_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID0)) & 0x00000000))
+#define SET_ID_TB1(_VAL_) (REG32(ADR_RD_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID1)) & 0x00000000))
+#define SET_ID_MNG_HALT(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_CFG)) & 0xffffffef))
+#define SET_ID_MNG_ERR_HALT_EN(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_CFG)) & 0xffffffdf))
+#define SET_ID_EXCEPT_FLG_CLR(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_CFG)) & 0xffffffbf))
+#define SET_ID_EXCEPT_FLG(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_CFG)) & 0xffffff7f))
+#define SET_ID_FULL(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 0) | ((REG32(ADR_IMD_STA)) & 0xfffffffe))
+#define SET_ID_MNG_BUSY(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 1) | ((REG32(ADR_IMD_STA)) & 0xfffffffd))
+#define SET_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 2) | ((REG32(ADR_IMD_STA)) & 0xfffffffb))
+#define SET_CH0_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_STA)) & 0xffffffef))
+#define SET_CH1_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_STA)) & 0xffffffdf))
+#define SET_CH2_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_STA)) & 0xffffffbf))
+#define SET_CH3_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_STA)) & 0xffffff7f))
+#define SET_REQ_LOCK_INT_EN(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 8) | ((REG32(ADR_IMD_STA)) & 0xfffffeff))
+#define SET_REQ_LOCK_INT(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 9) | ((REG32(ADR_IMD_STA)) & 0xfffffdff))
+#define SET_MCU_ALC_READY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_STA)) & 0xfffffffe))
+#define SET_ALC_FAIL(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 1) | ((REG32(ADR_ALC_STA)) & 0xfffffffd))
+#define SET_ALC_BUSY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 2) | ((REG32(ADR_ALC_STA)) & 0xfffffffb))
+#define SET_CH0_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 4) | ((REG32(ADR_ALC_STA)) & 0xffffffef))
+#define SET_CH1_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 5) | ((REG32(ADR_ALC_STA)) & 0xffffffdf))
+#define SET_CH2_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 6) | ((REG32(ADR_ALC_STA)) & 0xffffffbf))
+#define SET_CH3_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 7) | ((REG32(ADR_ALC_STA)) & 0xffffff7f))
+#define SET_ALC_INT_ID(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_STA)) & 0xffff80ff))
+#define SET_ALC_TIMEOUT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_STA)) & 0xfc00ffff))
+#define SET_ALC_TIMEOUT_INT_EN(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 30) | ((REG32(ADR_ALC_STA)) & 0xbfffffff))
+#define SET_ALC_TIMEOUT_INT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_STA)) & 0x7fffffff))
+#define SET_TX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffffff00))
+#define SET_RX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffff00ff))
+#define SET_TX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffffff00))
+#define SET_RX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffff00ff))
+#define SET_ID_THOLD_RX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfffeffff))
+#define SET_RX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 17) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfff1ffff))
+#define SET_ID_THOLD_TX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 20) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffefffff))
+#define SET_TX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 21) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xff1fffff))
+#define SET_ID_THOLD_INT_EN(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfeffffff))
+#define SET_TX_ID_TB0(_VAL_) (REG32(ADR_TX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID0)) & 0x00000000))
+#define SET_TX_ID_TB1(_VAL_) (REG32(ADR_TX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID1)) & 0x00000000))
+#define SET_RX_ID_TB0(_VAL_) (REG32(ADR_RX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID0)) & 0x00000000))
+#define SET_RX_ID_TB1(_VAL_) (REG32(ADR_RX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID1)) & 0x00000000))
+#define SET_DOUBLE_RLS_INT_EN(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 0) | ((REG32(ADR_RTN_STA)) & 0xfffffffe))
+#define SET_ID_DOUBLE_RLS_INT(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 1) | ((REG32(ADR_RTN_STA)) & 0xfffffffd))
+#define SET_DOUBLE_RLS_ID(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 8) | ((REG32(ADR_RTN_STA)) & 0xffff80ff))
+#define SET_ID_LEN_THOLD_INT_EN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffe))
+#define SET_ALL_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 1) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffd))
+#define SET_TX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 2) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffb))
+#define SET_RX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 3) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffff7))
+#define SET_ID_TX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 4) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffffe00f))
+#define SET_ID_RX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 13) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffc01fff))
+#define SET_ID_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 22) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x803fffff))
+#define SET_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffffe00))
+#define SET_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 9) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffc01ff))
+#define SET_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 18) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xf803ffff))
+#define SET_CH_ARB_EN(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffffe))
+#define SET_CH_PRI1(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffffcf))
+#define SET_CH_PRI2(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffcff))
+#define SET_CH_PRI3(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffcfff))
+#define SET_CH_PRI4(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 16) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffcffff))
+#define SET_TX_ID_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xffffff80))
+#define SET_TX_PAGE_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xfffe00ff))
+#define SET_ID_PAGE_MAX_SIZE(_VAL_) (REG32(ADR_ID_INFO_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ID_INFO_STA)) & 0xfffffe00))
+#define SET_TX_PAGE_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xfffffe00))
+#define SET_TX_COUNT_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xff00ffff))
+#define SET_TX_LIMIT_INT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 30) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xbfffffff))
+#define SET_TX_LIMIT_INT_EN(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 31) | ((REG32(ADR_TX_LIMIT_INTR)) & 0x7fffffff))
+#define SET_TX_PAGE_USE_7_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffff00))
+#define SET_TX_ID_USE_5_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffc0ff))
+#define SET_EDCA0_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 14) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xfffc3fff))
+#define SET_EDCA1_FFO_CNT_3_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 18) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffc3ffff))
+#define SET_EDCA2_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xf83fffff))
+#define SET_EDCA3_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 27) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0x07ffffff))
+#define SET_ID_TB2(_VAL_) (REG32(ADR_RD_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID2)) & 0x00000000))
+#define SET_ID_TB3(_VAL_) (REG32(ADR_RD_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID3)) & 0x00000000))
+#define SET_TX_ID_TB2(_VAL_) (REG32(ADR_TX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID2)) & 0x00000000))
+#define SET_TX_ID_TB3(_VAL_) (REG32(ADR_TX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID3)) & 0x00000000))
+#define SET_RX_ID_TB2(_VAL_) (REG32(ADR_RX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID2)) & 0x00000000))
+#define SET_RX_ID_TB3(_VAL_) (REG32(ADR_RX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID3)) & 0x00000000))
+#define SET_TX_PAGE_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffffe00))
+#define SET_TX_ID_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffe01ff))
+#define SET_EDCA4_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xffe1ffff))
+#define SET_TX_PAGE_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffffe00))
+#define SET_TX_ID_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffe01ff))
+#define SET_EDCA1_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 21) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfc1fffff))
+#define SET_EDCA4_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 26) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xc3ffffff))
+#define SET_TX_PAGE_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffffe00))
+#define SET_TX_ID_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffe01ff))
+#define SET_EDCA2_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xffc1ffff))
+#define SET_EDCA3_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xf83fffff))
+#define SET_TX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfffffe00))
+#define SET_RX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfe00ffff))
+#define SET_MAX_ALL_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INFO)) & 0xffffff00))
+#define SET_MAX_TX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_ID_INFO)) & 0xffff00ff))
+#define SET_MAX_RX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_ID_INFO)) & 0xff00ffff))
+#define SET_MAX_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffffe00))
+#define SET_MAX_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 9) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffc01ff))
+#define SET_MAX_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 18) | ((REG32(ADR_ALC_ID_INF1)) & 0xf803ffff))
+#define SET_RG_PMDLBK(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_0)) & 0xfffffffe))
+#define SET_RG_RDYACK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff9))
+#define SET_RG_ADEDGE_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff7))
+#define SET_RG_SIGN_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_0)) & 0xffffffef))
+#define SET_RG_IQ_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_0)) & 0xffffffdf))
+#define SET_RG_Q_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_0)) & 0xffffffbf))
+#define SET_RG_I_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_EN_0)) & 0xffffff7f))
+#define SET_RG_BYPASS_ACI(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_0)) & 0xfffffeff))
+#define SET_RG_LBK_ANA_PATH(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_EN_0)) & 0xfffffdff))
+#define SET_RG_SPECTRUM_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_EN_0)) & 0xfffff3ff))
+#define SET_RG_SPECTRUM_BW(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_0)) & 0xffffcfff))
+#define SET_RG_SPECTRUM_FREQ_MANUAL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_0)) & 0xffffbfff))
+#define SET_RG_SPECTRUM_EN(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_0)) & 0xffff7fff))
+#define SET_RG_TXPWRLVL_SET(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_0)) & 0xff00ffff))
+#define SET_RG_TXPWRLVL_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_EN_0)) & 0xfeffffff))
+#define SET_RG_RF_BB_CLK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_EN_0)) & 0x7fffffff))
+#define SET_RG_PHY_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffe))
+#define SET_RG_PHYRX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffd))
+#define SET_RG_PHYTX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffb))
+#define SET_RG_PHY11GN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_1)) & 0xfffffff7))
+#define SET_RG_PHY11B_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_1)) & 0xffffffef))
+#define SET_RG_PHYRXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_1)) & 0xffffffdf))
+#define SET_RG_PHYTXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_1)) & 0xffffffbf))
+#define SET_RG_PHY11BGN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_1)) & 0xfffffeff))
+#define SET_RG_FORCE_11GN_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_1)) & 0xffffefff))
+#define SET_RG_FORCE_11B_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 13) | ((REG32(ADR_PHY_EN_1)) & 0xffffdfff))
+#define SET_RG_FFT_MEM_CLK_EN_RX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_1)) & 0xffffbfff))
+#define SET_RG_FFT_MEM_CLK_EN_TX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_1)) & 0xffff7fff))
+#define SET_RG_PHY_IQ_TRIG_SEL(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_1)) & 0xfff0ffff))
+#define SET_RG_SPECTRUM_FREQ(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_EN_1)) & 0xc00fffff))
+#define SET_SVN_VERSION(_VAL_) (REG32(ADR_SVN_VERSION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SVN_VERSION_REG)) & 0x00000000))
+#define SET_RG_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffff0000))
+#define SET_RG_PKT_MODE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xfff8ffff))
+#define SET_RG_CH_BW(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 19) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffc7ffff))
+#define SET_RG_PRM(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 22) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffbfffff))
+#define SET_RG_SHORTGI(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xff7fffff))
+#define SET_RG_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0x80ffffff))
+#define SET_RG_L_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xfffff000))
+#define SET_RG_L_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff8fff))
+#define SET_RG_SERVICE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0x0000ffff))
+#define SET_RG_SMOOTHING(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffe))
+#define SET_RG_NO_SOUND(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffd))
+#define SET_RG_AGGREGATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffb))
+#define SET_RG_STBC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffe7))
+#define SET_RG_FEC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffdf))
+#define SET_RG_N_ESS(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffff3f))
+#define SET_RG_TXPWRLVL(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffff00ff))
+#define SET_RG_TX_START(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffffe))
+#define SET_RG_IFS_TIME(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xffffff03))
+#define SET_RG_CONTINUOUS_DATA(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffeff))
+#define SET_RG_DATA_SEL(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffff9ff))
+#define SET_RG_TX_D(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xff00ffff))
+#define SET_RG_TX_CNT_TARGET(_VAL_) (REG32(ADR_PHY_PKT_GEN_4)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_4)) & 0x00000000))
+#define SET_RG_FFT_IFFT_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_REG_00)) & 0xffffff3f))
+#define SET_RG_DAC_DBG_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_00)) & 0xfffffeff))
+#define SET_RG_DAC_SGN_SWAP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_REG_00)) & 0xfffffdff))
+#define SET_RG_TXD_SEL(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_REG_00)) & 0xfffff3ff))
+#define SET_RG_UP8X(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_00)) & 0xff00ffff))
+#define SET_RG_IQ_DC_BYP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_00)) & 0xfeffffff))
+#define SET_RG_IQ_DC_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_00)) & 0xcfffffff))
+#define SET_RG_DAC_DCEN(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_01)) & 0xfffffffe))
+#define SET_RG_DAC_DCQ(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_01)) & 0xffffc00f))
+#define SET_RG_DAC_DCI(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_01)) & 0xfc00ffff))
+#define SET_RG_PGA_REFDB_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffffff80))
+#define SET_RG_PGA_REFDB_TOP(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffff80ff))
+#define SET_RG_PGA_REF_UND(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xfc00ffff))
+#define SET_RG_RF_REF_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_02_AGC)) & 0x0fffffff))
+#define SET_RG_PGAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xfffffff0))
+#define SET_RG_PGAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffffef))
+#define SET_RG_RFGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff9f))
+#define SET_RG_RFGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff7f))
+#define SET_RG_WAIT_T_RXAGC(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffc0ff))
+#define SET_RG_RXAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffbfff))
+#define SET_RG_RXAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffff7fff))
+#define SET_RG_WAIT_T_FINAL(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffc0ffff))
+#define SET_RG_WAIT_T(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xc0ffffff))
+#define SET_RG_ULG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffffff0))
+#define SET_RG_LG_PGA_UND_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffffff0f))
+#define SET_RG_LG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffff0ff))
+#define SET_RG_LG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffff0fff))
+#define SET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfff0ffff))
+#define SET_RG_HG_PGA_SAT2_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xff0fffff))
+#define SET_RG_HG_PGA_SAT1_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xf0ffffff))
+#define SET_RG_HG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_04_AGC)) & 0x0fffffff))
+#define SET_RG_MG_PGA_JB_TH(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xfffffff0))
+#define SET_RG_MA_PGA_LOW_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xffe0ffff))
+#define SET_RG_WR_RFGC_INIT_SET(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 21) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff9fffff))
+#define SET_RG_WR_RFGC_INIT_EN(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff7fffff))
+#define SET_RG_MA_PGA_HIGH_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xe0ffffff))
+#define SET_RG_AGC_THRESHOLD(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xffffc000))
+#define SET_RG_ACI_POINT_CNT_LMT_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xff80ffff))
+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xfcffffff))
+#define SET_RG_WR_ACI_GAIN_INI_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffffff00))
+#define SET_RG_WR_ACI_GAIN_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffff00ff))
+#define SET_RG_ACI_DAGC_SET_VALUE_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xff80ffff))
+#define SET_RG_WR_ACI_GAIN_OW_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x7fffffff))
+#define SET_RG_ACI_POINT_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xffffff00))
+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xfffffcff))
+#define SET_RG_ACI_DAGC_DONE_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00ffffff))
+#define SET_RG_ACI_DAGC_SET_VALUE_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffffff80))
+#define SET_RG_ACI_GAIN_INI_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffff00ff))
+#define SET_RG_ACI_GAIN_OW_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xff00ffff))
+#define SET_RG_ACI_GAIN_OW_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x7fffffff))
+#define SET_RO_CCA_PWR_MA_11GN(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffffff80))
+#define SET_RO_ED_STATE(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffff7fff))
+#define SET_RO_CCA_PWR_MA_11B(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xff80ffff))
+#define SET_RO_PGA_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RO_PGA_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RO_PGA_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RG_TX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffffe0))
+#define SET_RG_TX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffe0ff))
+#define SET_RG_TX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xe0ffffff))
+#define SET_RG_TX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffffe0))
+#define SET_RG_TX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffe0ff))
+#define SET_RG_TX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xe0ffffff))
+#define SET_RG_TX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffffe))
+#define SET_RG_TX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffffef))
+#define SET_RG_TX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffeff))
+#define SET_RG_TX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffefff))
+#define SET_RG_TX_DES_PWRLVL(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xe0ffffff))
+#define SET_RG_RX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffffc0))
+#define SET_RG_RX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffc0ff))
+#define SET_RG_RX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffc0ffff))
+#define SET_RG_RX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xc0ffffff))
+#define SET_RG_RX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffffc0))
+#define SET_RG_RX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffc0ff))
+#define SET_RG_RX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffc0ffff))
+#define SET_RG_RX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xc0ffffff))
+#define SET_RG_RX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffffe))
+#define SET_RG_RX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffffef))
+#define SET_RG_RX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffeff))
+#define SET_RG_RX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffefff))
+#define SET_RG_RX_DES_SNR(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfff0ffff))
+#define SET_RG_RX_DES_RCPI(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xff0fffff))
+#define SET_RG_RX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xc0ffffff))
+#define SET_RO_TX_DES_EXCP_RATE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffffff00))
+#define SET_RO_TX_DES_EXCP_CH_BW_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffff00ff))
+#define SET_RO_TX_DES_EXCP_MODE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xff00ffff))
+#define SET_RG_TX_DES_EXCP_RATE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xf8ffffff))
+#define SET_RG_TX_DES_EXCP_MODE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x8fffffff))
+#define SET_RG_TX_DES_EXCP_CLR(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x7fffffff))
+#define SET_RG_TX_DES_ACK_WIDTH(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffffe))
+#define SET_RG_TX_DES_ACK_PRD(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffff1))
+#define SET_RG_RX_DES_SNR_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xffc0ffff))
+#define SET_RG_RX_DES_RCPI_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xc0ffffff))
+#define SET_RG_TST_TBUS_SEL(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfffffff0))
+#define SET_RG_RSSI_OFFSET(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xff00ffff))
+#define SET_RG_RSSI_INV(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfeffffff))
+#define SET_RG_TST_ADC_ON(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xbfffffff))
+#define SET_RG_TST_EXT_GAIN(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x7fffffff))
+#define SET_RG_DAC_Q_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xfffffc00))
+#define SET_RG_DAC_I_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xffc00fff))
+#define SET_RG_DAC_EN_MAN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xefffffff))
+#define SET_RG_IQC_FFT_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xdfffffff))
+#define SET_RG_DAC_MAN_Q_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xbfffffff))
+#define SET_RG_DAC_MAN_I_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x7fffffff))
+#define SET_RO_MRX_EN_CNT(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0xffff0000))
+#define SET_RG_MRX_EN_CNT_RST_N(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x7fffffff))
+#define SET_RG_PA_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffffff00))
+#define SET_RG_RFTX_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffff00ff))
+#define SET_RG_DAC_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff00ffff))
+#define SET_RG_SW_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ffffff))
+#define SET_RG_PA_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffffff00))
+#define SET_RG_RFTX_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffff00ff))
+#define SET_RG_DAC_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff00ffff))
+#define SET_RG_SW_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ffffff))
+#define SET_RG_ANT_SW_0(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xfffffff8))
+#define SET_RG_ANT_SW_1(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xffffffc7))
+#define SET_RG_MTX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MTX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MTX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MTX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MTX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MTX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MRX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MRX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MRX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MRX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MRX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MRX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x7fffffff))
+#define SET_RO_MTX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000))
+#define SET_RO_MTX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff))
+#define SET_RO_MRX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000))
+#define SET_RO_MRX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff))
+#define SET_RG_MODE_REG_IN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffff0000))
+#define SET_RG_PARALLEL_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffefffff))
+#define SET_RG_MBRUN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_28_BIST)) & 0x7fffffff))
+#define SET_RO_MODE_REG_OUT_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xffff0000))
+#define SET_RO_MODE_REG_SO_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_16(_VAL_) (REG32(ADR_PHY_READ_REG_07_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_07_BIST)) & 0xfff80000))
+#define SET_RG_MRX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffffff00))
+#define SET_RG_MRX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffff00ff))
+#define SET_RG_MTX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff00ffff))
+#define SET_RG_MTX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ffffff))
+#define SET_RO_MTX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000))
+#define SET_RO_MTX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff))
+#define SET_RO_MRX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000))
+#define SET_RO_MRX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff))
+#define SET_RG_HB_COEF0(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xfffff000))
+#define SET_RG_HB_COEF1(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xf000ffff))
+#define SET_RG_HB_COEF2(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xfffff000))
+#define SET_RG_HB_COEF3(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xf000ffff))
+#define SET_RG_HB_COEF4(_VAL_) (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0xfffff000))
+#define SET_RO_TBUS_O(_VAL_) (REG32(ADR_PHY_READ_TBUS)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_TBUS)) & 0xfff00000))
+#define SET_RG_LPF4_00(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_00)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_00)) & 0xffffe000))
+#define SET_RG_LPF4_01(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_01)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_01)) & 0xffffe000))
+#define SET_RG_LPF4_02(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_02)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_02)) & 0xffffe000))
+#define SET_RG_LPF4_03(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_03)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_03)) & 0xffffe000))
+#define SET_RG_LPF4_04(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_04)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_04)) & 0xffffe000))
+#define SET_RG_LPF4_05(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_05)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_05)) & 0xffffe000))
+#define SET_RG_LPF4_06(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_06)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_06)) & 0xffffe000))
+#define SET_RG_LPF4_07(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_07)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_07)) & 0xffffe000))
+#define SET_RG_LPF4_08(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_08)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_08)) & 0xffffe000))
+#define SET_RG_LPF4_09(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_09)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_09)) & 0xffffe000))
+#define SET_RG_LPF4_10(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_10)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_10)) & 0xffffe000))
+#define SET_RG_LPF4_11(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_11)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_11)) & 0xffffe000))
+#define SET_RG_LPF4_12(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_12)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_12)) & 0xffffe000))
+#define SET_RG_LPF4_13(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_13)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_13)) & 0xffffe000))
+#define SET_RG_LPF4_14(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_14)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_14)) & 0xffffe000))
+#define SET_RG_LPF4_15(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_15)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_15)) & 0xffffe000))
+#define SET_RG_LPF4_16(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_16)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_16)) & 0xffffe000))
+#define SET_RG_LPF4_17(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_17)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_17)) & 0xffffe000))
+#define SET_RG_LPF4_18(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_18)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_18)) & 0xffffe000))
+#define SET_RG_LPF4_19(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_19)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_19)) & 0xffffe000))
+#define SET_RG_LPF4_20(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_20)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_20)) & 0xffffe000))
+#define SET_RG_LPF4_21(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_21)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_21)) & 0xffffe000))
+#define SET_RG_LPF4_22(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_22)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_22)) & 0xffffe000))
+#define SET_RG_LPF4_23(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_23)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_23)) & 0xffffe000))
+#define SET_RG_LPF4_24(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_24)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_24)) & 0xffffe000))
+#define SET_RG_LPF4_25(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_25)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_25)) & 0xffffe000))
+#define SET_RG_LPF4_26(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_26)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_26)) & 0xffffe000))
+#define SET_RG_LPF4_27(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_27)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_27)) & 0xffffe000))
+#define SET_RG_LPF4_28(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_28)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_28)) & 0xffffe000))
+#define SET_RG_LPF4_29(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_29)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_29)) & 0xffffe000))
+#define SET_RG_LPF4_30(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_30)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_30)) & 0xffffe000))
+#define SET_RG_LPF4_31(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_31)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_31)) & 0xffffe000))
+#define SET_RG_LPF4_32(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_32)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_32)) & 0xffffe000))
+#define SET_RG_LPF4_33(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_33)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_33)) & 0xffffe000))
+#define SET_RG_LPF4_34(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_34)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_34)) & 0xffffe000))
+#define SET_RG_LPF4_35(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_35)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_35)) & 0xffffe000))
+#define SET_RG_LPF4_36(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_36)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_36)) & 0xffffe000))
+#define SET_RG_LPF4_37(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_37)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_37)) & 0xffffe000))
+#define SET_RG_LPF4_38(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_38)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_38)) & 0xffffe000))
+#define SET_RG_LPF4_39(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_39)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_39)) & 0xffffe000))
+#define SET_RG_LPF4_40(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_40)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_40)) & 0xffffe000))
+#define SET_RG_BP_SMB(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 13) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffdfff))
+#define SET_RG_EN_SRVC(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 14) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffbfff))
+#define SET_RG_DES_SPD(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 16) | ((REG32(ADR_TX_11B_PLCP)) & 0xfffcffff))
+#define SET_RG_BB_11B_RISE_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_RAMP)) & 0xffffff00))
+#define SET_RG_BB_11B_FALL_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11B_RAMP)) & 0xffff00ff))
+#define SET_RG_WR_TX_EN_CNT_RST_N(_VAL_) (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0xfffffffe))
+#define SET_RO_TX_EN_CNT(_VAL_) (REG32(ADR_TX_11B_EN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT)) & 0xffff0000))
+#define SET_RO_TX_CNT(_VAL_) (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0x00000000))
+#define SET_RG_POS_DES_11B_L_EXT(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xfffffff0))
+#define SET_RG_PRE_DES_11B_DLY(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xffffff0f))
+#define SET_RG_CNT_CCA_LMT(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_0)) & 0xfff0ffff))
+#define SET_RG_BYPASS_DESCRAMBLER(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11B_CCA_0)) & 0xdfffffff))
+#define SET_RG_BYPASS_AGC(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11B_CCA_0)) & 0x7fffffff))
+#define SET_RG_CCA_BIT_CNT_LMT_RX(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CCA_1)) & 0xffffff0f))
+#define SET_RG_CCA_SCALE_BF(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_1)) & 0xff80ffff))
+#define SET_RG_PEAK_IDX_CNT_SEL(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11B_CCA_1)) & 0xcfffffff))
+#define SET_RG_TR_KI_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffffff8))
+#define SET_RG_TR_KP_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffffff8f))
+#define SET_RG_TR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffff8ff))
+#define SET_RG_TR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffff8fff))
+#define SET_RG_CR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xfff8ffff))
+#define SET_RG_CR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xff8fffff))
+#define SET_RG_CHIP_CNT_SLICER(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffffffe0))
+#define SET_RG_CE_T4_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffff00ff))
+#define SET_RG_CE_T3_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff00ffff))
+#define SET_RG_CE_T2_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ffffff))
+#define SET_RG_CE_MU_T1(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xfffffff8))
+#define SET_RG_CE_DLY_SEL(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xffc0ffff))
+#define SET_RG_CE_MU_T8(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffffff8))
+#define SET_RG_CE_MU_T7(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffffff8f))
+#define SET_RG_CE_MU_T6(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffff8ff))
+#define SET_RG_CE_MU_T5(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffff8fff))
+#define SET_RG_CE_MU_T4(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfff8ffff))
+#define SET_RG_CE_MU_T3(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xff8fffff))
+#define SET_RG_CE_MU_T2(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xf8ffffff))
+#define SET_RG_EQ_MU_FB_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfffffff0))
+#define SET_RG_EQ_MU_FF_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xffffff0f))
+#define SET_RG_EQ_MU_FB_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfff0ffff))
+#define SET_RG_EQ_MU_FF_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xff0fffff))
+#define SET_RG_EQ_MU_FB_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfffffff0))
+#define SET_RG_EQ_MU_FF_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xffffff0f))
+#define SET_RG_EQ_MU_FB_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfff0ffff))
+#define SET_RG_EQ_MU_FF_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xff0fffff))
+#define SET_RG_EQ_KI_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfffff8ff))
+#define SET_RG_EQ_KP_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xffff8fff))
+#define SET_RG_EQ_KI_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfff8ffff))
+#define SET_RG_EQ_KP_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xff8fffff))
+#define SET_RG_TR_LPF_RATE(_VAL_) (REG32(ADR_RX_11B_LPF_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_LPF_RATE)) & 0xffc00000))
+#define SET_RG_CE_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff80))
+#define SET_RG_CE_CH_MAIN_SET(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff7f))
+#define SET_RG_TC_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffff80ff))
+#define SET_RG_CR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xff80ffff))
+#define SET_RG_TR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x80ffffff))
+#define SET_RG_EQ_MAIN_TAP_MAN(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xfffffffe))
+#define SET_RG_EQ_MAIN_TAP_COEF(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xf800ffff))
+#define SET_RG_PWRON_DLY_TH_11B(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xffffff00))
+#define SET_RG_SFD_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xff00ffff))
+#define SET_RG_CCA_PWR_TH_RX(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffff8000))
+#define SET_RG_CCA_PWR_CNT_TH(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffe0ffff))
+#define SET_B_FREQ_OS(_VAL_) (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0xfffff800))
+#define SET_B_SNR(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xffffff80))
+#define SET_B_RCPI(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xff80ffff))
+#define SET_CRC_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000))
+#define SET_SFD_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff))
+#define SET_B_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xffff0000))
+#define SET_PACKET_ERR(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xfffeffff))
+#define SET_B_PACKET_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
+#define SET_B_CCA_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
+#define SET_B_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000))
+#define SET_SFD_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff))
+#define SET_SIGNAL_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffffff00))
+#define SET_B_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffff00ff))
+#define SET_CRC_CORRECT(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xfffeffff))
+#define SET_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xfffffff0))
+#define SET_RG_PACKET_STAT_EN_11B(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffefffff))
+#define SET_RG_BIT_REVERSE(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffdfffff))
+#define SET_RX_PHY_11B_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffffffe))
+#define SET_RG_CE_BYPASS_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xffffff0f))
+#define SET_RG_EQ_BYPASS_FBW_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffff0ff))
+#define SET_RG_BB_11GN_RISE_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffffff00))
+#define SET_RG_BB_11GN_FALL_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffff00ff))
+#define SET_RG_HTCARR52_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP)) & 0xfffffc00))
+#define SET_RG_HTCARR56_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 12) | ((REG32(ADR_TX_11GN_PLCP)) & 0xffc00fff))
+#define SET_RG_PACKET_STAT_EN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 23) | ((REG32(ADR_TX_11GN_PLCP)) & 0xff7fffff))
+#define SET_RG_SMB_DEF(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 24) | ((REG32(ADR_TX_11GN_PLCP)) & 0x80ffffff))
+#define SET_RG_CONTINUOUS_DATA_11GN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 31) | ((REG32(ADR_TX_11GN_PLCP)) & 0x7fffffff))
+#define SET_RO_TX_CNT_R(_VAL_) (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0x00000000))
+#define SET_RO_PACKET_ERR_CNT(_VAL_) (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0xffff0000))
+#define SET_RG_POS_DES_11GN_L_EXT(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xfffffff0))
+#define SET_RG_PRE_DES_11GN_DLY(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xffffff0f))
+#define SET_RG_TR_LPF_KI_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffffff0f))
+#define SET_RG_TR_CNT_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffff00ff))
+#define SET_RG_TR_LPF_KI_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfff0ffff))
+#define SET_RG_TR_LPF_KP_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TR_0)) & 0xff0fffff))
+#define SET_RG_TR_CNT_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_TR_0)) & 0x00ffffff))
+#define SET_RG_TR_LPF_KI_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_1)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffffff0f))
+#define SET_RG_TR_CNT_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffff00ff))
+#define SET_RG_TR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_2)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_2)) & 0xffffff0f))
+#define SET_RG_TR_LPF_RATE_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_2)) & 0xc00000ff))
+#define SET_RG_CR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xfffffff8))
+#define SET_RG_SYM_BOUND_CNT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xffff80ff))
+#define SET_RG_XSCOR32_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xff80ffff))
+#define SET_RG_ATCOR64_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_0)) & 0x80ffffff))
+#define SET_RG_ATCOR16_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xffff80ff))
+#define SET_RG_ATCOR16_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xff80ffff))
+#define SET_RG_ATCOR16_RATIO_SB(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_1)) & 0x80ffffff))
+#define SET_RG_XSCOR64_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_2)) & 0xff80ffff))
+#define SET_RG_XSCOR64_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_2)) & 0x80ffffff))
+#define SET_RG_RX_FFT_SCALE(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffffc00))
+#define SET_RG_VITERBI_AB_SWAP(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffeffff))
+#define SET_RG_ATCOR16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xf0ffffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_LOW_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_LOW_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_3(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_SNR_2(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_SNR_1(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_SNR_0(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0x00ffffff))
+#define SET_RG_SNR_TH_64QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffffff80))
+#define SET_RG_SNR_TH_16QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffff80ff))
+#define SET_RG_ATCOR16_CNT_PLUS_LMT2(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffffff80))
+#define SET_RG_ATCOR16_CNT_PLUS_LMT1(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffff80ff))
+#define SET_RG_SYM_BOUND_METHOD(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xfffcffff))
+#define SET_RG_PWRON_DLY_TH_11GN(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffffff00))
+#define SET_RG_SB_START_CNT(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffff80ff))
+#define SET_RG_POW16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xffffff0f))
+#define SET_RG_POW16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xfffff8ff))
+#define SET_RG_POW16_TH_L(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0x80ffffff))
+#define SET_RG_XSCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfffffff8))
+#define SET_RG_XSCOR16_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xffff80ff))
+#define SET_RG_ATCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfff8ffff))
+#define SET_RG_ATCOR16_RATIO_CCD(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0x80ffffff))
+#define SET_RG_ATCOR64_ACC_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xffffff80))
+#define SET_RG_ATCOR16_SHORT_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xfff8ffff))
+#define SET_RG_VITERBI_TB_BITS(_VAL_) (REG32(ADR_RX_11GN_VTB_TB)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_VTB_TB)) & 0x00ffffff))
+#define SET_RG_CR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xffffff00))
+#define SET_RG_TR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xff00ffff))
+#define SET_RG_BYPASS_CPE_MA(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffffffef))
+#define SET_RG_PILOT_BNDRY_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfffff8ff))
+#define SET_RG_EQ_SHORT_GI_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffff8fff))
+#define SET_RG_FFT_WDW_SHORT_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfff8ffff))
+#define SET_RG_CHSMTH_COEF(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffcffff))
+#define SET_RG_CHSMTH_EN(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 18) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffbffff))
+#define SET_RG_CHEST_DD_FACTOR(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xf8ffffff))
+#define SET_RG_CH_UPDATE(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x7fffffff))
+#define SET_RG_FMT_DET_MM_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffffff00))
+#define SET_RG_FMT_DET_GF_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffff00ff))
+#define SET_RG_DO_NOT_CHECK_L_RATE(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xfdffffff))
+#define SET_RG_FMT_DET_LENGTH_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000))
+#define SET_RG_L_LENGTH_MAX(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff))
+#define SET_RG_TX_TIME_EXT(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xffffff00))
+#define SET_RG_MAC_DES_SPACE(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xff0fffff))
+#define SET_RG_TR_LPF_STBC_GF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffffff0))
+#define SET_RG_TR_LPF_STBC_GF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffffff0f))
+#define SET_RG_TR_LPF_STBC_MF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffff0ff))
+#define SET_RG_TR_LPF_STBC_MF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffff0fff))
+#define SET_RG_MODE_REG_IN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfffe0000))
+#define SET_RG_PARALLEL_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xffefffff))
+#define SET_RG_MBRUN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_0)) & 0x7fffffff))
+#define SET_RG_MODE_REG_IN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffff0000))
+#define SET_RG_PARALLEL_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffefffff))
+#define SET_RG_MBRUN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_1)) & 0x7fffffff))
+#define SET_RO_MODE_REG_OUT_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfffe0000))
+#define SET_RO_MODE_REG_SO_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_80(_VAL_) (REG32(ADR_RX_11GN_BIST_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_3)) & 0xffc00000))
+#define SET_RO_MODE_REG_OUT_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xffff0000))
+#define SET_RO_MODE_REG_SO_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_64(_VAL_) (REG32(ADR_RX_11GN_BIST_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_5)) & 0xfff80000))
+#define SET_RO_SPECTRUM_DATA(_VAL_) (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0x00000000))
+#define SET_GN_SNR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffffff80))
+#define SET_GN_NOISE_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffff80ff))
+#define SET_GN_RCPI(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_READ_0)) & 0xff80ffff))
+#define SET_GN_SIGNAL_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_READ_0)) & 0x80ffffff))
+#define SET_RO_FREQ_OS_LTS(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xffff8000))
+#define SET_CSTATE(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xfff0ffff))
+#define SET_SIGNAL_FIELD0(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0xff000000))
+#define SET_SIGNAL_FIELD1(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0xff000000))
+#define SET_GN_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0xffff0000))
+#define SET_GN_PACKET_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
+#define SET_GN_CCA_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
+#define SET_GN_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000))
+#define SET_GN_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff))
+#define SET_RO_HT_MCS_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffff80))
+#define SET_RO_L_RATE_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffc0ff))
+#define SET_RG_DAGC_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xfffffffc))
+#define SET_RG_PACKET_STAT_EN_11GN(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xffefffff))
+#define SET_RX_PHY_11GN_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffe))
+#define SET_RG_RIFS_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 1) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffd))
+#define SET_RG_STBC_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 2) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffb))
+#define SET_RG_COR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 3) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffff7))
+#define SET_RG_INI_PHASE(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffcf))
+#define SET_RG_HT_LTF_SEL_EQ(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 6) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffbf))
+#define SET_RG_HT_LTF_SEL_PILOT(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffff7f))
+#define SET_RG_CCA_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 9) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffdff))
+#define SET_RG_CCA_XSCOR_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 10) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffbff))
+#define SET_RG_CCA_XSCOR_AVGPWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 11) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffff7ff))
+#define SET_RG_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffff0fff))
+#define SET_RG_POST_CLK_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffeffff))
+#define SET_IQCAL_RF_TX_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffe))
+#define SET_IQCAL_RF_TX_PA_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 1) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffd))
+#define SET_IQCAL_RF_TX_DAC_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 2) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffb))
+#define SET_IQCAL_RF_RX_AGC(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 3) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffff7))
+#define SET_IQCAL_RF_PGAG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffff0ff))
+#define SET_IQCAL_RF_RFG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 12) | ((REG32(ADR_RF_CONTROL_0)) & 0xffffcfff))
+#define SET_RG_TONEGEN_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_CONTROL_0)) & 0xff80ffff))
+#define SET_RG_TONEGEN_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 23) | ((REG32(ADR_RF_CONTROL_0)) & 0xff7fffff))
+#define SET_RG_TONEGEN_INIT_PH(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_CONTROL_0)) & 0x80ffffff))
+#define SET_RG_TONEGEN2_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff80))
+#define SET_RG_TONEGEN2_EN(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 7) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff7f))
+#define SET_RG_TONEGEN2_SCALE(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_1)) & 0xffff00ff))
+#define SET_RG_TXIQ_CLP_THD_I(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfffffc00))
+#define SET_RG_TXIQ_CLP_THD_Q(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfc00ffff))
+#define SET_RG_TX_I_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffffff00))
+#define SET_RG_TX_Q_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffff00ff))
+#define SET_RG_TX_IQ_SWP(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffeffff))
+#define SET_RG_TX_SGN_OUT(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 17) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffdffff))
+#define SET_RG_TXIQ_EMU_IDX(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 18) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffc3ffff))
+#define SET_RG_TX_IQ_SRC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfcffffff))
+#define SET_RG_TX_I_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfffffc00))
+#define SET_RG_TX_Q_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfc00ffff))
+#define SET_RG_TX_IQ_THETA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffffe0))
+#define SET_RG_TX_IQ_ALPHA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffe0ff))
+#define SET_RG_TXIQ_NOSHRINK(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffdfff))
+#define SET_RG_TX_I_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff00ffff))
+#define SET_RG_TX_Q_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 24) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ffffff))
+#define SET_RG_RX_IQ_THETA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffffe0))
+#define SET_RG_RX_IQ_ALPHA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffe0ff))
+#define SET_RG_RXIQ_NOSHRINK(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffdfff))
+#define SET_RG_MA_DPTH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffff0))
+#define SET_RG_INTG_PH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffc0f))
+#define SET_RG_INTG_PRD(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 10) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffffe3ff))
+#define SET_RG_INTG_MU(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 13) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffff9fff))
+#define SET_RG_IQCAL_SPRM_SELQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffeffff))
+#define SET_RG_IQCAL_SPRM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 17) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffdffff))
+#define SET_RG_IQCAL_SPRM_FREQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 18) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xff03ffff))
+#define SET_RG_IQCAL_IQCOL_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfeffffff))
+#define SET_RG_IQCAL_ALPHA_ESTM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfdffffff))
+#define SET_RG_IQCAL_DC_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfbffffff))
+#define SET_RG_PHEST_STBY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xf7ffffff))
+#define SET_RG_PHEST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xefffffff))
+#define SET_RG_GP_DIV_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xdfffffff))
+#define SET_RG_DPD_GAIN_EST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xbfffffff))
+#define SET_RG_IQCAL_MULT_OP0(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfffffc00))
+#define SET_RG_IQCAL_MULT_OP1(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfc00ffff))
+#define SET_RO_IQCAL_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfff00000))
+#define SET_RO_IQCAL_SPRM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 20) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffefffff))
+#define SET_RO_IQCAL_IQCOL_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 21) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffdfffff))
+#define SET_RO_IQCAL_ALPHA_ESTM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 22) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffbfffff))
+#define SET_RO_IQCAL_DC_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 23) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xff7fffff))
+#define SET_RO_IQCAL_MULT_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfeffffff))
+#define SET_RO_FFT_ENRG_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfdffffff))
+#define SET_RO_PHEST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfbffffff))
+#define SET_RO_GP_DIV_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xf7ffffff))
+#define SET_RO_GAIN_EST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xefffffff))
+#define SET_RO_AMP_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0xfffffe00))
+#define SET_RG_RX_I_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffffff00))
+#define SET_RG_RX_Q_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffff00ff))
+#define SET_RG_RX_I_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff00ffff))
+#define SET_RG_RX_Q_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ffffff))
+#define SET_RG_RX_IQ_SWP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffe))
+#define SET_RG_RX_SGN_IN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffd))
+#define SET_RG_RX_IQ_SRC(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 2) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffff3))
+#define SET_RG_ACI_GAIN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffff00f))
+#define SET_RG_FFT_EN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 12) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffefff))
+#define SET_RG_FFT_MOD(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 13) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffdfff))
+#define SET_RG_FFT_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 14) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xff003fff))
+#define SET_RG_FFT_ENRG_FREQ(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xc0ffffff))
+#define SET_RG_FPGA_80M_PH_UP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 30) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xbfffffff))
+#define SET_RG_FPGA_80M_PH_STP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 31) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0x7fffffff))
+#define SET_RG_ADC2LA_SEL(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffe))
+#define SET_RG_ADC2LA_CLKPH(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffd))
+#define SET_RG_RXIQ_EMU_IDX(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xfffffff0))
+#define SET_RG_IQCAL_BP_ACI(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xffffffef))
+#define SET_RG_DPD_AM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffe))
+#define SET_RG_DPD_PM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffd))
+#define SET_RG_DPD_PM_AMSEL(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffb))
+#define SET_RG_DPD_020_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfffffc00))
+#define SET_RG_DPD_040_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfc00ffff))
+#define SET_RG_DPD_060_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfffffc00))
+#define SET_RG_DPD_080_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfc00ffff))
+#define SET_RG_DPD_0A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfffffc00))
+#define SET_RG_DPD_0C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfc00ffff))
+#define SET_RG_DPD_0D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfffffc00))
+#define SET_RG_DPD_0E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfc00ffff))
+#define SET_RG_DPD_0F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfffffc00))
+#define SET_RG_DPD_100_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfc00ffff))
+#define SET_RG_DPD_110_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfffffc00))
+#define SET_RG_DPD_120_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfc00ffff))
+#define SET_RG_DPD_130_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfffffc00))
+#define SET_RG_DPD_140_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfc00ffff))
+#define SET_RG_DPD_150_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfffffc00))
+#define SET_RG_DPD_160_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfc00ffff))
+#define SET_RG_DPD_170_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfffffc00))
+#define SET_RG_DPD_180_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfc00ffff))
+#define SET_RG_DPD_190_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfffffc00))
+#define SET_RG_DPD_1A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfc00ffff))
+#define SET_RG_DPD_1B0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfffffc00))
+#define SET_RG_DPD_1C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfc00ffff))
+#define SET_RG_DPD_1D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfffffc00))
+#define SET_RG_DPD_1E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfc00ffff))
+#define SET_RG_DPD_1F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfffffc00))
+#define SET_RG_DPD_200_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfc00ffff))
+#define SET_RG_DPD_020_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xffffe000))
+#define SET_RG_DPD_040_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xe000ffff))
+#define SET_RG_DPD_060_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xffffe000))
+#define SET_RG_DPD_080_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xe000ffff))
+#define SET_RG_DPD_0A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xffffe000))
+#define SET_RG_DPD_0C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xe000ffff))
+#define SET_RG_DPD_0D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xffffe000))
+#define SET_RG_DPD_0E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xe000ffff))
+#define SET_RG_DPD_0F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xffffe000))
+#define SET_RG_DPD_100_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xe000ffff))
+#define SET_RG_DPD_110_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xffffe000))
+#define SET_RG_DPD_120_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xe000ffff))
+#define SET_RG_DPD_130_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xffffe000))
+#define SET_RG_DPD_140_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xe000ffff))
+#define SET_RG_DPD_150_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xffffe000))
+#define SET_RG_DPD_160_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xe000ffff))
+#define SET_RG_DPD_170_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xffffe000))
+#define SET_RG_DPD_180_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xe000ffff))
+#define SET_RG_DPD_190_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xffffe000))
+#define SET_RG_DPD_1A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xe000ffff))
+#define SET_RG_DPD_1B0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xffffe000))
+#define SET_RG_DPD_1C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xe000ffff))
+#define SET_RG_DPD_1D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xffffe000))
+#define SET_RG_DPD_1E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xe000ffff))
+#define SET_RG_DPD_1F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xffffe000))
+#define SET_RG_DPD_200_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xe000ffff))
+#define SET_RG_DPD_GAIN_EST_Y0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfffffe00))
+#define SET_RG_DPD_GAIN_EST_Y1(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfe00ffff))
+#define SET_RG_DPD_LOOP_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0xfffffc00))
+#define SET_RG_DPD_GAIN_EST_X0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfffffe00))
+#define SET_RO_DPD_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfc00ffff))
+#define SET_TX_SCALE_11B(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffffff00))
+#define SET_TX_SCALE_11B_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 8) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffff00ff))
+#define SET_TX_SCALE_11G(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xff00ffff))
+#define SET_TX_SCALE_11G_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 24) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ffffff))
+#define SET_RG_EN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
+#define SET_RG_TX_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
+#define SET_RG_TX_PA_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
+#define SET_RG_TX_DAC_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
+#define SET_RG_RX_AGC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
+#define SET_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
+#define SET_RG_RFG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
+#define SET_RG_PGAG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
+#define SET_RG_MODE(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
+#define SET_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
+#define SET_RG_EN_SX(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
+#define SET_RG_EN_RX_LNA(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
+#define SET_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
+#define SET_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
+#define SET_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
+#define SET_RG_EN_RX_TZ(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
+#define SET_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
+#define SET_RG_EN_RX_HPF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
+#define SET_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
+#define SET_RG_EN_ADC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
+#define SET_RG_EN_TX_MOD(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
+#define SET_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
+#define SET_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
+#define SET_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
+#define SET_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
+#define SET_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
+#define SET_RG_EN_CLK_960MBY13_UART(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x7fffffff))
+#define SET_RG_EN_TX_DPD(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
+#define SET_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
+#define SET_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
+#define SET_RG_EN_IREF_RX(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_RG_EN_TX_DAC_VOUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffdfff))
+#define SET_RG_EN_SX_LCK_BIN(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffbfff))
+#define SET_RG_RTC_CAL_MODE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffeffff))
+#define SET_RG_EN_IQPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffdffff))
+#define SET_RG_EN_TESTPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffbffff))
+#define SET_RG_EN_TRXBF_BYPASS(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfff7ffff))
+#define SET_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffff8))
+#define SET_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_LDO_REGISTER)) & 0xffffffc7))
+#define SET_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffe3f))
+#define SET_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_LDO_REGISTER)) & 0xfffff1ff))
+#define SET_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_LDO_REGISTER)) & 0xffff8fff))
+#define SET_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_LDO_REGISTER)) & 0xfffc7fff))
+#define SET_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_LDO_REGISTER)) & 0xffe3ffff))
+#define SET_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_LDO_REGISTER)) & 0xff1fffff))
+#define SET_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_LDO_REGISTER)) & 0xf8ffffff))
+#define SET_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffe))
+#define SET_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffd))
+#define SET_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffb))
+#define SET_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffe07))
+#define SET_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffdff))
+#define SET_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffbff))
+#define SET_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffff7ff))
+#define SET_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffffcfff))
+#define SET_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffff3fff))
+#define SET_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffcffff))
+#define SET_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfff3ffff))
+#define SET_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffcfffff))
+#define SET_RG_RX_HPF3M(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffbfffff))
+#define SET_RG_RX_HPF300K(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_1)) & 0xff7fffff))
+#define SET_RG_RX_HPFI(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfcffffff))
+#define SET_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_ABB_REGISTER_1)) & 0xf3ffffff))
+#define SET_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_ABB_REGISTER_1)) & 0xcfffffff))
+#define SET_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffffc))
+#define SET_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffff3))
+#define SET_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffffcf))
+#define SET_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffff3f))
+#define SET_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffcff))
+#define SET_RG_RX_OUTVCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffff3ff))
+#define SET_RG_RX_TZI(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffcfff))
+#define SET_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffbfff))
+#define SET_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffe7fff))
+#define SET_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfff1ffff))
+#define SET_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffefffff))
+#define SET_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_ABB_REGISTER_2)) & 0xff9fffff))
+#define SET_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfe7fffff))
+#define SET_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfdffffff))
+#define SET_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffffffc))
+#define SET_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffff03))
+#define SET_RG_TXPGA_STEER(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffc0ff))
+#define SET_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffff3fff))
+#define SET_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffcffff))
+#define SET_RG_PACELL_EN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffe3ffff))
+#define SET_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfe1fffff))
+#define SET_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_TX_FE_REGISTER)) & 0xf3ffffff))
+#define SET_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_TX_FE_REGISTER)) & 0xcfffffff))
+#define SET_RG_RX_SQDC(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffffff8))
+#define SET_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffffe7))
+#define SET_RG_RX_LOBUF(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffff9f))
+#define SET_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffff87f))
+#define SET_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffff87ff))
+#define SET_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffc7fff))
+#define SET_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffe3ffff))
+#define SET_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffdfffff))
+#define SET_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xff3fffff))
+#define SET_RG_PACASCODE_CTRL(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xf8ffffff))
+#define SET_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
+#define SET_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
+#define SET_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
+#define SET_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
+#define SET_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
+#define SET_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
+#define SET_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
+#define SET_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
+#define SET_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
+#define SET_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
+#define SET_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
+#define SET_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
+#define SET_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
+#define SET_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
+#define SET_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
+#define SET_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
+#define SET_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
+#define SET_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
+#define SET_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
+#define SET_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
+#define SET_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
+#define SET_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
+#define SET_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
+#define SET_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
+#define SET_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffe))
+#define SET_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffd))
+#define SET_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffb))
+#define SET_RG_HPF_T1A(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffffe7))
+#define SET_RG_HPF_T1B(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffff9f))
+#define SET_RG_HPF_T1C(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffe7f))
+#define SET_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffff9ff))
+#define SET_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffe7ff))
+#define SET_RG_TXGAIN_PHYCTRL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffdfff))
+#define SET_RG_TX_GAIN(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffc03fff))
+#define SET_RG_TXGAIN_MANUAL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffbfffff))
+#define SET_RG_TX_GAIN_OFFSET(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xf87fffff))
+#define SET_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffffe))
+#define SET_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff9))
+#define SET_RG_ADC_DIVR(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff7))
+#define SET_RG_ADC_DVCMI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffffffcf))
+#define SET_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffc3f))
+#define SET_RG_ADC_STNBY(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffbff))
+#define SET_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffff7ff))
+#define SET_RG_ADC_TSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffff0fff))
+#define SET_RG_ADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffcffff))
+#define SET_RG_DICMP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfff3ffff))
+#define SET_RG_DIOP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffcfffff))
+#define SET_RG_SARADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xff3fffff))
+#define SET_RG_EN_SAR_TEST(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfcffffff))
+#define SET_RG_SARADC_THERMAL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfbffffff))
+#define SET_RG_SARADC_TSSI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xf7ffffff))
+#define SET_RG_CLK_SAR_SEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xcfffffff))
+#define SET_RG_EN_SARADC(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xbfffffff))
+#define SET_RG_DACI1ST(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffffc))
+#define SET_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffff3))
+#define SET_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffffcf))
+#define SET_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffff3f))
+#define SET_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffeff))
+#define SET_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffff9ff))
+#define SET_RG_TX_DAC_OS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffc7ff))
+#define SET_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffff3fff))
+#define SET_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfff0ffff))
+#define SET_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffefffff))
+#define SET_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffdfffff))
+#define SET_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffbfffff))
+#define SET_RG_TX_DAC_IOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xf87fffff))
+#define SET_RG_TX_DAC_QOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_TX_DAC_REGISTER)) & 0x87ffffff))
+#define SET_RG_EN_SX_R3(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_RG_EN_SX_CH(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_RG_EN_SX_CHP(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_RG_EN_SX_VCO(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_RG_EN_SX_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffefff))
+#define SET_RG_EN_SX_DIV(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffdfff))
+#define SET_RG_EN_SX_LPF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffbfff))
+#define SET_RG_EN_DPL_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffff7fff))
+#define SET_RG_DPL_MOD_ORDER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffcffff))
+#define SET_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_1)) & 0xff000000))
+#define SET_RG_SX_SEL_CP(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_REGISTER_1)) & 0xf0ffffff))
+#define SET_RG_SX_SEL_CS(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_REGISTER_1)) & 0x0fffffff))
+#define SET_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfffff800))
+#define SET_RG_SX_SEL_C3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_REGISTER_2)) & 0xffff87ff))
+#define SET_RG_SX_SEL_RS(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfff07fff))
+#define SET_RG_SX_SEL_R3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfe0fffff))
+#define SET_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffffe0))
+#define SET_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffffc1f))
+#define SET_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffc3ff))
+#define SET_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffc3fff))
+#define SET_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffbffff))
+#define SET_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffc7ffff))
+#define SET_RG_SX_PFDSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffbfffff))
+#define SET_RG_SX_PFD_SET(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_SYN_PFD_CHP)) & 0xff7fffff))
+#define SET_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfeffffff))
+#define SET_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfdffffff))
+#define SET_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfbffffff))
+#define SET_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_SYN_PFD_CHP)) & 0xf7ffffff))
+#define SET_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_PFD_CHP)) & 0xefffffff))
+#define SET_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_SYN_PFD_CHP)) & 0xdfffffff))
+#define SET_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_SYN_PFD_CHP)) & 0xbfffffff))
+#define SET_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffffff8))
+#define SET_RG_SX_VCORSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffffff07))
+#define SET_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffff0ff))
+#define SET_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffff0fff))
+#define SET_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfff0ffff))
+#define SET_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xff0fffff))
+#define SET_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xf0ffffff))
+#define SET_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_VCO_LOBF)) & 0x0fffffff))
+#define SET_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
+#define SET_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
+#define SET_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
+#define SET_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
+#define SET_RG_SX_XO_GM(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
+#define SET_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
+#define SET_RG_SX_LCKEN(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
+#define SET_RG_SX_PREVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
+#define SET_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
+#define SET_RG_SX_PH(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffdfff))
+#define SET_RG_SX_PL(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffbfff))
+#define SET_RG_XOSC_CBANK_XO(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xfff87fff))
+#define SET_RG_XOSC_CBANK_XI(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xff87ffff))
+#define SET_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffffe))
+#define SET_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 1) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffff9))
+#define SET_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffe7))
+#define SET_RG_SX_VT_SET(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffdf))
+#define SET_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 6) | ((REG32(ADR_SYN_LCK_VT)) & 0xffff803f))
+#define SET_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffffe))
+#define SET_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffff9))
+#define SET_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffffe7))
+#define SET_RG_DP_CK320BY2(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffbfff))
+#define SET_RG_DP_OD_TEST(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffdfffff))
+#define SET_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
+#define SET_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
+#define SET_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
+#define SET_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
+#define SET_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
+#define SET_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
+#define SET_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
+#define SET_RG_DP_RP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
+#define SET_RG_DP_RHP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
+#define SET_RG_DP_BBPLL_SDM_EDGE(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x7fffffff))
+#define SET_RG_DP_FODIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xfff80fff))
+#define SET_RG_DP_REFDIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xe03fffff))
+#define SET_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
+#define SET_RG_DP_BBPLL_BS(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 24) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xc0ffffff))
+#define SET_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
+#define SET_RG_EN_RCAL(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffe))
+#define SET_RG_RCAL_SPD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffd))
+#define SET_RG_RCAL_TMR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffe03))
+#define SET_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffdff))
+#define SET_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RCAL_REGISTER)) & 0xffff83ff))
+#define SET_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfffffffe))
+#define SET_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 1) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffffff01))
+#define SET_RG_SX_LCK_BIN_OFFSET(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff87fff))
+#define SET_RG_SX_LCK_BIN_PRECISION(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 19) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff7ffff))
+#define SET_RG_SX_LOCK_EN_N(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 20) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffefffff))
+#define SET_RG_SX_LOCK_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 21) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffdfffff))
+#define SET_RG_SX_SUB_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 22) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffbfffff))
+#define SET_RG_SX_SUB_SEL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xc07fffff))
+#define SET_RG_SX_MUX_SEL_VTH_BINL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 30) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xbfffffff))
+#define SET_RG_TRX_DUMMMY(_VAL_) (REG32(ADR_TRX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_DUMMY_REGISTER)) & 0x00000000))
+#define SET_RG_SX_DUMMMY(_VAL_) (REG32(ADR_SX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_DUMMY_REGISTER)) & 0x00000000))
+#define SET_RCAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
+#define SET_LCK_BIN_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
+#define SET_VT_MON_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
+#define SET_DA_R_CODE_LUT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
+#define SET_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
+#define SET_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
+#define SET_RTC_CAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 15) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff7fff))
+#define SET_RG_SARADC_BIT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 16) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffc0ffff))
+#define SET_SAR_ADC_FSM_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 22) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffbfffff))
+#define SET_AD_CIRCUIT_VERSION(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 23) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xf87fffff))
+#define SET_DA_R_CAL_CODE(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
+#define SET_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
+#define SET_RG_DPL_RFCTRL_CH(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xfffff800))
+#define SET_RG_RSSIADC_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 11) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xffff87ff))
+#define SET_RG_RX_ADC_I_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xff807fff))
+#define SET_RG_RX_ADC_Q_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x807fffff))
+#define SET_RG_DPL_RFCTRL_F(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0xff000000))
+#define SET_RG_SX_TARGET_CNT(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0xffffe000))
+#define SET_RG_RTC_OFFSET(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 0) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xffffff00))
+#define SET_RG_RTC_CAL_TARGET_COUNT(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 8) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xfff000ff))
+#define SET_RG_RF_D_REG(_VAL_) (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0xffff0000))
+#define SET_DIRECT_MODE(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffe))
+#define SET_TAG_INTERLEAVE_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffd))
+#define SET_DIS_DEMAND(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffb))
+#define SET_SAME_ID_ALLOC_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_MMU_CTRL)) & 0xfffffff7))
+#define SET_HS_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_MMU_CTRL)) & 0xffffffef))
+#define SET_SRAM_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 5) | ((REG32(ADR_MMU_CTRL)) & 0xffffffdf))
+#define SET_NOHIT_RPASS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 6) | ((REG32(ADR_MMU_CTRL)) & 0xffffffbf))
+#define SET_DMN_FLAG_CLR(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_MMU_CTRL)) & 0xffffff7f))
+#define SET_ERR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_CTRL)) & 0xfffffeff))
+#define SET_ALR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_MMU_CTRL)) & 0xfffffdff))
+#define SET_MCH_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_MMU_CTRL)) & 0xfffffbff))
+#define SET_TAG_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_MMU_CTRL)) & 0xfffff7ff))
+#define SET_ABT_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_CTRL)) & 0xffffefff))
+#define SET_MMU_VER(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_MMU_CTRL)) & 0xffff1fff))
+#define SET_MMU_SHARE_MCU(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_CTRL)) & 0xff00ffff))
+#define SET_HS_WR(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_HS_CTRL)) & 0xfffffffe))
+#define SET_HS_FLAG(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_HS_CTRL)) & 0xffffffef))
+#define SET_HS_ID(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_HS_CTRL)) & 0xffff80ff))
+#define SET_HS_CHANNEL(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_HS_CTRL)) & 0xfff0ffff))
+#define SET_HS_PAGE(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 20) | ((REG32(ADR_HS_CTRL)) & 0xff0fffff))
+#define SET_HS_DATA(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 24) | ((REG32(ADR_HS_CTRL)) & 0x00ffffff))
+#define SET_CPU_POR0(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR0_7)) & 0xfffffff0))
+#define SET_CPU_POR1(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR0_7)) & 0xffffff0f))
+#define SET_CPU_POR2(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR0_7)) & 0xfffff0ff))
+#define SET_CPU_POR3(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR0_7)) & 0xffff0fff))
+#define SET_CPU_POR4(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR0_7)) & 0xfff0ffff))
+#define SET_CPU_POR5(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR0_7)) & 0xff0fffff))
+#define SET_CPU_POR6(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR0_7)) & 0xf0ffffff))
+#define SET_CPU_POR7(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR0_7)) & 0x0fffffff))
+#define SET_CPU_POR8(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR8_F)) & 0xfffffff0))
+#define SET_CPU_POR9(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR8_F)) & 0xffffff0f))
+#define SET_CPU_PORA(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR8_F)) & 0xfffff0ff))
+#define SET_CPU_PORB(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR8_F)) & 0xffff0fff))
+#define SET_CPU_PORC(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR8_F)) & 0xfff0ffff))
+#define SET_CPU_PORD(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR8_F)) & 0xff0fffff))
+#define SET_CPU_PORE(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR8_F)) & 0xf0ffffff))
+#define SET_CPU_PORF(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR8_F)) & 0x0fffffff))
+#define SET_ACC_WR_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffffc0))
+#define SET_ACC_RD_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffc0ff))
+#define SET_REQ_NACK_CLR(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 15) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffff7fff))
+#define SET_NACK_FLAG_BUS(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_REG_LEN_CTRL)) & 0x0000ffff))
+#define SET_DMN_R_PASS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xffff0000))
+#define SET_PARA_ALC_RLS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfffeffff))
+#define SET_REQ_PORNS_CHGEN(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 24) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfeffffff))
+#define SET_ALC_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffffff80))
+#define SET_ALC_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffff7fff))
+#define SET_RLS_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xff80ffff))
+#define SET_RLS_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_RLS_ABORT)) & 0x7fffffff))
+#define SET_DEBUG_CTL(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_CTL)) & 0xffffff00))
+#define SET_DEBUG_H16(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_DEBUG_CTL)) & 0xfffffeff))
+#define SET_DEBUG_OUT(_VAL_) (REG32(ADR_DEBUG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_OUT)) & 0x00000000))
+#define SET_ALC_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffe))
+#define SET_RLS_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffd))
+#define SET_AL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_STATUS)) & 0xfffff8ff))
+#define SET_RL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_STATUS)) & 0xffff8fff))
+#define SET_ALC_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_STATUS)) & 0xff80ffff))
+#define SET_RLS_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MMU_STATUS)) & 0x80ffffff))
+#define SET_DMN_NOHIT_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffe))
+#define SET_DMN_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffd))
+#define SET_DMN_WR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_STATUS)) & 0xfffffff7))
+#define SET_DMN_PORT(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_STATUS)) & 0xffffff0f))
+#define SET_DMN_NHIT_ID(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_STATUS)) & 0xffff80ff))
+#define SET_DMN_NHIT_ADDR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_STATUS)) & 0x0000ffff))
+#define SET_TX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_STATUS)) & 0xffffff00))
+#define SET_RX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TAG_STATUS)) & 0xffff00ff))
+#define SET_AVA_TAG(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_STATUS)) & 0xfe00ffff))
+#define SET_PKTBUF_FULL(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 31) | ((REG32(ADR_TAG_STATUS)) & 0x7fffffff))
+#define SET_DMN_NOHIT_MCU(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffe))
+#define SET_DMN_MCU_FLAG(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffd))
+#define SET_DMN_MCU_WR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffff7))
+#define SET_DMN_MCU_PORT(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffffff0f))
+#define SET_DMN_MCU_ID(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffff80ff))
+#define SET_DMN_MCU_ADDR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_MCU_STATUS)) & 0x0000ffff))
+#define SET_MB_IDTBL_31_0(_VAL_) (REG32(ADR_MB_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_63_32(_VAL_) (REG32(ADR_MB_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_95_64(_VAL_) (REG32(ADR_MB_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_127_96(_VAL_) (REG32(ADR_MB_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_31_0(_VAL_) (REG32(ADR_PKT_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_63_32(_VAL_) (REG32(ADR_PKT_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_95_64(_VAL_) (REG32(ADR_PKT_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_127_96(_VAL_) (REG32(ADR_PKT_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_31_0(_VAL_) (REG32(ADR_DMN_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_63_32(_VAL_) (REG32(ADR_DMN_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_95_64(_VAL_) (REG32(ADR_DMN_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_127_96(_VAL_) (REG32(ADR_DMN_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_31_0(_VAL_) (REG32(ADR_MB_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_0_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_63_32(_VAL_) (REG32(ADR_MB_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_1_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_95_64(_VAL_) (REG32(ADR_MB_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_2_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_127_96(_VAL_) (REG32(ADR_MB_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_3_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_31_0(_VAL_) (REG32(ADR_PKT_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_0_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_63_32(_VAL_) (REG32(ADR_PKT_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_1_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_95_64(_VAL_) (REG32(ADR_PKT_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_2_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_127_96(_VAL_) (REG32(ADR_PKT_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_3_STATUS)) & 0x00000000))
+#define SET_ALC_NOCHG_ID(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffffff80))
+#define SET_ALC_NOCHG_INT(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffff7fff))
+#define SET_NEQ_PKT_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfffeffff))
+#define SET_NEQ_MB_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfeffffff))
+#define SET_SRAM_TAG_0(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000))
+#define SET_SRAM_TAG_1(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff))
+#define SET_SRAM_TAG_2(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000))
+#define SET_SRAM_TAG_3(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff))
+#define SET_SRAM_TAG_4(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000))
+#define SET_SRAM_TAG_5(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff))
+#define SET_SRAM_TAG_6(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000))
+#define SET_SRAM_TAG_7(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff))
+#define SET_SRAM_TAG_8(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000))
+#define SET_SRAM_TAG_9(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff))
+#define SET_SRAM_TAG_10(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000))
+#define SET_SRAM_TAG_11(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff))
+#define SET_SRAM_TAG_12(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000))
+#define SET_SRAM_TAG_13(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff))
+#define SET_SRAM_TAG_14(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000))
+#define SET_SRAM_TAG_15(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff))
+#define DEF_BRG_SW_RST() (REG32(ADR_BRG_SW_RST)) = (0x00000000)
+#define DEF_BOOT() (REG32(ADR_BOOT)) = (0x00040000)
+#define DEF_CHIP_ID_0() (REG32(ADR_CHIP_ID_0)) = (0x31333131)
+#define DEF_CHIP_ID_1() (REG32(ADR_CHIP_ID_1)) = (0x322d3230)
+#define DEF_CHIP_ID_2() (REG32(ADR_CHIP_ID_2)) = (0x32303041)
+#define DEF_CHIP_ID_3() (REG32(ADR_CHIP_ID_3)) = (0x53535636)
+#define DEF_CLOCK_SELECTION() (REG32(ADR_CLOCK_SELECTION)) = (0x00000000)
+#define DEF_PLATFORM_CLOCK_ENABLE() (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (0x008fffff)
+#define DEF_SYS_CSR_CLOCK_ENABLE() (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (0x00000400)
+#define DEF_MCU_DBG_SEL() (REG32(ADR_MCU_DBG_SEL)) = (0x00000000)
+#define DEF_MCU_DBG_DATA() (REG32(ADR_MCU_DBG_DATA)) = (0x00000000)
+#define DEF_AHB_BRG_STATUS() (REG32(ADR_AHB_BRG_STATUS)) = (0x00000000)
+#define DEF_BIST_BIST_CTRL() (REG32(ADR_BIST_BIST_CTRL)) = (0x00000000)
+#define DEF_BIST_MODE_REG_IN() (REG32(ADR_BIST_MODE_REG_IN)) = (0x001ffe3e)
+#define DEF_BIST_MODE_REG_OUT() (REG32(ADR_BIST_MODE_REG_OUT)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_LSB() (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_MSB() (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (0x00000000)
+#define DEF_TB_ADR_SEL() (REG32(ADR_TB_ADR_SEL)) = (0x00000000)
+#define DEF_TB_RDATA() (REG32(ADR_TB_RDATA)) = (0x00000000)
+#define DEF_UART_W2B() (REG32(ADR_UART_W2B)) = (0x00000000)
+#define DEF_AHB_ILL_ADDR() (REG32(ADR_AHB_ILL_ADDR)) = (0x00000000)
+#define DEF_AHB_FEN_ADDR() (REG32(ADR_AHB_FEN_ADDR)) = (0x00000000)
+#define DEF_AHB_ILLFEN_STATUS() (REG32(ADR_AHB_ILLFEN_STATUS)) = (0x00000000)
+#define DEF_PWM_A() (REG32(ADR_PWM_A)) = (0x400a1010)
+#define DEF_PWM_B() (REG32(ADR_PWM_B)) = (0x400a1010)
+#define DEF_HBUSREQ_LOCK() (REG32(ADR_HBUSREQ_LOCK)) = (0x00001ffd)
+#define DEF_HBURST_LOCK() (REG32(ADR_HBURST_LOCK)) = (0x00000000)
+#define DEF_PRESCALER_USTIMER() (REG32(ADR_PRESCALER_USTIMER)) = (0x00000028)
+#define DEF_BIST_MODE_REG_IN_MMU() (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (0x0000fe3e)
+#define DEF_BIST_MODE_REG_OUT_MMU() (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_MMU() (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (0x00000000)
+#define DEF_TEST_MODE() (REG32(ADR_TEST_MODE)) = (0x00000000)
+#define DEF_BOOT_INFO() (REG32(ADR_BOOT_INFO)) = (0x00000000)
+#define DEF_SD_INIT_CFG() (REG32(ADR_SD_INIT_CFG)) = (0x00000000)
+#define DEF_SPARE_UART_INFO() (REG32(ADR_SPARE_UART_INFO)) = (0x00000000)
+#define DEF_TU0_MICROSECOND_TIMER() (REG32(ADR_TU0_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU0_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU0_DUMMY_BIT_0() (REG32(ADR_TU0_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU0_DUMMY_BIT_1() (REG32(ADR_TU0_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU1_MICROSECOND_TIMER() (REG32(ADR_TU1_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU1_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU1_DUMMY_BIT_0() (REG32(ADR_TU1_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU1_DUMMY_BIT_1() (REG32(ADR_TU1_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU2_MICROSECOND_TIMER() (REG32(ADR_TU2_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU2_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU2_DUMMY_BIT_0() (REG32(ADR_TU2_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU2_DUMMY_BIT_1() (REG32(ADR_TU2_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU3_MICROSECOND_TIMER() (REG32(ADR_TU3_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU3_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU3_DUMMY_BIT_0() (REG32(ADR_TU3_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU3_DUMMY_BIT_1() (REG32(ADR_TU3_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM0_MILISECOND_TIMER() (REG32(ADR_TM0_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM0_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM0_DUMMY_BIT_0() (REG32(ADR_TM0_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM0_DUMMY_BIT_1() (REG32(ADR_TM0_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM1_MILISECOND_TIMER() (REG32(ADR_TM1_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM1_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM1_DUMMY_BIT_0() (REG32(ADR_TM1_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM1_DUMMY_BIT_1() (REG32(ADR_TM1_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM2_MILISECOND_TIMER() (REG32(ADR_TM2_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM2_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM2_DUMMY_BIT_0() (REG32(ADR_TM2_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM2_DUMMY_BIT_1() (REG32(ADR_TM2_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM3_MILISECOND_TIMER() (REG32(ADR_TM3_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM3_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM3_DUMMY_BIT_0() (REG32(ADR_TM3_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM3_DUMMY_BIT_1() (REG32(ADR_TM3_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_MCU_WDOG_REG() (REG32(ADR_MCU_WDOG_REG)) = (0x00000000)
+#define DEF_SYS_WDOG_REG() (REG32(ADR_SYS_WDOG_REG)) = (0x00000000)
+#define DEF_PAD6() (REG32(ADR_PAD6)) = (0x00000008)
+#define DEF_PAD7() (REG32(ADR_PAD7)) = (0x00000008)
+#define DEF_PAD8() (REG32(ADR_PAD8)) = (0x00000008)
+#define DEF_PAD9() (REG32(ADR_PAD9)) = (0x00000008)
+#define DEF_PAD11() (REG32(ADR_PAD11)) = (0x00000008)
+#define DEF_PAD15() (REG32(ADR_PAD15)) = (0x0000000a)
+#define DEF_PAD16() (REG32(ADR_PAD16)) = (0x0000000a)
+#define DEF_PAD17() (REG32(ADR_PAD17)) = (0x0000000a)
+#define DEF_PAD18() (REG32(ADR_PAD18)) = (0x0000000a)
+#define DEF_PAD19() (REG32(ADR_PAD19)) = (0x00007000)
+#define DEF_PAD20() (REG32(ADR_PAD20)) = (0x0000000a)
+#define DEF_PAD21() (REG32(ADR_PAD21)) = (0x0000000a)
+#define DEF_PAD22() (REG32(ADR_PAD22)) = (0x00000009)
+#define DEF_PAD24() (REG32(ADR_PAD24)) = (0x00000008)
+#define DEF_PAD25() (REG32(ADR_PAD25)) = (0x0000000b)
+#define DEF_PAD27() (REG32(ADR_PAD27)) = (0x00000008)
+#define DEF_PAD28() (REG32(ADR_PAD28)) = (0x00000008)
+#define DEF_PAD29() (REG32(ADR_PAD29)) = (0x00000009)
+#define DEF_PAD30() (REG32(ADR_PAD30)) = (0x0000000a)
+#define DEF_PAD31() (REG32(ADR_PAD31)) = (0x0000000a)
+#define DEF_PAD32() (REG32(ADR_PAD32)) = (0x0000000a)
+#define DEF_PAD33() (REG32(ADR_PAD33)) = (0x0000000a)
+#define DEF_PAD34() (REG32(ADR_PAD34)) = (0x0000000a)
+#define DEF_PAD42() (REG32(ADR_PAD42)) = (0x0000000a)
+#define DEF_PAD43() (REG32(ADR_PAD43)) = (0x0000000a)
+#define DEF_PAD44() (REG32(ADR_PAD44)) = (0x0000000a)
+#define DEF_PAD45() (REG32(ADR_PAD45)) = (0x0000000a)
+#define DEF_PAD46() (REG32(ADR_PAD46)) = (0x0000000a)
+#define DEF_PAD47() (REG32(ADR_PAD47)) = (0x00100000)
+#define DEF_PAD48() (REG32(ADR_PAD48)) = (0x00100808)
+#define DEF_PAD49() (REG32(ADR_PAD49)) = (0x00100008)
+#define DEF_PAD50() (REG32(ADR_PAD50)) = (0x00100008)
+#define DEF_PAD51() (REG32(ADR_PAD51)) = (0x00100008)
+#define DEF_PAD52() (REG32(ADR_PAD52)) = (0x00100000)
+#define DEF_PAD53() (REG32(ADR_PAD53)) = (0x0000000a)
+#define DEF_PAD54() (REG32(ADR_PAD54)) = (0x00000000)
+#define DEF_PAD56() (REG32(ADR_PAD56)) = (0x00000000)
+#define DEF_PAD57() (REG32(ADR_PAD57)) = (0x00000008)
+#define DEF_PAD58() (REG32(ADR_PAD58)) = (0x0000000a)
+#define DEF_PAD59() (REG32(ADR_PAD59)) = (0x0000000a)
+#define DEF_PAD60() (REG32(ADR_PAD60)) = (0x0000000a)
+#define DEF_PAD61() (REG32(ADR_PAD61)) = (0x0000000a)
+#define DEF_PAD62() (REG32(ADR_PAD62)) = (0x0000000a)
+#define DEF_PAD64() (REG32(ADR_PAD64)) = (0x00000009)
+#define DEF_PAD65() (REG32(ADR_PAD65)) = (0x00000009)
+#define DEF_PAD66() (REG32(ADR_PAD66)) = (0x00000008)
+#define DEF_PAD68() (REG32(ADR_PAD68)) = (0x00000008)
+#define DEF_PAD67() (REG32(ADR_PAD67)) = (0x00000159)
+#define DEF_PAD69() (REG32(ADR_PAD69)) = (0x0000000b)
+#define DEF_PAD70() (REG32(ADR_PAD70)) = (0x00000008)
+#define DEF_PAD231() (REG32(ADR_PAD231)) = (0x00000008)
+#define DEF_PIN_SEL_0() (REG32(ADR_PIN_SEL_0)) = (0x00000000)
+#define DEF_PIN_SEL_1() (REG32(ADR_PIN_SEL_1)) = (0x00000000)
+#define DEF_IO_PORT_REG() (REG32(ADR_IO_PORT_REG)) = (0x00010000)
+#define DEF_INT_MASK_REG() (REG32(ADR_INT_MASK_REG)) = (0x000000ff)
+#define DEF_INT_STATUS_REG() (REG32(ADR_INT_STATUS_REG)) = (0x00000000)
+#define DEF_FN1_STATUS_REG() (REG32(ADR_FN1_STATUS_REG)) = (0x00000000)
+#define DEF_CARD_PKT_STATUS_TEST() (REG32(ADR_CARD_PKT_STATUS_TEST)) = (0x00000000)
+#define DEF_SYSTEM_INFORMATION_REG() (REG32(ADR_SYSTEM_INFORMATION_REG)) = (0x00000000)
+#define DEF_CARD_RCA_REG() (REG32(ADR_CARD_RCA_REG)) = (0x00000000)
+#define DEF_SDIO_FIFO_WR_THLD_REG() (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (0x00000000)
+#define DEF_SDIO_FIFO_WR_LIMIT_REG() (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (0x00000000)
+#define DEF_SDIO_TX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_THLD_FOR_CMD53RD_REG() (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (0x00000000)
+#define DEF_SDIO_RX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_LOG_START_END_DATA_REG() (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (0x00000000)
+#define DEF_SDIO_BYTE_MODE_BATCH_SIZE_REG() (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_LAST_CMD_INDEX_CRC_REG() (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (0x00000000)
+#define DEF_SDIO_LAST_CMD_ARG_REG() (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (0x00000000)
+#define DEF_SDIO_BUS_STATE_DEBUG_MONITOR() (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (0x00000000)
+#define DEF_SDIO_CARD_STATUS_REG() (REG32(ADR_SDIO_CARD_STATUS_REG)) = (0x00000000)
+#define DEF_R5_RESP_FLAG_OUT_TIMING() (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (0x00000000)
+#define DEF_CMD52_DATA_FOR_LAST_TIME() (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (0x00000000)
+#define DEF_FN1_DMA_START_ADDR_REG() (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (0x00000000)
+#define DEF_FN1_INT_CTRL_RESET() (REG32(ADR_FN1_INT_CTRL_RESET)) = (0x00000000)
+#define DEF_IO_REG_PORT_REG() (REG32(ADR_IO_REG_PORT_REG)) = (0x00010020)
+#define DEF_SDIO_FIFO_ERROR_CNT() (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (0x00000000)
+#define DEF_SDIO_CRC7_CRC16_ERROR_REG() (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (0x00000000)
+#define DEF_SDIO_BLOCK_CNT_INFO() (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (0x00000000)
+#define DEF_RX_DATA_CMD52_ABORT_COUNT() (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (0x00000000)
+#define DEF_FIFO_PTR_READ_BLOCK_CNT() (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (0x00000000)
+#define DEF_TX_TIME_OUT_READ_CTRL() (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (0x00000000)
+#define DEF_SDIO_TX_ALLOC_REG() (REG32(ADR_SDIO_TX_ALLOC_REG)) = (0x00000000)
+#define DEF_SDIO_TX_INFORM() (REG32(ADR_SDIO_TX_INFORM)) = (0x00000000)
+#define DEF_F1_BLOCK_SIZE_0_REG() (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (0x00000000)
+#define DEF_SDIO_COMMAND_LOG_DATA_31_0() (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (0x000000ec)
+#define DEF_SDIO_COMMAND_LOG_DATA_63_32() (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (0xce000000)
+#define DEF_SYSTEM_INFORMATION_REGISTER() (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (0x00000000)
+#define DEF_CCCR_00H_REG() (REG32(ADR_CCCR_00H_REG)) = (0x00000000)
+#define DEF_CCCR_04H_REG() (REG32(ADR_CCCR_04H_REG)) = (0x00000000)
+#define DEF_CCCR_08H_REG() (REG32(ADR_CCCR_08H_REG)) = (0x00000000)
+#define DEF_CCCR_13H_REG() (REG32(ADR_CCCR_13H_REG)) = (0x00000000)
+#define DEF_FBR_100H_REG() (REG32(ADR_FBR_100H_REG)) = (0x00000000)
+#define DEF_FBR_109H_REG() (REG32(ADR_FBR_109H_REG)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_0() (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_1() (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_2() (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_3() (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_4() (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_5() (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_6() (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_7() (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_8() (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_9() (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_10() (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_11() (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_12() (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_13() (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_14() (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_15() (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_0() (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_1() (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_2() (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_3() (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_4() (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_5() (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_6() (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_7() (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_8() (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_9() (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_10() (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_11() (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_12() (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_13() (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_14() (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_15() (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (0x00000000)
+#define DEF_SPI_MODE() (REG32(ADR_SPI_MODE)) = (0x00000000)
+#define DEF_RX_QUOTA() (REG32(ADR_RX_QUOTA)) = (0x00000000)
+#define DEF_CONDITION_NUMBER() (REG32(ADR_CONDITION_NUMBER)) = (0x00000004)
+#define DEF_HOST_PATH() (REG32(ADR_HOST_PATH)) = (0x00000001)
+#define DEF_TX_SEG() (REG32(ADR_TX_SEG)) = (0x00000000)
+#define DEF_DEBUG_BURST_MODE() (REG32(ADR_DEBUG_BURST_MODE)) = (0x00000000)
+#define DEF_SPI_TO_PHY_PARAM1() (REG32(ADR_SPI_TO_PHY_PARAM1)) = (0x000e0006)
+#define DEF_SPI_TO_PHY_PARAM2() (REG32(ADR_SPI_TO_PHY_PARAM2)) = (0x000e000e)
+#define DEF_SPI_STS() (REG32(ADR_SPI_STS)) = (0x00000000)
+#define DEF_TX_ALLOC_SET() (REG32(ADR_TX_ALLOC_SET)) = (0x00000000)
+#define DEF_TX_ALLOC() (REG32(ADR_TX_ALLOC)) = (0x00000000)
+#define DEF_DBG_CNT() (REG32(ADR_DBG_CNT)) = (0x00000000)
+#define DEF_DBG_CNT2() (REG32(ADR_DBG_CNT2)) = (0x00000000)
+#define DEF_DBG_CNT3() (REG32(ADR_DBG_CNT3)) = (0x00000000)
+#define DEF_DBG_CNT4() (REG32(ADR_DBG_CNT4)) = (0x00000000)
+#define DEF_INT_TAG() (REG32(ADR_INT_TAG)) = (0x00000000)
+#define DEF_I2CM_EN() (REG32(ADR_I2CM_EN)) = (0x00000074)
+#define DEF_I2CM_DEV_A() (REG32(ADR_I2CM_DEV_A)) = (0x00008000)
+#define DEF_I2CM_LEN() (REG32(ADR_I2CM_LEN)) = (0x00000000)
+#define DEF_I2CM_WDAT() (REG32(ADR_I2CM_WDAT)) = (0x00000000)
+#define DEF_I2CM_RDAT() (REG32(ADR_I2CM_RDAT)) = (0x00000000)
+#define DEF_I2CM_EN_2() (REG32(ADR_I2CM_EN_2)) = (0x00010000)
+#define DEF_UART_DATA() (REG32(ADR_UART_DATA)) = (0x00000000)
+#define DEF_UART_IER() (REG32(ADR_UART_IER)) = (0x00000000)
+#define DEF_UART_FCR() (REG32(ADR_UART_FCR)) = (0x00000001)
+#define DEF_UART_LCR() (REG32(ADR_UART_LCR)) = (0x00000003)
+#define DEF_UART_MCR() (REG32(ADR_UART_MCR)) = (0x00000000)
+#define DEF_UART_LSR() (REG32(ADR_UART_LSR)) = (0x00000000)
+#define DEF_UART_MSR() (REG32(ADR_UART_MSR)) = (0x00000000)
+#define DEF_UART_SPR() (REG32(ADR_UART_SPR)) = (0x00000000)
+#define DEF_UART_RTHR() (REG32(ADR_UART_RTHR)) = (0x000000c8)
+#define DEF_UART_ISR() (REG32(ADR_UART_ISR)) = (0x000000c1)
+#define DEF_DAT_UART_DATA() (REG32(ADR_DAT_UART_DATA)) = (0x00000000)
+#define DEF_DAT_UART_IER() (REG32(ADR_DAT_UART_IER)) = (0x00000000)
+#define DEF_DAT_UART_FCR() (REG32(ADR_DAT_UART_FCR)) = (0x00000001)
+#define DEF_DAT_UART_LCR() (REG32(ADR_DAT_UART_LCR)) = (0x00000003)
+#define DEF_DAT_UART_MCR() (REG32(ADR_DAT_UART_MCR)) = (0x00000000)
+#define DEF_DAT_UART_LSR() (REG32(ADR_DAT_UART_LSR)) = (0x00000000)
+#define DEF_DAT_UART_MSR() (REG32(ADR_DAT_UART_MSR)) = (0x00000000)
+#define DEF_DAT_UART_SPR() (REG32(ADR_DAT_UART_SPR)) = (0x00000000)
+#define DEF_DAT_UART_RTHR() (REG32(ADR_DAT_UART_RTHR)) = (0x000000c8)
+#define DEF_DAT_UART_ISR() (REG32(ADR_DAT_UART_ISR)) = (0x000000c1)
+#define DEF_INT_MASK() (REG32(ADR_INT_MASK)) = (0xffffffff)
+#define DEF_INT_MODE() (REG32(ADR_INT_MODE)) = (0x00000000)
+#define DEF_INT_IRQ_STS() (REG32(ADR_INT_IRQ_STS)) = (0x00000000)
+#define DEF_INT_FIQ_STS() (REG32(ADR_INT_FIQ_STS)) = (0x00000000)
+#define DEF_INT_IRQ_RAW() (REG32(ADR_INT_IRQ_RAW)) = (0x00000000)
+#define DEF_INT_FIQ_RAW() (REG32(ADR_INT_FIQ_RAW)) = (0x00000000)
+#define DEF_INT_PERI_MASK() (REG32(ADR_INT_PERI_MASK)) = (0xffffffff)
+#define DEF_INT_PERI_STS() (REG32(ADR_INT_PERI_STS)) = (0x00000000)
+#define DEF_INT_PERI_RAW() (REG32(ADR_INT_PERI_RAW)) = (0x00000000)
+#define DEF_INT_GPI_CFG() (REG32(ADR_INT_GPI_CFG)) = (0x00000000)
+#define DEF_SYS_INT_FOR_HOST() (REG32(ADR_SYS_INT_FOR_HOST)) = (0x00000001)
+#define DEF_SPI_IPC() (REG32(ADR_SPI_IPC)) = (0x00000000)
+#define DEF_SDIO_IPC() (REG32(ADR_SDIO_IPC)) = (0x00000000)
+#define DEF_SDIO_MASK() (REG32(ADR_SDIO_MASK)) = (0xffffffff)
+#define DEF_SDIO_IRQ_STS() (REG32(ADR_SDIO_IRQ_STS)) = (0x00000000)
+#define DEF_SD_PERI_MASK() (REG32(ADR_SD_PERI_MASK)) = (0xffffffff)
+#define DEF_SD_PERI_STS() (REG32(ADR_SD_PERI_STS)) = (0x00000000)
+#define DEF_DBG_SPI_MODE() (REG32(ADR_DBG_SPI_MODE)) = (0x00000000)
+#define DEF_DBG_RX_QUOTA() (REG32(ADR_DBG_RX_QUOTA)) = (0x00000000)
+#define DEF_DBG_CONDITION_NUMBER() (REG32(ADR_DBG_CONDITION_NUMBER)) = (0x00000004)
+#define DEF_DBG_HOST_PATH() (REG32(ADR_DBG_HOST_PATH)) = (0x00000001)
+#define DEF_DBG_TX_SEG() (REG32(ADR_DBG_TX_SEG)) = (0x00000000)
+#define DEF_DBG_DEBUG_BURST_MODE() (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (0x00000000)
+#define DEF_DBG_SPI_TO_PHY_PARAM1() (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (0x000e0006)
+#define DEF_DBG_SPI_TO_PHY_PARAM2() (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (0x000e000e)
+#define DEF_DBG_SPI_STS() (REG32(ADR_DBG_SPI_STS)) = (0x00000000)
+#define DEF_DBG_TX_ALLOC_SET() (REG32(ADR_DBG_TX_ALLOC_SET)) = (0x00000000)
+#define DEF_DBG_TX_ALLOC() (REG32(ADR_DBG_TX_ALLOC)) = (0x00000000)
+#define DEF_DBG_DBG_CNT() (REG32(ADR_DBG_DBG_CNT)) = (0x00000000)
+#define DEF_DBG_DBG_CNT2() (REG32(ADR_DBG_DBG_CNT2)) = (0x00000000)
+#define DEF_DBG_DBG_CNT3() (REG32(ADR_DBG_DBG_CNT3)) = (0x00000000)
+#define DEF_DBG_DBG_CNT4() (REG32(ADR_DBG_DBG_CNT4)) = (0x00000000)
+#define DEF_DBG_INT_TAG() (REG32(ADR_DBG_INT_TAG)) = (0x00000000)
+#define DEF_BOOT_ADDR() (REG32(ADR_BOOT_ADDR)) = (0x00000000)
+#define DEF_VERIFY_DATA() (REG32(ADR_VERIFY_DATA)) = (0x5e11aa11)
+#define DEF_FLASH_ADDR() (REG32(ADR_FLASH_ADDR)) = (0x00000000)
+#define DEF_SRAM_ADDR() (REG32(ADR_SRAM_ADDR)) = (0x00000000)
+#define DEF_LEN() (REG32(ADR_LEN)) = (0x00000000)
+#define DEF_SPI_PARAM() (REG32(ADR_SPI_PARAM)) = (0x000f000f)
+#define DEF_SPI_PARAM2() (REG32(ADR_SPI_PARAM2)) = (0x00040001)
+#define DEF_CHECK_SUM_RESULT() (REG32(ADR_CHECK_SUM_RESULT)) = (0x00000000)
+#define DEF_CHECK_SUM_IN_FILE() (REG32(ADR_CHECK_SUM_IN_FILE)) = (0x00000000)
+#define DEF_COMMAND_LEN() (REG32(ADR_COMMAND_LEN)) = (0x00000000)
+#define DEF_COMMAND_ADDR() (REG32(ADR_COMMAND_ADDR)) = (0x00000000)
+#define DEF_DMA_ADR_SRC() (REG32(ADR_DMA_ADR_SRC)) = (0x00000000)
+#define DEF_DMA_ADR_DST() (REG32(ADR_DMA_ADR_DST)) = (0x00000000)
+#define DEF_DMA_CTRL() (REG32(ADR_DMA_CTRL)) = (0x000000aa)
+#define DEF_DMA_INT() (REG32(ADR_DMA_INT)) = (0x00000001)
+#define DEF_DMA_FILL_CONST() (REG32(ADR_DMA_FILL_CONST)) = (0x00000000)
+#define DEF_PMU_0() (REG32(ADR_PMU_0)) = (0x0f000040)
+#define DEF_PMU_1() (REG32(ADR_PMU_1)) = (0x015d015d)
+#define DEF_PMU_2() (REG32(ADR_PMU_2)) = (0x00000000)
+#define DEF_PMU_3() (REG32(ADR_PMU_3)) = (0x55550000)
+#define DEF_RTC_1() (REG32(ADR_RTC_1)) = (0x7fff0000)
+#define DEF_RTC_2() (REG32(ADR_RTC_2)) = (0x00000003)
+#define DEF_RTC_3W() (REG32(ADR_RTC_3W)) = (0x00000000)
+#define DEF_RTC_3R() (REG32(ADR_RTC_3R)) = (0x00000000)
+#define DEF_RTC_4() (REG32(ADR_RTC_4)) = (0x00000000)
+#define DEF_D2_DMA_ADR_SRC() (REG32(ADR_D2_DMA_ADR_SRC)) = (0x00000000)
+#define DEF_D2_DMA_ADR_DST() (REG32(ADR_D2_DMA_ADR_DST)) = (0x00000000)
+#define DEF_D2_DMA_CTRL() (REG32(ADR_D2_DMA_CTRL)) = (0x000000aa)
+#define DEF_D2_DMA_INT() (REG32(ADR_D2_DMA_INT)) = (0x00000001)
+#define DEF_D2_DMA_FILL_CONST() (REG32(ADR_D2_DMA_FILL_CONST)) = (0x00000000)
+#define DEF_CONTROL() (REG32(ADR_CONTROL)) = (0x02700008)
+#define DEF_SDIO_WAKE_MODE() (REG32(ADR_SDIO_WAKE_MODE)) = (0x00000000)
+#define DEF_TX_FLOW_0() (REG32(ADR_TX_FLOW_0)) = (0x00000000)
+#define DEF_TX_FLOW_1() (REG32(ADR_TX_FLOW_1)) = (0x00000000)
+#define DEF_THREASHOLD() (REG32(ADR_THREASHOLD)) = (0x09000000)
+#define DEF_TXFID_INCREASE() (REG32(ADR_TXFID_INCREASE)) = (0x00000000)
+#define DEF_GLOBAL_SEQUENCE() (REG32(ADR_GLOBAL_SEQUENCE)) = (0x00000000)
+#define DEF_HCI_TX_RX_INFO_SIZE() (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (0x00040450)
+#define DEF_HCI_TX_INFO_CLEAR() (REG32(ADR_HCI_TX_INFO_CLEAR)) = (0x00000008)
+#define DEF_TX_ETHER_TYPE_0() (REG32(ADR_TX_ETHER_TYPE_0)) = (0x00000000)
+#define DEF_TX_ETHER_TYPE_1() (REG32(ADR_TX_ETHER_TYPE_1)) = (0x00000000)
+#define DEF_RX_ETHER_TYPE_0() (REG32(ADR_RX_ETHER_TYPE_0)) = (0x00000000)
+#define DEF_RX_ETHER_TYPE_1() (REG32(ADR_RX_ETHER_TYPE_1)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_0() (REG32(ADR_PACKET_COUNTER_INFO_0)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_1() (REG32(ADR_PACKET_COUNTER_INFO_1)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_2() (REG32(ADR_PACKET_COUNTER_INFO_2)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_3() (REG32(ADR_PACKET_COUNTER_INFO_3)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_4() (REG32(ADR_PACKET_COUNTER_INFO_4)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_5() (REG32(ADR_PACKET_COUNTER_INFO_5)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_6() (REG32(ADR_PACKET_COUNTER_INFO_6)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_7() (REG32(ADR_PACKET_COUNTER_INFO_7)) = (0x00000000)
+#define DEF_SDIO_TX_RX_FAIL_COUNTER_0() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (0x00000000)
+#define DEF_SDIO_TX_RX_FAIL_COUNTER_1() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_0() (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_1() (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_2() (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_3() (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_4() (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_5() (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_6() (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_7() (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_8() (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_9() (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_10() (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (0x00000000)
+#define DEF_CS_START_ADDR() (REG32(ADR_CS_START_ADDR)) = (0x00000000)
+#define DEF_CS_ADD_LEN() (REG32(ADR_CS_ADD_LEN)) = (0x00000000)
+#define DEF_CS_CMD() (REG32(ADR_CS_CMD)) = (0x00000000)
+#define DEF_CS_INI_BUF() (REG32(ADR_CS_INI_BUF)) = (0x00000000)
+#define DEF_CS_PSEUDO_BUF() (REG32(ADR_CS_PSEUDO_BUF)) = (0x00000000)
+#define DEF_CS_CHECK_SUM() (REG32(ADR_CS_CHECK_SUM)) = (0x00000000)
+#define DEF_RAND_EN() (REG32(ADR_RAND_EN)) = (0x00000000)
+#define DEF_RAND_NUM() (REG32(ADR_RAND_NUM)) = (0x00000000)
+#define DEF_MUL_OP1() (REG32(ADR_MUL_OP1)) = (0x00000000)
+#define DEF_MUL_OP2() (REG32(ADR_MUL_OP2)) = (0x00000000)
+#define DEF_MUL_ANS0() (REG32(ADR_MUL_ANS0)) = (0x00000000)
+#define DEF_MUL_ANS1() (REG32(ADR_MUL_ANS1)) = (0x00000000)
+#define DEF_DMA_RDATA() (REG32(ADR_DMA_RDATA)) = (0x00000000)
+#define DEF_DMA_WDATA() (REG32(ADR_DMA_WDATA)) = (0x00000000)
+#define DEF_DMA_LEN() (REG32(ADR_DMA_LEN)) = (0x00000000)
+#define DEF_DMA_CLR() (REG32(ADR_DMA_CLR)) = (0x00000000)
+#define DEF_NAV_DATA() (REG32(ADR_NAV_DATA)) = (0x00000000)
+#define DEF_CO_NAV() (REG32(ADR_CO_NAV)) = (0x00000000)
+#define DEF_SHA_DST_ADDR() (REG32(ADR_SHA_DST_ADDR)) = (0x00000000)
+#define DEF_SHA_SRC_ADDR() (REG32(ADR_SHA_SRC_ADDR)) = (0x00000000)
+#define DEF_SHA_SETTING() (REG32(ADR_SHA_SETTING)) = (0x00000002)
+#define DEF_EFUSE_CLK_FREQ() (REG32(ADR_EFUSE_CLK_FREQ)) = (0x610100d0)
+#define DEF_EFUSE_LDO_TIME() (REG32(ADR_EFUSE_LDO_TIME)) = (0x00020002)
+#define DEF_EFUSE_AHB_RDATA_0() (REG32(ADR_EFUSE_AHB_RDATA_0)) = (0x00000000)
+#define DEF_EFUSE_WDATA_0() (REG32(ADR_EFUSE_WDATA_0)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_1() (REG32(ADR_EFUSE_AHB_RDATA_1)) = (0x00000000)
+#define DEF_EFUSE_WDATA_1() (REG32(ADR_EFUSE_WDATA_1)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_2() (REG32(ADR_EFUSE_AHB_RDATA_2)) = (0x00000000)
+#define DEF_EFUSE_WDATA_2() (REG32(ADR_EFUSE_WDATA_2)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_3() (REG32(ADR_EFUSE_AHB_RDATA_3)) = (0x00000000)
+#define DEF_EFUSE_WDATA_3() (REG32(ADR_EFUSE_WDATA_3)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_4() (REG32(ADR_EFUSE_AHB_RDATA_4)) = (0x00000000)
+#define DEF_EFUSE_WDATA_4() (REG32(ADR_EFUSE_WDATA_4)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_5() (REG32(ADR_EFUSE_AHB_RDATA_5)) = (0x00000000)
+#define DEF_EFUSE_WDATA_5() (REG32(ADR_EFUSE_WDATA_5)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_6() (REG32(ADR_EFUSE_AHB_RDATA_6)) = (0x00000000)
+#define DEF_EFUSE_WDATA_6() (REG32(ADR_EFUSE_WDATA_6)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_7() (REG32(ADR_EFUSE_AHB_RDATA_7)) = (0x00000000)
+#define DEF_EFUSE_WDATA_7() (REG32(ADR_EFUSE_WDATA_7)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD0_EN() (REG32(ADR_EFUSE_SPI_RD0_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD1_EN() (REG32(ADR_EFUSE_SPI_RD1_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD2_EN() (REG32(ADR_EFUSE_SPI_RD2_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD3_EN() (REG32(ADR_EFUSE_SPI_RD3_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD4_EN() (REG32(ADR_EFUSE_SPI_RD4_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD5_EN() (REG32(ADR_EFUSE_SPI_RD5_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD6_EN() (REG32(ADR_EFUSE_SPI_RD6_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD7_EN() (REG32(ADR_EFUSE_SPI_RD7_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_BUSY() (REG32(ADR_EFUSE_SPI_BUSY)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_0() (REG32(ADR_EFUSE_SPI_RDATA_0)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_1() (REG32(ADR_EFUSE_SPI_RDATA_1)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_2() (REG32(ADR_EFUSE_SPI_RDATA_2)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_3() (REG32(ADR_EFUSE_SPI_RDATA_3)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_4() (REG32(ADR_EFUSE_SPI_RDATA_4)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_5() (REG32(ADR_EFUSE_SPI_RDATA_5)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_6() (REG32(ADR_EFUSE_SPI_RDATA_6)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_7() (REG32(ADR_EFUSE_SPI_RDATA_7)) = (0x00000000)
+#define DEF_SMS4_CFG1() (REG32(ADR_SMS4_CFG1)) = (0x00000002)
+#define DEF_SMS4_CFG2() (REG32(ADR_SMS4_CFG2)) = (0x00000000)
+#define DEF_SMS4_MODE1() (REG32(ADR_SMS4_MODE1)) = (0x00000000)
+#define DEF_SMS4_TRIG() (REG32(ADR_SMS4_TRIG)) = (0x00000000)
+#define DEF_SMS4_STATUS1() (REG32(ADR_SMS4_STATUS1)) = (0x00000000)
+#define DEF_SMS4_STATUS2() (REG32(ADR_SMS4_STATUS2)) = (0x00000000)
+#define DEF_SMS4_DATA_IN0() (REG32(ADR_SMS4_DATA_IN0)) = (0x00000000)
+#define DEF_SMS4_DATA_IN1() (REG32(ADR_SMS4_DATA_IN1)) = (0x00000000)
+#define DEF_SMS4_DATA_IN2() (REG32(ADR_SMS4_DATA_IN2)) = (0x00000000)
+#define DEF_SMS4_DATA_IN3() (REG32(ADR_SMS4_DATA_IN3)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT0() (REG32(ADR_SMS4_DATA_OUT0)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT1() (REG32(ADR_SMS4_DATA_OUT1)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT2() (REG32(ADR_SMS4_DATA_OUT2)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT3() (REG32(ADR_SMS4_DATA_OUT3)) = (0x00000000)
+#define DEF_SMS4_KEY_0() (REG32(ADR_SMS4_KEY_0)) = (0x00000000)
+#define DEF_SMS4_KEY_1() (REG32(ADR_SMS4_KEY_1)) = (0x00000000)
+#define DEF_SMS4_KEY_2() (REG32(ADR_SMS4_KEY_2)) = (0x00000000)
+#define DEF_SMS4_KEY_3() (REG32(ADR_SMS4_KEY_3)) = (0x00000000)
+#define DEF_SMS4_MODE_IV0() (REG32(ADR_SMS4_MODE_IV0)) = (0x00000000)
+#define DEF_SMS4_MODE_IV1() (REG32(ADR_SMS4_MODE_IV1)) = (0x00000000)
+#define DEF_SMS4_MODE_IV2() (REG32(ADR_SMS4_MODE_IV2)) = (0x00000000)
+#define DEF_SMS4_MODE_IV3() (REG32(ADR_SMS4_MODE_IV3)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC0() (REG32(ADR_SMS4_OFB_ENC0)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC1() (REG32(ADR_SMS4_OFB_ENC1)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC2() (REG32(ADR_SMS4_OFB_ENC2)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC3() (REG32(ADR_SMS4_OFB_ENC3)) = (0x00000000)
+#define DEF_MRX_MCAST_TB0_0() (REG32(ADR_MRX_MCAST_TB0_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB0_1() (REG32(ADR_MRX_MCAST_TB0_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK0_0() (REG32(ADR_MRX_MCAST_MK0_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK0_1() (REG32(ADR_MRX_MCAST_MK0_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL0() (REG32(ADR_MRX_MCAST_CTRL0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB1_0() (REG32(ADR_MRX_MCAST_TB1_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB1_1() (REG32(ADR_MRX_MCAST_TB1_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK1_0() (REG32(ADR_MRX_MCAST_MK1_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK1_1() (REG32(ADR_MRX_MCAST_MK1_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL1() (REG32(ADR_MRX_MCAST_CTRL1)) = (0x00000000)
+#define DEF_MRX_MCAST_TB2_0() (REG32(ADR_MRX_MCAST_TB2_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB2_1() (REG32(ADR_MRX_MCAST_TB2_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK2_0() (REG32(ADR_MRX_MCAST_MK2_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK2_1() (REG32(ADR_MRX_MCAST_MK2_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL2() (REG32(ADR_MRX_MCAST_CTRL2)) = (0x00000000)
+#define DEF_MRX_MCAST_TB3_0() (REG32(ADR_MRX_MCAST_TB3_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB3_1() (REG32(ADR_MRX_MCAST_TB3_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK3_0() (REG32(ADR_MRX_MCAST_MK3_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK3_1() (REG32(ADR_MRX_MCAST_MK3_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL3() (REG32(ADR_MRX_MCAST_CTRL3)) = (0x00000000)
+#define DEF_MRX_PHY_INFO() (REG32(ADR_MRX_PHY_INFO)) = (0x00000000)
+#define DEF_MRX_BA_DBG() (REG32(ADR_MRX_BA_DBG)) = (0x00000000)
+#define DEF_MRX_FLT_TB0() (REG32(ADR_MRX_FLT_TB0)) = (0x00003df5)
+#define DEF_MRX_FLT_TB1() (REG32(ADR_MRX_FLT_TB1)) = (0x000031f6)
+#define DEF_MRX_FLT_TB2() (REG32(ADR_MRX_FLT_TB2)) = (0x000035f9)
+#define DEF_MRX_FLT_TB3() (REG32(ADR_MRX_FLT_TB3)) = (0x000021c1)
+#define DEF_MRX_FLT_TB4() (REG32(ADR_MRX_FLT_TB4)) = (0x00004bf9)
+#define DEF_MRX_FLT_TB5() (REG32(ADR_MRX_FLT_TB5)) = (0x00004db1)
+#define DEF_MRX_FLT_TB6() (REG32(ADR_MRX_FLT_TB6)) = (0x000011fe)
+#define DEF_MRX_FLT_TB7() (REG32(ADR_MRX_FLT_TB7)) = (0x00000bfe)
+#define DEF_MRX_FLT_TB8() (REG32(ADR_MRX_FLT_TB8)) = (0x00000000)
+#define DEF_MRX_FLT_TB9() (REG32(ADR_MRX_FLT_TB9)) = (0x00000000)
+#define DEF_MRX_FLT_TB10() (REG32(ADR_MRX_FLT_TB10)) = (0x00000000)
+#define DEF_MRX_FLT_TB11() (REG32(ADR_MRX_FLT_TB11)) = (0x00000006)
+#define DEF_MRX_FLT_TB12() (REG32(ADR_MRX_FLT_TB12)) = (0x00000001)
+#define DEF_MRX_FLT_TB13() (REG32(ADR_MRX_FLT_TB13)) = (0x00000003)
+#define DEF_MRX_FLT_TB14() (REG32(ADR_MRX_FLT_TB14)) = (0x00000005)
+#define DEF_MRX_FLT_TB15() (REG32(ADR_MRX_FLT_TB15)) = (0x00000007)
+#define DEF_MRX_FLT_EN0() (REG32(ADR_MRX_FLT_EN0)) = (0x00002008)
+#define DEF_MRX_FLT_EN1() (REG32(ADR_MRX_FLT_EN1)) = (0x00001001)
+#define DEF_MRX_FLT_EN2() (REG32(ADR_MRX_FLT_EN2)) = (0x00000808)
+#define DEF_MRX_FLT_EN3() (REG32(ADR_MRX_FLT_EN3)) = (0x00001000)
+#define DEF_MRX_FLT_EN4() (REG32(ADR_MRX_FLT_EN4)) = (0x00002008)
+#define DEF_MRX_FLT_EN5() (REG32(ADR_MRX_FLT_EN5)) = (0x0000800e)
+#define DEF_MRX_FLT_EN6() (REG32(ADR_MRX_FLT_EN6)) = (0x00000838)
+#define DEF_MRX_FLT_EN7() (REG32(ADR_MRX_FLT_EN7)) = (0x00002008)
+#define DEF_MRX_FLT_EN8() (REG32(ADR_MRX_FLT_EN8)) = (0x00002008)
+#define DEF_MRX_LEN_FLT() (REG32(ADR_MRX_LEN_FLT)) = (0x00000000)
+#define DEF_RX_FLOW_DATA() (REG32(ADR_RX_FLOW_DATA)) = (0x00105034)
+#define DEF_RX_FLOW_MNG() (REG32(ADR_RX_FLOW_MNG)) = (0x00000004)
+#define DEF_RX_FLOW_CTRL() (REG32(ADR_RX_FLOW_CTRL)) = (0x00000004)
+#define DEF_RX_TIME_STAMP_CFG() (REG32(ADR_RX_TIME_STAMP_CFG)) = (0x00001c00)
+#define DEF_DBG_FF_FULL() (REG32(ADR_DBG_FF_FULL)) = (0x00000000)
+#define DEF_DBG_WFF_FULL() (REG32(ADR_DBG_WFF_FULL)) = (0x00000000)
+#define DEF_DBG_MB_FULL() (REG32(ADR_DBG_MB_FULL)) = (0x00000000)
+#define DEF_BA_CTRL() (REG32(ADR_BA_CTRL)) = (0x00000008)
+#define DEF_BA_TA_0() (REG32(ADR_BA_TA_0)) = (0x00000000)
+#define DEF_BA_TA_1() (REG32(ADR_BA_TA_1)) = (0x00000000)
+#define DEF_BA_TID() (REG32(ADR_BA_TID)) = (0x00000000)
+#define DEF_BA_ST_SEQ() (REG32(ADR_BA_ST_SEQ)) = (0x00000000)
+#define DEF_BA_SB0() (REG32(ADR_BA_SB0)) = (0x00000000)
+#define DEF_BA_SB1() (REG32(ADR_BA_SB1)) = (0x00000000)
+#define DEF_MRX_WATCH_DOG() (REG32(ADR_MRX_WATCH_DOG)) = (0x0000ffff)
+#define DEF_ACK_GEN_EN() (REG32(ADR_ACK_GEN_EN)) = (0x00000000)
+#define DEF_ACK_GEN_PARA() (REG32(ADR_ACK_GEN_PARA)) = (0x00000000)
+#define DEF_ACK_GEN_RA_0() (REG32(ADR_ACK_GEN_RA_0)) = (0x00000000)
+#define DEF_ACK_GEN_RA_1() (REG32(ADR_ACK_GEN_RA_1)) = (0x00000000)
+#define DEF_MIB_LEN_FAIL() (REG32(ADR_MIB_LEN_FAIL)) = (0x00000000)
+#define DEF_TRAP_HW_ID() (REG32(ADR_TRAP_HW_ID)) = (0x00000000)
+#define DEF_ID_IN_USE() (REG32(ADR_ID_IN_USE)) = (0x00000000)
+#define DEF_MRX_ERR() (REG32(ADR_MRX_ERR)) = (0x00000000)
+#define DEF_WSID0_TID0_RX_SEQ() (REG32(ADR_WSID0_TID0_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID1_RX_SEQ() (REG32(ADR_WSID0_TID1_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID2_RX_SEQ() (REG32(ADR_WSID0_TID2_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID3_RX_SEQ() (REG32(ADR_WSID0_TID3_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID4_RX_SEQ() (REG32(ADR_WSID0_TID4_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID5_RX_SEQ() (REG32(ADR_WSID0_TID5_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID6_RX_SEQ() (REG32(ADR_WSID0_TID6_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID7_RX_SEQ() (REG32(ADR_WSID0_TID7_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID0_RX_SEQ() (REG32(ADR_WSID1_TID0_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID1_RX_SEQ() (REG32(ADR_WSID1_TID1_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID2_RX_SEQ() (REG32(ADR_WSID1_TID2_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID3_RX_SEQ() (REG32(ADR_WSID1_TID3_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID4_RX_SEQ() (REG32(ADR_WSID1_TID4_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID5_RX_SEQ() (REG32(ADR_WSID1_TID5_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID6_RX_SEQ() (REG32(ADR_WSID1_TID6_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID7_RX_SEQ() (REG32(ADR_WSID1_TID7_RX_SEQ)) = (0x00000000)
+#define DEF_HDR_ADDR_SEL() (REG32(ADR_HDR_ADDR_SEL)) = (0x00003e79)
+#define DEF_FRAME_TYPE_CNTR_SET() (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (0x00000000)
+#define DEF_PHY_INFO() (REG32(ADR_PHY_INFO)) = (0x00000000)
+#define DEF_AMPDU_SIG() (REG32(ADR_AMPDU_SIG)) = (0x0000004e)
+#define DEF_MIB_AMPDU() (REG32(ADR_MIB_AMPDU)) = (0x00000000)
+#define DEF_LEN_FLT() (REG32(ADR_LEN_FLT)) = (0x00000000)
+#define DEF_MIB_DELIMITER() (REG32(ADR_MIB_DELIMITER)) = (0x00000000)
+#define DEF_MTX_INT_STS() (REG32(ADR_MTX_INT_STS)) = (0x00000000)
+#define DEF_MTX_INT_EN() (REG32(ADR_MTX_INT_EN)) = (0x00000000)
+#define DEF_MTX_MISC_EN() (REG32(ADR_MTX_MISC_EN)) = (0x00c00c00)
+#define DEF_MTX_EDCCA_TOUT() (REG32(ADR_MTX_EDCCA_TOUT)) = (0x00000200)
+#define DEF_MTX_BCN_INT_STS() (REG32(ADR_MTX_BCN_INT_STS)) = (0x00000000)
+#define DEF_MTX_BCN_EN_INT() (REG32(ADR_MTX_BCN_EN_INT)) = (0x00000000)
+#define DEF_MTX_BCN_EN_MISC() (REG32(ADR_MTX_BCN_EN_MISC)) = (0x00000042)
+#define DEF_MTX_BCN_MISC() (REG32(ADR_MTX_BCN_MISC)) = (0x00000000)
+#define DEF_MTX_BCN_PRD() (REG32(ADR_MTX_BCN_PRD)) = (0x00000064)
+#define DEF_MTX_BCN_TSF_L() (REG32(ADR_MTX_BCN_TSF_L)) = (0x00000000)
+#define DEF_MTX_BCN_TSF_U() (REG32(ADR_MTX_BCN_TSF_U)) = (0x00000000)
+#define DEF_MTX_BCN_CFG0() (REG32(ADR_MTX_BCN_CFG0)) = (0x00000000)
+#define DEF_MTX_BCN_CFG1() (REG32(ADR_MTX_BCN_CFG1)) = (0x00000000)
+#define DEF_MTX_STATUS() (REG32(ADR_MTX_STATUS)) = (0x00000000)
+#define DEF_MTX_DBG_CTRL() (REG32(ADR_MTX_DBG_CTRL)) = (0x00000000)
+#define DEF_MTX_DBG_DAT0() (REG32(ADR_MTX_DBG_DAT0)) = (0x00000000)
+#define DEF_MTX_DBG_DAT1() (REG32(ADR_MTX_DBG_DAT1)) = (0x00000000)
+#define DEF_MTX_DBG_DAT2() (REG32(ADR_MTX_DBG_DAT2)) = (0x00000000)
+#define DEF_MTX_DUR_TOUT() (REG32(ADR_MTX_DUR_TOUT)) = (0x00002c2c)
+#define DEF_MTX_DUR_IFS() (REG32(ADR_MTX_DUR_IFS)) = (0x12d40a05)
+#define DEF_MTX_DUR_SIFS_G() (REG32(ADR_MTX_DUR_SIFS_G)) = (0x12c90100)
+#define DEF_MTX_DBG_DAT3() (REG32(ADR_MTX_DBG_DAT3)) = (0x00000000)
+#define DEF_MTX_NAV() (REG32(ADR_MTX_NAV)) = (0x00000000)
+#define DEF_MTX_MIB_WSID0() (REG32(ADR_MTX_MIB_WSID0)) = (0x00000000)
+#define DEF_MTX_MIB_WSID1() (REG32(ADR_MTX_MIB_WSID1)) = (0x00000000)
+#define DEF_MTX_DBG_DAT4() (REG32(ADR_MTX_DBG_DAT4)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_MISC_EN() (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_AIFSN() (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ0_MTX_Q_BKF_CNT() (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ0_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_MISC_EN() (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_AIFSN() (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ1_MTX_Q_BKF_CNT() (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ1_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_MISC_EN() (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_AIFSN() (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ2_MTX_Q_BKF_CNT() (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ2_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_MISC_EN() (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_AIFSN() (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ3_MTX_Q_BKF_CNT() (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ3_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_MISC_EN() (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_AIFSN() (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ4_MTX_Q_BKF_CNT() (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ4_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_WSID0() (REG32(ADR_WSID0)) = (0x00000000)
+#define DEF_PEER_MAC0_0() (REG32(ADR_PEER_MAC0_0)) = (0x00000000)
+#define DEF_PEER_MAC0_1() (REG32(ADR_PEER_MAC0_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_0() (REG32(ADR_TX_ACK_POLICY_0_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_0() (REG32(ADR_TX_SEQ_CTRL_0_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_1() (REG32(ADR_TX_ACK_POLICY_0_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_1() (REG32(ADR_TX_SEQ_CTRL_0_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_2() (REG32(ADR_TX_ACK_POLICY_0_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_2() (REG32(ADR_TX_SEQ_CTRL_0_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_3() (REG32(ADR_TX_ACK_POLICY_0_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_3() (REG32(ADR_TX_SEQ_CTRL_0_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_4() (REG32(ADR_TX_ACK_POLICY_0_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_4() (REG32(ADR_TX_SEQ_CTRL_0_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_5() (REG32(ADR_TX_ACK_POLICY_0_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_5() (REG32(ADR_TX_SEQ_CTRL_0_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_6() (REG32(ADR_TX_ACK_POLICY_0_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_6() (REG32(ADR_TX_SEQ_CTRL_0_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_7() (REG32(ADR_TX_ACK_POLICY_0_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_7() (REG32(ADR_TX_SEQ_CTRL_0_7)) = (0x00000000)
+#define DEF_WSID1() (REG32(ADR_WSID1)) = (0x00000000)
+#define DEF_PEER_MAC1_0() (REG32(ADR_PEER_MAC1_0)) = (0x00000000)
+#define DEF_PEER_MAC1_1() (REG32(ADR_PEER_MAC1_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_0() (REG32(ADR_TX_ACK_POLICY_1_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_0() (REG32(ADR_TX_SEQ_CTRL_1_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_1() (REG32(ADR_TX_ACK_POLICY_1_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_1() (REG32(ADR_TX_SEQ_CTRL_1_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_2() (REG32(ADR_TX_ACK_POLICY_1_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_2() (REG32(ADR_TX_SEQ_CTRL_1_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_3() (REG32(ADR_TX_ACK_POLICY_1_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_3() (REG32(ADR_TX_SEQ_CTRL_1_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_4() (REG32(ADR_TX_ACK_POLICY_1_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_4() (REG32(ADR_TX_SEQ_CTRL_1_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_5() (REG32(ADR_TX_ACK_POLICY_1_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_5() (REG32(ADR_TX_SEQ_CTRL_1_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_6() (REG32(ADR_TX_ACK_POLICY_1_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_6() (REG32(ADR_TX_SEQ_CTRL_1_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_7() (REG32(ADR_TX_ACK_POLICY_1_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_7() (REG32(ADR_TX_SEQ_CTRL_1_7)) = (0x00000000)
+#define DEF_INFO0() (REG32(ADR_INFO0)) = (0x00000000)
+#define DEF_INFO1() (REG32(ADR_INFO1)) = (0x00000100)
+#define DEF_INFO2() (REG32(ADR_INFO2)) = (0x00000200)
+#define DEF_INFO3() (REG32(ADR_INFO3)) = (0x00000300)
+#define DEF_INFO4() (REG32(ADR_INFO4)) = (0x00000140)
+#define DEF_INFO5() (REG32(ADR_INFO5)) = (0x00000240)
+#define DEF_INFO6() (REG32(ADR_INFO6)) = (0x00000340)
+#define DEF_INFO7() (REG32(ADR_INFO7)) = (0x00000001)
+#define DEF_INFO8() (REG32(ADR_INFO8)) = (0x00000101)
+#define DEF_INFO9() (REG32(ADR_INFO9)) = (0x00000201)
+#define DEF_INFO10() (REG32(ADR_INFO10)) = (0x00000301)
+#define DEF_INFO11() (REG32(ADR_INFO11)) = (0x00000401)
+#define DEF_INFO12() (REG32(ADR_INFO12)) = (0x00000501)
+#define DEF_INFO13() (REG32(ADR_INFO13)) = (0x00000601)
+#define DEF_INFO14() (REG32(ADR_INFO14)) = (0x00000701)
+#define DEF_INFO15() (REG32(ADR_INFO15)) = (0x00030002)
+#define DEF_INFO16() (REG32(ADR_INFO16)) = (0x00030102)
+#define DEF_INFO17() (REG32(ADR_INFO17)) = (0x00030202)
+#define DEF_INFO18() (REG32(ADR_INFO18)) = (0x00030302)
+#define DEF_INFO19() (REG32(ADR_INFO19)) = (0x00030402)
+#define DEF_INFO20() (REG32(ADR_INFO20)) = (0x00030502)
+#define DEF_INFO21() (REG32(ADR_INFO21)) = (0x00030602)
+#define DEF_INFO22() (REG32(ADR_INFO22)) = (0x00030702)
+#define DEF_INFO23() (REG32(ADR_INFO23)) = (0x00030082)
+#define DEF_INFO24() (REG32(ADR_INFO24)) = (0x00030182)
+#define DEF_INFO25() (REG32(ADR_INFO25)) = (0x00030282)
+#define DEF_INFO26() (REG32(ADR_INFO26)) = (0x00030382)
+#define DEF_INFO27() (REG32(ADR_INFO27)) = (0x00030482)
+#define DEF_INFO28() (REG32(ADR_INFO28)) = (0x00030582)
+#define DEF_INFO29() (REG32(ADR_INFO29)) = (0x00030682)
+#define DEF_INFO30() (REG32(ADR_INFO30)) = (0x00030782)
+#define DEF_INFO31() (REG32(ADR_INFO31)) = (0x00030042)
+#define DEF_INFO32() (REG32(ADR_INFO32)) = (0x00030142)
+#define DEF_INFO33() (REG32(ADR_INFO33)) = (0x00030242)
+#define DEF_INFO34() (REG32(ADR_INFO34)) = (0x00030342)
+#define DEF_INFO35() (REG32(ADR_INFO35)) = (0x00030442)
+#define DEF_INFO36() (REG32(ADR_INFO36)) = (0x00030542)
+#define DEF_INFO37() (REG32(ADR_INFO37)) = (0x00030642)
+#define DEF_INFO38() (REG32(ADR_INFO38)) = (0x00030742)
+#define DEF_INFO_MASK() (REG32(ADR_INFO_MASK)) = (0x00007fc7)
+#define DEF_INFO_RATE_OFFSET() (REG32(ADR_INFO_RATE_OFFSET)) = (0x00040000)
+#define DEF_INFO_IDX_ADDR() (REG32(ADR_INFO_IDX_ADDR)) = (0x00000000)
+#define DEF_INFO_LEN_ADDR() (REG32(ADR_INFO_LEN_ADDR)) = (0x00000000)
+#define DEF_IC_TIME_TAG_0() (REG32(ADR_IC_TIME_TAG_0)) = (0x00000000)
+#define DEF_IC_TIME_TAG_1() (REG32(ADR_IC_TIME_TAG_1)) = (0x00000000)
+#define DEF_PACKET_ID_ALLOCATION_PRIORITY() (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (0x00000000)
+#define DEF_MAC_MODE() (REG32(ADR_MAC_MODE)) = (0x00000000)
+#define DEF_ALL_SOFTWARE_RESET() (REG32(ADR_ALL_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_ENG_SOFTWARE_RESET() (REG32(ADR_ENG_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_CSR_SOFTWARE_RESET() (REG32(ADR_CSR_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_MAC_CLOCK_ENABLE() (REG32(ADR_MAC_CLOCK_ENABLE)) = (0x00003efb)
+#define DEF_MAC_ENGINE_CLOCK_ENABLE() (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (0x0000f07b)
+#define DEF_MAC_CSR_CLOCK_ENABLE() (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (0x0000ec02)
+#define DEF_GLBLE_SET() (REG32(ADR_GLBLE_SET)) = (0x000e5000)
+#define DEF_REASON_TRAP0() (REG32(ADR_REASON_TRAP0)) = (0x00000000)
+#define DEF_REASON_TRAP1() (REG32(ADR_REASON_TRAP1)) = (0x00000000)
+#define DEF_BSSID_0() (REG32(ADR_BSSID_0)) = (0x00000000)
+#define DEF_BSSID_1() (REG32(ADR_BSSID_1)) = (0x00000000)
+#define DEF_SCRT_STATE() (REG32(ADR_SCRT_STATE)) = (0x00000000)
+#define DEF_STA_MAC_0() (REG32(ADR_STA_MAC_0)) = (0x00000000)
+#define DEF_STA_MAC_1() (REG32(ADR_STA_MAC_1)) = (0x00000000)
+#define DEF_SCRT_SET() (REG32(ADR_SCRT_SET)) = (0x00000000)
+#define DEF_BTCX0() (REG32(ADR_BTCX0)) = (0x00000006)
+#define DEF_BTCX1() (REG32(ADR_BTCX1)) = (0x00000000)
+#define DEF_SWITCH_CTL() (REG32(ADR_SWITCH_CTL)) = (0x00000000)
+#define DEF_MIB_EN() (REG32(ADR_MIB_EN)) = (0x00000000)
+#define DEF_MTX_WSID0_SUCC() (REG32(ADR_MTX_WSID0_SUCC)) = (0x00000000)
+#define DEF_MTX_WSID0_FRM() (REG32(ADR_MTX_WSID0_FRM)) = (0x00000000)
+#define DEF_MTX_WSID0_RETRY() (REG32(ADR_MTX_WSID0_RETRY)) = (0x00000000)
+#define DEF_MTX_WSID0_TOTAL() (REG32(ADR_MTX_WSID0_TOTAL)) = (0x00000000)
+#define DEF_MTX_GROUP() (REG32(ADR_MTX_GROUP)) = (0x00000000)
+#define DEF_MTX_FAIL() (REG32(ADR_MTX_FAIL)) = (0x00000000)
+#define DEF_MTX_RETRY() (REG32(ADR_MTX_RETRY)) = (0x00000000)
+#define DEF_MTX_MULTI_RETRY() (REG32(ADR_MTX_MULTI_RETRY)) = (0x00000000)
+#define DEF_MTX_RTS_SUCCESS() (REG32(ADR_MTX_RTS_SUCCESS)) = (0x00000000)
+#define DEF_MTX_RTS_FAIL() (REG32(ADR_MTX_RTS_FAIL)) = (0x00000000)
+#define DEF_MTX_ACK_FAIL() (REG32(ADR_MTX_ACK_FAIL)) = (0x00000000)
+#define DEF_MTX_FRM() (REG32(ADR_MTX_FRM)) = (0x00000000)
+#define DEF_MTX_ACK_TX() (REG32(ADR_MTX_ACK_TX)) = (0x00000000)
+#define DEF_MTX_CTS_TX() (REG32(ADR_MTX_CTS_TX)) = (0x00000000)
+#define DEF_MRX_DUP_FRM() (REG32(ADR_MRX_DUP_FRM)) = (0x00000000)
+#define DEF_MRX_FRG_FRM() (REG32(ADR_MRX_FRG_FRM)) = (0x00000000)
+#define DEF_MRX_GROUP_FRM() (REG32(ADR_MRX_GROUP_FRM)) = (0x00000000)
+#define DEF_MRX_FCS_ERR() (REG32(ADR_MRX_FCS_ERR)) = (0x00000000)
+#define DEF_MRX_FCS_SUCC() (REG32(ADR_MRX_FCS_SUCC)) = (0x00000000)
+#define DEF_MRX_MISS() (REG32(ADR_MRX_MISS)) = (0x00000000)
+#define DEF_MRX_ALC_FAIL() (REG32(ADR_MRX_ALC_FAIL)) = (0x00000000)
+#define DEF_MRX_DAT_NTF() (REG32(ADR_MRX_DAT_NTF)) = (0x00000000)
+#define DEF_MRX_RTS_NTF() (REG32(ADR_MRX_RTS_NTF)) = (0x00000000)
+#define DEF_MRX_CTS_NTF() (REG32(ADR_MRX_CTS_NTF)) = (0x00000000)
+#define DEF_MRX_ACK_NTF() (REG32(ADR_MRX_ACK_NTF)) = (0x00000000)
+#define DEF_MRX_BA_NTF() (REG32(ADR_MRX_BA_NTF)) = (0x00000000)
+#define DEF_MRX_DATA_NTF() (REG32(ADR_MRX_DATA_NTF)) = (0x00000000)
+#define DEF_MRX_MNG_NTF() (REG32(ADR_MRX_MNG_NTF)) = (0x00000000)
+#define DEF_MRX_DAT_CRC_NTF() (REG32(ADR_MRX_DAT_CRC_NTF)) = (0x00000000)
+#define DEF_MRX_BAR_NTF() (REG32(ADR_MRX_BAR_NTF)) = (0x00000000)
+#define DEF_MRX_MB_MISS() (REG32(ADR_MRX_MB_MISS)) = (0x00000000)
+#define DEF_MRX_NIDLE_MISS() (REG32(ADR_MRX_NIDLE_MISS)) = (0x00000000)
+#define DEF_MRX_CSR_NTF() (REG32(ADR_MRX_CSR_NTF)) = (0x00000000)
+#define DEF_DBG_Q0_FRM_SUCCESS() (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q0_FRM_FAIL() (REG32(ADR_DBG_Q0_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q0_ACK_SUCCESS() (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q0_ACK_FAIL() (REG32(ADR_DBG_Q0_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q1_FRM_SUCCESS() (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q1_FRM_FAIL() (REG32(ADR_DBG_Q1_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q1_ACK_SUCCESS() (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q1_ACK_FAIL() (REG32(ADR_DBG_Q1_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q2_FRM_SUCCESS() (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q2_FRM_FAIL() (REG32(ADR_DBG_Q2_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q2_ACK_SUCCESS() (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q2_ACK_FAIL() (REG32(ADR_DBG_Q2_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q3_FRM_SUCCESS() (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q3_FRM_FAIL() (REG32(ADR_DBG_Q3_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q3_ACK_SUCCESS() (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q3_ACK_FAIL() (REG32(ADR_DBG_Q3_ACK_FAIL)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP0() (REG32(ADR_MIB_SCRT_TKIP0)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP1() (REG32(ADR_MIB_SCRT_TKIP1)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP2() (REG32(ADR_MIB_SCRT_TKIP2)) = (0x00000000)
+#define DEF_MIB_SCRT_CCMP0() (REG32(ADR_MIB_SCRT_CCMP0)) = (0x00000000)
+#define DEF_MIB_SCRT_CCMP1() (REG32(ADR_MIB_SCRT_CCMP1)) = (0x00000000)
+#define DEF_DBG_LEN_CRC_FAIL() (REG32(ADR_DBG_LEN_CRC_FAIL)) = (0x00000000)
+#define DEF_DBG_LEN_ALC_FAIL() (REG32(ADR_DBG_LEN_ALC_FAIL)) = (0x00000000)
+#define DEF_DBG_AMPDU_PASS() (REG32(ADR_DBG_AMPDU_PASS)) = (0x00000000)
+#define DEF_DBG_AMPDU_FAIL() (REG32(ADR_DBG_AMPDU_FAIL)) = (0x00000000)
+#define DEF_ID_ALC_FAIL1() (REG32(ADR_ID_ALC_FAIL1)) = (0x00000000)
+#define DEF_ID_ALC_FAIL2() (REG32(ADR_ID_ALC_FAIL2)) = (0x00000000)
+#define DEF_CBR_HARD_WIRE_PIN_REGISTER() (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
+#define DEF_CBR_MANUAL_ENABLE_REGISTER() (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (0x00001fc0)
+#define DEF_CBR_LDO_REGISTER() (REG32(ADR_CBR_LDO_REGISTER)) = (0x2496db1b)
+#define DEF_CBR_ABB_REGISTER_1() (REG32(ADR_CBR_ABB_REGISTER_1)) = (0x151558dd)
+#define DEF_CBR_ABB_REGISTER_2() (REG32(ADR_CBR_ABB_REGISTER_2)) = (0x01011a88)
+#define DEF_CBR_TX_FE_REGISTER() (REG32(ADR_CBR_TX_FE_REGISTER)) = (0x3cbe84fe)
+#define DEF_CBR_RX_FE_REGISTER_1() (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (0x00657579)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
+#define DEF_CBR_RX_FSM_REGISTER() (REG32(ADR_CBR_RX_FSM_REGISTER)) = (0x00000ca8)
+#define DEF_CBR_RX_ADC_REGISTER() (REG32(ADR_CBR_RX_ADC_REGISTER)) = (0x002a0224)
+#define DEF_CBR_TX_DAC_REGISTER() (REG32(ADR_CBR_TX_DAC_REGISTER)) = (0x00002655)
+#define DEF_CBR_SX_ENABLE_RGISTER() (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (0x0000647c)
+#define DEF_CBR_SYN_RGISTER_1() (REG32(ADR_CBR_SYN_RGISTER_1)) = (0xaa800000)
+#define DEF_CBR_SYN_RGISTER_2() (REG32(ADR_CBR_SYN_RGISTER_2)) = (0x00550800)
+#define DEF_CBR_SYN_PFD_CHP() (REG32(ADR_CBR_SYN_PFD_CHP)) = (0x07c0894a)
+#define DEF_CBR_SYN_VCO_LOBF() (REG32(ADR_CBR_SYN_VCO_LOBF)) = (0xfcccca27)
+#define DEF_CBR_SYN_DIV_SDM_XOSC() (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (0x2773c93c)
+#define DEF_CBR_SYN_LCK1() (REG32(ADR_CBR_SYN_LCK1)) = (0x00000a7c)
+#define DEF_CBR_SYN_LCK2() (REG32(ADR_CBR_SYN_LCK2)) = (0x01c67ff4)
+#define DEF_CBR_DPLL_VCO_REGISTER() (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (0x00103014)
+#define DEF_CBR_DPLL_CP_PFD_REGISTER() (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (0x0001848c)
+#define DEF_CBR_DPLL_DIVIDER_REGISTER() (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (0x034061e0)
+#define DEF_CBR_DCOC_IDAC_REGISTER1() (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER2() (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER3() (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER4() (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER5() (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER6() (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER7() (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER8() (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (0x00820820)
+#define DEF_CBR_RCAL_REGISTER() (REG32(ADR_CBR_RCAL_REGISTER)) = (0x00004080)
+#define DEF_CBR_MANUAL_REGISTER() (REG32(ADR_CBR_MANUAL_REGISTER)) = (0x00003e7e)
+#define DEF_CBR_TRX_DUMMY_REGISTER() (REG32(ADR_CBR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_CBR_SX_DUMMY_REGISTER() (REG32(ADR_CBR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_CBR_RG_PKT_GEN_0() (REG32(ADR_CBR_RG_PKT_GEN_0)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_1() (REG32(ADR_CBR_RG_PKT_GEN_1)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_2() (REG32(ADR_CBR_RG_PKT_GEN_2)) = (0x00000000)
+#define DEF_CBR_RG_INTEGRATION() (REG32(ADR_CBR_RG_INTEGRATION)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_TXCNT() (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (0x00000000)
+#define DEF_CBR_PATTERN_GEN() (REG32(ADR_CBR_PATTERN_GEN)) = (0xff000000)
+#define DEF_MB_CPU_INT() (REG32(ADR_MB_CPU_INT)) = (0x00000000)
+#define DEF_CPU_ID_TB0() (REG32(ADR_CPU_ID_TB0)) = (0x00000000)
+#define DEF_CPU_ID_TB1() (REG32(ADR_CPU_ID_TB1)) = (0x00000000)
+#define DEF_CH0_TRIG_1() (REG32(ADR_CH0_TRIG_1)) = (0x00000000)
+#define DEF_CH0_TRIG_0() (REG32(ADR_CH0_TRIG_0)) = (0x00000000)
+#define DEF_CH0_PRI_TRIG() (REG32(ADR_CH0_PRI_TRIG)) = (0x00000000)
+#define DEF_MCU_STATUS() (REG32(ADR_MCU_STATUS)) = (0x00000000)
+#define DEF_RD_IN_FFCNT1() (REG32(ADR_RD_IN_FFCNT1)) = (0x00000000)
+#define DEF_RD_IN_FFCNT2() (REG32(ADR_RD_IN_FFCNT2)) = (0x00000000)
+#define DEF_RD_FFIN_FULL() (REG32(ADR_RD_FFIN_FULL)) = (0x00000000)
+#define DEF_MBOX_HALT_CFG() (REG32(ADR_MBOX_HALT_CFG)) = (0x00000000)
+#define DEF_MB_DBG_CFG1() (REG32(ADR_MB_DBG_CFG1)) = (0x00080000)
+#define DEF_MB_DBG_CFG2() (REG32(ADR_MB_DBG_CFG2)) = (0x00000000)
+#define DEF_MB_DBG_CFG3() (REG32(ADR_MB_DBG_CFG3)) = (0x00000000)
+#define DEF_MB_DBG_CFG4() (REG32(ADR_MB_DBG_CFG4)) = (0xffffffff)
+#define DEF_MB_OUT_QUEUE_CFG() (REG32(ADR_MB_OUT_QUEUE_CFG)) = (0x00000002)
+#define DEF_MB_OUT_QUEUE_FLUSH() (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT1() (REG32(ADR_RD_FFOUT_CNT1)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT2() (REG32(ADR_RD_FFOUT_CNT2)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT3() (REG32(ADR_RD_FFOUT_CNT3)) = (0x00000000)
+#define DEF_RD_FFOUT_FULL() (REG32(ADR_RD_FFOUT_FULL)) = (0x00000000)
+#define DEF_MB_THRESHOLD6() (REG32(ADR_MB_THRESHOLD6)) = (0x00000000)
+#define DEF_MB_THRESHOLD7() (REG32(ADR_MB_THRESHOLD7)) = (0x00000000)
+#define DEF_MB_THRESHOLD8() (REG32(ADR_MB_THRESHOLD8)) = (0x00000000)
+#define DEF_MB_THRESHOLD9() (REG32(ADR_MB_THRESHOLD9)) = (0x00000000)
+#define DEF_MB_THRESHOLD10() (REG32(ADR_MB_THRESHOLD10)) = (0x00000000)
+#define DEF_MB_TRASH_CFG() (REG32(ADR_MB_TRASH_CFG)) = (0x01000001)
+#define DEF_MB_IN_FF_FLUSH() (REG32(ADR_MB_IN_FF_FLUSH)) = (0x00000000)
+#define DEF_CPU_ID_TB2() (REG32(ADR_CPU_ID_TB2)) = (0x00000000)
+#define DEF_CPU_ID_TB3() (REG32(ADR_CPU_ID_TB3)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_CFG0() (REG32(ADR_PHY_IQ_LOG_CFG0)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_CFG1() (REG32(ADR_PHY_IQ_LOG_CFG1)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_LEN() (REG32(ADR_PHY_IQ_LOG_LEN)) = (0x00001000)
+#define DEF_PHY_IQ_LOG_PTR() (REG32(ADR_PHY_IQ_LOG_PTR)) = (0x00000000)
+#define DEF_WR_ALC() (REG32(ADR_WR_ALC)) = (0x00000000)
+#define DEF_GETID() (REG32(ADR_GETID)) = (0x00000000)
+#define DEF_CH_STA_PRI() (REG32(ADR_CH_STA_PRI)) = (0x00000213)
+#define DEF_RD_ID0() (REG32(ADR_RD_ID0)) = (0x00000000)
+#define DEF_RD_ID1() (REG32(ADR_RD_ID1)) = (0x00000000)
+#define DEF_IMD_CFG() (REG32(ADR_IMD_CFG)) = (0x00000000)
+#define DEF_IMD_STA() (REG32(ADR_IMD_STA)) = (0x00000000)
+#define DEF_ALC_STA() (REG32(ADR_ALC_STA)) = (0x01000000)
+#define DEF_TRX_ID_COUNT() (REG32(ADR_TRX_ID_COUNT)) = (0x00000000)
+#define DEF_TRX_ID_THRESHOLD() (REG32(ADR_TRX_ID_THRESHOLD)) = (0x01ee3c3c)
+#define DEF_TX_ID0() (REG32(ADR_TX_ID0)) = (0x00000000)
+#define DEF_TX_ID1() (REG32(ADR_TX_ID1)) = (0x00000000)
+#define DEF_RX_ID0() (REG32(ADR_RX_ID0)) = (0x00000000)
+#define DEF_RX_ID1() (REG32(ADR_RX_ID1)) = (0x00000000)
+#define DEF_RTN_STA() (REG32(ADR_RTN_STA)) = (0x00000001)
+#define DEF_ID_LEN_THREADSHOLD1() (REG32(ADR_ID_LEN_THREADSHOLD1)) = (0x000f0641)
+#define DEF_ID_LEN_THREADSHOLD2() (REG32(ADR_ID_LEN_THREADSHOLD2)) = (0x00000000)
+#define DEF_CH_ARB_PRI() (REG32(ADR_CH_ARB_PRI)) = (0x00031201)
+#define DEF_TX_ID_REMAIN_STATUS() (REG32(ADR_TX_ID_REMAIN_STATUS)) = (0x00000000)
+#define DEF_ID_INFO_STA() (REG32(ADR_ID_INFO_STA)) = (0x00000100)
+#define DEF_TX_LIMIT_INTR() (REG32(ADR_TX_LIMIT_INTR)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO() (REG32(ADR_TX_ID_ALL_INFO)) = (0x00000000)
+#define DEF_RD_ID2() (REG32(ADR_RD_ID2)) = (0x00000000)
+#define DEF_RD_ID3() (REG32(ADR_RD_ID3)) = (0x00000000)
+#define DEF_TX_ID2() (REG32(ADR_TX_ID2)) = (0x00000000)
+#define DEF_TX_ID3() (REG32(ADR_TX_ID3)) = (0x00000000)
+#define DEF_RX_ID2() (REG32(ADR_RX_ID2)) = (0x00000000)
+#define DEF_RX_ID3() (REG32(ADR_RX_ID3)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO2() (REG32(ADR_TX_ID_ALL_INFO2)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO_A() (REG32(ADR_TX_ID_ALL_INFO_A)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO_B() (REG32(ADR_TX_ID_ALL_INFO_B)) = (0x00000000)
+#define DEF_TX_ID_REMAIN_STATUS2() (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (0x01000100)
+#define DEF_ALC_ID_INFO() (REG32(ADR_ALC_ID_INFO)) = (0x00000000)
+#define DEF_ALC_ID_INF1() (REG32(ADR_ALC_ID_INF1)) = (0x00000000)
+#define DEF_PHY_EN_0() (REG32(ADR_PHY_EN_0)) = (0x00000014)
+#define DEF_PHY_EN_1() (REG32(ADR_PHY_EN_1)) = (0x00000000)
+#define DEF_SVN_VERSION_REG() (REG32(ADR_SVN_VERSION_REG)) = (0x00000000)
+#define DEF_PHY_PKT_GEN_0() (REG32(ADR_PHY_PKT_GEN_0)) = (0x00000064)
+#define DEF_PHY_PKT_GEN_1() (REG32(ADR_PHY_PKT_GEN_1)) = (0x00000fff)
+#define DEF_PHY_PKT_GEN_2() (REG32(ADR_PHY_PKT_GEN_2)) = (0x00000003)
+#define DEF_PHY_PKT_GEN_3() (REG32(ADR_PHY_PKT_GEN_3)) = (0x005a0220)
+#define DEF_PHY_PKT_GEN_4() (REG32(ADR_PHY_PKT_GEN_4)) = (0x00000001)
+#define DEF_PHY_REG_00() (REG32(ADR_PHY_REG_00)) = (0x10000000)
+#define DEF_PHY_REG_01() (REG32(ADR_PHY_REG_01)) = (0x00000000)
+#define DEF_PHY_REG_02_AGC() (REG32(ADR_PHY_REG_02_AGC)) = (0x80046771)
+#define DEF_PHY_REG_03_AGC() (REG32(ADR_PHY_REG_03_AGC)) = (0x1f300f6f)
+#define DEF_PHY_REG_04_AGC() (REG32(ADR_PHY_REG_04_AGC)) = (0x663f36d0)
+#define DEF_PHY_REG_05_AGC() (REG32(ADR_PHY_REG_05_AGC)) = (0x106c0000)
+#define DEF_PHY_REG_06_11B_DAGC() (REG32(ADR_PHY_REG_06_11B_DAGC)) = (0x01603fff)
+#define DEF_PHY_REG_07_11B_DAGC() (REG32(ADR_PHY_REG_07_11B_DAGC)) = (0x00600808)
+#define DEF_PHY_REG_08_11GN_DAGC() (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (0xff000160)
+#define DEF_PHY_REG_09_11GN_DAGC() (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (0x00080840)
+#define DEF_PHY_READ_REG_00_DIG_PWR() (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_01_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_02_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_03_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_REG_10_TX_DES() (REG32(ADR_PHY_REG_10_TX_DES)) = (0x00010405)
+#define DEF_PHY_REG_11_TX_DES() (REG32(ADR_PHY_REG_11_TX_DES)) = (0x06090813)
+#define DEF_PHY_REG_12_TX_DES() (REG32(ADR_PHY_REG_12_TX_DES)) = (0x12070000)
+#define DEF_PHY_REG_13_RX_DES() (REG32(ADR_PHY_REG_13_RX_DES)) = (0x01000405)
+#define DEF_PHY_REG_14_RX_DES() (REG32(ADR_PHY_REG_14_RX_DES)) = (0x06090813)
+#define DEF_PHY_REG_15_RX_DES() (REG32(ADR_PHY_REG_15_RX_DES)) = (0x12010000)
+#define DEF_PHY_REG_16_TX_DES_EXCP() (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (0x00000000)
+#define DEF_PHY_REG_17_TX_DES_EXCP() (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (0x10110000)
+#define DEF_PHY_REG_18_RSSI_SNR() (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (0x00fc000f)
+#define DEF_PHY_REG_19_DAC_MANUAL() (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (0x00000000)
+#define DEF_PHY_REG_20_MRX_CNT() (REG32(ADR_PHY_REG_20_MRX_CNT)) = (0x00000000)
+#define DEF_PHY_REG_21_TRX_RAMP() (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (0x3c012801)
+#define DEF_PHY_REG_22_TRX_RAMP() (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (0x24243724)
+#define DEF_PHY_REG_23_ANT() (REG32(ADR_PHY_REG_23_ANT)) = (0x00000011)
+#define DEF_PHY_REG_24_MTX_LEN_CNT() (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_25_MTX_LEN_CNT() (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_26_MRX_LEN_CNT() (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_27_MRX_LEN_CNT() (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_READ_REG_04() (REG32(ADR_PHY_READ_REG_04)) = (0x00000000)
+#define DEF_PHY_READ_REG_05() (REG32(ADR_PHY_READ_REG_05)) = (0x00000000)
+#define DEF_PHY_REG_28_BIST() (REG32(ADR_PHY_REG_28_BIST)) = (0x0000fe3e)
+#define DEF_PHY_READ_REG_06_BIST() (REG32(ADR_PHY_READ_REG_06_BIST)) = (0x00000000)
+#define DEF_PHY_READ_REG_07_BIST() (REG32(ADR_PHY_READ_REG_07_BIST)) = (0x00000000)
+#define DEF_PHY_REG_29_MTRX_MAC() (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (0xffffffff)
+#define DEF_PHY_READ_REG_08_MTRX_MAC() (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (0x00000000)
+#define DEF_PHY_READ_REG_09_MTRX_MAC() (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (0x00000000)
+#define DEF_PHY_REG_30_TX_UP_FIL() (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (0x0ead04f5)
+#define DEF_PHY_REG_31_TX_UP_FIL() (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (0x0fd60080)
+#define DEF_PHY_REG_32_TX_UP_FIL() (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (0x00000009)
+#define DEF_PHY_READ_TBUS() (REG32(ADR_PHY_READ_TBUS)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_00() (REG32(ADR_TX_11B_FIL_COEF_00)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_01() (REG32(ADR_TX_11B_FIL_COEF_01)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_02() (REG32(ADR_TX_11B_FIL_COEF_02)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_03() (REG32(ADR_TX_11B_FIL_COEF_03)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_04() (REG32(ADR_TX_11B_FIL_COEF_04)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_05() (REG32(ADR_TX_11B_FIL_COEF_05)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_06() (REG32(ADR_TX_11B_FIL_COEF_06)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_07() (REG32(ADR_TX_11B_FIL_COEF_07)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_08() (REG32(ADR_TX_11B_FIL_COEF_08)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_09() (REG32(ADR_TX_11B_FIL_COEF_09)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_10() (REG32(ADR_TX_11B_FIL_COEF_10)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_11() (REG32(ADR_TX_11B_FIL_COEF_11)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_12() (REG32(ADR_TX_11B_FIL_COEF_12)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_13() (REG32(ADR_TX_11B_FIL_COEF_13)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_14() (REG32(ADR_TX_11B_FIL_COEF_14)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_15() (REG32(ADR_TX_11B_FIL_COEF_15)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_16() (REG32(ADR_TX_11B_FIL_COEF_16)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_17() (REG32(ADR_TX_11B_FIL_COEF_17)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_18() (REG32(ADR_TX_11B_FIL_COEF_18)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_19() (REG32(ADR_TX_11B_FIL_COEF_19)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_20() (REG32(ADR_TX_11B_FIL_COEF_20)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_21() (REG32(ADR_TX_11B_FIL_COEF_21)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_22() (REG32(ADR_TX_11B_FIL_COEF_22)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_23() (REG32(ADR_TX_11B_FIL_COEF_23)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_24() (REG32(ADR_TX_11B_FIL_COEF_24)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_25() (REG32(ADR_TX_11B_FIL_COEF_25)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_26() (REG32(ADR_TX_11B_FIL_COEF_26)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_27() (REG32(ADR_TX_11B_FIL_COEF_27)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_28() (REG32(ADR_TX_11B_FIL_COEF_28)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_29() (REG32(ADR_TX_11B_FIL_COEF_29)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_30() (REG32(ADR_TX_11B_FIL_COEF_30)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_31() (REG32(ADR_TX_11B_FIL_COEF_31)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_32() (REG32(ADR_TX_11B_FIL_COEF_32)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_33() (REG32(ADR_TX_11B_FIL_COEF_33)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_34() (REG32(ADR_TX_11B_FIL_COEF_34)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_35() (REG32(ADR_TX_11B_FIL_COEF_35)) = (0x00000005)
+#define DEF_TX_11B_FIL_COEF_36() (REG32(ADR_TX_11B_FIL_COEF_36)) = (0x0000003d)
+#define DEF_TX_11B_FIL_COEF_37() (REG32(ADR_TX_11B_FIL_COEF_37)) = (0x00000162)
+#define DEF_TX_11B_FIL_COEF_38() (REG32(ADR_TX_11B_FIL_COEF_38)) = (0x00000400)
+#define DEF_TX_11B_FIL_COEF_39() (REG32(ADR_TX_11B_FIL_COEF_39)) = (0x00000699)
+#define DEF_TX_11B_FIL_COEF_40() (REG32(ADR_TX_11B_FIL_COEF_40)) = (0x00000787)
+#define DEF_TX_11B_PLCP() (REG32(ADR_TX_11B_PLCP)) = (0x00000000)
+#define DEF_TX_11B_RAMP() (REG32(ADR_TX_11B_RAMP)) = (0x0000403c)
+#define DEF_TX_11B_EN_CNT_RST_N() (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (0x00000001)
+#define DEF_TX_11B_EN_CNT() (REG32(ADR_TX_11B_EN_CNT)) = (0x00000000)
+#define DEF_TX_11B_PKT_GEN_CNT() (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (0x00000000)
+#define DEF_RX_11B_DES_DLY() (REG32(ADR_RX_11B_DES_DLY)) = (0x00000044)
+#define DEF_RX_11B_CCA_0() (REG32(ADR_RX_11B_CCA_0)) = (0x00040000)
+#define DEF_RX_11B_CCA_1() (REG32(ADR_RX_11B_CCA_1)) = (0x00400040)
+#define DEF_RX_11B_TR_KP_KI_0() (REG32(ADR_RX_11B_TR_KP_KI_0)) = (0x00003467)
+#define DEF_RX_11B_TR_KP_KI_1() (REG32(ADR_RX_11B_TR_KP_KI_1)) = (0x00540000)
+#define DEF_RX_11B_CE_CNT_THRESHOLD() (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (0x12243615)
+#define DEF_RX_11B_CE_MU_0() (REG32(ADR_RX_11B_CE_MU_0)) = (0x00390002)
+#define DEF_RX_11B_CE_MU_1() (REG32(ADR_RX_11B_CE_MU_1)) = (0x03456777)
+#define DEF_RX_11B_EQ_MU_0() (REG32(ADR_RX_11B_EQ_MU_0)) = (0x00350046)
+#define DEF_RX_11B_EQ_MU_1() (REG32(ADR_RX_11B_EQ_MU_1)) = (0x00570057)
+#define DEF_RX_11B_EQ_CR_KP_KI() (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (0x00236700)
+#define DEF_RX_11B_LPF_RATE() (REG32(ADR_RX_11B_LPF_RATE)) = (0x000d1746)
+#define DEF_RX_11B_CIT_CNT_THRESHOLD() (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (0x04061787)
+#define DEF_RX_11B_EQ_CH_MAIN_TAP() (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (0x07800000)
+#define DEF_RX_11B_SEARCH_CNT_TH() (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (0x00c0000a)
+#define DEF_RX_11B_CCA_CONTROL() (REG32(ADR_RX_11B_CCA_CONTROL)) = (0x00000000)
+#define DEF_RX_11B_FREQUENCY_OFFSET() (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (0x00000000)
+#define DEF_RX_11B_SNR_RSSI() (REG32(ADR_RX_11B_SNR_RSSI)) = (0x00000000)
+#define DEF_RX_11B_SFD_CRC_CNT() (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (0x00000000)
+#define DEF_RX_11B_PKT_ERR_AND_PKT_ERR_CNT() (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11B_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
+#define DEF_RX_11B_SFD_FILED_0() (REG32(ADR_RX_11B_SFD_FILED_0)) = (0x00000000)
+#define DEF_RX_11B_SFD_FIELD_1() (REG32(ADR_RX_11B_SFD_FIELD_1)) = (0x00000000)
+#define DEF_RX_11B_PKT_STAT_EN() (REG32(ADR_RX_11B_PKT_STAT_EN)) = (0x00100000)
+#define DEF_RX_11B_SOFT_RST() (REG32(ADR_RX_11B_SOFT_RST)) = (0x00000001)
+#define DEF_TX_11GN_RAMP() (REG32(ADR_TX_11GN_RAMP)) = (0x0000233c)
+#define DEF_TX_11GN_PLCP() (REG32(ADR_TX_11GN_PLCP)) = (0x5d08908e)
+#define DEF_TX_11GN_PKT_GEN_CNT() (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (0x00000000)
+#define DEF_TX_11GN_PLCP_CRC_ERR_CNT() (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11GN_DES_DLY() (REG32(ADR_RX_11GN_DES_DLY)) = (0x00000044)
+#define DEF_RX_11GN_TR_0() (REG32(ADR_RX_11GN_TR_0)) = (0x00750075)
+#define DEF_RX_11GN_TR_1() (REG32(ADR_RX_11GN_TR_1)) = (0x00000075)
+#define DEF_RX_11GN_TR_2() (REG32(ADR_RX_11GN_TR_2)) = (0x10000075)
+#define DEF_RX_11GN_CCA_0() (REG32(ADR_RX_11GN_CCA_0)) = (0x38324705)
+#define DEF_RX_11GN_CCA_1() (REG32(ADR_RX_11GN_CCA_1)) = (0x30182000)
+#define DEF_RX_11GN_CCA_2() (REG32(ADR_RX_11GN_CCA_2)) = (0x20600000)
+#define DEF_RX_11GN_CCA_FFT_SCALE() (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (0x0a010100)
+#define DEF_RX_11GN_SOFT_DEMAP_0() (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_1() (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (0x50000000)
+#define DEF_RX_11GN_SOFT_DEMAP_2() (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_3() (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_4() (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (0x50000000)
+#define DEF_RX_11GN_SOFT_DEMAP_5() (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (0x00000000)
+#define DEF_RX_11GN_SYM_BOUND_0() (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (0x00001420)
+#define DEF_RX_11GN_SYM_BOUND_1() (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (0x0000200a)
+#define DEF_RX_11GN_CCA_PWR() (REG32(ADR_RX_11GN_CCA_PWR)) = (0x30000280)
+#define DEF_RX_11GN_CCA_CNT() (REG32(ADR_RX_11GN_CCA_CNT)) = (0x30023002)
+#define DEF_RX_11GN_CCA_ATCOR_RE_CHECK() (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (0x0000003a)
+#define DEF_RX_11GN_VTB_TB() (REG32(ADR_RX_11GN_VTB_TB)) = (0x40000000)
+#define DEF_RX_11GN_ERR_UPDATE() (REG32(ADR_RX_11GN_ERR_UPDATE)) = (0x009e007e)
+#define DEF_RX_11GN_SHORT_GI() (REG32(ADR_RX_11GN_SHORT_GI)) = (0x00044400)
+#define DEF_RX_11GN_CHANNEL_UPDATE() (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (0x82000000)
+#define DEF_RX_11GN_PKT_FORMAT_0() (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (0x02003030)
+#define DEF_RX_11GN_PKT_FORMAT_1() (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (0x092a092a)
+#define DEF_RX_11GN_TX_TIME() (REG32(ADR_RX_11GN_TX_TIME)) = (0x00700010)
+#define DEF_RX_11GN_STBC_TR_KP_KI() (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (0x00007575)
+#define DEF_RX_11GN_BIST_0() (REG32(ADR_RX_11GN_BIST_0)) = (0x0001fe3e)
+#define DEF_RX_11GN_BIST_1() (REG32(ADR_RX_11GN_BIST_1)) = (0x0000fe3e)
+#define DEF_RX_11GN_BIST_2() (REG32(ADR_RX_11GN_BIST_2)) = (0x00000000)
+#define DEF_RX_11GN_BIST_3() (REG32(ADR_RX_11GN_BIST_3)) = (0x00000000)
+#define DEF_RX_11GN_BIST_4() (REG32(ADR_RX_11GN_BIST_4)) = (0x00000000)
+#define DEF_RX_11GN_BIST_5() (REG32(ADR_RX_11GN_BIST_5)) = (0x00000000)
+#define DEF_RX_11GN_SPECTRUM_ANALYZER() (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (0x00000000)
+#define DEF_RX_11GN_READ_0() (REG32(ADR_RX_11GN_READ_0)) = (0x00000000)
+#define DEF_RX_11GN_FREQ_OFFSET() (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (0x00000000)
+#define DEF_RX_11GN_SIGNAL_FIELD_0() (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (0x00000000)
+#define DEF_RX_11GN_SIGNAL_FIELD_1() (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (0x00000000)
+#define DEF_RX_11GN_PKT_ERR_CNT() (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11GN_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
+#define DEF_RX_11GN_SERVICE_LENGTH_FIELD() (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (0x00000000)
+#define DEF_RX_11GN_RATE() (REG32(ADR_RX_11GN_RATE)) = (0x00000000)
+#define DEF_RX_11GN_STAT_EN() (REG32(ADR_RX_11GN_STAT_EN)) = (0x00100001)
+#define DEF_RX_11GN_SOFT_RST() (REG32(ADR_RX_11GN_SOFT_RST)) = (0x00000001)
+#define DEF_RF_CONTROL_0() (REG32(ADR_RF_CONTROL_0)) = (0x00000000)
+#define DEF_RF_CONTROL_1() (REG32(ADR_RF_CONTROL_1)) = (0x00008000)
+#define DEF_TX_IQ_CONTROL_0() (REG32(ADR_TX_IQ_CONTROL_0)) = (0x00200020)
+#define DEF_TX_IQ_CONTROL_1() (REG32(ADR_TX_IQ_CONTROL_1)) = (0x00028080)
+#define DEF_TX_IQ_CONTROL_2() (REG32(ADR_TX_IQ_CONTROL_2)) = (0x00000000)
+#define DEF_TX_COMPENSATION_CONTROL() (REG32(ADR_TX_COMPENSATION_CONTROL)) = (0x00000000)
+#define DEF_RX_COMPENSATION_CONTROL() (REG32(ADR_RX_COMPENSATION_CONTROL)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_0() (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (0x000028ff)
+#define DEF_RX_OBSERVATION_CIRCUIT_1() (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_2() (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_3() (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (0x00000000)
+#define DEF_RF_IQ_CONTROL_0() (REG32(ADR_RF_IQ_CONTROL_0)) = (0x00000202)
+#define DEF_RF_IQ_CONTROL_1() (REG32(ADR_RF_IQ_CONTROL_1)) = (0x00ffc200)
+#define DEF_RF_IQ_CONTROL_2() (REG32(ADR_RF_IQ_CONTROL_2)) = (0x00000000)
+#define DEF_RF_IQ_CONTROL_3() (REG32(ADR_RF_IQ_CONTROL_3)) = (0x00000000)
+#define DEF_DPD_CONTROL() (REG32(ADR_DPD_CONTROL)) = (0x00000000)
+#define DEF_DPD_GAIN_TABLE_0() (REG32(ADR_DPD_GAIN_TABLE_0)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_1() (REG32(ADR_DPD_GAIN_TABLE_1)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_2() (REG32(ADR_DPD_GAIN_TABLE_2)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_3() (REG32(ADR_DPD_GAIN_TABLE_3)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_4() (REG32(ADR_DPD_GAIN_TABLE_4)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_5() (REG32(ADR_DPD_GAIN_TABLE_5)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_6() (REG32(ADR_DPD_GAIN_TABLE_6)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_7() (REG32(ADR_DPD_GAIN_TABLE_7)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_8() (REG32(ADR_DPD_GAIN_TABLE_8)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_9() (REG32(ADR_DPD_GAIN_TABLE_9)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_A() (REG32(ADR_DPD_GAIN_TABLE_A)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_B() (REG32(ADR_DPD_GAIN_TABLE_B)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_C() (REG32(ADR_DPD_GAIN_TABLE_C)) = (0x02000200)
+#define DEF_DPD_PH_TABLE_0() (REG32(ADR_DPD_PH_TABLE_0)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_1() (REG32(ADR_DPD_PH_TABLE_1)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_2() (REG32(ADR_DPD_PH_TABLE_2)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_3() (REG32(ADR_DPD_PH_TABLE_3)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_4() (REG32(ADR_DPD_PH_TABLE_4)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_5() (REG32(ADR_DPD_PH_TABLE_5)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_6() (REG32(ADR_DPD_PH_TABLE_6)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_7() (REG32(ADR_DPD_PH_TABLE_7)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_8() (REG32(ADR_DPD_PH_TABLE_8)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_9() (REG32(ADR_DPD_PH_TABLE_9)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_A() (REG32(ADR_DPD_PH_TABLE_A)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_B() (REG32(ADR_DPD_PH_TABLE_B)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_C() (REG32(ADR_DPD_PH_TABLE_C)) = (0x00000000)
+#define DEF_DPD_GAIN_ESTIMATION_0() (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (0x00000000)
+#define DEF_DPD_GAIN_ESTIMATION_1() (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (0x00000100)
+#define DEF_DPD_GAIN_ESTIMATION_2() (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (0x00000000)
+#define DEF_TX_GAIN_FACTOR() (REG32(ADR_TX_GAIN_FACTOR)) = (0x80808080)
+#define DEF_HARD_WIRE_PIN_REGISTER() (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
+#define DEF_MANUAL_ENABLE_REGISTER() (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (0x00000fc0)
+#define DEF_LDO_REGISTER() (REG32(ADR_LDO_REGISTER)) = (0x000db71b)
+#define DEF_ABB_REGISTER_1() (REG32(ADR_ABB_REGISTER_1)) = (0x151558dd)
+#define DEF_ABB_REGISTER_2() (REG32(ADR_ABB_REGISTER_2)) = (0x01011a88)
+#define DEF_TX_FE_REGISTER() (REG32(ADR_TX_FE_REGISTER)) = (0x3d3e84fe)
+#define DEF_RX_FE_REGISTER_1() (REG32(ADR_RX_FE_REGISTER_1)) = (0x03457579)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
+#define DEF_RX_TX_FSM_REGISTER() (REG32(ADR_RX_TX_FSM_REGISTER)) = (0x00030ca8)
+#define DEF_RX_ADC_REGISTER() (REG32(ADR_RX_ADC_REGISTER)) = (0x20ea0224)
+#define DEF_TX_DAC_REGISTER() (REG32(ADR_TX_DAC_REGISTER)) = (0x44000655)
+#define DEF_SX_ENABLE_REGISTER() (REG32(ADR_SX_ENABLE_REGISTER)) = (0x0003e07c)
+#define DEF_SYN_REGISTER_1() (REG32(ADR_SYN_REGISTER_1)) = (0xaa800000)
+#define DEF_SYN_REGISTER_2() (REG32(ADR_SYN_REGISTER_2)) = (0x00550800)
+#define DEF_SYN_PFD_CHP() (REG32(ADR_SYN_PFD_CHP)) = (0x07c0894a)
+#define DEF_SYN_VCO_LOBF() (REG32(ADR_SYN_VCO_LOBF)) = (0xfcccca27)
+#define DEF_SYN_DIV_SDM_XOSC() (REG32(ADR_SYN_DIV_SDM_XOSC)) = (0x07700830)
+#define DEF_SYN_KVCO_XO_FINE_TUNE_CBANK() (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (0x00440000)
+#define DEF_SYN_LCK_VT() (REG32(ADR_SYN_LCK_VT)) = (0x00007ff4)
+#define DEF_DPLL_VCO_REGISTER() (REG32(ADR_DPLL_VCO_REGISTER)) = (0x0000000e)
+#define DEF_DPLL_CP_PFD_REGISTER() (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (0x00088008)
+#define DEF_DPLL_DIVIDER_REGISTER() (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (0x00406000)
+#define DEF_DCOC_IDAC_REGISTER1() (REG32(ADR_DCOC_IDAC_REGISTER1)) = (0x08820820)
+#define DEF_DCOC_IDAC_REGISTER2() (REG32(ADR_DCOC_IDAC_REGISTER2)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER3() (REG32(ADR_DCOC_IDAC_REGISTER3)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER4() (REG32(ADR_DCOC_IDAC_REGISTER4)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER5() (REG32(ADR_DCOC_IDAC_REGISTER5)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER6() (REG32(ADR_DCOC_IDAC_REGISTER6)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER7() (REG32(ADR_DCOC_IDAC_REGISTER7)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER8() (REG32(ADR_DCOC_IDAC_REGISTER8)) = (0x00820820)
+#define DEF_RCAL_REGISTER() (REG32(ADR_RCAL_REGISTER)) = (0x00004080)
+#define DEF_SX_LCK_BIN_REGISTERS_I() (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (0x20080080)
+#define DEF_TRX_DUMMY_REGISTER() (REG32(ADR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_SX_DUMMY_REGISTER() (REG32(ADR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_DPLL_FB_DIVIDER_REGISTERS_II() (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (0x00ec2ec5)
+#define DEF_SX_LCK_BIN_REGISTERS_II() (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (0x00000f13)
+#define DEF_RC_OSC_32K_CAL_REGISTERS() (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (0x00098900)
+#define DEF_RF_D_DIGITAL_DEBUG_PORT_REGISTER() (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (0x00000000)
+#define DEF_MMU_CTRL() (REG32(ADR_MMU_CTRL)) = (0x00002042)
+#define DEF_HS_CTRL() (REG32(ADR_HS_CTRL)) = (0x00000000)
+#define DEF_CPU_POR0_7() (REG32(ADR_CPU_POR0_7)) = (0x00000000)
+#define DEF_CPU_POR8_F() (REG32(ADR_CPU_POR8_F)) = (0x00000000)
+#define DEF_REG_LEN_CTRL() (REG32(ADR_REG_LEN_CTRL)) = (0x00000f0f)
+#define DEF_DMN_READ_BYPASS() (REG32(ADR_DMN_READ_BYPASS)) = (0x0000ffff)
+#define DEF_ALC_RLS_ABORT() (REG32(ADR_ALC_RLS_ABORT)) = (0x00000000)
+#define DEF_DEBUG_CTL() (REG32(ADR_DEBUG_CTL)) = (0x00000000)
+#define DEF_DEBUG_OUT() (REG32(ADR_DEBUG_OUT)) = (0x00000000)
+#define DEF_MMU_STATUS() (REG32(ADR_MMU_STATUS)) = (0x00000000)
+#define DEF_DMN_STATUS() (REG32(ADR_DMN_STATUS)) = (0x00000000)
+#define DEF_TAG_STATUS() (REG32(ADR_TAG_STATUS)) = (0x00000000)
+#define DEF_DMN_MCU_STATUS() (REG32(ADR_DMN_MCU_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_0_STATUS() (REG32(ADR_MB_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_1_STATUS() (REG32(ADR_MB_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_2_STATUS() (REG32(ADR_MB_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_3_STATUS() (REG32(ADR_MB_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_0_STATUS() (REG32(ADR_PKT_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_1_STATUS() (REG32(ADR_PKT_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_2_STATUS() (REG32(ADR_PKT_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_3_STATUS() (REG32(ADR_PKT_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_0_STATUS() (REG32(ADR_DMN_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_1_STATUS() (REG32(ADR_DMN_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_2_STATUS() (REG32(ADR_DMN_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_3_STATUS() (REG32(ADR_DMN_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_0_STATUS() (REG32(ADR_MB_NEQID_0_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_1_STATUS() (REG32(ADR_MB_NEQID_1_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_2_STATUS() (REG32(ADR_MB_NEQID_2_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_3_STATUS() (REG32(ADR_MB_NEQID_3_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_0_STATUS() (REG32(ADR_PKT_NEQID_0_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_1_STATUS() (REG32(ADR_PKT_NEQID_1_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_2_STATUS() (REG32(ADR_PKT_NEQID_2_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_3_STATUS() (REG32(ADR_PKT_NEQID_3_STATUS)) = (0x00000000)
+#define DEF_ALC_NOCHG_ID_STATUS() (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_0() (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_1() (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_2() (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_3() (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_4() (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_5() (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_6() (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_7() (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (0x00000000)
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h b/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
new file mode 100644
index 000000000000..e15a481ba300
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "ssv6200_reg.h"
+#define BANK_COUNT 49
+static const u32 BASE_BANK_SSV6200[] = {
+ SYS_REG_BASE,
+ WBOOT_REG_BASE,
+ TU0_US_REG_BASE,
+ TU1_US_REG_BASE,
+ TU2_US_REG_BASE,
+ TU3_US_REG_BASE,
+ TM0_MS_REG_BASE,
+ TM1_MS_REG_BASE,
+ TM2_MS_REG_BASE,
+ TM3_MS_REG_BASE,
+ MCU_WDT_REG_BASE,
+ SYS_WDT_REG_BASE,
+ GPIO_REG_BASE,
+ SD_REG_BASE,
+ SPI_REG_BASE,
+ CSR_I2C_MST_BASE,
+ UART_REG_BASE,
+ DAT_UART_REG_BASE,
+ INT_REG_BASE,
+ DBG_SPI_REG_BASE,
+ FLASH_SPI_REG_BASE,
+ DMA_REG_BASE,
+ CSR_PMU_BASE,
+ CSR_RTC_BASE,
+ RTC_RAM_BASE,
+ D2_DMA_REG_BASE,
+ HCI_REG_BASE,
+ CO_REG_BASE,
+ EFS_REG_BASE,
+ SMS4_REG_BASE,
+ MRX_REG_BASE,
+ AMPDU_REG_BASE,
+ MT_REG_CSR_BASE,
+ TXQ0_MT_Q_REG_CSR_BASE,
+ TXQ1_MT_Q_REG_CSR_BASE,
+ TXQ2_MT_Q_REG_CSR_BASE,
+ TXQ3_MT_Q_REG_CSR_BASE,
+ TXQ4_MT_Q_REG_CSR_BASE,
+ HIF_INFO_BASE,
+ PHY_RATE_INFO_BASE,
+ MAC_GLB_SET_BASE,
+ BTCX_REG_BASE,
+ MIB_REG_BASE,
+ CBR_A_REG_BASE,
+ MB_REG_BASE,
+ ID_MNG_REG_BASE,
+ CSR_PHY_BASE,
+ CSR_RF_BASE,
+ MMU_REG_BASE,
+ 0x00000000
+};
+
+static const char *STR_BANK_SSV6200[] = {
+ "SYS_REG",
+ "WBOOT_REG",
+ "TU0_US_REG",
+ "TU1_US_REG",
+ "TU2_US_REG",
+ "TU3_US_REG",
+ "TM0_MS_REG",
+ "TM1_MS_REG",
+ "TM2_MS_REG",
+ "TM3_MS_REG",
+ "MCU_WDT_REG",
+ "SYS_WDT_REG",
+ "GPIO_REG",
+ "SD_REG",
+ "SPI_REG",
+ "CSR_I2C_MST",
+ "UART_REG",
+ "DAT_UART_REG",
+ "INT_REG",
+ "DBG_SPI_REG",
+ "FLASH_SPI_REG",
+ "DMA_REG",
+ "CSR_PMU",
+ "CSR_RTC",
+ "RTC_RAM",
+ "D2_DMA_REG",
+ "HCI_REG",
+ "CO_REG",
+ "EFS_REG",
+ "SMS4_REG",
+ "MRX_REG",
+ "AMPDU_REG",
+ "MT_REG_CSR",
+ "TXQ0_MT_Q_REG_CSR",
+ "TXQ1_MT_Q_REG_CSR",
+ "TXQ2_MT_Q_REG_CSR",
+ "TXQ3_MT_Q_REG_CSR",
+ "TXQ4_MT_Q_REG_CSR",
+ "HIF_INFO",
+ "PHY_RATE_INFO",
+ "MAC_GLB_SET",
+ "BTCX_REG",
+ "MIB_REG",
+ "CBR_A_REG",
+ "MB_REG",
+ "ID_MNG_REG",
+ "CSR_PHY",
+ "CSR_RF",
+ "MMU_REG",
+ ""
+};
+
+static const u32 SIZE_BANK_SSV6200[] = {
+ SYS_REG_BANK_SIZE,
+ WBOOT_REG_BANK_SIZE,
+ TU0_US_REG_BANK_SIZE,
+ TU1_US_REG_BANK_SIZE,
+ TU2_US_REG_BANK_SIZE,
+ TU3_US_REG_BANK_SIZE,
+ TM0_MS_REG_BANK_SIZE,
+ TM1_MS_REG_BANK_SIZE,
+ TM2_MS_REG_BANK_SIZE,
+ TM3_MS_REG_BANK_SIZE,
+ MCU_WDT_REG_BANK_SIZE,
+ SYS_WDT_REG_BANK_SIZE,
+ GPIO_REG_BANK_SIZE,
+ SD_REG_BANK_SIZE,
+ SPI_REG_BANK_SIZE,
+ CSR_I2C_MST_BANK_SIZE,
+ UART_REG_BANK_SIZE,
+ DAT_UART_REG_BANK_SIZE,
+ INT_REG_BANK_SIZE,
+ DBG_SPI_REG_BANK_SIZE,
+ FLASH_SPI_REG_BANK_SIZE,
+ DMA_REG_BANK_SIZE,
+ CSR_PMU_BANK_SIZE,
+ CSR_RTC_BANK_SIZE,
+ RTC_RAM_BANK_SIZE,
+ D2_DMA_REG_BANK_SIZE,
+ HCI_REG_BANK_SIZE,
+ CO_REG_BANK_SIZE,
+ EFS_REG_BANK_SIZE,
+ SMS4_REG_BANK_SIZE,
+ MRX_REG_BANK_SIZE,
+ AMPDU_REG_BANK_SIZE,
+ MT_REG_CSR_BANK_SIZE,
+ TXQ0_MT_Q_REG_CSR_BANK_SIZE,
+ TXQ1_MT_Q_REG_CSR_BANK_SIZE,
+ TXQ2_MT_Q_REG_CSR_BANK_SIZE,
+ TXQ3_MT_Q_REG_CSR_BANK_SIZE,
+ TXQ4_MT_Q_REG_CSR_BANK_SIZE,
+ HIF_INFO_BANK_SIZE,
+ PHY_RATE_INFO_BANK_SIZE,
+ MAC_GLB_SET_BANK_SIZE,
+ BTCX_REG_BANK_SIZE,
+ MIB_REG_BANK_SIZE,
+ CBR_A_REG_BANK_SIZE,
+ MB_REG_BANK_SIZE,
+ ID_MNG_REG_BANK_SIZE,
+ CSR_PHY_BANK_SIZE,
+ CSR_RF_BANK_SIZE,
+ MMU_REG_BANK_SIZE,
+ 0x00000000
+};
diff --git a/drivers/net/wireless/ssv6051/include/ssv_cfg.h b/drivers/net/wireless/ssv6051/include/ssv_cfg.h
new file mode 100644
index 000000000000..79b75619936e
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv_cfg.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_CFG_H_
+#define _SSV_CFG_H_
+#define SSV6200_HW_CAP_HT 0x00000001
+#define SSV6200_HW_CAP_GF 0x00000002
+#define SSV6200_HW_CAP_2GHZ 0x00000004
+#define SSV6200_HW_CAP_5GHZ 0x00000008
+#define SSV6200_HW_CAP_SECURITY 0x00000010
+#define SSV6200_HT_CAP_SGI_20 0x00000020
+#define SSV6200_HT_CAP_SGI_40 0x00000040
+#define SSV6200_HW_CAP_AP 0x00000080
+#define SSV6200_HW_CAP_P2P 0x00000100
+#define SSV6200_HW_CAP_AMPDU_RX 0x00000200
+#define SSV6200_HW_CAP_AMPDU_TX 0x00000400
+#define SSV6200_HW_CAP_TDLS 0x00000800
+#define EXTERNEL_CONFIG_SUPPORT 64
+struct ssv6xxx_cfg {
+ u32 hw_caps;
+ u32 def_chan;
+ u32 crystal_type;
+ u32 volt_regulator;
+ u32 force_chip_identity;
+ u8 maddr[2][6];
+ u32 n_maddr;
+ u32 use_wpa2_only;
+ u32 ignore_reset_in_ap;
+ u32 r_calbration_result;
+ u32 sar_result;
+ u32 crystal_frequency_offset;
+ u32 tx_power_index_1;
+ u32 tx_power_index_2;
+ u32 chip_identity;
+ u32 wifi_tx_gain_level_gn;
+ u32 wifi_tx_gain_level_b;
+ u32 rssi_ctl;
+ u32 sr_bhvr;
+ u32 configuration[EXTERNEL_CONFIG_SUPPORT + 1][2];
+ u8 firmware_path[128];
+ u8 flash_bin_path[128];
+ u8 mac_address_path[128];
+ u8 mac_output_path[128];
+ u32 ignore_efuse_mac;
+ u32 mac_address_mode;
+};
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h b/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
new file mode 100644
index 000000000000..7fabbe308f9d
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_FIRMWARE_VERSION_H_
+#define _SSV_FIRMWARE_VERSION_H_
+static u32 ssv_firmware_version = 16380;
+#define SSV_FIRMWARE_URl "http://192.168.15.30/svn/software/wifi/tag/smac-release-tag/6051.Q0.1009.21.000000/ssv6xxx/smac/firmware"
+#define FIRMWARE_COMPILERHOST "ssv-ThinkPad-X230"
+#define FIRMWARE_COMPILERDATE "11-06-2017-09:17:18"
+#define FIRMWARE_COMPILEROS "linux"
+#define FIRMWARE_COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv_version.h b/drivers/net/wireless/ssv6051/include/ssv_version.h
new file mode 100644
index 000000000000..99be5354f783
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv_version.h
@@ -0,0 +1,12 @@
+#ifndef _SSV_VERSION_H_
+#define _SSV_VERSION_H_
+
+static u32 ssv_root_version = 16529;
+
+#define SSV_ROOT_URl "http://192.168.15.30/svn/software/project/release/android/box/rk3x28/6051.Q0.1009.21.400401/ssv6xxx"
+#define COMPILERHOST "icomm-buildserver-T320"
+#define COMPILERDATE "12-08-2017-10:34:54"
+#define COMPILEROS "linux"
+#define COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
+
+#endif
diff --git a/drivers/net/wireless/ssv6051/platform-config.mak b/drivers/net/wireless/ssv6051/platform-config.mak
new file mode 100644
index 000000000000..b1b6f0510d28
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/platform-config.mak
@@ -0,0 +1,97 @@
+
+ccflags-y += -DCONFIG_SSV6200_CORE
+
+###########################################################################
+# Compiler options #
+###########################################################################
+
+# Enable -g to help debug. Deassembly from .o to .S would help to track to
+# the problomatic line from call stack dump.
+#ccflags-y += -g
+ccflags += -Os
+
+############################################################
+# If you change the settings, please change the file synchronization
+# smac\firmware\include\config.h & compiler firmware
+############################################################
+#ccflags-y += -DCONFIG_SSV_CABRIO_A
+ccflags-y += -DCONFIG_SSV_CABRIO_E
+
+#CONFIG_SSV_SUPPORT_BTCX=y
+
+#ccflags-y += -DDEBUG
+ccflags-y += -DCONFIG_SSV6200_CLI_ENABLE
+
+#PADPD
+#ccflags-y += -DCONFIG_SSV_DPD
+
+#ccflags-y += -DCONFIG_SSV_CABRIO_MB_DEBUG
+#ccflags-y += -DCONFIG_SSV6XXX_DEBUGFS
+
+#SDIO
+ccflags-y += -DCONFIG_SSV_TX_LOWTHRESHOLD
+
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+#ccflags-y += -DKTHREAD_BIND
+#ccflags-y += -DROCKCHIP_WIFI_AUTO_SUPPORT
+ccflags-y += -DCONFIG_SSV_RSSI
+ccflags-y += -DCONFIG_SSV_VENDOR_EXT_SUPPORT
+
+############################################################
+# Rate control update for MPDU.
+############################################################
+ccflags-y += -DRATE_CONTROL_REALTIME_UPDATA
+
+#workaround
+#ccflags-y += -DCONFIG_SSV_CABRIO_EXT_PA
+
+############################################################
+# NOTE:
+# Only one of the following flags could be turned on.
+# It also turned off the following flags. In this case,
+# pure software security or pure hardware security is used.
+#
+############################################################
+#ccflags-y += -DCONFIG_SSV_SW_ENCRYPT_HW_DECRYPT
+#ccflags-y += -DCONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
+
+# FOR WFA
+#ccflags-y += -DWIFI_CERTIFIED
+
+#ccflags-y += -DCONFIG_SSV_SDIO_EXT_INT
+
+#######################################################
+ccflags-y += -DCONFIG_SSV6200_HAS_RX_WORKQUEUE
+#ccflags-y += -DUSE_THREAD_RX
+ccflags-y += -DUSE_THREAD_TX
+ccflags-y += -DENABLE_AGGREGATE_IN_TIME
+ccflags-y += -DENABLE_INCREMENTAL_AGGREGATION
+
+# Generic decision table applicable to both AP and STA modes.
+ccflags-y += -DUSE_GENERIC_DECI_TBL
+
+#ccflags-y += -DCONFIG_SSV_WAPI
+
+ccflags-y += -DFW_WSID_WATCH_LIST
+#ccflags-y += -DUSE_BATCH_RX
+#ccflags-y += -DCONFIG_IRQ_DEBUG_COUNT
+
+ccflags-y += -DSSV6200_ECO
+#ccflags-y += -DENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+ccflags-y += -DHAS_CRYPTO_LOCK
+ccflags-y += -DENABLE_TX_Q_FLOW_CONTROL
+
+#ccflags-y += -DCONFIG_DEBUG_SKB_TIMESTAMP
+
+
+#enable p2p client to parse GO broadcast noa
+#ccflags-y += -DCONFIG_P2P_NOA
+
+#enable rx management frame check
+#ccflags-y += -DCONFIG_RX_MGMT_CHECK
+
+#force SW Broadcast/Multicast decryption
+ccflags-y += -DUSE_MAC80211_DECRYPT_BROADCAST
\ No newline at end of file
diff --git a/drivers/net/wireless/ssv6051/rules.mak b/drivers/net/wireless/ssv6051/rules.mak
new file mode 100644
index 000000000000..b3262852249c
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/rules.mak
@@ -0,0 +1,19 @@
+
+
+$(KMODULE_NAME)-y += $(KERN_SRCS:.c=.o)
+obj-$(CONFIG_SSV6200_CORE) += $(KMODULE_NAME).o
+
+
+.PHONY: all clean install
+
+all:
+ @$(MAKE) -C /lib/modules/$(KVERSION)/build \
+ SUBDIRS=$(KBUILD_DIR) CONFIG_DEBUG_SECTION_MISMATCH=y \
+ modules
+
+clean:
+ @$(MAKE) -C /lib/modules/$(KVERSION)/build SUBDIRS=$(KBUILD_DIR) clean
+
+install:
+ @$(MAKE) INSTALL_MOD_DIR=$(DRVPATH) -C /lib/modules/$(KVERSION)/build \
+ M=$(KBUILD_DIR) modules_install
diff --git a/drivers/net/wireless/ssv6051/smac/ampdu.c b/drivers/net/wireless/ssv6051/smac/ampdu.c
new file mode 100644
index 000000000000..846830f3d209
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ampdu.c
@@ -0,0 +1,2111 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ap.h"
+#include "sec.h"
+#include "ssv_rc_common.h"
+#include "ssv_ht_rc.h"
+extern struct ieee80211_ops ssv6200_ops;
+
+// Hack: redefine MAX_AMPDU_BUF because buf_size here is a 8-bit char
+// and mainline kernel value is 0x100, which overflows
+#ifdef IEEE80211_MAX_AMPDU_BUF
+#undef IEEE80211_MAX_AMPDU_BUF
+#endif
+#define IEEE80211_MAX_AMPDU_BUF 0x40
+
+#define BA_WAIT_TIMEOUT (800)
+#define AMPDU_BA_FRAME_LEN (68)
+#define ampdu_skb_hdr(skb) ((struct ieee80211_hdr*)((u8*)((skb)->data)+AMPDU_DELIMITER_LEN))
+#define ampdu_skb_ssn(skb) ((ampdu_skb_hdr(skb)->seq_ctrl)>>SSV_SEQ_NUM_SHIFT)
+#define ampdu_hdr_ssn(hdr) ((hdr)->seq_ctrl>>SSV_SEQ_NUM_SHIFT)
+#undef prn_aggr_dbg
+#define prn_aggr_dbg(fmt,...)
+static void void_func(const char *fmt, ...)
+{
+}
+
+#define prn_aggr_err(fmt,...) \
+ do { \
+ void_func(KERN_ERR fmt, ##__VA_ARGS__);\
+ } while (0)
+#define get_tid_aggr_len(agg_len,tid_data) \
+ ({ \
+ u32 agg_max_num = (tid_data)->agg_num_max; \
+ u32 to_agg_len = (agg_len); \
+ (agg_len >= agg_max_num) ? agg_max_num : to_agg_len; \
+ })
+#define INDEX_PKT_BY_SSN(tid,ssn) \
+ ((tid)->aggr_pkts[(ssn) % SSV_AMPDU_BA_WINDOW_SIZE])
+#define NEXT_PKT_SN(sn) \
+ ({ (sn + 1) % SSV_AMPDU_MAX_SSN; })
+#define INC_PKT_SN(sn) \
+ ({ \
+ sn = NEXT_PKT_SN(sn); \
+ sn; \
+ })
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+static ssize_t ampdu_tx_mib_dump(struct ssv_sta_priv_data *ssv_sta_priv,
+ char *mib_str, ssize_t length);
+static int _dump_ba_skb(char *buf, int buf_size, struct sk_buff *ba_skb);
+#endif
+static struct sk_buff *_aggr_retry_mpdu(struct ssv_softc *sc,
+ struct AMPDU_TID_st *cur_AMPDU_TID,
+ struct sk_buff_head *retry_queue,
+ u32 max_aggr_len);
+static int _dump_BA_notification(char *buf,
+ struct ampdu_ba_notify_data *ba_notification);
+static struct sk_buff *_alloc_ampdu_skb(struct ssv_softc *sc,
+ struct AMPDU_TID_st *ampdu_tid,
+ u32 len);
+static bool _sync_ampdu_pkt_arr(struct AMPDU_TID_st *ampdu_tid,
+ struct sk_buff *ampdu_skb, bool retry);
+static void _put_mpdu_to_ampdu(struct sk_buff *ampdu, struct sk_buff *mpdu);
+static void _add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb);
+static u32 _flush_early_ampdu_q(struct ssv_softc *sc,
+ struct AMPDU_TID_st *ampdu_tid);
+static bool _is_skb_q_empty(struct ssv_softc *sc, struct sk_buff *skb);
+static void _aggr_ampdu_tx_q(struct ieee80211_hw *hw,
+ struct AMPDU_TID_st *ampdu_tid);
+static void _queue_early_ampdu(struct ssv_softc *sc,
+ struct AMPDU_TID_st *ampdu_tid,
+ struct sk_buff *ampdu_skb);
+static int _mark_skb_retry(struct SKB_info_st *skb_info, struct sk_buff *skb);
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage)
+{
+ unsigned int timeout;
+ SKB_info *mpdu_skb_info;
+ u16 ssn = 0;
+ struct sk_buff *mpdu = NULL;
+ struct ampdu_hdr_st *ampdu_hdr = NULL;
+ ktime_t current_ktime;
+ ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
+ ssn = ampdu_hdr->ssn[0];
+ mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn);
+ if (mpdu == NULL)
+ return 0;
+ mpdu_skb_info = (SKB_info *) (mpdu->head);
+ current_ktime = ktime_get();
+ timeout =
+ (unsigned int)
+ ktime_to_ms(ktime_sub(current_ktime, mpdu_skb_info->timestamp));
+ if (timeout > SKB_DURATION_TIMEOUT_MS) {
+ if (stage == SKB_DURATION_STAGE_TO_SDIO)
+ pr_debug("*a_to_sdio: %ums\n", timeout);
+ else if (stage == SKB_DURATION_STAGE_TX_ENQ)
+ pr_debug("*a_to_txenqueue: %ums\n", timeout);
+ else
+ pr_debug("*a_in_hwq: %ums\n", timeout);
+ }
+ return timeout;
+}
+#endif
+static u8 _cal_ampdu_delm_half_crc(u8 value)
+{
+ u32 c32 = value, v32 = value;
+ c32 ^= (v32 >> 1) | (v32 << 7);
+ c32 ^= (v32 >> 2);
+ if (v32 & 2)
+ c32 ^= (0xC0);
+ c32 ^= ((v32 << 4) & 0x30);
+ return (u8) c32;
+}
+
+static u8 _cal_ampdu_delm_crc(u8 * pointer)
+{
+ u8 crc = 0xCF;
+ crc ^= _cal_ampdu_delm_half_crc(*pointer++);
+ crc =
+ _cal_ampdu_delm_half_crc(crc) ^ _cal_ampdu_delm_half_crc(*pointer);
+ return ~crc;
+}
+
+static bool ssv6200_ampdu_add_delimiter_and_crc32(struct sk_buff *mpdu)
+{
+ p_AMPDU_DELIMITER delimiter_p;
+ struct ieee80211_hdr *mpdu_hdr;
+ int ret;
+ u32 orig_mpdu_len = mpdu->len;
+ u32 pad = (4 - (orig_mpdu_len % 4)) % 4;
+ mpdu_hdr = (struct ieee80211_hdr *)(mpdu->data);
+ mpdu_hdr->duration_id = AMPDU_TX_NAV_MCS_567;
+ ret = skb_padto(mpdu, mpdu->len + (AMPDU_FCS_LEN + pad));
+ if (ret) {
+ pr_err("Failed to extand skb for aggregation\n");
+ return false;
+ }
+ skb_put(mpdu, AMPDU_FCS_LEN + pad);
+ skb_push(mpdu, AMPDU_DELIMITER_LEN);
+ delimiter_p = (p_AMPDU_DELIMITER) mpdu->data;
+ delimiter_p->reserved = 0;
+ delimiter_p->length = orig_mpdu_len + AMPDU_FCS_LEN;
+ delimiter_p->signature = AMPDU_SIGNATURE;
+ delimiter_p->crc = _cal_ampdu_delm_crc((u8 *) (delimiter_p));
+ return true;
+}
+
+static void ssv6200_ampdu_hw_init(struct ieee80211_hw *hw)
+{
+ struct ssv_softc *sc = hw->priv;
+ u32 temp32;
+ SMAC_REG_READ(sc->sh, ADR_MTX_MISC_EN, &temp32);
+ temp32 |= (0x1 << MTX_AMPDU_CRC_AUTO_SFT);
+ SMAC_REG_WRITE(sc->sh, ADR_MTX_MISC_EN, temp32);
+ SMAC_REG_READ(sc->sh, ADR_MTX_MISC_EN, &temp32);
+}
+
+bool _sync_ampdu_pkt_arr(struct AMPDU_TID_st *ampdu_tid, struct sk_buff *ampdu,
+ bool retry)
+{
+ struct sk_buff **pp_aggr_pkt;
+ struct sk_buff *p_aggr_pkt;
+ unsigned long flags;
+ struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
+ struct sk_buff *mpdu;
+ u32 first_ssn = SSV_ILLEGAL_SN;
+ u32 old_aggr_pkt_num;
+ u32 old_baw_head;
+ u32 sync_num = skb_queue_len(&ampdu_hdr->mpdu_q);
+ bool ret = true;
+ spin_lock_irqsave(&ampdu_tid->pkt_array_lock, flags);
+ old_baw_head = ampdu_tid->ssv_baw_head;
+ old_aggr_pkt_num = ampdu_tid->aggr_pkt_num;
+ ampdu_tid->mib.ampdu_mib_ampdu_counter += 1;
+ ampdu_tid->mib.ampdu_mib_dist[sync_num] += 1;
+ do {
+ if (!retry) {
+ ampdu_tid->mib.ampdu_mib_mpdu_counter += sync_num;
+ mpdu = skb_peek_tail(&ampdu_hdr->mpdu_q);
+ if (mpdu == NULL) {
+ ret = false;
+ break;
+ } else {
+ u32 ssn = ampdu_skb_ssn(mpdu);
+ p_aggr_pkt = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+ if (p_aggr_pkt != NULL) {
+ char msg[256];
+ u32 sn = ampdu_skb_ssn(mpdu);
+ skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
+ sn = ampdu_skb_ssn(mpdu);
+ sprintf(msg, " %d", sn);
+ }
+ prn_aggr_err("ES %d -> %d (%s)\n",
+ ssn,
+ ampdu_skb_ssn(p_aggr_pkt),
+ msg);
+ ret = false;
+ break;
+ }
+ }
+ } else
+ ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1;
+ skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
+ u32 ssn = ampdu_skb_ssn(mpdu);
+ SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head);
+ if (first_ssn == SSV_ILLEGAL_SN)
+ first_ssn = ssn;
+ pp_aggr_pkt = &INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+ p_aggr_pkt = *pp_aggr_pkt;
+ *pp_aggr_pkt = mpdu;
+ if (!retry)
+ ampdu_tid->aggr_pkt_num++;
+ mpdu_skb_info->ampdu_tx_status = AMPDU_ST_AGGREGATED;
+ if (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN) {
+ ampdu_tid->ssv_baw_head = ssn;
+ }
+ if ((p_aggr_pkt != NULL) && (mpdu != p_aggr_pkt))
+ prn_aggr_err("%d -> %d (H%d, N%d, Q%d)\n",
+ ssn, ampdu_skb_ssn(p_aggr_pkt),
+ old_baw_head, old_aggr_pkt_num,
+ sync_num);
+ }
+ } while (0);
+ spin_unlock_irqrestore(&ampdu_tid->pkt_array_lock, flags);
+ {
+ u32 page_count = (ampdu->len + SSV6200_ALLOC_RSVD);
+ if (page_count & HW_MMU_PAGE_MASK)
+ page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
+ else
+ page_count = page_count >> HW_MMU_PAGE_SHIFT;
+ if (page_count > (SSV6200_PAGE_TX_THRESHOLD / 2))
+ pr_err("AMPDU requires pages %d(%d-%d-%d) exceeds resource limit %d.\n",
+ page_count, ampdu->len, ampdu_hdr->max_size,
+ ampdu_hdr->size,
+ (SSV6200_PAGE_TX_THRESHOLD / 2));
+ }
+ return ret;
+}
+
+struct sk_buff *_aggr_retry_mpdu(struct ssv_softc *sc,
+ struct AMPDU_TID_st *ampdu_tid,
+ struct sk_buff_head *retry_queue,
+ u32 max_aggr_len)
+{
+ struct sk_buff *retry_mpdu;
+ struct sk_buff *new_ampdu_skb;
+ u32 num_retry_mpdu;
+ u32 temp_i;
+ u32 total_skb_size;
+ unsigned long flags;
+ u16 head_ssn = ampdu_tid->ssv_baw_head;
+ struct ampdu_hdr_st *ampdu_hdr;
+ BUG_ON(head_ssn == SSV_ILLEGAL_SN);
+ num_retry_mpdu = skb_queue_len(retry_queue);
+ if (num_retry_mpdu == 0)
+ return NULL;
+ new_ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, max_aggr_len);
+ if (new_ampdu_skb == 0)
+ return NULL;
+ ampdu_hdr = (struct ampdu_hdr_st *)new_ampdu_skb->head;
+ total_skb_size = 0;
+ spin_lock_irqsave(&retry_queue->lock, flags);
+ for (temp_i = 0; temp_i < ampdu_tid->agg_num_max; temp_i++) {
+ struct ieee80211_hdr *mpdu_hdr;
+ u16 mpdu_sn;
+ u16 diff;
+ u32 new_total_skb_size;
+ retry_mpdu = skb_peek(retry_queue);
+ if (retry_mpdu == NULL) {
+ break;
+ }
+ mpdu_hdr = ampdu_skb_hdr(retry_mpdu);
+ mpdu_sn = ampdu_hdr_ssn(mpdu_hdr);
+ diff = SSV_AMPDU_SN_a_minus_b(head_ssn, mpdu_sn);
+ if ((head_ssn != SSV_ILLEGAL_SN)
+ && (diff > 0)
+ && (diff <= ampdu_tid->ssv_baw_size)) {
+ struct SKB_info_st *skb_info;
+ prn_aggr_err("Z. release skb (s %d, h %d, d %d)\n",
+ mpdu_sn, head_ssn, diff);
+ skb_info = (struct SKB_info_st *)(retry_mpdu->head);
+ skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
+ ampdu_tid->mib.ampdu_mib_discard_counter++;
+ continue;
+ }
+ new_total_skb_size = total_skb_size + retry_mpdu->len;
+ if (new_total_skb_size > ampdu_hdr->max_size)
+ break;
+ total_skb_size = new_total_skb_size;
+ retry_mpdu = __skb_dequeue(retry_queue);
+ _put_mpdu_to_ampdu(new_ampdu_skb, retry_mpdu);
+ ampdu_tid->mib.ampdu_mib_retry_counter++;
+ }
+ ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1;
+ ampdu_tid->mib.ampdu_mib_dist[temp_i] += 1;
+ spin_unlock_irqrestore(&retry_queue->lock, flags);
+ if (ampdu_hdr->mpdu_num == 0) {
+ dev_kfree_skb_any(new_ampdu_skb);
+ return NULL;
+ }
+ return new_ampdu_skb;
+}
+
+static void _add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb)
+{
+ struct ssv6200_tx_desc *tx_desc;
+ ssv6xxx_add_txinfo(sc, ampdu_skb);
+ tx_desc = (struct ssv6200_tx_desc *)ampdu_skb->data;
+ tx_desc->tx_report = 1;
+}
+
+void _send_hci_skb(struct ssv_softc *sc, struct sk_buff *skb, u32 tx_flag)
+{
+ struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data;
+ int ret = AMPDU_HCI_SEND(sc->sh, skb, tx_desc->txq_idx, tx_flag);
+ if ((tx_desc->txq_idx > 3) && (ret <= 0)) {
+ prn_aggr_err("BUG!! %d %d\n", tx_desc->txq_idx, ret);
+ }
+}
+
+static void ssv6200_ampdu_add_txinfo_and_send_HCI(struct ssv_softc *sc,
+ struct sk_buff *ampdu_skb,
+ u32 tx_flag)
+{
+ _add_ampdu_txinfo(sc, ampdu_skb);
+ _send_hci_skb(sc, ampdu_skb, tx_flag);
+}
+
+static void ssv6200_ampdu_send_retry(struct ieee80211_hw *hw,
+ AMPDU_TID * cur_ampdu_tid,
+ struct sk_buff_head
+ *ampdu_skb_retry_queue_p,
+ bool send_aggr_tx)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct sk_buff *ampdu_retry_skb;
+ u32 ampdu_skb_retry_queue_len;
+ u32 max_agg_len;
+ u16 lowest_rate;
+ struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
+ ampdu_skb_retry_queue_len = skb_queue_len(ampdu_skb_retry_queue_p);
+ if (ampdu_skb_retry_queue_len == 0)
+ return;
+ ampdu_retry_skb = skb_peek(ampdu_skb_retry_queue_p);
+ lowest_rate = ssv62xx_ht_rate_update(ampdu_retry_skb, sc, rates);
+ max_agg_len = ampdu_max_transmit_length[lowest_rate];
+ if (max_agg_len > 0) {
+ u32 cur_ampdu_max_size = SSV_GET_MAX_AMPDU_SIZE(sc->sh);
+ if (max_agg_len >= cur_ampdu_max_size)
+ max_agg_len = cur_ampdu_max_size;
+ while (ampdu_skb_retry_queue_len > 0) {
+ struct sk_buff *retry_mpdu =
+ skb_peek(ampdu_skb_retry_queue_p);
+ SKB_info *mpdu_skb_info =
+ (SKB_info *) (retry_mpdu->head);
+ mpdu_skb_info->lowest_rate = lowest_rate;
+ memcpy(mpdu_skb_info->rates, rates, sizeof(rates));
+ ampdu_retry_skb =
+ _aggr_retry_mpdu(sc, cur_ampdu_tid,
+ ampdu_skb_retry_queue_p,
+ max_agg_len);
+ if (ampdu_retry_skb != NULL) {
+ _sync_ampdu_pkt_arr(cur_ampdu_tid,
+ ampdu_retry_skb, true);
+ ssv6200_ampdu_add_txinfo_and_send_HCI(sc,
+ ampdu_retry_skb,
+ AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL);
+ } else {
+ prn_aggr_err("AMPDU retry failed.\n");
+ return;
+ }
+ ampdu_skb_retry_queue_len =
+ skb_queue_len(ampdu_skb_retry_queue_p);
+ }
+ } else {
+ struct ieee80211_tx_rate rates[IEEE80211_TX_MAX_RATES];
+ struct ieee80211_tx_info *info =
+ IEEE80211_SKB_CB(ampdu_retry_skb);
+ memcpy(rates, info->control.rates, sizeof(info->control.rates));
+ while ((ampdu_retry_skb =
+ __skb_dequeue_tail(ampdu_skb_retry_queue_p)) != NULL) {
+ struct ieee80211_tx_info *info =
+ IEEE80211_SKB_CB(ampdu_retry_skb);
+ info->flags &= ~IEEE80211_TX_CTL_AMPDU;
+ memcpy(info->control.rates, rates,
+ sizeof(info->control.rates));
+ ssv6xxx_update_txinfo(sc, ampdu_retry_skb);
+ _send_hci_skb(sc, ampdu_retry_skb,
+ AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL);
+ }
+ }
+}
+
+void ssv6200_ampdu_init(struct ieee80211_hw *hw)
+{
+ struct ssv_softc *sc = hw->priv;
+ ssv6200_ampdu_hw_init(hw);
+ sc->tx.ampdu_tx_group_id = 0;
+#ifdef USE_ENCRYPT_WORK
+ INIT_WORK(&sc->ampdu_tx_encry_work, encry_work);
+ INIT_WORK(&sc->sync_hwkey_work, sync_hw_key_work);
+#endif
+}
+
+void ssv6200_ampdu_deinit(struct ieee80211_hw *hw)
+{
+}
+
+void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw)
+{
+ ieee80211_free_txskb(hw, skb);
+}
+
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+struct mib_dump_data {
+ char *prt_buff;
+ size_t buff_size;
+ size_t prt_len;
+};
+#define AMPDU_TX_MIB_SUMMARY_BUF_SIZE (4096)
+static ssize_t ampdu_tx_mib_summary_read(struct file *file,
+ char __user * user_buf, size_t count,
+ loff_t * ppos)
+{
+ struct ssv_sta_priv_data *ssv_sta_priv =
+ (struct ssv_sta_priv_data *)file->private_data;
+ char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL);
+ ssize_t summary_size;
+ ssize_t ret;
+ if (!summary_buf)
+ return -ENOMEM;
+ summary_size = ampdu_tx_mib_dump(ssv_sta_priv, summary_buf,
+ AMPDU_TX_MIB_SUMMARY_BUF_SIZE);
+ ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf,
+ summary_size);
+ kfree(summary_buf);
+ return ret;
+}
+
+static int ampdu_tx_mib_summary_open(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+static const struct file_operations mib_summary_fops = {.read =
+ ampdu_tx_mib_summary_read,.open = ampdu_tx_mib_summary_open,
+};
+
+static ssize_t ampdu_tx_tid_window_read(struct file *file,
+ char __user * user_buf, size_t count,
+ loff_t * ppos)
+{
+ struct AMPDU_TID_st *ampdu_tid =
+ (struct AMPDU_TID_st *)file->private_data;
+ char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL);
+ ssize_t ret;
+ char *prn_ptr = summary_buf;
+ int prt_size;
+ int buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE;
+ int i;
+ struct sk_buff *ba_skb, *tmp_ba_skb;
+ if (!summary_buf)
+ return -ENOMEM;
+ prt_size = snprintf(prn_ptr, buf_size, "\nWMM_TID %d:\n"
+ "\tWindow:", ampdu_tid->tidno);
+ prn_ptr += prt_size;
+ buf_size -= prt_size;
+ for (i = 0; i < SSV_AMPDU_BA_WINDOW_SIZE; i++) {
+ struct sk_buff *skb = ampdu_tid->aggr_pkts[i];
+ if ((i % 8) == 0) {
+ prt_size = snprintf(prn_ptr, buf_size, "\n\t\t");
+ prn_ptr += prt_size;
+ buf_size -= prt_size;
+ }
+ if (skb == NULL)
+ prt_size = snprintf(prn_ptr, buf_size, " %s", "NULL ");
+ else {
+ struct SKB_info_st *skb_info =
+ (struct SKB_info_st *)(skb->head);
+ const char status_symbol[] = { 'N',
+ 'A',
+ 'S',
+ 'R',
+ 'P',
+ 'D'
+ };
+ prt_size =
+ snprintf(prn_ptr, buf_size, " %4d%c",
+ ampdu_skb_ssn(skb),
+ ((skb_info->ampdu_tx_status <=
+ AMPDU_ST_DONE)
+ ? status_symbol[skb_info->ampdu_tx_status]
+ : 'X'));
+ }
+ prn_ptr += prt_size;
+ buf_size -= prt_size;
+ }
+ prt_size =
+ snprintf(prn_ptr, buf_size, "\n\tEarly aggregated #: %d\n",
+ ampdu_tid->early_aggr_skb_num);
+ prn_ptr += prt_size;
+ buf_size -= prt_size;
+ prt_size =
+ snprintf(prn_ptr, buf_size, "\tBAW skb #: %d\n",
+ ampdu_tid->aggr_pkt_num);
+ prn_ptr += prt_size;
+ buf_size -= prt_size;
+ prt_size =
+ snprintf(prn_ptr, buf_size, "\tBAW head: %d\n",
+ ampdu_tid->ssv_baw_head);
+ prn_ptr += prt_size;
+ buf_size -= prt_size;
+ prt_size =
+ snprintf(prn_ptr, buf_size, "\tState: %d\n", ampdu_tid->state);
+ prn_ptr += prt_size;
+ buf_size -= prt_size;
+ prt_size = snprintf(prn_ptr, buf_size, "\tBA:\n");
+ prn_ptr += prt_size;
+ buf_size -= prt_size;
+ skb_queue_walk_safe(&ampdu_tid->ba_q, ba_skb, tmp_ba_skb) {
+ prt_size = _dump_ba_skb(prn_ptr, buf_size, ba_skb);
+ prn_ptr += prt_size;
+ buf_size -= prt_size;
+ }
+ buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE - buf_size;
+ ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf,
+ buf_size);
+ kfree(summary_buf);
+ return ret;
+}
+
+static int ampdu_tx_tid_window_open(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+static const struct file_operations tid_window_fops = {.read =
+ ampdu_tx_tid_window_read,.open = ampdu_tx_tid_window_open,
+};
+
+static int ampdu_tx_mib_reset_open(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+static ssize_t ampdu_tx_mib_reset_read(struct file *file,
+ char __user * user_buf, size_t count,
+ loff_t * ppos)
+{
+ char *reset_buf = kzalloc(64, GFP_KERNEL);
+ ssize_t ret;
+ u32 reset_size;
+ if (!reset_buf)
+ return -ENOMEM;
+ reset_size = snprintf(reset_buf, 63, "%d", 0);
+ ret = simple_read_from_buffer(user_buf, count, ppos, reset_buf,
+ reset_size);
+ kfree(reset_buf);
+ return ret;
+}
+
+static ssize_t ampdu_tx_mib_reset_write(struct file *file,
+ const char __user * buffer,
+ size_t count, loff_t * pos)
+{
+ struct AMPDU_TID_st *ampdu_tid =
+ (struct AMPDU_TID_st *)file->private_data;
+ memset(&ampdu_tid->mib, 0, sizeof(struct AMPDU_MIB_st));
+ return count;
+}
+
+static const struct file_operations mib_reset_fops
+ = {.read = ampdu_tx_mib_reset_read,
+ .open = ampdu_tx_mib_reset_open,
+ .write = ampdu_tx_mib_reset_write
+};
+
+static void ssv6200_ampdu_tx_init_debugfs(struct ssv_softc *sc,
+ struct ssv_sta_priv_data
+ *ssv_sta_priv)
+{
+ struct ssv_sta_info *sta_info = ssv_sta_priv->sta_info;
+ int i;
+ struct dentry *sta_debugfs_dir = sta_info->debugfs_dir;
+ dev_info(sc->dev, "Creating AMPDU TX debugfs.\n");
+ if (sta_debugfs_dir == NULL) {
+ dev_err(sc->dev, "No STA debugfs.\n");
+ return;
+ }
+ debugfs_create_file("ampdu_tx_summary", 00444, sta_debugfs_dir,
+ ssv_sta_priv, &mib_summary_fops);
+ debugfs_create_u32("total_BA", 00644, sta_debugfs_dir,
+ &ssv_sta_priv->ampdu_mib_total_BA_counter);
+ for (i = 0; i < WMM_TID_NUM; i++) {
+ char debugfs_name[20];
+ struct dentry *ampdu_tx_debugfs_dir;
+ int j;
+ struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i];
+ struct AMPDU_MIB_st *ampdu_mib = &ampdu_tid->mib;
+ snprintf(debugfs_name, sizeof(debugfs_name), "ampdu_tx_%d", i);
+ ampdu_tx_debugfs_dir = debugfs_create_dir(debugfs_name,
+ sta_debugfs_dir);
+ if (ampdu_tx_debugfs_dir == NULL) {
+ dev_err(sc->dev,
+ "Failed to create debugfs for AMPDU TX TID %d: %s\n",
+ i, debugfs_name);
+ continue;
+ }
+ ssv_sta_priv->ampdu_tid[i].debugfs_dir = ampdu_tx_debugfs_dir;
+ debugfs_create_file("baw_status", 00444, ampdu_tx_debugfs_dir,
+ ampdu_tid, &tid_window_fops);
+ debugfs_create_file("reset", 00644, ampdu_tx_debugfs_dir,
+ ampdu_tid, &mib_reset_fops);
+ debugfs_create_u32("total", 00444, ampdu_tx_debugfs_dir,
+ &ampdu_mib->ampdu_mib_ampdu_counter);
+ debugfs_create_u32("retry", 00444, ampdu_tx_debugfs_dir,
+ &ampdu_mib->ampdu_mib_retry_counter);
+ debugfs_create_u32("aggr_retry", 00444, ampdu_tx_debugfs_dir,
+ &ampdu_mib->ampdu_mib_aggr_retry_counter);
+ debugfs_create_u32("BAR", 00444, ampdu_tx_debugfs_dir,
+ &ampdu_mib->ampdu_mib_bar_counter);
+ debugfs_create_u32("Discarded", 00444, ampdu_tx_debugfs_dir,
+ &ampdu_mib->ampdu_mib_discard_counter);
+ debugfs_create_u32("BA", 00444, ampdu_tx_debugfs_dir,
+ &ampdu_mib->ampdu_mib_BA_counter);
+ debugfs_create_u32("Pass", 00444, ampdu_tx_debugfs_dir,
+ &ampdu_mib->ampdu_mib_pass_counter);
+ for (j = 0; j <= SSV_AMPDU_aggr_num_max; j++) {
+ char dist_dbg_name[10];
+ snprintf(dist_dbg_name, sizeof(dist_dbg_name),
+ "aggr_%d", j);
+ debugfs_create_u32(dist_dbg_name, 00444,
+ ampdu_tx_debugfs_dir,
+ &ampdu_mib->ampdu_mib_dist[j]);
+ }
+ skb_queue_head_init(&ssv_sta_priv->ampdu_tid[i].ba_q);
+ }
+}
+#endif
+void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw,
+ struct ieee80211_sta *sta)
+{
+ struct ssv_sta_priv_data *ssv_sta_priv;
+ struct ssv_softc *sc;
+ u32 temp_i;
+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ sc = (struct ssv_softc *)hw->priv;
+ for (temp_i = 0; temp_i < WMM_TID_NUM; temp_i++) {
+ ssv_sta_priv->ampdu_tid[temp_i].sta = sta;
+ ssv_sta_priv->ampdu_tid[temp_i].state = AMPDU_STATE_STOP;
+ spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i].
+ ampdu_skb_tx_queue_lock);
+ spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i].pkt_array_lock);
+ }
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ ssv6200_ampdu_tx_init_debugfs(sc, ssv_sta_priv);
+#endif
+}
+
+void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta,
+ struct ieee80211_hw *hw, u16 * ssn)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ssv_sta_priv_data *ssv_sta_priv;
+ struct AMPDU_TID_st *ampdu_tid;
+ int i;
+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ ampdu_tid = &ssv_sta_priv->ampdu_tid[tid];
+ ampdu_tid->ssv_baw_head = SSV_ILLEGAL_SN;
+#ifdef DEBUG_AMPDU_FLUSH
+ pr_debug("Adding %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n",
+ sta->addr[0], sta->addr[1], sta->addr[2],
+ sta->addr[3], sta->addr[4], sta->addr[5],
+ ampdu_tid->tidno, ampdu_tid);
+ {
+ int j;
+ for (j = 0; j <= MAX_TID; j++) {
+ if (sc->tid[j] == 0)
+ break;
+ }
+ if (j == MAX_TID) {
+ dev_err(sc->dev, "No room for new TID.\n");
+ } else
+ sc->tid[j] = ampdu_tid;
+ }
+#endif
+ list_add_tail_rcu(&ampdu_tid->list, &sc->tx.ampdu_tx_que);
+ skb_queue_head_init(&ampdu_tid->ampdu_skb_tx_queue);
+ skb_queue_head_init(&ampdu_tid->early_aggr_ampdu_q);
+ ampdu_tid->early_aggr_skb_num = 0;
+ skb_queue_head_init(&ampdu_tid->ampdu_skb_wait_encry_queue);
+ skb_queue_head_init(&ampdu_tid->retry_queue);
+ skb_queue_head_init(&ampdu_tid->release_queue);
+ for (i = 0;
+ i <
+ (sizeof(ampdu_tid->aggr_pkts) / sizeof(ampdu_tid->aggr_pkts[0]));
+ i++)
+ ampdu_tid->aggr_pkts[i] = 0;
+ ampdu_tid->aggr_pkt_num = 0;
+ ampdu_tid->cur_ampdu_pkt = _alloc_ampdu_skb(sc, ampdu_tid, 0);
+#ifdef AMPDU_CHECK_SKB_SEQNO
+ ssv_sta_priv->ampdu_tid[tid].last_seqno = (-1);
+#endif
+ ssv_sta_priv->ampdu_mib_total_BA_counter = 0;
+ memset(&ssv_sta_priv->ampdu_tid[tid].mib, 0,
+ sizeof(struct AMPDU_MIB_st));
+ ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_START;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ skb_queue_head_init(&ssv_sta_priv->ampdu_tid[tid].ba_q);
+#endif
+}
+
+void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta,
+ struct ieee80211_hw *hw, u8 buffer_size)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ssv_sta_priv_data *ssv_sta_priv;
+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ ssv_sta_priv->ampdu_tid[tid].tidno = tid;
+ ssv_sta_priv->ampdu_tid[tid].sta = sta;
+ ssv_sta_priv->ampdu_tid[tid].agg_num_max = MAX_AGGR_NUM;
+ if (buffer_size > IEEE80211_MAX_AMPDU_BUF) {
+ buffer_size = IEEE80211_MAX_AMPDU_BUF;
+ }
+ dev_info(sc->dev, "AMPDU buffer_size=%d\n", buffer_size);
+ ssv_sta_priv->ampdu_tid[tid].ssv_baw_size = SSV_AMPDU_WINDOW_SIZE;
+ ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_OPERATION;
+}
+
+static void _clear_mpdu_q(struct ieee80211_hw *hw, struct sk_buff_head *q,
+ bool aggregated_mpdu)
+{
+ struct sk_buff *skb;
+ while (1) {
+ skb = skb_dequeue(q);
+ if (!skb)
+ break;
+ if (aggregated_mpdu)
+ skb_pull(skb, AMPDU_DELIMITER_LEN);
+ ieee80211_tx_status(hw, skb);
+ }
+}
+
+void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta,
+ struct ieee80211_hw *hw)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ssv_sta_priv_data *ssv_sta_priv;
+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ if (ssv_sta_priv->ampdu_tid[tid].state == AMPDU_STATE_STOP)
+ return;
+ ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_STOP;
+ dev_dbg(sc->dev, "ssv6200_ampdu_tx_stop\n");
+ if (!list_empty(&sc->tx.ampdu_tx_que)) {
+#ifdef DEBUG_AMPDU_FLUSH
+ {
+ int j;
+ struct AMPDU_TID_st *ampdu_tid =
+ &ssv_sta_priv->ampdu_tid[tid];
+ for (j = 0; j <= MAX_TID; j++) {
+ if (sc->tid[j] == ampdu_tid)
+ break;
+ }
+ if (j == MAX_TID) {
+ dev_dbg(sc->dev, "No TID found when deleting it.\n");
+ } else
+ sc->tid[j] = NULL;
+ dev_dbg(sc->dev, "Deleting %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n",
+ sta->addr[0], sta->addr[1], sta->addr[2],
+ sta->addr[3], sta->addr[4], sta->addr[5],
+ ampdu_tid->tidno, ampdu_tid);
+ }
+#endif
+ list_del_rcu(&ssv_sta_priv->ampdu_tid[tid].list);
+ }
+ dev_dbg(sc->dev, "clear tx q len=%d\n",
+ skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue));
+ _clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue,
+ true);
+ dev_dbg(sc->dev, "clear retry q len=%d\n",
+ skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].retry_queue));
+ _clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].retry_queue, true);
+#ifdef USE_ENCRYPT_WORK
+ dev_dbg(sc->dev, "clear encrypt q len=%d\n",
+ skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].
+ ampdu_skb_wait_encry_queue));
+ _clear_mpdu_q(sc->hw,
+ &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_wait_encry_queue,
+ false);
+#endif
+ if (ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt != NULL) {
+ dev_kfree_skb_any(ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt);
+ ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt = NULL;
+ }
+ ssv6200_tx_flow_control((void *)sc,
+ sc->tx.hw_txqid[ssv_sta_priv->ampdu_tid[tid].
+ ac], false, 1000);
+}
+
+static void ssv6200_ampdu_tx_state_stop_func(struct ssv_softc *sc,
+ struct ieee80211_sta *sta,
+ struct sk_buff *skb,
+ struct AMPDU_TID_st *cur_AMPDU_TID)
+{
+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+ u8 *skb_qos_ctl = ieee80211_get_qos_ctl(hdr);
+ u8 tid_no = skb_qos_ctl[0] & 0xf;
+ if ((sta->deflink.ht_cap.ht_supported == true)
+ && (!!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) {
+ ieee80211_start_tx_ba_session(sta, tid_no, 0);
+ ampdu_db_log("start ampdu_tx(rc) : tid_no = %d\n", tid_no);
+ }
+}
+
+static void ssv6200_ampdu_tx_state_operation_func(struct ssv_softc *sc,
+ struct ieee80211_sta *sta,
+ struct sk_buff *skb,
+ struct AMPDU_TID_st
+ *cur_AMPDU_TID)
+{
+}
+
+void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta,
+ struct sk_buff *skb)
+{
+ struct ssv_softc *sc = (struct ssv_softc *)priv;
+ struct ssv_sta_priv_data *ssv_sta_priv =
+ (struct ssv_sta_priv_data *)sta->drv_priv;
+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+ u8 *skb_qos_ctl;
+ u8 tid_no;
+ {
+ skb_qos_ctl = ieee80211_get_qos_ctl(hdr);
+ tid_no = skb_qos_ctl[0] & 0xf;
+ switch (ssv_sta_priv->ampdu_tid[tid_no].state) {
+ case AMPDU_STATE_STOP:
+ ssv6200_ampdu_tx_state_stop_func(sc, sta, skb,
+ &(ssv_sta_priv->
+ ampdu_tid[tid_no]));
+ break;
+ case AMPDU_STATE_START:
+ break;
+ case AMPDU_STATE_OPERATION:
+ ssv6200_ampdu_tx_state_operation_func(sc, sta, skb,
+ &(ssv_sta_priv->
+ ampdu_tid
+ [tid_no]));
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+void _put_mpdu_to_ampdu(struct sk_buff *ampdu, struct sk_buff *mpdu)
+{
+ bool is_empty_ampdu = (ampdu->len == 0);
+ unsigned char *data_dest;
+ struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
+ BUG_ON(skb_tailroom(ampdu) < mpdu->len);
+ data_dest = skb_tail_pointer(ampdu);
+ skb_put(ampdu, mpdu->len);
+ if (is_empty_ampdu) {
+ struct ieee80211_tx_info *ampdu_info = IEEE80211_SKB_CB(ampdu);
+ struct ieee80211_tx_info *mpdu_info = IEEE80211_SKB_CB(mpdu);
+ SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head);
+ u32 max_size_for_rate =
+ ampdu_max_transmit_length[mpdu_skb_info->lowest_rate];
+ BUG_ON(max_size_for_rate == 0);
+ memcpy(ampdu_info, mpdu_info, sizeof(struct ieee80211_tx_info));
+ skb_set_queue_mapping(ampdu, skb_get_queue_mapping(mpdu));
+ ampdu_hdr->first_sn = ampdu_skb_ssn(mpdu);
+ ampdu_hdr->sta = ((struct SKB_info_st *)mpdu->head)->sta;
+ if (ampdu_hdr->max_size > max_size_for_rate)
+ ampdu_hdr->max_size = max_size_for_rate;
+ memcpy(ampdu_hdr->rates, mpdu_skb_info->rates,
+ sizeof(ampdu_hdr->rates));
+ }
+ memcpy(data_dest, mpdu->data, mpdu->len);
+ __skb_queue_tail(&ampdu_hdr->mpdu_q, mpdu);
+ ampdu_hdr->ssn[ampdu_hdr->mpdu_num++] = ampdu_skb_ssn(mpdu);
+ ampdu_hdr->size += mpdu->len;
+ BUG_ON(ampdu_hdr->size > ampdu_hdr->max_size);
+}
+
+u32 _flush_early_ampdu_q(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid)
+{
+ u32 flushed_ampdu = 0;
+ unsigned long flags;
+ struct sk_buff_head *early_aggr_ampdu_q =
+ &ampdu_tid->early_aggr_ampdu_q;
+ spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+ while (skb_queue_len(early_aggr_ampdu_q)) {
+ struct sk_buff *head_ampdu;
+ struct ampdu_hdr_st *head_ampdu_hdr;
+ u32 ampdu_aggr_num;
+ head_ampdu = skb_peek(early_aggr_ampdu_q);
+ head_ampdu_hdr = (struct ampdu_hdr_st *)head_ampdu->head;
+ ampdu_aggr_num = skb_queue_len(&head_ampdu_hdr->mpdu_q);
+ if ((SSV_AMPDU_BA_WINDOW_SIZE - ampdu_tid->aggr_pkt_num)
+ < ampdu_aggr_num)
+ break;
+ if (_sync_ampdu_pkt_arr(ampdu_tid, head_ampdu, false)) {
+ head_ampdu = __skb_dequeue(early_aggr_ampdu_q);
+ ampdu_tid->early_aggr_skb_num -= ampdu_aggr_num;
+#ifdef SSV_AMPDU_FLOW_CONTROL
+ if (ampdu_tid->early_aggr_skb_num
+ <= SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND) {
+ ssv6200_tx_flow_control((void *)sc,
+ sc->tx.
+ hw_txqid[ampdu_tid->ac],
+ false, 1000);
+ }
+#endif
+ if ((skb_queue_len(early_aggr_ampdu_q) == 0)
+ && (ampdu_tid->early_aggr_skb_num > 0)) {
+ dev_warn(sc->dev, "Empty early Q w. %d.\n",
+ ampdu_tid->early_aggr_skb_num);
+ }
+ spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
+ flags);
+ _send_hci_skb(sc, head_ampdu,
+ AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
+ spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+ flushed_ampdu++;
+ } else
+ break;
+ }
+ spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
+ return flushed_ampdu;
+}
+
+volatile int max_aggr_num = 24;
+void _aggr_ampdu_tx_q(struct ieee80211_hw *hw, struct AMPDU_TID_st *ampdu_tid)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct sk_buff *ampdu_skb = ampdu_tid->cur_ampdu_pkt;
+ while (skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue)) {
+ u32 aggr_len;
+ struct sk_buff *mpdu_skb;
+ struct ampdu_hdr_st *ampdu_hdr;
+ bool is_aggr_full = false;
+ if (ampdu_skb == NULL) {
+ ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, 0);
+ if (ampdu_skb == NULL)
+ break;
+ ampdu_tid->cur_ampdu_pkt = ampdu_skb;
+ }
+ ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
+ aggr_len = skb_queue_len(&ampdu_hdr->mpdu_q);
+ do {
+ struct sk_buff_head *tx_q =
+ &ampdu_tid->ampdu_skb_tx_queue;
+ unsigned long flags;
+ spin_lock_irqsave(&tx_q->lock, flags);
+ mpdu_skb = skb_peek(&ampdu_tid->ampdu_skb_tx_queue);
+ if (mpdu_skb == NULL) {
+ spin_unlock_irqrestore(&tx_q->lock, flags);
+ break;
+ }
+ if ((mpdu_skb->len + ampdu_hdr->size) >
+ ampdu_hdr->max_size) {
+ is_aggr_full = true;
+ spin_unlock_irqrestore(&tx_q->lock, flags);
+ break;
+ }
+ mpdu_skb =
+ __skb_dequeue(&ampdu_tid->ampdu_skb_tx_queue);
+ spin_unlock_irqrestore(&tx_q->lock, flags);
+ _put_mpdu_to_ampdu(ampdu_skb, mpdu_skb);
+ } while (++aggr_len < max_aggr_num);
+ if ((is_aggr_full || (aggr_len >= max_aggr_num))
+ || ((aggr_len > 0)
+ && (skb_queue_len(&ampdu_tid->early_aggr_ampdu_q) == 0)
+ && (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN)
+ && _is_skb_q_empty(sc, ampdu_skb))) {
+ _add_ampdu_txinfo(sc, ampdu_skb);
+ _queue_early_ampdu(sc, ampdu_tid, ampdu_skb);
+ ampdu_tid->cur_ampdu_pkt = ampdu_skb = NULL;
+ }
+ _flush_early_ampdu_q(sc, ampdu_tid);
+ }
+}
+
+void _queue_early_ampdu(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid,
+ struct sk_buff *ampdu_skb)
+{
+ unsigned long flags;
+ struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
+ spin_lock_irqsave(&ampdu_tid->early_aggr_ampdu_q.lock, flags);
+ __skb_queue_tail(&ampdu_tid->early_aggr_ampdu_q, ampdu_skb);
+ ampdu_tid->early_aggr_skb_num += skb_queue_len(&ampdu_hdr->mpdu_q);
+#ifdef SSV_AMPDU_FLOW_CONTROL
+ if (ampdu_tid->early_aggr_skb_num >= SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND) {
+ ssv6200_tx_flow_control((void *)sc,
+ sc->tx.hw_txqid[ampdu_tid->ac], true,
+ 1000);
+ }
+#endif
+ spin_unlock_irqrestore(&ampdu_tid->early_aggr_ampdu_q.lock, flags);
+}
+
+void _flush_mpdu(struct ssv_softc *sc, struct ieee80211_sta *sta)
+{
+ unsigned long flags;
+ struct ssv_sta_priv_data *ssv_sta_priv =
+ (struct ssv_sta_priv_data *)sta->drv_priv;
+ int i;
+ for (i = 0;
+ i <
+ (sizeof(ssv_sta_priv->ampdu_tid) /
+ sizeof(ssv_sta_priv->ampdu_tid[0])); i++) {
+ struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i];
+ struct sk_buff_head *early_aggr_ampdu_q;
+ struct sk_buff *ampdu;
+ struct ampdu_hdr_st *ampdu_hdr;
+ struct sk_buff_head *mpdu_q;
+ struct sk_buff *mpdu;
+ if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+ continue;
+ early_aggr_ampdu_q = &ampdu_tid->early_aggr_ampdu_q;
+ spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+ while ((ampdu = __skb_dequeue(early_aggr_ampdu_q)) != NULL) {
+ ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
+ mpdu_q = &ampdu_hdr->mpdu_q;
+ spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
+ flags);
+ while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) {
+ _send_hci_skb(sc, mpdu,
+ AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
+ }
+ ssv6200_ampdu_release_skb(ampdu, sc->hw);
+ spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+ }
+ if (ampdu_tid->cur_ampdu_pkt != NULL) {
+ ampdu_hdr =
+ (struct ampdu_hdr_st *)ampdu_tid->cur_ampdu_pkt->
+ head;
+ mpdu_q = &ampdu_hdr->mpdu_q;
+ spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
+ flags);
+ while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) {
+ _send_hci_skb(sc, mpdu,
+ AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
+ }
+ ssv6200_ampdu_release_skb(ampdu_tid->cur_ampdu_pkt,
+ sc->hw);
+ spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+ ampdu_tid->cur_ampdu_pkt = NULL;
+ }
+ spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
+ }
+}
+
+bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+#ifdef REPORT_TX_STATUS_DIRECTLY
+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+ struct sk_buff *tx_skb = skb;
+ struct sk_buff *copy_skb = NULL;
+#endif
+ struct SKB_info_st *mpdu_skb_info_p = (SKB_info *) (skb->head);
+ struct ieee80211_sta *sta = mpdu_skb_info_p->sta;
+ struct ssv_sta_priv_data *ssv_sta_priv =
+ (struct ssv_sta_priv_data *)sta->drv_priv;
+ u8 tidno;
+ struct AMPDU_TID_st *ampdu_tid;
+ if (sta == NULL) {
+ WARN_ON(1);
+ return false;
+ }
+ tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+ ampdu_db_log("tidno = %d\n", tidno);
+ ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
+ if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+ return false;
+#ifdef AMPDU_CHECK_SKB_SEQNO
+ {
+ u32 skb_seqno = ((struct ieee80211_hdr *)(skb->data))->seq_ctrl
+ >> SSV_SEQ_NUM_SHIFT;
+ u32 tid_seqno = ampdu_tid->last_seqno;
+ if ((tid_seqno != (-1))
+ && (skb_seqno != NEXT_PKT_SN(tid_seqno))) {
+ prn_aggr_err("Non continueous seq no: %d - %d\n",
+ tid_seqno, skb_seqno);
+ return false;
+ }
+ ampdu_tid->last_seqno = skb_seqno;
+ }
+#endif
+ mpdu_skb_info_p->lowest_rate =
+ ssv62xx_ht_rate_update(skb, sc, mpdu_skb_info_p->rates);
+ if (ampdu_max_transmit_length[mpdu_skb_info_p->lowest_rate] == 0) {
+ _flush_mpdu(sc, sta);
+ return false;
+ }
+ mpdu_skb_info_p = (SKB_info *) (skb->head);
+ mpdu_skb_info_p->mpdu_retry_counter = 0;
+ mpdu_skb_info_p->ampdu_tx_status = AMPDU_ST_NON_AMPDU;
+ mpdu_skb_info_p->ampdu_tx_final_retry_count = 0;
+ ssv_sta_priv->ampdu_tid[tidno].ac = skb_get_queue_mapping(skb);
+#ifdef REPORT_TX_STATUS_DIRECTLY
+ info->flags |= IEEE80211_TX_STAT_ACK;
+ copy_skb = skb_copy(tx_skb, GFP_ATOMIC);
+ if (!copy_skb) {
+ dev_err(sc->dev, "create TX skb copy failed!\n");
+ return false;
+ }
+ ieee80211_tx_status(sc->hw, tx_skb);
+ skb = copy_skb;
+#endif
+ {
+ bool ret;
+ ret = ssv6200_ampdu_add_delimiter_and_crc32(skb);
+ if (ret == false) {
+ ssv6200_ampdu_release_skb(skb, hw);
+ return false;
+ }
+ skb_queue_tail(&ssv_sta_priv->ampdu_tid[tidno].
+ ampdu_skb_tx_queue, skb);
+ ssv_sta_priv->ampdu_tid[tidno].timestamp = jiffies;
+ }
+ _aggr_ampdu_tx_q(hw, &ssv_sta_priv->ampdu_tid[tidno]);
+ return true;
+}
+
+u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct AMPDU_TID_st *cur_AMPDU_TID;
+ u32 flushed_ampdu = 0;
+ u32 tid_idx = 0;
+ if (!list_empty(&sc->tx.ampdu_tx_que)) {
+ list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que,
+ list) {
+ tid_idx++;
+#ifdef DEBUG_AMPDU_FLUSH
+ {
+ int i = 0;
+ for (i = 0; i < MAX_TID; i++)
+ if (sc->tid[i] == cur_AMPDU_TID)
+ break;
+ if (i == MAX_TID) {
+ dev_err(sc->dev, "No matching TID (%d) found! %p\n",
+ tid_idx, cur_AMPDU_TID);
+ continue;
+ }
+ }
+#endif
+ if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION) {
+ struct ieee80211_sta *sta = cur_AMPDU_TID->sta;
+ struct ssv_sta_priv_data *sta_priv =
+ (struct ssv_sta_priv_data *)sta->drv_priv;
+ dev_dbg(sc->dev, "STA %d TID %d is @%d\n",
+ sta_priv->sta_idx, cur_AMPDU_TID->tidno,
+ cur_AMPDU_TID->state);
+ continue;
+ }
+ if ((cur_AMPDU_TID->state == AMPDU_STATE_OPERATION)
+ &&
+ (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q)
+ == 0)
+ && (cur_AMPDU_TID->cur_ampdu_pkt != NULL)) {
+ struct ampdu_hdr_st *ampdu_hdr =
+ (struct ampdu_hdr_st *)(cur_AMPDU_TID->
+ cur_ampdu_pkt->
+ head);
+ u32 aggr_len =
+ skb_queue_len(&ampdu_hdr->mpdu_q);
+ if (aggr_len) {
+ struct sk_buff *ampdu_skb =
+ cur_AMPDU_TID->cur_ampdu_pkt;
+ cur_AMPDU_TID->cur_ampdu_pkt = NULL;
+ _add_ampdu_txinfo(sc, ampdu_skb);
+ _queue_early_ampdu(sc, cur_AMPDU_TID,
+ ampdu_skb);
+ }
+ }
+ if (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q) >
+ 0)
+ flushed_ampdu +=
+ _flush_early_ampdu_q(sc, cur_AMPDU_TID);
+ }
+ }
+ return flushed_ampdu;
+}
+
+int _dump_BA_notification(char *buf,
+ struct ampdu_ba_notify_data *ba_notification)
+{
+ int i;
+ char *orig_buf = buf;
+ for (i = 0; i < MAX_AGGR_NUM; i++) {
+ if (ba_notification->seq_no[i] == (u16) (-1))
+ break;
+ buf += sprintf(buf, " %d", ba_notification->seq_no[i]);
+ }
+ return ((size_t)buf - (size_t)orig_buf);
+}
+
+int _dump_ba_skb(char *buf, int buf_size, struct sk_buff *ba_skb)
+{
+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(ba_skb->data
+ +
+ SSV6XXX_RX_DESC_LEN);
+ AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
+ u32 ssn = BA_frame->BA_ssn;
+ struct ampdu_ba_notify_data *ba_notification =
+ (struct ampdu_ba_notify_data *)(ba_skb->data + ba_skb->len
+ -
+ sizeof(struct
+ ampdu_ba_notify_data));
+ int prt_size;
+ prt_size = snprintf(buf, buf_size, "\n\t\t%04d %08X %08X -",
+ ssn, BA_frame->BA_sn_bit_map[0],
+ BA_frame->BA_sn_bit_map[1]);
+ buf_size -= prt_size;
+ buf += prt_size;
+ prt_size = prt_size + _dump_BA_notification(buf, ba_notification);
+ return prt_size;
+}
+
+static bool _ssn_to_bit_idx(u32 start_ssn, u32 mpdu_ssn, u32 * word_idx,
+ u32 * bit_idx)
+{
+ u32 ret_bit_idx, ret_word_idx = 0;
+ s32 diff = mpdu_ssn - start_ssn;
+ if (diff >= 0) {
+ if (diff >= SSV_AMPDU_BA_WINDOW_SIZE) {
+ return false;
+ }
+ ret_bit_idx = diff;
+ } else {
+ diff = -diff;
+ if (diff <= (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) {
+ *word_idx = 0;
+ *bit_idx = 0;
+ return false;
+ }
+ ret_bit_idx = SSV_AMPDU_MAX_SSN - diff;
+ }
+ if (ret_bit_idx >= 32) {
+ ret_bit_idx -= 32;
+ ret_word_idx = 1;
+ }
+ *bit_idx = ret_bit_idx;
+ *word_idx = ret_word_idx;
+ return true;
+}
+
+static bool _inc_bit_idx(u32 ssn_1st, u32 ssn_next, u32 * word_idx,
+ u32 * bit_idx)
+{
+ u32 ret_word_idx = *word_idx, ret_bit_idx = *bit_idx;
+ s32 diff = (s32) ssn_1st - (s32) ssn_next;
+ if (diff > 0) {
+ if (diff < (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) {
+ prn_aggr_err
+ ("Irrational SN distance in AMPDU: %d %d.\n",
+ ssn_1st, ssn_next);
+ return false;
+ }
+ diff = SSV_AMPDU_MAX_SSN - diff;
+ } else {
+ diff = -diff;
+ }
+ if (diff > SSV_AMPDU_MAX_SSN)
+ prn_aggr_err("DF %d - %d = %d\n", ssn_1st, ssn_next, diff);
+ ret_bit_idx += diff;
+ if (ret_bit_idx >= 32) {
+ ret_bit_idx -= 32;
+ ret_word_idx++;
+ }
+ *word_idx = ret_word_idx;
+ *bit_idx = ret_bit_idx;
+ return true;
+}
+
+static void _release_frames(struct AMPDU_TID_st *ampdu_tid)
+{
+ u32 head_ssn, head_ssn_before, last_ssn;
+ struct sk_buff **skb;
+ struct SKB_info_st *skb_info;
+ spin_lock_bh(&ampdu_tid->pkt_array_lock);
+ head_ssn_before = ampdu_tid->ssv_baw_head;
+ if (head_ssn_before >= SSV_AMPDU_MAX_SSN) {
+ spin_unlock_bh(&ampdu_tid->pkt_array_lock);
+ prn_aggr_err("l x.x %d\n", head_ssn_before);
+ return;
+ }
+ head_ssn = ampdu_tid->ssv_baw_head;
+ last_ssn = head_ssn;
+ do {
+ skb = &INDEX_PKT_BY_SSN(ampdu_tid, head_ssn);
+ if (*skb == NULL) {
+ head_ssn = SSV_ILLEGAL_SN;
+ {
+ int i;
+ char sn_str[66 * 5] = "";
+ char *str = sn_str;
+ for (i = 0; i < 64; i++)
+ if (ampdu_tid->aggr_pkts[i] != NULL) {
+ str += sprintf(str, "%d ",
+ ampdu_skb_ssn
+ (ampdu_tid->
+ aggr_pkts[i]));
+ }
+ *str = 0;
+ if (str == sn_str) {
+ } else
+ prn_aggr_err("ILL %d %d - %d (%s)\n",
+ head_ssn_before, last_ssn,
+ ampdu_tid->aggr_pkt_num,
+ sn_str);
+ }
+ break;
+ }
+ skb_info = (struct SKB_info_st *)((*skb)->head);
+ if ((skb_info->ampdu_tx_status == AMPDU_ST_DONE)
+ || (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)) {
+ __skb_queue_tail(&ampdu_tid->release_queue, *skb);
+ *skb = NULL;
+ last_ssn = head_ssn;
+ INC_PKT_SN(head_ssn);
+ ampdu_tid->aggr_pkt_num--;
+ if (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)
+ ampdu_tid->mib.ampdu_mib_discard_counter++;
+ } else {
+ break;
+ }
+ } while (1);
+ ampdu_tid->ssv_baw_head = head_ssn;
+ spin_unlock_bh(&ampdu_tid->pkt_array_lock);
+}
+
+static int _collect_retry_frames(struct AMPDU_TID_st *ampdu_tid)
+{
+ u16 ssn, head_ssn, end_ssn;
+ int num_retry = 0;
+ int timeout_check = 1;
+ unsigned long check_jiffies = jiffies;
+ head_ssn = ampdu_tid->ssv_baw_head;
+ ssn = head_ssn;
+ if (ssn == SSV_ILLEGAL_SN)
+ return 0;
+ end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN;
+ do {
+ struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+ struct SKB_info_st *skb_info;
+ int timeout_retry = 0;
+ if (skb == NULL)
+ break;
+ skb_info = (SKB_info *) (skb->head);
+ if (timeout_check
+ && (skb_info->ampdu_tx_status == AMPDU_ST_SENT)) {
+ unsigned long cur_jiffies = jiffies;
+ unsigned long timeout_jiffies = skb_info->aggr_timestamp
+ + msecs_to_jiffies(BA_WAIT_TIMEOUT);
+ u32 delta_ms;
+ if (time_before(cur_jiffies, timeout_jiffies)) {
+ timeout_check = 0;
+ continue;
+ }
+ _mark_skb_retry(skb_info, skb);
+ delta_ms =
+ jiffies_to_msecs(cur_jiffies -
+ skb_info->aggr_timestamp);
+ prn_aggr_err("t S%d-T%d-%d (%u)\n",
+ ((struct ssv_sta_priv_data *)skb_info->
+ sta->drv_priv)->sta_idx, ampdu_tid->tidno,
+ ssn, delta_ms);
+ if (delta_ms > 1000) {
+ prn_aggr_err("Last checktime %lu - %lu = %u\n",
+ check_jiffies,
+ ampdu_tid->timestamp,
+ jiffies_to_msecs(check_jiffies -
+ ampdu_tid->
+ timestamp));
+ }
+ timeout_retry = 1;
+ }
+ if (skb_info->ampdu_tx_status == AMPDU_ST_RETRY) {
+ skb_queue_tail(&ampdu_tid->retry_queue, skb);
+ ampdu_tid->mib.ampdu_mib_retry_counter++;
+ num_retry++;
+ }
+ INC_PKT_SN(ssn);
+ } while (ssn != end_ssn);
+ ampdu_tid->timestamp = check_jiffies;
+ return num_retry;
+}
+
+int _mark_skb_retry(struct SKB_info_st *skb_info, struct sk_buff *skb)
+{
+ if (skb_info->mpdu_retry_counter < SSV_AMPDU_retry_counter_max) {
+ if (skb_info->mpdu_retry_counter == 0) {
+ struct ieee80211_hdr *skb_hdr = ampdu_skb_hdr(skb);
+ skb_hdr->frame_control |=
+ cpu_to_le16(IEEE80211_FCTL_RETRY);
+ }
+ skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
+ skb_info->mpdu_retry_counter++;
+ return 1;
+ } else {
+ skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
+ prn_aggr_err("p %d\n", ampdu_skb_ssn(skb));
+ return 0;
+ }
+}
+
+static u32 _ba_map_walker(struct AMPDU_TID_st *ampdu_tid, u32 start_ssn,
+ u32 sn_bit_map[2],
+ struct ampdu_ba_notify_data *ba_notify_data,
+ u32 * p_acked_num)
+{
+ int i = 0;
+ u32 ssn = ba_notify_data->seq_no[0];
+ u32 word_idx = (-1), bit_idx = (-1);
+ bool found = _ssn_to_bit_idx(start_ssn, ssn, &word_idx, &bit_idx);
+ bool first_found = found;
+ u32 aggr_num = 0;
+ u32 acked_num = 0;
+ if (found && (word_idx >= 2 || bit_idx >= 32))
+ prn_aggr_err("idx error 1: %d %d %d %d\n",
+ start_ssn, ssn, word_idx, bit_idx);
+ while ((i < MAX_AGGR_NUM) && (ssn < SSV_AMPDU_MAX_SSN)) {
+ u32 cur_ssn;
+ struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+ u32 skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
+ struct SKB_info_st *skb_info;
+ aggr_num++;
+ if (skb_ssn != ssn) {
+ prn_aggr_err("Unmatched SSN packet: %d - %d - %d\n",
+ ssn, skb_ssn, start_ssn);
+ } else {
+ skb_info = (struct SKB_info_st *)(skb->head);
+ if (found && (sn_bit_map[word_idx] & (1 << bit_idx))) {
+ if (skb_info->ampdu_tx_status != AMPDU_ST_SENT) {
+ pr_err("BA marks a MPDU of status %d!\n",
+ skb_info->ampdu_tx_status);
+ }
+ skb_info->ampdu_tx_status = AMPDU_ST_DONE;
+ acked_num++;
+ } else {
+ _mark_skb_retry(skb_info, skb);
+ }
+ }
+ cur_ssn = ssn;
+ if (++i >= MAX_AGGR_NUM)
+ break;
+ ssn = ba_notify_data->seq_no[i];
+ if (ssn >= SSV_AMPDU_MAX_SSN)
+ break;
+ if (first_found) {
+ u32 old_word_idx = word_idx, old_bit_idx = bit_idx;
+ found = _inc_bit_idx(cur_ssn, ssn, &word_idx, &bit_idx);
+ if (found && (word_idx >= 2 || bit_idx >= 32)) {
+ prn_aggr_err
+ ("idx error 2: %d 0x%08X 0X%08X %d %d (%d %d) (%d %d)\n",
+ start_ssn, sn_bit_map[1], sn_bit_map[0],
+ cur_ssn, ssn, word_idx, bit_idx,
+ old_word_idx, old_bit_idx);
+ found = false;
+ } else if (!found) {
+ char strbuf[256];
+ _dump_BA_notification(strbuf, ba_notify_data);
+ prn_aggr_err("SN out-of-order: %d\n%s\n",
+ start_ssn, strbuf);
+ }
+ } else {
+ found =
+ _ssn_to_bit_idx(start_ssn, ssn, &word_idx,
+ &bit_idx);
+ first_found = found;
+ if (found && (word_idx >= 2 || bit_idx >= 32))
+ prn_aggr_err("idx error 3: %d %d %d %d\n",
+ cur_ssn, ssn, word_idx, bit_idx);
+ }
+ }
+ _release_frames(ampdu_tid);
+ if (p_acked_num != NULL)
+ *p_acked_num = acked_num;
+ return aggr_num;
+}
+
+static void _flush_release_queue(struct ieee80211_hw *hw,
+ struct sk_buff_head *release_queue)
+{
+ do {
+ struct sk_buff *ampdu_skb = __skb_dequeue(release_queue);
+ struct ieee80211_tx_info *tx_info;
+ struct SKB_info_st *skb_info;
+ if (ampdu_skb == NULL)
+ break;
+ skb_info = (struct SKB_info_st *)(ampdu_skb->head);
+ skb_pull(ampdu_skb, AMPDU_DELIMITER_LEN);
+ tx_info = IEEE80211_SKB_CB(ampdu_skb);
+ ieee80211_tx_info_clear_status(tx_info);
+ tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
+ if (skb_info->ampdu_tx_status == AMPDU_ST_DONE)
+ tx_info->flags |= IEEE80211_TX_STAT_ACK;
+ tx_info->status.ampdu_len = 1;
+ tx_info->status.ampdu_ack_len = 1;
+#ifdef REPORT_TX_STATUS_DIRECTLY
+ dev_kfree_skb_any(ampdu_skb);
+#else
+#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_TX_DATA)
+ ieee80211_tx_status(hw, ampdu_skb);
+#else
+ ieee80211_tx_status_irqsafe(hw, ampdu_skb);
+#endif
+#endif
+ } while (1);
+}
+
+void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+ struct cfg_host_event *host_event = (struct cfg_host_event *)skb->data;
+ struct ampdu_ba_notify_data *ba_notification =
+ (struct ampdu_ba_notify_data *)&host_event->dat[0];
+ struct ieee80211_hdr *hdr =
+ (struct ieee80211_hdr *)(ba_notification + 1);
+ struct ssv_softc *sc = hw->priv;
+ struct ieee80211_sta *sta = ssv6xxx_find_sta_by_addr(sc, hdr->addr1);
+ u8 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+ struct ssv_sta_priv_data *ssv_sta_priv;
+ char seq_str[256];
+ struct AMPDU_TID_st *ampdu_tid;
+ int i;
+ u16 aggr_num = 0;
+ struct firmware_rate_control_report_data *report_data;
+ if (sta == NULL) {
+ prn_aggr_err
+ ("NO BA for %d to unmatched STA %02X-%02X-%02X-%02X-%02X-%02X: %s\n",
+ tidno, hdr->addr1[0], hdr->addr1[1], hdr->addr1[2],
+ hdr->addr1[3], hdr->addr1[4], hdr->addr1[5], seq_str);
+ dev_kfree_skb_any(skb);
+ return;
+ }
+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ _dump_BA_notification(seq_str, ba_notification);
+ prn_aggr_err("NO BA for %d to %02X-%02X-%02X-%02X-%02X-%02X: %s\n",
+ tidno, sta->addr[0], sta->addr[1], sta->addr[2],
+ sta->addr[3], sta->addr[4], sta->addr[5], seq_str);
+ ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
+ if (ampdu_tid->state != AMPDU_STATE_OPERATION) {
+ dev_kfree_skb_any(skb);
+ return;
+ }
+ for (i = 0; i < MAX_AGGR_NUM; i++) {
+ u32 ssn = ba_notification->seq_no[i];
+ struct sk_buff *skb;
+ u32 skb_ssn;
+ struct SKB_info_st *skb_info;
+ if (ssn >= (4096))
+ break;
+ aggr_num++;
+ skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+ skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
+ if (skb_ssn != ssn) {
+ prn_aggr_err("Unmatched SSN packet: %d - %d\n", ssn,
+ skb_ssn);
+ continue;
+ }
+ skb_info = (struct SKB_info_st *)(skb->head);
+ if (skb_info->ampdu_tx_status == AMPDU_ST_SENT) {
+ if (skb_info->mpdu_retry_counter <
+ SSV_AMPDU_retry_counter_max) {
+ if (skb_info->mpdu_retry_counter == 0) {
+ struct ieee80211_hdr *skb_hdr =
+ ampdu_skb_hdr(skb);
+ skb_hdr->frame_control |=
+ cpu_to_le16(IEEE80211_FCTL_RETRY);
+ }
+ skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
+ skb_info->mpdu_retry_counter++;
+ } else {
+ skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
+ prn_aggr_err("p %d\n", skb_ssn);
+ }
+ } else {
+ prn_aggr_err("S %d %d\n", skb_ssn,
+ skb_info->ampdu_tx_status);
+ }
+ }
+ _release_frames(ampdu_tid);
+ host_event->h_event = SOC_EVT_RC_AMPDU_REPORT;
+ report_data =
+ (struct firmware_rate_control_report_data *)&host_event->dat[0];
+ report_data->ampdu_len = aggr_num;
+ report_data->ampdu_ack_len = 0;
+ report_data->wsid = ssv_sta_priv->sta_info->hw_wsid;
+ skb_queue_tail(&sc->rc_report_queue, skb);
+ if (sc->rc_sample_sechedule == 0)
+ queue_work(sc->rc_sample_workqueue, &sc->rc_sample_work);
+}
+
+void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data
+ +
+ SSV6XXX_RX_DESC_LEN);
+ AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
+ struct ieee80211_sta *sta;
+ struct ssv_sta_priv_data *ssv_sta_priv;
+ struct ampdu_ba_notify_data *ba_notification;
+ u32 ssn, aggr_num = 0, acked_num = 0;
+ u8 tid_no;
+ u32 sn_bit_map[2];
+ struct firmware_rate_control_report_data *report_data;
+ HDR_HostEvent *host_evt;
+ sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
+ if (sta == NULL) {
+ if (skb->len > AMPDU_BA_FRAME_LEN) {
+ char strbuf[256];
+ struct ampdu_ba_notify_data *ba_notification =
+ (struct ampdu_ba_notify_data *)(skb->data + skb->len
+ -
+ sizeof(struct
+ ampdu_ba_notify_data));
+ _dump_BA_notification(strbuf, ba_notification);
+ prn_aggr_err
+ ("BA from not connected STA (%02X-%02X-%02X-%02X-%02X-%02X) (%s)\n",
+ BA_frame->ta_addr[0], BA_frame->ta_addr[1],
+ BA_frame->ta_addr[2], BA_frame->ta_addr[3],
+ BA_frame->ta_addr[4], BA_frame->ta_addr[5],
+ strbuf);
+ }
+ dev_kfree_skb_any(skb);
+ return;
+ }
+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ ssn = BA_frame->BA_ssn;
+ sn_bit_map[0] = BA_frame->BA_sn_bit_map[0];
+ sn_bit_map[1] = BA_frame->BA_sn_bit_map[1];
+ tid_no = BA_frame->tid_info;
+ ssv_sta_priv->ampdu_mib_total_BA_counter++;
+ if (ssv_sta_priv->ampdu_tid[tid_no].state == AMPDU_STATE_STOP) {
+ prn_aggr_err
+ ("ssv6200_ampdu_BA_handler state == AMPDU_STATE_STOP.\n");
+ dev_kfree_skb_any(skb);
+ return;
+ }
+ ssv_sta_priv->ampdu_tid[tid_no].mib.ampdu_mib_BA_counter++;
+ if (skb->len <= AMPDU_BA_FRAME_LEN) {
+ prn_aggr_err("b %d\n", ssn);
+ dev_kfree_skb_any(skb);
+ return;
+ }
+ ba_notification =
+ (struct ampdu_ba_notify_data *)(skb->data + skb->len
+ -
+ sizeof(struct
+ ampdu_ba_notify_data));
+ aggr_num =
+ _ba_map_walker(&(ssv_sta_priv->ampdu_tid[tid_no]), ssn, sn_bit_map,
+ ba_notification, &acked_num);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (ssv_sta_priv->ampdu_tid[tid_no].debugfs_dir) {
+ struct sk_buff *dup_skb;
+ if (skb_queue_len(&ssv_sta_priv->ampdu_tid[tid_no].ba_q) > 24) {
+ struct sk_buff *ba_skb =
+ skb_dequeue(&ssv_sta_priv->ampdu_tid[tid_no].ba_q);
+ if (ba_skb)
+ dev_kfree_skb_any(ba_skb);
+ }
+ dup_skb = skb_clone(skb, GFP_ATOMIC);
+ if (dup_skb)
+ skb_queue_tail(&ssv_sta_priv->ampdu_tid[tid_no].ba_q,
+ dup_skb);
+ }
+#endif
+ skb_trim(skb, skb->len - sizeof(struct ampdu_ba_notify_data));
+ host_evt = (HDR_HostEvent *) skb->data;
+ host_evt->h_event = SOC_EVT_RC_AMPDU_REPORT;
+ report_data =
+ (struct firmware_rate_control_report_data *)&host_evt->dat[0];
+ memcpy(report_data, ba_notification,
+ sizeof(struct firmware_rate_control_report_data));
+ report_data->ampdu_len = aggr_num;
+ report_data->ampdu_ack_len = acked_num;
+#ifdef RATE_CONTROL_HT_PERCENTAGE_TRACE
+ if ((acked_num) && (acked_num != aggr_num)) {
+ int i;
+ for (i = 0; i < SSV62XX_TX_MAX_RATES; i++) {
+ if (report_data->rates[i].data_rate == -1)
+ break;
+ if (report_data->rates[i].count == 0)
+ dev_err(sc->dev, "illegal HT report\n");
+
+ dev_dbg(sc->dev, "i=[%d] rate[%d] count[%d]\n", i,
+ report_data->rates[i].data_rate,
+ report_data->rates[i].count);
+ }
+ dev_dbg(sc->dev, "AMPDU percentage = %d%% \n",
+ acked_num * 100 / aggr_num);
+ } else if (acked_num == 0) {
+ dev_dbg(sc->dev, "AMPDU percentage = 0%% aggr_num=%d acked_num=%d\n",
+ aggr_num, acked_num);
+ }
+#endif
+ skb_queue_tail(&sc->rc_report_queue, skb);
+ if (sc->rc_sample_sechedule == 0)
+ queue_work(sc->rc_sample_workqueue, &sc->rc_sample_work);
+}
+
+static void _postprocess_BA(struct ssv_softc *sc, struct ssv_sta_info *sta_info,
+ void *param)
+{
+ int j;
+ struct ssv_sta_priv_data *ssv_sta_priv;
+ if ((sta_info->sta == NULL)
+ || ((sta_info->s_flags & STA_FLAG_VALID) == 0))
+ return;
+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+ for (j = 0; j < WMM_TID_NUM; j++) {
+ AMPDU_TID *ampdu_tid = &ssv_sta_priv->ampdu_tid[j];
+ if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+ continue;
+ _collect_retry_frames(ampdu_tid);
+ ssv6200_ampdu_send_retry(sc->hw, ampdu_tid,
+ &ampdu_tid->retry_queue, true);
+ _flush_early_ampdu_q(sc, ampdu_tid);
+ _flush_release_queue(sc->hw, &ampdu_tid->release_queue);
+ }
+}
+
+void ssv6xxx_ampdu_postprocess_BA(struct ieee80211_hw *hw)
+{
+ struct ssv_softc *sc = hw->priv;
+ ssv6xxx_foreach_sta(sc, _postprocess_BA, NULL);
+}
+
+static void ssv6200_hw_set_rx_ba_session(struct ssv_hw *sh, bool on, u8 * ta,
+ u16 tid, u16 ssn, u8 buf_size)
+{
+ if (on) {
+ u32 u32ta;
+ u32ta = 0;
+ u32ta |= (ta[0] & 0xff) << (8 * 0);
+ u32ta |= (ta[1] & 0xff) << (8 * 1);
+ u32ta |= (ta[2] & 0xff) << (8 * 2);
+ u32ta |= (ta[3] & 0xff) << (8 * 3);
+ SMAC_REG_WRITE(sh, ADR_BA_TA_0, u32ta);
+ u32ta = 0;
+ u32ta |= (ta[4] & 0xff) << (8 * 0);
+ u32ta |= (ta[5] & 0xff) << (8 * 1);
+ SMAC_REG_WRITE(sh, ADR_BA_TA_1, u32ta);
+ SMAC_REG_WRITE(sh, ADR_BA_TID, tid);
+ SMAC_REG_WRITE(sh, ADR_BA_ST_SEQ, ssn);
+ SMAC_REG_WRITE(sh, ADR_BA_SB0, 0);
+ SMAC_REG_WRITE(sh, ADR_BA_SB1, 0);
+ SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0xb);
+ } else {
+ SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0x0);
+ }
+}
+
+void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work)
+{
+ struct ssv_softc
+ *sc = container_of(work, struct ssv_softc, set_ampdu_rx_add_work);
+ ssv6200_hw_set_rx_ba_session(sc->sh, true, sc->ba_ra_addr, sc->ba_tid,
+ sc->ba_ssn, 64);
+}
+
+void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work)
+{
+ struct ssv_softc *sc = container_of(work, struct ssv_softc,
+ set_ampdu_rx_del_work);
+ u8 addr[6] = { 0 };
+ ssv6200_hw_set_rx_ba_session(sc->sh, false, addr, 0, 0, 0);
+}
+
+static void _reset_ampdu_mib(struct ssv_softc *sc,
+ struct ssv_sta_info *sta_info, void *param)
+{
+ struct ieee80211_sta *sta = sta_info->sta;
+ struct ssv_sta_priv_data *ssv_sta_priv;
+ int i;
+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ for (i = 0; i < WMM_TID_NUM; i++) {
+ ssv_sta_priv->ampdu_tid[i].ampdu_mib_reset = 1;
+ }
+}
+
+void ssv6xxx_ampdu_mib_reset(struct ieee80211_hw *hw)
+{
+ struct ssv_softc *sc = hw->priv;
+ if (sc == NULL)
+ return;
+ ssv6xxx_foreach_sta(sc, _reset_ampdu_mib, NULL);
+}
+
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ssize_t ampdu_tx_mib_dump(struct ssv_sta_priv_data *ssv_sta_priv,
+ char *mib_str, ssize_t length)
+{
+ ssize_t buf_size = length;
+ ssize_t prt_size;
+ int j;
+ struct ssv_sta_info *ssv_sta = ssv_sta_priv->sta_info;
+ if (ssv_sta->sta == NULL) {
+ prt_size = snprintf(mib_str, buf_size, "\n NULL STA.\n");
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ goto mib_dump_exit;
+ }
+ for (j = 0; j < WMM_TID_NUM; j++) {
+ int k;
+ struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[j];
+ struct AMPDU_MIB_st *ampdu_mib = &ampdu_tid->mib;
+ prt_size =
+ snprintf(mib_str, buf_size, "\n WMM_TID %d@%d\n", j,
+ ampdu_tid->state);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+ continue;
+ prt_size =
+ snprintf(mib_str, buf_size, " BA window size: %d\n",
+ ampdu_tid->ssv_baw_size);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ prt_size =
+ snprintf(mib_str, buf_size, " BA window head: %d\n",
+ ampdu_tid->ssv_baw_head);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ prt_size = snprintf(mib_str, buf_size,
+ " Sending aggregated #: %d\n",
+ ampdu_tid->aggr_pkt_num);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ prt_size =
+ snprintf(mib_str, buf_size, " Waiting #: %d\n",
+ skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue));
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ prt_size =
+ snprintf(mib_str, buf_size, " Early aggregated %d\n",
+ ampdu_tid->early_aggr_skb_num);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ prt_size = snprintf(mib_str, buf_size,
+ " MPDU: %d\n",
+ ampdu_mib->ampdu_mib_mpdu_counter);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ prt_size = snprintf(mib_str, buf_size,
+ " Passed: %d\n",
+ ampdu_mib->ampdu_mib_pass_counter);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ prt_size = snprintf(mib_str, buf_size,
+ " Retry: %d\n",
+ ampdu_mib->ampdu_mib_retry_counter);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ prt_size = snprintf(mib_str, buf_size,
+ " AMPDU: %d\n",
+ ampdu_mib->ampdu_mib_ampdu_counter);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ prt_size = snprintf(mib_str, buf_size,
+ " Retry AMPDU: %d\n",
+ ampdu_mib->ampdu_mib_aggr_retry_counter);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ prt_size = snprintf(mib_str, buf_size,
+ " BAR count: %d\n",
+ ampdu_mib->ampdu_mib_bar_counter);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ prt_size = snprintf(mib_str, buf_size,
+ " Discard count: %d\n",
+ ampdu_mib->ampdu_mib_discard_counter);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ prt_size = snprintf(mib_str, buf_size,
+ " BA count: %d\n",
+ ampdu_mib->ampdu_mib_BA_counter);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ prt_size =
+ snprintf(mib_str, buf_size, " Total BA count: %d\n",
+ ssv_sta_priv->ampdu_mib_total_BA_counter);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ prt_size =
+ snprintf(mib_str, buf_size, " Aggr # count:\n");
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ for (k = 0; k <= SSV_AMPDU_aggr_num_max; k++) {
+ prt_size =
+ snprintf(mib_str, buf_size, " %d: %d\n",
+ k, ampdu_mib->ampdu_mib_dist[k]);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ }
+ }
+ mib_dump_exit:
+ return (length - buf_size);
+}
+
+static void _dump_ampdu_mib(struct ssv_softc *sc, struct ssv_sta_info *sta_info,
+ void *param)
+{
+ struct mib_dump_data *dump_data = (struct mib_dump_data *)param;
+ struct ieee80211_sta *sta;
+ struct ssv_sta_priv_data *ssv_sta_priv;
+ ssize_t buf_size;
+ ssize_t prt_size;
+ char *mib_str = dump_data->prt_buff;
+ if (param == NULL)
+ return;
+ buf_size = dump_data->buff_size - 1;
+ sta = sta_info->sta;
+ if ((sta == NULL) || ((sta_info->s_flags & STA_FLAG_VALID) == 0))
+ return;
+ prt_size = snprintf(mib_str, buf_size,
+ "STA: %02X-%02X-%02X-%02X-%02X-%02X:\n",
+ sta->addr[0], sta->addr[1], sta->addr[2],
+ sta->addr[3], sta->addr[4], sta->addr[5]);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ prt_size = ampdu_tx_mib_dump(ssv_sta_priv, mib_str, buf_size);
+ mib_str += prt_size;
+ buf_size -= prt_size;
+ dump_data->prt_len = (dump_data->buff_size - 1 - buf_size);
+ dump_data->prt_buff = mib_str;
+ dump_data->buff_size = buf_size;
+}
+
+ssize_t ssv6xxx_ampdu_mib_dump(struct ieee80211_hw *hw, char *mib_str,
+ ssize_t length)
+{
+ struct ssv_softc *sc = hw->priv;
+ ssize_t buf_size = length - 1;
+ struct mib_dump_data dump_data = { mib_str, buf_size, 0 };
+ if (sc == NULL)
+ return 0;
+ ssv6xxx_foreach_sta(sc, _dump_ampdu_mib, &dump_data);
+ return dump_data.prt_len;
+}
+#endif
+struct sk_buff *_alloc_ampdu_skb(struct ssv_softc *sc,
+ struct AMPDU_TID_st *ampdu_tid, u32 len)
+{
+ unsigned char *payload_addr;
+ u32 headroom = sc->hw->extra_tx_headroom;
+ u32 offset;
+ u32 cur_max_ampdu_size = SSV_GET_MAX_AMPDU_SIZE(sc->sh);
+ u32 extra_room = sc->sh->tx_desc_len * 2 + 48;
+ u32 max_physical_len = (len
+ && ((len + extra_room) < cur_max_ampdu_size))
+ ? (len + extra_room)
+ : cur_max_ampdu_size;
+ u32 skb_len = max_physical_len + headroom + 3;
+ struct sk_buff *ampdu_skb = __dev_alloc_skb(skb_len, GFP_KERNEL);
+ struct ampdu_hdr_st *ampdu_hdr;
+ if (ampdu_skb == NULL) {
+ dev_err(sc->dev, "AMPDU allocation of size %d(%d) failed\n",
+ len, skb_len);
+ return NULL;
+ }
+ payload_addr = ampdu_skb->data + headroom - sc->sh->tx_desc_len;
+ offset = ((size_t)payload_addr) % 4U;
+ if (offset) {
+ dev_dbg(sc->dev, "Align AMPDU data %d\n", offset);
+ skb_reserve(ampdu_skb, headroom + 4 - offset);
+ } else
+ skb_reserve(ampdu_skb, headroom);
+ ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
+ skb_queue_head_init(&ampdu_hdr->mpdu_q);
+ ampdu_hdr->max_size = max_physical_len - extra_room;
+ ampdu_hdr->size = 0;
+ ampdu_hdr->ampdu_tid = ampdu_tid;
+ memset(ampdu_hdr->ssn, 0xFF, sizeof(ampdu_hdr->ssn));
+ ampdu_hdr->mpdu_num = 0;
+ return ampdu_skb;
+}
+
+bool _is_skb_q_empty(struct ssv_softc *sc, struct sk_buff *skb)
+{
+ u32 ac = skb_get_queue_mapping(skb);
+ u32 hw_txqid = sc->tx.hw_txqid[ac];
+ return AMPDU_HCI_Q_EMPTY(sc->sh, hw_txqid);
+}
+
+static u32 _check_timeout(struct AMPDU_TID_st *ampdu_tid)
+{
+ u16 ssn, head_ssn, end_ssn;
+ unsigned long check_jiffies = jiffies;
+ u32 has_retry = 0;
+ head_ssn = ampdu_tid->ssv_baw_head;
+ ssn = head_ssn;
+ if (ssn == SSV_ILLEGAL_SN)
+ return 0;
+ end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN;
+ do {
+ struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+ struct SKB_info_st *skb_info;
+ unsigned long cur_jiffies;
+ unsigned long timeout_jiffies;
+ u32 delta_ms;
+ if (skb == NULL)
+ break;
+ skb_info = (SKB_info *) (skb->head);
+ cur_jiffies = jiffies;
+ timeout_jiffies =
+ skb_info->aggr_timestamp +
+ msecs_to_jiffies(BA_WAIT_TIMEOUT);
+ if ((skb_info->ampdu_tx_status != AMPDU_ST_SENT)
+ || time_before(cur_jiffies, timeout_jiffies))
+ break;
+ delta_ms =
+ jiffies_to_msecs(cur_jiffies - skb_info->aggr_timestamp);
+ prn_aggr_err("rt S%d-T%d-%d (%u)\n",
+ ((struct ssv_sta_priv_data *)skb_info->sta->
+ drv_priv)->sta_idx, ampdu_tid->tidno, ssn,
+ delta_ms);
+ if (delta_ms > 1000) {
+ prn_aggr_err("Last checktime %lu - %lu = %u\n",
+ check_jiffies, ampdu_tid->timestamp,
+ jiffies_to_msecs(check_jiffies -
+ ampdu_tid->timestamp));
+ }
+ has_retry += _mark_skb_retry(skb_info, skb);
+ INC_PKT_SN(ssn);
+ } while (ssn != end_ssn);
+ ampdu_tid->timestamp = check_jiffies;
+ return has_retry;
+}
+
+void ssv6xxx_ampdu_check_timeout(struct ieee80211_hw *hw)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct AMPDU_TID_st *cur_AMPDU_TID;
+ if (!list_empty(&sc->tx.ampdu_tx_que)) {
+ list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que,
+ list) {
+ u32 has_retry;
+ if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION)
+ continue;
+ has_retry = _check_timeout(cur_AMPDU_TID);
+ if (has_retry) {
+ _collect_retry_frames(cur_AMPDU_TID);
+ ssv6200_ampdu_send_retry(sc->hw, cur_AMPDU_TID,
+ &cur_AMPDU_TID->
+ retry_queue, true);
+ }
+ }
+ }
+}
+
+void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
+ struct sk_buff *mpdu;
+ unsigned long cur_jiffies = jiffies;
+ int i;
+ SKB_info *mpdu_skb_info;
+ u16 ssn;
+ if (ampdu_hdr->ampdu_tid->state != AMPDU_STATE_OPERATION)
+ return;
+ spin_lock_bh(&ampdu_hdr->ampdu_tid->pkt_array_lock);
+ for (i = 0; i < ampdu_hdr->mpdu_num; i++) {
+ ssn = ampdu_hdr->ssn[i];
+ mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn);
+ if (mpdu == NULL) {
+ dev_err(sc->dev, "T%d-%d is a NULL MPDU.\n",
+ ampdu_hdr->ampdu_tid->tidno, ssn);
+ continue;
+ }
+ if (ampdu_skb_ssn(mpdu) != ssn) {
+ dev_err(sc->dev, "T%d-%d does not match %d MPDU.\n",
+ ampdu_hdr->ampdu_tid->tidno, ssn,
+ ampdu_skb_ssn(mpdu));
+ continue;
+ }
+ mpdu_skb_info = (SKB_info *) (mpdu->head);
+ mpdu_skb_info->aggr_timestamp = cur_jiffies;
+ mpdu_skb_info->ampdu_tx_status = AMPDU_ST_SENT;
+ }
+ spin_unlock_bh(&ampdu_hdr->ampdu_tid->pkt_array_lock);
+}
diff --git a/drivers/net/wireless/ssv6051/smac/ampdu.h b/drivers/net/wireless/ssv6051/smac/ampdu.h
new file mode 100644
index 000000000000..faa61c4f9297
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ampdu.h
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _AMPDU_H_
+#define _AMPDU_H_
+#include <linux/version.h>
+#include <ssv6200_common.h>
+#define Enable_ampdu_debug_log (0)
+#define Enable_AMPDU_Live_Time (0)
+#define Enable_HW_AUTO_CRC_32 (1)
+#define Enable_AMPDU_Rx (1)
+#define Enable_AMPDU_Tx (1)
+#define Enable_AMPDU_FW_Retry (1)
+#define Enable_AMPDU_delay_work (1)
+#define USE_FLUSH_RETRY
+#define USE_AMPDU_TX_STATUS_ARRAY
+#define SSV_AMPDU_FLOW_CONTROL
+#define AMPDU_CHECK_SKB_SEQNO
+#define REPORT_TX_STATUS_DIRECTLY
+#define SSV_AMPDU_aggr_num_max MAX_AGGR_NUM
+#define SSV_AMPDU_seq_num_max (4096)
+#define SSV_AMPDU_retry_counter_max (3)
+#define SSV_AMPDU_tx_group_id_max (64)
+#define SSV_AMPDU_MAX_SSN (4096)
+#define SSV_AMPDU_BA_WINDOW_SIZE (64)
+#define SSV_AMPDU_WINDOW_SIZE (64)
+#define SSV_GET_MAX_AMPDU_SIZE(sh) (((sh)->tx_page_available/(sh)->ampdu_divider) << HW_MMU_PAGE_SHIFT)
+#define SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND (64)
+#define SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND (48)
+#define SSV_AMPDU_timer_period (50)
+#define SSV_AMPDU_TX_TIME_THRESHOLD (50)
+#define SSV_AMPDU_MPDU_LIVE_TIME (SSV_AMPDU_retry_counter_max*8)
+#define SSV_AMPDU_BA_TIME (50)
+#define SSV_ILLEGAL_SN (0xffff)
+#define AMPDU_BUFFER_SIZE (32*1024)
+#define AMPDU_SIGNATURE (0x4E)
+#define AMPDU_DELIMITER_LEN (4)
+#define AMPDU_FCS_LEN (4)
+#define AMPDU_RESERVED_LEN (3)
+#define AMPDU_TX_NAV_MCS_567 (48)
+#define SSV_SEQ_NUM_SHIFT (4)
+#define SSV_RETRY_BIT_SHIFT (11)
+#define IEEE80211_SEQ_SEQ_SHIFT (4)
+#define IEEE80211_AMPDU_BA_LEN (34)
+#define SSV6200_AMPDU_TRIGGER_INDEX 0
+#define SSV_SN_STATUS_Release (0xaa)
+#define SSV_SN_STATUS_Retry (0xbb)
+#define SSV_SN_STATUS_Wait_BA (0xcc)
+#define SSV_SN_STATUS_Discard (0xdd)
+#define AMPDU_HCI_SEND_TAIL_WITH_FLOWCTRL (0)
+#define AMPDU_HCI_SEND_HEAD_WITH_FLOWCTRL (1)
+#define AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL (2)
+#define AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL (3)
+#define SSV_BAR_CTRL_ACK_POLICY_NORMAL (0x0000)
+#define SSV_BAR_CTRL_CBMTID_COMPRESSED_BA (0x0004)
+#define SSV_BAR_CTRL_TID_INFO_SHIFT (12)
+#define AMPDU_STATE_START BIT(0)
+#define AMPDU_STATE_OPERATION BIT(1)
+#define AMPDU_STATE_STOP BIT(2)
+typedef enum {
+ AMPDU_REKEY_PAUSE_STOP = 0,
+ AMPDU_REKEY_PAUSE_START,
+ AMPDU_REKEY_PAUSE_ONGOING,
+ AMPDU_REKEY_PAUSE_DEFER,
+ AMPDU_REKEY_PAUSE_HWKEY_SYNC,
+} AMPDU_REKEY_PAUSE_STATE;
+#define SSV_a_minus_b_in_c(a,b,c) (((a)>=(b))?((a)-(b)):((c)-(b)+(a)))
+#define SSV_AMPDU_SN_a_minus_b(a,b) (SSV_a_minus_b_in_c((a), (b), SSV_AMPDU_seq_num_max))
+#define AMPDU_HCI_SEND(_sh,_sk,_q,_flag) (_sh)->hci.hci_ops->hci_tx((_sk), (_q), (_flag))
+#define AMPDU_HCI_Q_EMPTY(_sh,_q) (_sh)->hci.hci_ops->hci_txq_empty((_q))
+struct ampdu_hdr_st {
+ u32 first_sn;
+ struct sk_buff_head mpdu_q;
+ u32 max_size;
+ u32 size;
+ struct AMPDU_TID_st *ampdu_tid;
+ u16 ssn[MAX_AGGR_NUM];
+ u16 mpdu_num;
+ struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
+ struct ieee80211_sta *sta;
+};
+enum AMPDU_TX_STATUS_E {
+ AMPDU_ST_NON_AMPDU,
+ AMPDU_ST_AGGREGATED,
+ AMPDU_ST_SENT,
+ AMPDU_ST_RETRY,
+ AMPDU_ST_DROPPED,
+ AMPDU_ST_DONE,
+};
+typedef struct AMPDU_MIB_st {
+ u32 ampdu_mib_mpdu_counter;
+ u32 ampdu_mib_retry_counter;
+ u32 ampdu_mib_ampdu_counter;
+ u32 ampdu_mib_aggr_retry_counter;
+ u32 ampdu_mib_bar_counter;
+ u32 ampdu_mib_discard_counter;
+ u32 ampdu_mib_total_BA_counter;
+ u32 ampdu_mib_BA_counter;
+ u32 ampdu_mib_pass_counter;
+ u32 ampdu_mib_dist[SSV_AMPDU_aggr_num_max + 1];
+} AMPDU_MIB;
+typedef struct AMPDU_TID_st {
+ struct list_head list;
+ volatile unsigned long timestamp;
+ u32 tidno;
+ u16 ac;
+ struct ieee80211_sta *sta;
+ u16 ssv_baw_size;
+ u8 agg_num_max;
+ u8 state;
+#ifdef AMPDU_CHECK_SKB_SEQNO
+ u32 last_seqno;
+#endif
+ struct sk_buff_head ampdu_skb_tx_queue;
+ spinlock_t ampdu_skb_tx_queue_lock;
+ struct sk_buff_head retry_queue;
+ struct sk_buff_head release_queue;
+ struct sk_buff *aggr_pkts[SSV_AMPDU_BA_WINDOW_SIZE];
+ volatile u32 aggr_pkt_num;
+ volatile u16 ssv_baw_head;
+ spinlock_t pkt_array_lock;
+ struct sk_buff *cur_ampdu_pkt;
+ struct sk_buff_head early_aggr_ampdu_q;
+ u32 early_aggr_skb_num;
+ struct sk_buff_head ampdu_skb_wait_encry_queue;
+ u32 ampdu_mib_reset;
+ struct AMPDU_MIB_st mib;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct dentry *debugfs_dir;
+ struct sk_buff_head ba_q;
+#endif
+} AMPDU_TID, *p_AMPDU_TID;
+typedef struct AMPDU_DELIMITER_st {
+ u16 reserved:4;
+ u16 length:12;
+ u8 crc;
+ u8 signature;
+} AMPDU_DELIMITER, *p_AMPDU_DELIMITER;
+typedef struct AMPDU_BLOCKACK_st {
+ u16 frame_control;
+ u16 duration;
+ u8 ra_addr[ETH_ALEN];
+ u8 ta_addr[ETH_ALEN];
+ u16 BA_ack_ploicy:1;
+ u16 multi_tid:1;
+ u16 compress_bitmap:1;
+ u16 reserved:9;
+ u16 tid_info:4;
+ u16 BA_fragment_sn:4;
+ u16 BA_ssn:12;
+ u32 BA_sn_bit_map[2];
+} AMPDU_BLOCKACK, *p_AMPDU_BLOCKACK;
+struct ssv_bar {
+ unsigned short frame_control;
+ unsigned short duration;
+ unsigned char ra[6];
+ unsigned char ta[6];
+ unsigned short control;
+ unsigned short start_seq_num;
+} __packed;
+#if Enable_ampdu_debug_log
+#define ampdu_db_log(format, args...) printk("~~~ampdu [%s:%d] "format, __FUNCTION__, __LINE__, ##args)
+#define ampdu_db_log_simple(format, args...) printk(format, ##args)
+#else
+#define ampdu_db_log(...) do {} while (0)
+#define ampdu_db_log_simple(...) do {} while (0)
+#endif
+#if Enable_AMPDU_delay_work
+void ssv6200_ampdu_delayed_work_callback_func(struct work_struct *work);
+#else
+void ssv6200_ampdu_timer_callback_func(unsigned long data);
+#endif
+void ssv6200_ampdu_init(struct ieee80211_hw *hw);
+void ssv6200_ampdu_deinit(struct ieee80211_hw *hw);
+void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw);
+void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta,
+ struct ieee80211_hw *hw, u16 * ssn);
+void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta,
+ struct ieee80211_hw *hw, u8 buffer_size);
+void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta,
+ struct ieee80211_hw *hw);
+bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
+u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw);
+void ssv6200_ampdu_timeout_tx(struct ieee80211_hw *hw);
+struct cfg_host_event;
+void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
+void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
+void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta,
+ struct sk_buff *skb);
+void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw,
+ struct ieee80211_sta *sta);
+void ssv6xxx_ampdu_postprocess_BA(struct ieee80211_hw *hw);
+void ssv6xxx_ampdu_check_timeout(struct ieee80211_hw *hw);
+void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu);
+extern void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work);
+extern void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work);
+void ssv6xxx_mib_reset(struct ieee80211_hw *hw);
+ssize_t ssv6xxx_mib_dump(struct ieee80211_hw *hw, char *mib_str,
+ ssize_t length);
+void encry_work(struct work_struct *work);
+void sync_hw_key_work(struct work_struct *work);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ap.c b/drivers/net/wireless/ssv6051/smac/ap.c
new file mode 100644
index 000000000000..0f2ba6a31a05
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ap.c
@@ -0,0 +1,598 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200.h>
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <linux/sched.h>
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include "lib.h"
+#include "dev.h"
+#include "ap.h"
+#include "ssv_rc_common.h"
+#include "ssv_rc.h"
+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);
+#define IS_EQUAL(a,b) ( (a) == (b) )
+#define SET_BIT(v,b) ( (v) |= (0x01<<b) )
+#define CLEAR_BIT(v,b) ( (v) &= ~(0x01<<b) )
+#define IS_BIT_SET(v,b) ( (v) & (0x01<<(b) ) )
+#define PBUF_BASE_ADDR 0x80000000
+#define PBUF_ADDR_SHIFT 16
+#define PBUF_MapPkttoID(_PKT) (((u32)_PKT&0x0FFF0000)>>PBUF_ADDR_SHIFT)
+#define PBUF_MapIDtoPkt(_ID) (PBUF_BASE_ADDR|((_ID)<<PBUF_ADDR_SHIFT))
+#define SSV6xxx_BEACON_MAX_ALLOCATE_CNT 10
+#define MTX_BCN_PKTID_CH_LOCK_SHIFT MTX_BCN_PKTID_CH_LOCK_SFT
+#define MTX_BCN_CFG_VLD_SHIFT MTX_BCN_CFG_VLD_SFT
+#define MTX_BCN_CFG_VLD_MASK MTX_BCN_CFG_VLD_MSK
+#define AUTO_BCN_ONGOING_MASK MTX_AUTO_BCN_ONGOING_MSK
+#define AUTO_BCN_ONGOING_SHIFT MTX_AUTO_BCN_ONGOING_SFT
+#define MTX_BCN_TIMER_EN_SHIFT MTX_BCN_TIMER_EN_SFT
+#define MTX_TSF_TIMER_EN_SHIFT MTX_TSF_TIMER_EN_SFT
+#define MTX_HALT_MNG_UNTIL_DTIM_SHIFT MTX_HALT_MNG_UNTIL_DTIM_SFT
+#define MTX_BCN_ENABLE_MASK (MTX_BCN_TIMER_EN_I_MSK)
+#define MTX_BCN_PERIOD_SHIFT MTX_BCN_PERIOD_SFT
+#define MTX_DTIM_NUM_SHIFT MTX_DTIM_NUM_SFT
+#define MTX_DTIM_OFST0 MTX_DTIM_OFST0_SFT
+enum ssv6xxx_beacon_type {
+ SSV6xxx_BEACON_0,
+ SSV6xxx_BEACON_1,
+};
+static const u32 ssv6xxx_beacon_adr[] = {
+ ADR_MTX_BCN_CFG0,
+ ADR_MTX_BCN_CFG1,
+};
+
+void ssv6xxx_beacon_reg_lock(struct ssv_softc *sc, bool block)
+{
+ u32 val;
+ val = block << MTX_BCN_PKTID_CH_LOCK_SHIFT;
+#ifdef BEACON_DEBUG
+ printk("ssv6xxx_beacon_reg_lock val[0x:%08x]\n ", val);
+#endif
+ SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_MISC, val);
+}
+
+void ssv6xxx_beacon_set_info(struct ssv_softc *sc, u8 beacon_interval,
+ u8 dtim_cnt)
+{
+ u32 val;
+ if (beacon_interval == 0)
+ beacon_interval = 100;
+#ifdef BEACON_DEBUG
+ printk("[A] BSS_CHANGED_BEACON_INT beacon_int[%d] dtim_cnt[%d]\n",
+ beacon_interval, (dtim_cnt));
+#endif
+ val =
+ (beacon_interval << MTX_BCN_PERIOD_SHIFT) | (dtim_cnt <<
+ MTX_DTIM_NUM_SHIFT);
+ SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_PRD, val);
+}
+
+bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable)
+{
+ u32 regval = 0;
+ int ret = 0;
+ if (bEnable && !sc->beacon_usage) {
+ printk
+ ("[A] Reject to set beacon!!!. ssv6xxx_beacon_enable bEnable[%d] sc->beacon_usage[%d]\n",
+ bEnable, sc->beacon_usage);
+ sc->enable_beacon = BEACON_WAITING_ENABLED;
+ return 0;
+ }
+ if ((bEnable && (BEACON_ENABLED & sc->enable_beacon)) ||
+ (!bEnable && !sc->enable_beacon)) {
+ printk
+ ("[A] ssv6xxx_beacon_enable bEnable[%d] and sc->enable_beacon[%d] are the same. no need to execute.\n",
+ bEnable, sc->enable_beacon);
+ if (bEnable) {
+ printk(" Ignore enable beacon cmd!!!!\n");
+ return 0;
+ }
+ }
+ SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, &regval);
+#ifdef BEACON_DEBUG
+ printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+#endif
+ regval &= MTX_BCN_ENABLE_MASK;
+#ifdef BEACON_DEBUG
+ printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+#endif
+ regval |= (bEnable << MTX_BCN_TIMER_EN_SHIFT);
+ ret = SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval);
+#ifdef BEACON_DEBUG
+ printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+#endif
+ sc->enable_beacon = (bEnable == true) ? BEACON_ENABLED : 0;
+ return ret;
+}
+
+int ssv6xxx_beacon_fill_content(struct ssv_softc *sc, u32 regaddr, u8 * beacon,
+ int size)
+{
+ u32 i, val;
+ u32 *ptr = (u32 *) beacon;
+ size = size / 4;
+ for (i = 0; i < size; i++) {
+ val = (u32) (*(ptr + i));
+#ifdef BEACON_DEBUG
+ printk("[%08x] ", val);
+#endif
+ SMAC_REG_WRITE(sc->sh, regaddr + i * 4, val);
+ }
+#ifdef BEACON_DEBUG
+ printk("\n");
+#endif
+ return 0;
+}
+
+void ssv6xxx_beacon_fill_tx_desc(struct ssv_softc *sc,
+ struct sk_buff *beacon_skb)
+{
+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(beacon_skb);
+ struct ssv6200_tx_desc *tx_desc;
+ u16 pb_offset = TXPB_OFFSET;
+ struct ssv_rate_info ssv_rate;
+ skb_push(beacon_skb, pb_offset);
+ tx_desc = (struct ssv6200_tx_desc *)beacon_skb->data;
+ memset(tx_desc, 0, pb_offset);
+ ssv6xxx_rc_hw_rate_idx(sc, tx_info, &ssv_rate);
+ tx_desc->len = beacon_skb->len - pb_offset;
+ tx_desc->c_type = M2_TXREQ;
+ tx_desc->f80211 = 1;
+ tx_desc->ack_policy = 1;
+ tx_desc->hdr_offset = pb_offset;
+ tx_desc->hdr_len = 24;
+ tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
+ tx_desc->crate_idx = ssv_rate.crate_hw_idx;
+ tx_desc->drate_idx = ssv_rate.drate_hw_idx;
+ skb_put(beacon_skb, 4);
+}
+
+inline enum ssv6xxx_beacon_type ssv6xxx_beacon_get_valid_reg(struct ssv_softc
+ *sc)
+{
+ u32 regval = 0;
+ SMAC_REG_READ(sc->sh, ADR_MTX_BCN_MISC, &regval);
+ regval &= MTX_BCN_CFG_VLD_MASK;
+ regval = regval >> MTX_BCN_CFG_VLD_SHIFT;
+ if (regval == 0x2 || regval == 0x0)
+ return SSV6xxx_BEACON_0;
+ else if (regval == 0x1)
+ return SSV6xxx_BEACON_1;
+ else
+ printk("=============>ERROR!!drv_bcn_reg_available\n");
+ return SSV6xxx_BEACON_0;
+}
+
+bool ssv6xxx_beacon_set(struct ssv_softc *sc, struct sk_buff *beacon_skb,
+ int dtim_offset)
+{
+ u32 reg_tx_beacon_adr = ADR_MTX_BCN_CFG0;
+ enum ssv6xxx_beacon_type avl_bcn_type = SSV6xxx_BEACON_0;
+ bool ret = true;
+ int val;
+ ssv6xxx_beacon_reg_lock(sc, 1);
+ avl_bcn_type = ssv6xxx_beacon_get_valid_reg(sc);
+ if (avl_bcn_type == SSV6xxx_BEACON_1)
+ reg_tx_beacon_adr = ADR_MTX_BCN_CFG1;
+#ifdef BEACON_DEBUG
+ printk("[A] ssv6xxx_beacon_set avl_bcn_type[%d]\n", avl_bcn_type);
+#endif
+ do {
+ if (IS_BIT_SET(sc->beacon_usage, avl_bcn_type)) {
+#ifdef BEACON_DEBUG
+ printk
+ ("[A] beacon has already been set old len[%d] new len[%d]\n",
+ sc->beacon_info[avl_bcn_type].len,
+ beacon_skb->len);
+#endif
+ if (sc->beacon_info[avl_bcn_type].len >=
+ beacon_skb->len) {
+ break;
+ } else {
+ if (false ==
+ ssv6xxx_pbuf_free(sc,
+ sc->
+ beacon_info[avl_bcn_type].
+ pubf_addr)) {
+#ifdef BEACON_DEBUG
+ printk
+ ("=============>ERROR!!Intend to allcoate beacon from ASIC fail.\n");
+#endif
+ ret = false;
+ goto out;
+ }
+ CLEAR_BIT(sc->beacon_usage, avl_bcn_type);
+ }
+ }
+ sc->beacon_info[avl_bcn_type].pubf_addr =
+ ssv6xxx_pbuf_alloc(sc, beacon_skb->len, TX_BUF);
+ sc->beacon_info[avl_bcn_type].len = beacon_skb->len;
+ if (sc->beacon_info[avl_bcn_type].pubf_addr == 0) {
+ ret = false;
+ goto out;
+ }
+ SET_BIT(sc->beacon_usage, avl_bcn_type);
+#ifdef BEACON_DEBUG
+ printk
+ ("[A] beacon type[%d] usage[%d] allocate new beacon addr[%08x] \n",
+ avl_bcn_type, sc->beacon_usage,
+ sc->beacon_info[avl_bcn_type].pubf_addr);
+#endif
+ } while (0);
+ ssv6xxx_beacon_fill_content(sc, sc->beacon_info[avl_bcn_type].pubf_addr,
+ beacon_skb->data, beacon_skb->len);
+ val =
+ (PBUF_MapPkttoID(sc->beacon_info[avl_bcn_type].pubf_addr)) |
+ (dtim_offset << MTX_DTIM_OFST0);
+ SMAC_REG_WRITE(sc->sh, reg_tx_beacon_adr, val);
+#ifdef BEACON_DEBUG
+ printk("[A] update to register reg_tx_beacon_adr[%08x] val[%08x]\n",
+ reg_tx_beacon_adr, val);
+#endif
+ out:
+ ssv6xxx_beacon_reg_lock(sc, 0);
+ if (sc->beacon_usage && (sc->enable_beacon & BEACON_WAITING_ENABLED)) {
+ printk("[A] enable beacon for BEACON_WAITING_ENABLED flags\n");
+ ssv6xxx_beacon_enable(sc, true);
+ }
+ return ret;
+}
+
+inline bool ssv6xxx_auto_bcn_ongoing(struct ssv_softc *sc)
+{
+ u32 regval;
+ SMAC_REG_READ(sc->sh, ADR_MTX_BCN_MISC, &regval);
+ return ((AUTO_BCN_ONGOING_MASK & regval) >> AUTO_BCN_ONGOING_SHIFT);
+}
+
+void ssv6xxx_beacon_release(struct ssv_softc *sc)
+{
+ int cnt = 10;
+ printk("[A] ssv6xxx_beacon_release Enter\n");
+ cancel_work_sync(&sc->set_tim_work);
+ do {
+ if (ssv6xxx_auto_bcn_ongoing(sc))
+ ssv6xxx_beacon_enable(sc, false);
+ else
+ break;
+ cnt--;
+ if (cnt <= 0)
+ break;
+ } while (1);
+ if (IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_0)) {
+ ssv6xxx_pbuf_free(sc,
+ sc->beacon_info[SSV6xxx_BEACON_0].pubf_addr);
+ CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_0);
+ }
+ if (IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_1)) {
+ ssv6xxx_pbuf_free(sc,
+ sc->beacon_info[SSV6xxx_BEACON_1].pubf_addr);
+ CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_1);
+ }
+ sc->enable_beacon = 0;
+ if (sc->beacon_buf) {
+ dev_kfree_skb_any(sc->beacon_buf);
+ sc->beacon_buf = NULL;
+ }
+#ifdef BEACON_DEBUG
+ printk("[A] ssv6xxx_beacon_release leave\n");
+#endif
+}
+
+void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif, bool aid0_bit_set)
+{
+ struct sk_buff *skb;
+ struct sk_buff *old_skb = NULL;
+ u16 tim_offset, tim_length;
+ if (sc == NULL || hw == NULL || vif == NULL) {
+ printk("[Error]........ssv6xxx_beacon_change input error\n");
+ return;
+ }
+ do {
+ skb = ieee80211_beacon_get_tim(hw, vif,
+ &tim_offset, &tim_length, 0);
+ if (skb == NULL) {
+ printk("[Error]........skb is NULL\n");
+ break;
+ }
+ if (tim_offset && tim_length >= 6) {
+ skb->data[tim_offset + 2] = 0;
+ if (aid0_bit_set)
+ skb->data[tim_offset + 4] |= 1;
+ else
+ skb->data[tim_offset + 4] &= ~1;
+ }
+#ifdef BEACON_DEBUG
+ printk("[A] beacon len [%d] tim_offset[%d]\n", skb->len,
+ tim_offset);
+#endif
+ ssv6xxx_beacon_fill_tx_desc(sc, skb);
+#ifdef BEACON_DEBUG
+ printk("[A] beacon len [%d] tim_offset[%d]\n", skb->len,
+ tim_offset);
+#endif
+ if (sc->beacon_buf) {
+ if (memcmp
+ (sc->beacon_buf->data, skb->data,
+ (skb->len - FCS_LEN)) == 0) {
+ old_skb = skb;
+ break;
+ } else {
+ old_skb = sc->beacon_buf;
+ sc->beacon_buf = skb;
+ }
+ } else {
+ sc->beacon_buf = skb;
+ }
+ tim_offset += 2;
+ if (ssv6xxx_beacon_set(sc, skb, tim_offset)) {
+ u8 dtim_cnt = vif->bss_conf.dtim_period - 1;
+ if (sc->beacon_dtim_cnt != dtim_cnt) {
+ sc->beacon_dtim_cnt = dtim_cnt;
+#ifdef BEACON_DEBUG
+ printk("[A] beacon_dtim_cnt [%d]\n",
+ sc->beacon_dtim_cnt);
+#endif
+ ssv6xxx_beacon_set_info(sc, sc->beacon_interval,
+ sc->beacon_dtim_cnt);
+ }
+ }
+ } while (0);
+ if (old_skb)
+ dev_kfree_skb_any(old_skb);
+}
+
+void ssv6200_set_tim_work(struct work_struct *work)
+{
+ struct ssv_softc *sc =
+ container_of(work, struct ssv_softc, set_tim_work);
+#ifdef BROADCAST_DEBUG
+ printk("%s() enter\n", __FUNCTION__);
+#endif
+ ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set);
+#ifdef BROADCAST_DEBUG
+ printk("%s() leave\n", __FUNCTION__);
+#endif
+}
+
+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq)
+{
+ u32 len;
+ unsigned long flags;
+ spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+ len = bcast_txq->cur_qsize;
+ spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+ return len;
+}
+
+struct sk_buff *ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq,
+ u8 * remain_len)
+{
+ struct sk_buff *skb = NULL;
+ unsigned long flags;
+ spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+ if (bcast_txq->cur_qsize) {
+ bcast_txq->cur_qsize--;
+ if (remain_len)
+ *remain_len = bcast_txq->cur_qsize;
+ skb = __skb_dequeue(&bcast_txq->qhead);
+ }
+ spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+ return skb;
+}
+
+int ssv6200_bcast_enqueue(struct ssv_softc *sc,
+ struct ssv6xxx_bcast_txq *bcast_txq,
+ struct sk_buff *skb)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+ if (bcast_txq->cur_qsize >= SSV6200_MAX_BCAST_QUEUE_LEN) {
+ struct sk_buff *old_skb;
+ old_skb = __skb_dequeue(&bcast_txq->qhead);
+ bcast_txq->cur_qsize--;
+ ssv6xxx_txbuf_free_skb(old_skb, (void *)sc);
+ printk("[B] ssv6200_bcast_enqueue - remove oldest queue\n");
+ }
+ __skb_queue_tail(&bcast_txq->qhead, skb);
+ bcast_txq->cur_qsize++;
+ spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+ return bcast_txq->cur_qsize;
+}
+
+void ssv6200_bcast_flush(struct ssv_softc *sc,
+ struct ssv6xxx_bcast_txq *bcast_txq)
+{
+ struct sk_buff *skb;
+ unsigned long flags;
+#ifdef BCAST_DEBUG
+ printk("ssv6200_bcast_flush\n");
+#endif
+ spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+ while (bcast_txq->cur_qsize > 0) {
+ skb = __skb_dequeue(&bcast_txq->qhead);
+ bcast_txq->cur_qsize--;
+ ssv6xxx_txbuf_free_skb(skb, (void *)sc);
+ }
+ spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+}
+
+static int queue_block_cnt = 0;
+void ssv6200_bcast_tx_work(struct work_struct *work)
+{
+ struct ssv_softc *sc =
+ container_of(work, struct ssv_softc, bcast_tx_work.work);
+ struct sk_buff *skb;
+ int i;
+ u8 remain_size;
+ unsigned long flags;
+ bool needtimer = true;
+ long tmo = sc->bcast_interval;
+ spin_lock_irqsave(&sc->ps_state_lock, flags);
+ do {
+#ifdef BCAST_DEBUG
+ printk
+ ("[B] bcast_timer: hw_mng_used[%d] HCI_TXQ_EMPTY[%d] bcast_queue_len[%d].....................\n",
+ sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4),
+ ssv6200_bcast_queue_len(&sc->bcast_txq));
+#endif
+ if (sc->hw_mng_used != 0 || false == HCI_TXQ_EMPTY(sc->sh, 4)) {
+#ifdef BCAST_DEBUG
+ printk
+ ("HW queue still have frames insdide. skip this one hw_mng_used[%d] bEmptyTXQ4[%d]\n",
+ sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4));
+#endif
+ queue_block_cnt++;
+ if (queue_block_cnt > 5) {
+ queue_block_cnt = 0;
+ ssv6200_bcast_flush(sc, &sc->bcast_txq);
+ needtimer = false;
+ }
+ break;
+ }
+ queue_block_cnt = 0;
+ for (i = 0; i < SSV6200_ID_MANAGER_QUEUE; i++) {
+ skb =
+ ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size);
+ if (!skb) {
+ needtimer = false;
+ break;
+ }
+ if ((0 != remain_size) &&
+ (SSV6200_ID_MANAGER_QUEUE - 1) != i) {
+ struct ieee80211_hdr *hdr;
+ struct ssv6200_tx_desc *tx_desc =
+ (struct ssv6200_tx_desc *)skb->data;
+ hdr =
+ (struct ieee80211_hdr *)((u8 *) tx_desc +
+ tx_desc->
+ hdr_offset);
+ hdr->frame_control |=
+ cpu_to_le16(IEEE80211_FCTL_MOREDATA);
+ }
+#ifdef BCAST_DEBUG
+ printk("[B] bcast_timer:tx remain_size[%d] i[%d]\n",
+ remain_size, i);
+#endif
+ spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+ if (HCI_SEND(sc->sh, skb, 4) < 0) {
+ printk("bcast_timer send fail!!!!!!! \n");
+ ssv6xxx_txbuf_free_skb(skb, (void *)sc);
+ BUG_ON(1);
+ }
+ spin_lock_irqsave(&sc->ps_state_lock, flags);
+ }
+ } while (0);
+ if (needtimer) {
+#ifdef BCAST_DEBUG
+ printk
+ ("[B] bcast_timer:need more timer to tx bcast frame time[%d]\n",
+ sc->bcast_interval);
+#endif
+ queue_delayed_work(sc->config_wq, &sc->bcast_tx_work, tmo);
+ } else {
+#ifdef BCAST_DEBUG
+ printk("[B] bcast_timer: ssv6200_bcast_stop\n");
+#endif
+ ssv6200_bcast_stop(sc);
+ }
+ spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+#ifdef BCAST_DEBUG
+ printk("[B] bcast_timer: leave.....................\n");
+#endif
+}
+
+void ssv6200_bcast_start_work(struct work_struct *work)
+{
+ struct ssv_softc *sc =
+ container_of(work, struct ssv_softc, bcast_start_work);
+#ifdef BCAST_DEBUG
+ printk("[B] ssv6200_bcast_start_work==\n");
+#endif
+ sc->bcast_interval = (sc->beacon_dtim_cnt + 1) *
+ (sc->beacon_interval + 20) * HZ / 1000;
+ if (!sc->aid0_bit_set) {
+ sc->aid0_bit_set = true;
+ ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set);
+ queue_delayed_work(sc->config_wq,
+ &sc->bcast_tx_work, sc->bcast_interval);
+#ifdef BCAST_DEBUG
+ printk("[B] bcast_start_work: Modify timer to DTIM[%d]ms==\n",
+ (sc->beacon_dtim_cnt + 1) * (sc->beacon_interval + 20));
+#endif
+ }
+}
+
+void ssv6200_bcast_stop_work(struct work_struct *work)
+{
+ struct ssv_softc *sc =
+ container_of(work, struct ssv_softc, bcast_stop_work.work);
+ long tmo = HZ / 100;
+#ifdef BCAST_DEBUG
+ printk("[B] ssv6200_bcast_stop_work\n");
+#endif
+ if (sc->aid0_bit_set) {
+ if (0 == ssv6200_bcast_queue_len(&sc->bcast_txq)) {
+ cancel_delayed_work_sync(&sc->bcast_tx_work);
+ sc->aid0_bit_set = false;
+ ssv6xxx_beacon_change(sc, sc->hw,
+ sc->ap_vif, sc->aid0_bit_set);
+#ifdef BCAST_DEBUG
+ printk("remove group bit in DTIM\n");
+#endif
+ } else {
+#ifdef BCAST_DEBUG
+ printk
+ ("bcast_stop_work: bcast queue still have data. just modify timer to 10ms\n");
+#endif
+ queue_delayed_work(sc->config_wq,
+ &sc->bcast_tx_work, tmo);
+ }
+ }
+}
+
+void ssv6200_bcast_stop(struct ssv_softc *sc)
+{
+ queue_delayed_work(sc->config_wq,
+ &sc->bcast_stop_work,
+ sc->beacon_interval * HZ / 1024);
+}
+
+void ssv6200_bcast_start(struct ssv_softc *sc)
+{
+ queue_work(sc->config_wq, &sc->bcast_start_work);
+}
+
+void ssv6200_release_bcast_frame_res(struct ssv_softc *sc,
+ struct ieee80211_vif *vif)
+{
+ unsigned long flags;
+ struct ssv_vif_priv_data *priv_vif =
+ (struct ssv_vif_priv_data *)vif->drv_priv;
+ spin_lock_irqsave(&sc->ps_state_lock, flags);
+ priv_vif->sta_asleep_mask = 0;
+ spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+ cancel_work_sync(&sc->bcast_start_work);
+ cancel_delayed_work_sync(&sc->bcast_stop_work);
+ ssv6200_bcast_flush(sc, &sc->bcast_txq);
+ cancel_delayed_work_sync(&sc->bcast_tx_work);
+}
diff --git a/drivers/net/wireless/ssv6051/smac/ap.h b/drivers/net/wireless/ssv6051/smac/ap.h
new file mode 100644
index 000000000000..93b5275715b5
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ap.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _AP_H_
+#define _AP_H_
+#define BEACON_WAITING_ENABLED 1<<0
+#define BEACON_ENABLED 1<<1
+void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif, bool aid0_bit_set);
+void ssv6xxx_beacon_set_info(struct ssv_softc *sc, u8 beacon_interval,
+ u8 dtim_cnt);
+bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable);
+void ssv6xxx_beacon_release(struct ssv_softc *sc);
+void ssv6200_set_tim_work(struct work_struct *work);
+void ssv6200_bcast_start_work(struct work_struct *work);
+void ssv6200_bcast_stop_work(struct work_struct *work);
+void ssv6200_bcast_tx_work(struct work_struct *work);
+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);
+struct sk_buff *ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq,
+ u8 * remain_len);
+int ssv6200_bcast_enqueue(struct ssv_softc *sc,
+ struct ssv6xxx_bcast_txq *bcast_txq,
+ struct sk_buff *skb);
+void ssv6200_bcast_start(struct ssv_softc *sc);
+void ssv6200_bcast_stop(struct ssv_softc *sc);
+void ssv6200_release_bcast_frame_res(struct ssv_softc *sc,
+ struct ieee80211_vif *vif);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/dev.c b/drivers/net/wireless/ssv6051/smac/dev.c
new file mode 100644
index 000000000000..214e93fae460
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/dev.c
@@ -0,0 +1,3881 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <linux/kthread.h>
+#include <linux/ktime.h>
+
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include <hci/hctrl.h>
+#include "linux_80211.h"
+#include "lib.h"
+#include "ssv_rc.h"
+#include "ssv_ht_rc.h"
+#include "dev.h"
+#include "ap.h"
+#include "init.h"
+#include "p2p.h"
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+#include "ssv6xxx_debugfs.h"
+#endif
+struct rssi_res_st rssi_res, *p_rssi_res;
+#define NO_USE_RXQ_LOCK
+#ifndef WLAN_CIPHER_SUITE_SMS4
+#define WLAN_CIPHER_SUITE_SMS4 0x00147201
+#endif
+#define MAX_TX_Q_LEN (64)
+#define LOW_TX_Q_LEN (MAX_TX_Q_LEN/2)
+static u16 bits_per_symbol[][2] = {
+ {26, 54},
+ {52, 108},
+ {78, 162},
+ {104, 216},
+ {156, 324},
+ {208, 432},
+ {234, 486},
+ {260, 540},
+};
+
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
+extern unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage);
+#endif
+struct ssv6xxx_calib_table {
+ u16 channel_id;
+ u32 rf_ctrl_N;
+ u32 rf_ctrl_F;
+ u16 rf_precision_default;
+};
+static void _process_rx_q(struct ssv_softc *sc, struct sk_buff_head *rx_q,
+ spinlock_t * rx_q_lock);
+static u32 _process_tx_done(struct ssv_softc *sc);
+
+void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args)
+{
+ struct ssv_softc *sc = (struct ssv_softc *)args;
+ if (!skb)
+ return;
+ ieee80211_free_txskb(sc->hw, skb);
+}
+
+#define ADDRESS_OFFSET 16
+#define HW_ID_OFFSET 7
+#define CH0_FULL_MASK CH0_FULL_MSK
+#define MAX_FAIL_COUNT 100
+#define MAX_RETRY_COUNT 20
+inline bool ssv6xxx_mcu_input_full(struct ssv_softc *sc)
+{
+ u32 regval = 0;
+ SMAC_REG_READ(sc->sh, ADR_MCU_STATUS, &regval);
+ return CH0_FULL_MASK & regval;
+}
+
+u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type)
+{
+ u32 regval, pad;
+ int cnt = MAX_RETRY_COUNT;
+ int page_cnt =
+ (size + ((1 << HW_MMU_PAGE_SHIFT) - 1)) >> HW_MMU_PAGE_SHIFT;
+ regval = 0;
+ mutex_lock(&sc->mem_mutex);
+ pad = size % 4;
+ size += pad;
+ do {
+ SMAC_REG_WRITE(sc->sh, ADR_WR_ALC, (size | (type << 16)));
+ SMAC_REG_READ(sc->sh, ADR_WR_ALC, &regval);
+ if (regval == 0) {
+ cnt--;
+ msleep(1);
+ } else
+ break;
+ } while (cnt);
+ if (type == TX_BUF) {
+ sc->sh->tx_page_available -= page_cnt;
+ sc->sh->page_count[PACKET_ADDR_2_ID(regval)] = page_cnt;
+ }
+ mutex_unlock(&sc->mem_mutex);
+ if (regval == 0)
+ dev_err(sc->dev,
+ "Failed to allocate packet buffer of %d bytes in %d type.",
+ size, type);
+ else {
+ dev_dbg(sc->dev,
+ "Allocated %d type packet buffer of size %d (%d) at address %x.\n",
+ type, size, page_cnt, regval);
+ }
+ return regval;
+}
+
+bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr)
+{
+ u32 regval = 0;
+ u16 failCount = 0;
+ u8 *p_tx_page_cnt = &sc->sh->page_count[PACKET_ADDR_2_ID(pbuf_addr)];
+ while (ssv6xxx_mcu_input_full(sc)) {
+ if (failCount++ < 1000)
+ continue;
+ dev_err(sc->dev, "Error in mailbox block after %d iterations\n", failCount);
+ return false;
+ }
+ mutex_lock(&sc->mem_mutex);
+ regval =
+ ((M_ENG_TRASH_CAN << HW_ID_OFFSET) | (pbuf_addr >> ADDRESS_OFFSET));
+ SMAC_REG_WRITE(sc->sh, ADR_CH0_TRIG_1, regval);
+ if (*p_tx_page_cnt) {
+ sc->sh->tx_page_available += *p_tx_page_cnt;
+ *p_tx_page_cnt = 0;
+ }
+ mutex_unlock(&sc->mem_mutex);
+ return true;
+}
+
+static const struct ssv6xxx_calib_table vt_tbl[SSV6XXX_IQK_CFG_XTAL_MAX][14] = {
+ {
+ {1, 0xB9, 0x89D89E, 3859},
+ {2, 0xB9, 0xEC4EC5, 3867},
+ {3, 0xBA, 0x4EC4EC, 3875},
+ {4, 0xBA, 0xB13B14, 3883},
+ {5, 0xBB, 0x13B13B, 3891},
+ {6, 0xBB, 0x762762, 3899},
+ {7, 0xBB, 0xD89D8A, 3907},
+ {8, 0xBC, 0x3B13B1, 3915},
+ {9, 0xBC, 0x9D89D9, 3923},
+ {10, 0xBD, 0x000000, 3931},
+ {11, 0xBD, 0x627627, 3939},
+ {12, 0xBD, 0xC4EC4F, 3947},
+ {13, 0xBE, 0x276276, 3955},
+ {14, 0xBF, 0x13B13B, 3974},
+ },
+ {
+ {1, 0xf1, 0x333333, 3859},
+ {2, 0xf1, 0xB33333, 3867},
+ {3, 0xf2, 0x333333, 3875},
+ {4, 0xf2, 0xB33333, 3883},
+ {5, 0xf3, 0x333333, 3891},
+ {6, 0xf3, 0xB33333, 3899},
+ {7, 0xf4, 0x333333, 3907},
+ {8, 0xf4, 0xB33333, 3915},
+ {9, 0xf5, 0x333333, 3923},
+ {10, 0xf5, 0xB33333, 3931},
+ {11, 0xf6, 0x333333, 3939},
+ {12, 0xf6, 0xB33333, 3947},
+ {13, 0xf7, 0x333333, 3955},
+ {14, 0xf8, 0x666666, 3974},
+ },
+ {
+ {1, 0xC9, 0x000000, 3859},
+ {2, 0xC9, 0x6AAAAB, 3867},
+ {3, 0xC9, 0xD55555, 3875},
+ {4, 0xCA, 0x400000, 3883},
+ {5, 0xCA, 0xAAAAAB, 3891},
+ {6, 0xCB, 0x155555, 3899},
+ {7, 0xCB, 0x800000, 3907},
+ {8, 0xCB, 0xEAAAAB, 3915},
+ {9, 0xCC, 0x555555, 3923},
+ {10, 0xCC, 0xC00000, 3931},
+ {11, 0xCD, 0x2AAAAB, 3939},
+ {12, 0xCD, 0x955555, 3947},
+ {13, 0xCE, 0x000000, 3955},
+ {14, 0xCF, 0x000000, 3974},
+ }
+};
+
+#define FAIL_MAX 100
+#define RETRY_MAX 20
+int ssv6xxx_set_channel(struct ssv_softc *sc, int ch)
+{
+ struct ssv_hw *sh = sc->sh;
+ int retry_cnt, fail_cnt = 0;
+ u32 regval;
+ int ret = -1;
+ int chidx;
+ bool chidx_vld = 0;
+ dev_dbg(sc->dev, "Setting channel to %d\n", ch);
+ if ((sh->cfg.chip_identity == SSV6051Z)
+ || (sc->sh->cfg.chip_identity == SSV6051P)) {
+ if ((ch == 13) || (ch == 14)) {
+ if (sh->ipd_channel_touch == 0) {
+ for (chidx = 0; chidx < sh->ch_cfg_size;
+ chidx++) {
+ SMAC_REG_WRITE(sh,
+ sh->p_ch_cfg[chidx].
+ reg_addr,
+ sh->p_ch_cfg[chidx].
+ ch13_14_value);
+ }
+ sh->ipd_channel_touch = 1;
+ }
+ } else {
+ if (sh->ipd_channel_touch) {
+ for (chidx = 0; chidx < sh->ch_cfg_size;
+ chidx++) {
+ SMAC_REG_WRITE(sh,
+ sh->p_ch_cfg[chidx].
+ reg_addr,
+ sh->p_ch_cfg[chidx].
+ ch1_12_value);
+ }
+ sh->ipd_channel_touch = 0;
+ }
+ }
+ }
+ for (chidx = 0; chidx < 14; chidx++) {
+ if (vt_tbl[sh->cfg.crystal_type][chidx].channel_id == ch) {
+ chidx_vld = 1;
+ break;
+ }
+ }
+ if (chidx_vld == 0) {
+ dev_dbg(sc->dev, "%s(): fail! channel_id not found in vt_tbl\n",
+ __FUNCTION__);
+ goto exit;
+ }
+ if ((ret = ssv6xxx_rf_disable(sc->sh)) != 0)
+ goto exit;
+ do {
+ if ((sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M)
+ || (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M)) {
+ if ((ret =
+ SMAC_REG_SET_BITS(sc->sh, ADR_SYN_DIV_SDM_XOSC,
+ (0x00 << 13),
+ (0x01 << 13))) != 0)
+ break;
+ } else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) {
+ if ((ret =
+ SMAC_REG_SET_BITS(sc->sh, ADR_SYN_DIV_SDM_XOSC,
+ (0x01 << 13),
+ (0x01 << 13))) != 0)
+ break;
+ } else {
+ dev_warn(sc->dev, "Illegal crystal setting in ssv6xxx_set_channel\n");
+ BUG_ON(1);
+ }
+ if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I,
+ (0x01 << 19), (0x01 << 19))) != 0)
+ break;
+ regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_F;
+ if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_1,
+ (regval << 0),
+ (0x00ffffff << 0))) != 0)
+ break;
+ regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_N;
+ if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_2,
+ (regval << 0),
+ (0x07ff << 0))) != 0)
+ break;
+ if ((ret =
+ SMAC_REG_READ(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I,
+ &regval)) != 0)
+ break;
+ regval =
+ vt_tbl[sh->cfg.crystal_type][chidx].rf_precision_default;
+ if ((ret =
+ SMAC_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_II,
+ (regval << 0), (0x1fff << 0))) != 0)
+ break;
+ if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER,
+ (0x00 << 14), (0x01 << 14))) != 0)
+ break;
+ if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER,
+ (0x01 << 14), (0x01 << 14))) != 0)
+ break;
+ retry_cnt = 0;
+ do {
+ mdelay(1);
+ if ((ret =
+ SMAC_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1,
+ &regval)) != 0)
+ break;
+ if (regval & 0x00000002) {
+ if ((ret =
+ SMAC_REG_READ(sc->sh,
+ ADR_READ_ONLY_FLAGS_2,
+ &regval)) != 0)
+ break;
+ ret = ssv6xxx_rf_enable(sc->sh);
+ //dev_info(sc->dev, "Lock to channel %d ([0xce010098]=%x)!!\n", vt_tbl[sh->cfg.crystal_type][chidx].channel_id, regval);
+ sc->hw_chan = ch;
+ goto exit;
+ }
+ retry_cnt++;
+ }
+ while (retry_cnt < RETRY_MAX);
+ fail_cnt++;
+ dev_warn(sc->dev, "calibation fail after %d iterations\n", fail_cnt);
+ }
+ while ((fail_cnt < FAIL_MAX) && (ret == 0));
+ exit:
+ if (ch == 14 && regval == 0xff0) {
+ SMAC_IFC_RESET(sc->sh);
+ ssv6xxx_restart_hw(sc);
+ }
+ if (ch <= 7) {
+ if (sh->cfg.tx_power_index_1) {
+ SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+ regval &= RG_TX_GAIN_OFFSET_I_MSK;
+ regval |=
+ (sh->cfg.tx_power_index_1 << RG_TX_GAIN_OFFSET_SFT);
+ SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+ } else if (sh->cfg.tx_power_index_2) {
+ SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+ regval &= RG_TX_GAIN_OFFSET_I_MSK;
+ SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+ }
+ } else {
+ if (sh->cfg.tx_power_index_2) {
+ SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+ regval &= RG_TX_GAIN_OFFSET_I_MSK;
+ regval |=
+ (sh->cfg.tx_power_index_2 << RG_TX_GAIN_OFFSET_SFT);
+ SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+ } else if (sh->cfg.tx_power_index_1) {
+ SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+ regval &= RG_TX_GAIN_OFFSET_I_MSK;
+ SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+ }
+ }
+ return ret;
+}
+
+#ifdef CONFIG_SSV_SMARTLINK
+int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch)
+{
+ *pch = sc->hw_chan;
+ return 0;
+}
+
+int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept)
+{
+ u32 val = 0;
+ if (accept) {
+ val = 0x2;
+ } else {
+ val = 0x3;
+ }
+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB13, val);
+ return 0;
+}
+
+int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept)
+{
+ u32 val = 0;
+ SMAC_REG_READ(sc->sh, ADR_MRX_FLT_TB13, &val);
+ if (val == 0x2) {
+ *paccept = 1;
+ } else {
+ *paccept = 0;
+ }
+ return 0;
+}
+#endif
+int ssv6xxx_rf_enable(struct ssv_hw *sh)
+{
+ return SMAC_REG_SET_BITS(sh, 0xce010000, (0x02 << 12), (0x03 << 12)
+ );
+}
+
+int ssv6xxx_rf_disable(struct ssv_hw *sh)
+{
+ return SMAC_REG_SET_BITS(sh, 0xce010000, (0x01 << 12), (0x03 << 12)
+ );
+}
+
+int ssv6xxx_update_decision_table(struct ssv_softc *sc)
+{
+ int i;
+ for (i = 0; i < MAC_DECITBL1_SIZE; i++) {
+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + i * 4,
+ sc->mac_deci_tbl[i]);
+ SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_TB0 + i * 4,
+ sc->mac_deci_tbl[i]);
+ }
+ for (i = 0; i < MAC_DECITBL2_SIZE; i++) {
+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN0 + i * 4,
+ sc->mac_deci_tbl[i + MAC_DECITBL1_SIZE]);
+ SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_EN0 + i * 4,
+ sc->mac_deci_tbl[i + MAC_DECITBL1_SIZE]);
+ }
+ return 0;
+}
+
+static int ssv6xxx_frame_hdrlen(struct ieee80211_hdr *hdr, bool is_ht)
+{
+#define CTRL_FRAME_INDEX(fc) ((hdr->frame_control-IEEE80211_STYPE_BACK_REQ)>>4)
+ u16 fc, CTRL_FLEN[] = { 16, 16, 16, 16, 10, 10, 16, 16 };
+ int hdr_len = 24;
+ fc = hdr->frame_control;
+ if (ieee80211_is_ctl(fc))
+ hdr_len = CTRL_FLEN[CTRL_FRAME_INDEX(fc)];
+ else if (ieee80211_is_mgmt(fc)) {
+ if (ieee80211_has_order(fc))
+ hdr_len += ((is_ht == 1) ? 4 : 0);
+ } else {
+ if (ieee80211_has_a4(fc))
+ hdr_len += 6;
+ if (ieee80211_is_data_qos(fc)) {
+ hdr_len += 2;
+ if (ieee80211_has_order(hdr->frame_control) &&
+ is_ht == true)
+ hdr_len += 4;
+ }
+ }
+ return hdr_len;
+}
+
+static u32 ssv6xxx_ht_txtime(u8 rix, int pktlen, int width,
+ int half_gi, bool is_gf)
+{
+ u32 nbits, nsymbits, duration, nsymbols;
+ int streams;
+ streams = 1;
+ nbits = (pktlen << 3) + OFDM_PLCP_BITS;
+ nsymbits = bits_per_symbol[rix % 8][width] * streams;
+ nsymbols = (nbits + nsymbits - 1) / nsymbits;
+ if (!half_gi)
+ duration = SYMBOL_TIME(nsymbols);
+ else {
+ if (!is_gf)
+ duration =
+ DIV_ROUND_UP(SYMBOL_TIME_HALFGI(nsymbols), 4) << 2;
+ else
+ duration = SYMBOL_TIME_HALFGI(nsymbols);
+ }
+ duration +=
+ L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams) +
+ HT_SIGNAL_EXT;
+ if (is_gf)
+ duration -= 12;
+ duration += HT_SIFS_TIME;
+ return duration;
+}
+
+static u32 ssv6xxx_non_ht_txtime(u8 phy, int kbps,
+ u32 frameLen, bool shortPreamble)
+{
+ u32 bits_per_symbol, num_bits, num_symbols;
+ u32 phy_time, tx_time;
+ if (kbps == 0)
+ return 0;
+ switch (phy) {
+ case WLAN_RC_PHY_CCK:
+ phy_time = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
+ if (shortPreamble)
+ phy_time >>= 1;
+ num_bits = frameLen << 3;
+ tx_time = CCK_SIFS_TIME + phy_time + ((num_bits * 1000) / kbps);
+ break;
+ case WLAN_RC_PHY_OFDM:
+ bits_per_symbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
+ num_bits = OFDM_PLCP_BITS + (frameLen << 3);
+ num_symbols = DIV_ROUND_UP(num_bits, bits_per_symbol);
+ tx_time = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
+ + (num_symbols * OFDM_SYMBOL_TIME);
+ break;
+ default:
+ pr_err("ssv6051: unknown phy %u\n", phy);
+ BUG_ON(1);
+ tx_time = 0;
+ break;
+ }
+ return tx_time;
+}
+
+static u32 ssv6xxx_set_frame_duration(struct ieee80211_tx_info *info,
+ struct ssv_rate_info *ssv_rate, u16 len,
+ struct ssv6200_tx_desc *tx_desc,
+ struct fw_rc_retry_params *rc_params,
+ struct ssv_softc *sc)
+{
+ struct ieee80211_tx_rate *tx_drate;
+ u32 frame_time = 0, ack_time = 0, rts_cts_nav = 0, frame_consume_time =
+ 0;
+ u32 l_length = 0, drate_kbps = 0, crate_kbps = 0;
+ bool ctrl_short_preamble = false, is_sgi, is_ht40;
+ bool is_ht, is_gf;
+ int d_phy, c_phy, nRCParams, mcsidx;
+ struct ssv_rate_ctrl *ssv_rc = NULL;
+ tx_drate = &info->control.rates[0];
+ is_sgi = !!(tx_drate->flags & IEEE80211_TX_RC_SHORT_GI);
+ is_ht40 = !!(tx_drate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
+ is_ht = !!(tx_drate->flags & IEEE80211_TX_RC_MCS);
+ is_gf = !!(tx_drate->flags & IEEE80211_TX_RC_GREEN_FIELD);
+ if ((info->control.short_preamble) ||
+ (tx_drate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
+ ctrl_short_preamble = true;
+ pr_debug("mcs = %d, data rate idx=%d\n", tx_drate->idx, tx_drate[3].count);
+ for (nRCParams = 0; (nRCParams < SSV62XX_TX_MAX_RATES); nRCParams++) {
+ if ((rc_params == NULL) || (sc == NULL)) {
+ mcsidx = tx_drate->idx;
+ drate_kbps = ssv_rate->drate_kbps;
+ crate_kbps = ssv_rate->crate_kbps;
+ } else {
+ if (rc_params[nRCParams].count == 0) {
+ break;
+ }
+ ssv_rc = sc->rc;
+ mcsidx =
+ (rc_params[nRCParams].drate -
+ SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES;
+ drate_kbps =
+ ssv_rc->rc_table[rc_params[nRCParams].drate].
+ rate_kbps;
+ crate_kbps =
+ ssv_rc->rc_table[rc_params[nRCParams].crate].
+ rate_kbps;
+ }
+ if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
+ frame_time = ssv6xxx_ht_txtime(mcsidx,
+ len, is_ht40, is_sgi,
+ is_gf);
+ d_phy = 0;
+ } else {
+ if ((info->band == INDEX_80211_BAND_2GHZ) &&
+ !(ssv_rate->d_flags & IEEE80211_RATE_ERP_G))
+ d_phy = WLAN_RC_PHY_CCK;
+ else
+ d_phy = WLAN_RC_PHY_OFDM;
+ frame_time = ssv6xxx_non_ht_txtime(d_phy, drate_kbps,
+ len,
+ ctrl_short_preamble);
+ }
+ if ((info->band == INDEX_80211_BAND_2GHZ) &&
+ !(ssv_rate->c_flags & IEEE80211_RATE_ERP_G))
+ c_phy = WLAN_RC_PHY_CCK;
+ else
+ c_phy = WLAN_RC_PHY_OFDM;
+ if (tx_desc->unicast) {
+ if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+ ack_time = ssv6xxx_non_ht_txtime(c_phy,
+ crate_kbps,
+ BA_LEN,
+ ctrl_short_preamble);
+ } else {
+ ack_time = ssv6xxx_non_ht_txtime(c_phy,
+ crate_kbps,
+ ACK_LEN,
+ ctrl_short_preamble);
+ }
+ }
+ if (tx_desc->do_rts_cts & IEEE80211_TX_RC_USE_RTS_CTS) {
+ rts_cts_nav = frame_time;
+ rts_cts_nav += ack_time;
+ rts_cts_nav += ssv6xxx_non_ht_txtime(c_phy,
+ crate_kbps,
+ CTS_LEN,
+ ctrl_short_preamble);
+ frame_consume_time = rts_cts_nav;
+ frame_consume_time += ssv6xxx_non_ht_txtime(c_phy,
+ crate_kbps,
+ RTS_LEN,
+ ctrl_short_preamble);
+ } else if (tx_desc->
+ do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
+ rts_cts_nav = frame_time;
+ rts_cts_nav += ack_time;
+ frame_consume_time = rts_cts_nav;
+ frame_consume_time += ssv6xxx_non_ht_txtime(c_phy,
+ crate_kbps,
+ CTS_LEN,
+ ctrl_short_preamble);
+ } else {;
+ }
+ if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
+ l_length = frame_time - HT_SIFS_TIME;
+ l_length = ((l_length - (HT_SIGNAL_EXT + 20)) + 3) >> 2;
+ l_length += ((l_length << 1) - 3);
+ }
+ if ((rc_params == NULL) || (sc == NULL)) {
+ tx_desc->rts_cts_nav = rts_cts_nav;
+ tx_desc->frame_consume_time =
+ (frame_consume_time >> 5) + 1;;
+ tx_desc->dl_length = l_length;
+ break;
+ } else {
+ rc_params[nRCParams].rts_cts_nav = rts_cts_nav;
+ rc_params[nRCParams].frame_consume_time =
+ (frame_consume_time >> 5) + 1;
+ rc_params[nRCParams].dl_length = l_length;
+ if (nRCParams == 0) {
+ tx_desc->drate_idx = rc_params[nRCParams].drate;
+ tx_desc->crate_idx = rc_params[nRCParams].crate;
+ tx_desc->rts_cts_nav =
+ rc_params[nRCParams].rts_cts_nav;
+ tx_desc->frame_consume_time =
+ rc_params[nRCParams].frame_consume_time;
+ tx_desc->dl_length =
+ rc_params[nRCParams].dl_length;
+ }
+ }
+ }
+ return ack_time;
+}
+
+static void ssv6200_hw_set_pair_type(struct ssv_hw *sh, u8 type)
+{
+ u32 temp;
+ SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
+ temp = (temp & PAIR_SCRT_I_MSK);
+ temp |= (type << PAIR_SCRT_SFT);
+ SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
+ dev_dbg(sh->sc->dev, "==>%s: write cipher type %d into hw\n", __func__, type);
+}
+
+static u32 ssv6200_hw_get_pair_type(struct ssv_hw *sh)
+{
+ u32 temp;
+ SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
+ temp &= PAIR_SCRT_MSK;
+ temp = (temp >> PAIR_SCRT_SFT);
+ SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
+ dev_dbg(sh->sc->dev, "==>%s: read cipher type %d from hw\n", __func__, temp);
+ return temp;
+}
+
+static void ssv6200_hw_set_group_type(struct ssv_hw *sh, u8 type)
+{
+ u32 temp;
+ SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
+ temp = temp & GRP_SCRT_I_MSK;
+ temp |= (type << GRP_SCRT_SFT);
+ SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
+ dev_dbg(sh->sc->dev, "Set group key type %d\n", type);
+}
+
+void ssv6xxx_reset_sec_module(struct ssv_softc *sc)
+{
+ ssv6200_hw_set_group_type(sc->sh, ME_NONE);
+ ssv6200_hw_set_pair_type(sc->sh, ME_NONE);
+}
+
+static int hw_update_watch_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,
+ struct ssv_sta_info *sta_info, int sta_idx,
+ int rx_hw_sec, int ops)
+{
+ int ret = 0;
+ int retry_cnt = 20;
+ struct sk_buff *skb = NULL;
+ struct cfg_host_cmd *host_cmd;
+ struct ssv6xxx_wsid_params *ptr;
+ dev_dbg(sc->dev, "cmd=%d for fw wsid list, wsid %d \n", ops, sta_idx);
+ skb =
+ ssv_skb_alloc(HOST_CMD_HDR_LEN +
+ sizeof(struct ssv6xxx_wsid_params));
+ if (skb == NULL || sta_info == NULL || sc == NULL)
+ return -1;
+ skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_wsid_params);
+ skb->len = skb->data_len;
+ host_cmd = (struct cfg_host_cmd *)skb->data;
+ host_cmd->c_type = HOST_CMD;
+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_WSID_OP;
+ host_cmd->len = skb->data_len;
+ ptr = (struct ssv6xxx_wsid_params *)host_cmd->dat8;
+ ptr->cmd = ops;
+ ptr->hw_security = rx_hw_sec;
+ if ((ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE)
+ && (ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE)) {
+ ptr->wsid_idx = (u8) (sta_idx - SSV_NUM_HW_STA);
+ } else {
+ ptr->wsid_idx = (u8) (sta_idx);
+ };
+ memcpy(&ptr->target_wsid, &sta->addr[0], 6);
+ while (((sc->sh->hci.hci_ops->hci_send_cmd(skb)) != 0) && (retry_cnt)) {
+ dev_dbg(sc->dev, "WSID cmd=%d retry=%d!!\n", ops, retry_cnt);
+ retry_cnt--;
+ }
+ dev_dbg(sc->dev, "%s: wsid_idx = %u\n", __FUNCTION__, ptr->wsid_idx);
+ ssv_skb_free(skb);
+ if (ops == SSV6XXX_WSID_OPS_ADD)
+ sta_info->hw_wsid = sta_idx;
+ return ret;
+}
+
+static void hw_crypto_key_clear(struct ieee80211_hw *hw, int index,
+ struct ieee80211_key_conf *key,
+ struct ssv_vif_priv_data *vif_priv,
+ struct ssv_sta_priv_data *sta_priv)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ssv_sta_info *sta_info = NULL;
+ if ((index == 0) && (sta_priv == NULL))
+ return;
+ if ((index < 0) || (index >= 4))
+ return;
+ if (index > 0) {
+ if (vif_priv)
+ vif_priv->group_key_idx = 0;
+ if (sta_priv)
+ sta_priv->group_key_idx = 0;
+ }
+ if (sta_priv) {
+ sta_info = &sc->sta_info[sta_priv->sta_idx];
+ if ((index == 0) && (sta_priv->has_hw_decrypt == true)
+ && (sta_info->hw_wsid >= SSV_NUM_HW_STA)) {
+ hw_update_watch_wsid(sc, sta_info->sta, sta_info,
+ sta_priv->sta_idx,
+ SSV6XXX_WSID_SEC_PAIRWISE,
+ SSV6XXX_WSID_OPS_DISABLE_CAPS);
+ }
+ }
+ if (vif_priv) {
+ if ((index != 0) && !list_empty(&vif_priv->sta_list)) {
+ struct ssv_sta_priv_data *sta_priv_iter;
+ list_for_each_entry(sta_priv_iter, &vif_priv->sta_list,
+ list) {
+ if (((sta_priv_iter->sta_info->
+ s_flags & STA_FLAG_VALID) == 0)
+ || (sta_priv_iter->sta_info->hw_wsid <
+ SSV_NUM_HW_STA))
+ continue;
+ hw_update_watch_wsid(sc,
+ sta_priv_iter->sta_info->
+ sta,
+ sta_priv_iter->sta_info,
+ sta_priv_iter->sta_idx,
+ SSV6XXX_WSID_SEC_GROUP,
+ SSV6XXX_WSID_OPS_DISABLE_CAPS);
+ }
+ }
+ }
+}
+
+static void _set_wep_sw_crypto_key(struct ssv_softc *sc,
+ struct ssv_vif_info *vif_info,
+ struct ssv_sta_info *sta_info, void *param)
+{
+ struct ssv_sta_priv_data *sta_priv =
+ (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+ struct ssv_vif_priv_data *vif_priv =
+ (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+ sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
+ sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
+ sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
+ sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
+}
+
+static void _set_wep_hw_crypto_pair_key(struct ssv_softc *sc,
+ struct ssv_vif_info *vif_info,
+ struct ssv_sta_info *sta_info,
+ void *param)
+{
+ int wsid = sta_info->hw_wsid;
+ struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param;
+ int address = 0;
+ int *pointer = NULL;
+ u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+ u32 sec_key_tbl = sec_key_tbl_base;
+ int i;
+ u8 *key = sram_key->sta_key[0].pair.key;
+ u32 key_len = *(u16 *) & sram_key->sta_key[0].reserve[0];
+ struct ssv_sta_priv_data *sta_priv =
+ (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+ struct ssv_vif_priv_data *vif_priv =
+ (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+ if (wsid == (-1))
+ return;
+ sram_key->sta_key[wsid].pair_key_idx = 0;
+ sram_key->sta_key[wsid].group_key_idx = 0;
+ sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
+ sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
+ sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
+ sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
+ if (wsid != 0)
+ memcpy(sram_key->sta_key[wsid].pair.key, key, key_len);
+ address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
+ + wsid * sizeof(struct ssv6xxx_hw_sta_key);
+ address += (0x10000 * wsid);
+ pointer = (int *)&sram_key->sta_key[wsid];
+ for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key) / 4); i++)
+ SMAC_REG_WRITE(sc->sh, address + (i * 4), *(pointer++));
+}
+
+static void _set_wep_hw_crypto_group_key(struct ssv_softc *sc,
+ struct ssv_vif_info *vif_info,
+ struct ssv_sta_info *sta_info,
+ void *param)
+{
+ int wsid = sta_info->hw_wsid;
+ struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param;
+ int address = 0;
+ int *pointer = NULL;
+ u32 key_idx = sram_key->sta_key[0].pair_key_idx;
+ u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+ u32 key_len = *(u16 *) & sram_key->sta_key[0].reserve[0];
+ u8 *key = sram_key->group_key[key_idx - 1].key;
+ u32 sec_key_tbl = sec_key_tbl_base;
+ struct ssv_sta_priv_data *sta_priv =
+ (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+ struct ssv_vif_priv_data *vif_priv =
+ (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+ if (wsid == (-1))
+ return;
+ if (wsid != 0) {
+ sram_key->sta_key[wsid].pair_key_idx = key_idx;
+ sram_key->sta_key[wsid].group_key_idx = key_idx;
+ sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
+ sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
+ sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
+ sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
+ }
+ if (wsid != 0)
+ memcpy(sram_key->group_key[key_idx - 1].key, key, key_len);
+ sec_key_tbl += (0x10000 * wsid);
+ address = sec_key_tbl + ((key_idx - 1) * sizeof(struct ssv6xxx_hw_key));
+ pointer = (int *)&sram_key->group_key[key_idx - 1];
+ {
+ int i;
+ for (i = 0; i < (sizeof(struct ssv6xxx_hw_key) / 4); i++)
+ SMAC_REG_WRITE(sc->sh, address + (i * 4), *(pointer++));
+ }
+ address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
+ + (wsid * sizeof(struct ssv6xxx_hw_sta_key));
+ pointer = (int *)&sram_key->sta_key[wsid];
+ SMAC_REG_WRITE(sc->sh, address, *(pointer));
+}
+
+static int hw_crypto_key_write_wep(struct ieee80211_hw *hw,
+ struct ieee80211_key_conf *key,
+ u8 algorithm, struct ssv_vif_info *vif_info)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey;
+ if (key->keyidx == 0) {
+ ssv6xxx_foreach_vif_sta(sc, vif_info,
+ _set_wep_hw_crypto_pair_key, sramKey);
+ } else {
+ ssv6xxx_foreach_vif_sta(sc, vif_info,
+ _set_wep_hw_crypto_group_key, sramKey);
+ }
+ return 0;
+}
+
+static void _set_aes_tkip_hw_crypto_group_key(struct ssv_softc *sc,
+ struct ssv_vif_info *vif_info,
+ struct ssv_sta_info *sta_info,
+ void *param)
+{
+ int wsid = sta_info->hw_wsid;
+ int j;
+ u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+ u32 sec_key_tbl = sec_key_tbl_base;
+ int address = 0;
+ int *pointer = 0;
+ struct ssv6xxx_hw_sec *sramKey = &(vif_info->sramKey);
+ int index = *(u8 *) param;
+ if (wsid == (-1))
+ return;
+ BUG_ON(index == 0);
+ sramKey->sta_key[wsid].group_key_idx = index;
+ sec_key_tbl += (0x10000 * wsid);
+ address = sec_key_tbl + ((index - 1) * sizeof(struct ssv6xxx_hw_key));
+ if (vif_info->vif_priv != NULL)
+ dev_dbg(sc->dev, "Write group key %d to VIF %d to %08X\n",
+ index, vif_info->vif_priv->vif_idx, address);
+ else
+ dev_err(sc->dev, "NULL VIF.\n");
+ pointer = (int *)&sramKey->group_key[index - 1];
+ for (j = 0; j < (sizeof(struct ssv6xxx_hw_key) / 4); j++)
+ SMAC_REG_WRITE(sc->sh, address + (j * 4), *(pointer++));
+ address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
+ + (wsid * sizeof(struct ssv6xxx_hw_sta_key));
+ pointer = (int *)&sramKey->sta_key[wsid];
+ SMAC_REG_WRITE(sc->sh, address, *(pointer));
+ if (wsid >= SSV_NUM_HW_STA) {
+ hw_update_watch_wsid(sc, sta_info->sta, sta_info,
+ wsid, SSV6XXX_WSID_SEC_GROUP,
+ SSV6XXX_WSID_OPS_ENABLE_CAPS);
+ }
+}
+
+static int _write_pairwise_key_to_hw(struct ssv_softc *sc,
+ int index, u8 algorithm,
+ const u8 * key, int key_len,
+ struct ieee80211_key_conf *keyconf,
+ struct ssv_vif_priv_data *vif_priv,
+ struct ssv_sta_priv_data *sta_priv)
+{
+ int i;
+ struct ssv6xxx_hw_sec *sramKey;
+ int address = 0;
+ int *pointer = NULL;
+ u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+ u32 sec_key_tbl;
+ int wsid = (-1);
+ if (sta_priv == NULL) {
+ dev_err(sc->dev, "Set pair-wise key with NULL STA.\n");
+ return -EOPNOTSUPP;
+ }
+ wsid = sta_priv->sta_info->hw_wsid;
+ if ((wsid < 0) || (wsid >= SSV_NUM_STA)) {
+ dev_err(sc->dev, "Set pair-wise key to invalid WSID %d.\n",
+ wsid);
+ return -EOPNOTSUPP;
+ }
+ dev_dbg(sc->dev, "Set STA %d's pair-wise key of %d bytes.\n", wsid,
+ key_len);
+ sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
+ sramKey->sta_key[wsid].pair_key_idx = 0;
+ sramKey->sta_key[wsid].group_key_idx = vif_priv->group_key_idx;
+ memcpy(sramKey->sta_key[wsid].pair.key, key, key_len);
+ sec_key_tbl = sec_key_tbl_base;
+ sec_key_tbl += (0x10000 * wsid);
+ address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
+ + wsid * sizeof(struct ssv6xxx_hw_sta_key);
+ pointer = (int *)&sramKey->sta_key[wsid];
+ for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key) / 4); i++)
+ SMAC_REG_WRITE(sc->sh, (address + (i * 4)), *(pointer++));
+ if (wsid >= SSV_NUM_HW_STA) {
+ hw_update_watch_wsid(sc, sta_priv->sta_info->sta,
+ sta_priv->sta_info, sta_priv->sta_idx,
+ SSV6XXX_WSID_SEC_PAIRWISE,
+ SSV6XXX_WSID_OPS_ENABLE_CAPS);
+ }
+ return 0;
+}
+
+static int _write_group_key_to_hw(struct ssv_softc *sc,
+ int index, u8 algorithm,
+ const u8 * key, int key_len,
+ struct ieee80211_key_conf *keyconf,
+ struct ssv_vif_priv_data *vif_priv,
+ struct ssv_sta_priv_data *sta_priv)
+{
+ struct ssv6xxx_hw_sec *sramKey;
+ int wsid = sta_priv ? sta_priv->sta_info->hw_wsid : (-1);
+ int ret = 0;
+ if (vif_priv == NULL) {
+ dev_err(sc->dev, "Setting group key to NULL VIF\n");
+ return -EOPNOTSUPP;
+ }
+ dev_dbg(sc->dev,
+ "Setting VIF %d group key %d of length %d to WSID %d.\n",
+ vif_priv->vif_idx, index, key_len, wsid);
+ sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
+ vif_priv->group_key_idx = index;
+ if (sta_priv)
+ sta_priv->group_key_idx = index;
+ memcpy(sramKey->group_key[index - 1].key, key, key_len);
+ WARN_ON(sc->vif_info[vif_priv->vif_idx].vif_priv == NULL);
+ ssv6xxx_foreach_vif_sta(sc, &sc->vif_info[vif_priv->vif_idx],
+ _set_aes_tkip_hw_crypto_group_key, &index);
+ ret = 0;
+ return ret;
+}
+
+static enum SSV_CIPHER_E _prepare_key(struct ieee80211_key_conf *key)
+{
+ enum SSV_CIPHER_E cipher;
+ switch (key->cipher) {
+ case WLAN_CIPHER_SUITE_WEP40:
+ cipher = SSV_CIPHER_WEP40;
+ break;
+ case WLAN_CIPHER_SUITE_WEP104:
+ cipher = SSV_CIPHER_WEP104;
+ break;
+ case WLAN_CIPHER_SUITE_TKIP:
+ key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
+ cipher = SSV_CIPHER_TKIP;
+ break;
+ case WLAN_CIPHER_SUITE_CCMP:
+ key->flags |=
+ (IEEE80211_KEY_FLAG_SW_MGMT_TX |
+ IEEE80211_KEY_FLAG_RX_MGMT);
+ cipher = SSV_CIPHER_CCMP;
+ break;
+ default:
+ cipher = SSV_CIPHER_INVALID;
+ break;
+ }
+ return cipher;
+}
+int _set_key_wep(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+ struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher,
+ struct ieee80211_key_conf *key)
+{
+ int ret = 0;
+ struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+ struct ssv6xxx_hw_sec *sram_key = &vif_info->sramKey;
+ sram_key->sta_key[0].pair_key_idx = key->keyidx;
+ sram_key->sta_key[0].group_key_idx = key->keyidx;
+ *(u16 *) & sram_key->sta_key[0].reserve[0] = key->keylen;
+ dev_dbg(sc->dev, "Set WEP %02X %02X %02X %02X %02X %02X %02X %02X... (%d %d)\n",
+ key->key[0], key->key[1], key->key[2], key->key[3], key->key[4],
+ key->key[5], key->key[6], key->key[7], key->keyidx, key->keylen);
+ if (key->keyidx == 0) {
+ memcpy(sram_key->sta_key[0].pair.key, key->key, key->keylen);
+ } else {
+ memcpy(sram_key->group_key[key->keyidx - 1].key, key->key,
+ key->keylen);
+ }
+ if (sc->sh->cfg.use_wpa2_only) {
+ dev_warn(sc->dev, "WEP: use WPA2 HW security mode only.\n");
+ }
+ if ((sc->sh->cfg.use_wpa2_only == 0)
+ && vif_priv->vif_idx == 0) {
+ vif_priv->has_hw_decrypt = true;
+ vif_priv->has_hw_encrypt = true;
+ vif_priv->need_sw_decrypt = false;
+ vif_priv->need_sw_encrypt = false;
+ vif_priv->use_mac80211_decrypt = false;
+ ssv6200_hw_set_pair_type(sc->sh, cipher);
+ ssv6200_hw_set_group_type(sc->sh, cipher);
+ hw_crypto_key_write_wep(sc->hw, key, cipher,
+ &sc->vif_info[vif_priv->vif_idx]);
+ } else {
+ vif_priv->has_hw_decrypt = false;
+ vif_priv->has_hw_encrypt = false;
+ vif_priv->need_sw_decrypt = false;
+ vif_priv->need_sw_encrypt = false;
+ vif_priv->use_mac80211_decrypt = true;
+ ssv6xxx_foreach_vif_sta(sc, vif_info, _set_wep_sw_crypto_key,
+ NULL);
+ ret = -EOPNOTSUPP;
+ }
+ vif_priv->pair_cipher = vif_priv->group_cipher = cipher;
+ vif_priv->is_security_valid = true;
+ return ret;
+}
+
+static int _set_pairwise_key_tkip_ccmp(struct ssv_softc *sc,
+ struct ssv_vif_priv_data *vif_priv,
+ struct ssv_sta_priv_data *sta_priv,
+ enum SSV_CIPHER_E cipher,
+ struct ieee80211_key_conf *key)
+{
+ int ret = 0;
+ const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP";
+ struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+ bool tdls_link = false, tdls_use_sw_cipher = false, tkip_use_sw_cipher =
+ false;
+ bool use_non_ccmp = false;
+ int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
+ struct ssv_vif_priv_data *another_vif_priv =
+ (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].vif_priv;
+ if (sta_priv == NULL) {
+ dev_err(sc->dev,
+ "Setting pairwise TKIP/CCMP key to NULL STA.\n");
+ return -EOPNOTSUPP;
+ }
+ if (sc->sh->cfg.use_wpa2_only) {
+ dev_warn(sc->dev, "Pairwise TKIP/CCMP: use WPA2 HW security mode only.\n");
+ }
+ if (vif_info->if_type == NL80211_IFTYPE_STATION) {
+ struct ssv_sta_priv_data *first_sta_priv =
+ list_first_entry(&vif_priv->sta_list,
+ struct ssv_sta_priv_data, list);
+ if (first_sta_priv->sta_idx != sta_priv->sta_idx) {
+ tdls_link = true;
+ }
+ dev_dbg(sc->dev, "first sta idx %d, current sta idx %d\n",
+ first_sta_priv->sta_idx, sta_priv->sta_idx);
+ }
+ if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)
+ && (sc->sh->cfg.use_wpa2_only == false)) {
+ tdls_use_sw_cipher = true;
+ }
+ if (another_vif_priv != NULL) {
+ if ((another_vif_priv->pair_cipher != SSV_CIPHER_CCMP)
+ && (another_vif_priv->pair_cipher != SSV_CIPHER_NONE)) {
+ use_non_ccmp = true;
+ dev_dbg(sc->dev, "another vif use none ccmp\n");
+ }
+ }
+ if ((((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP))
+ || (use_non_ccmp))
+ && (sc->sh->cfg.use_wpa2_only == 1) && (cipher == SSV_CIPHER_CCMP)) {
+ u32 val;
+ SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
+ if (((val >> 4) & 0xF) != M_ENG_CPU) {
+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+ ((val & 0xf) | (M_ENG_CPU << 4)
+ | (val & 0xfffffff0) << 4));
+ dev_dbg(sc->dev,
+ "orginal Rx_Flow %x , modified flow %x \n", val,
+ ((val & 0xf) | (M_ENG_CPU << 4) |
+ (val & 0xfffffff0) << 4));
+ }
+ }
+ if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) {
+ tkip_use_sw_cipher = true;
+ }
+ if (tkip_use_sw_cipher == true)
+ dev_info(sc->dev, "Using software TKIP cipher\n");
+ if ((((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false)
+ && (tkip_use_sw_cipher == false)))
+ || ((cipher == SSV_CIPHER_CCMP)
+ && (sc->sh->cfg.use_wpa2_only == 1))) {
+ sta_priv->has_hw_decrypt = true;
+ sta_priv->need_sw_decrypt = false;
+ if ((cipher == SSV_CIPHER_TKIP)
+ || ((!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX) ||
+ (sta_priv->sta_info->sta->deflink.ht_cap.ht_supported ==
+ false))
+ && (vif_priv->force_sw_encrypt == false))) {
+ dev_dbg(sc->dev,
+ "STA %d uses HW encrypter for pairwise.\n",
+ sta_priv->sta_idx);
+ sta_priv->has_hw_encrypt = true;
+ sta_priv->need_sw_encrypt = false;
+ sta_priv->use_mac80211_decrypt = false;
+ ret = 0;
+ } else {
+ sta_priv->has_hw_encrypt = false;
+ sta_priv->need_sw_encrypt = false;
+ sta_priv->use_mac80211_decrypt = true;
+ ret = -EOPNOTSUPP;
+ }
+ } else {
+ sta_priv->has_hw_encrypt = false;
+ sta_priv->has_hw_decrypt = false;
+ dev_err(sc->dev, "STA %d MAC80211's %s cipher.\n",
+ sta_priv->sta_idx, cipher_name);
+ sta_priv->need_sw_encrypt = false;
+ sta_priv->need_sw_decrypt = false;
+ sta_priv->use_mac80211_decrypt = true;
+ ret = -EOPNOTSUPP;
+ }
+ if (sta_priv->has_hw_encrypt || sta_priv->has_hw_decrypt) {
+ ssv6200_hw_set_pair_type(sc->sh, cipher);
+ _write_pairwise_key_to_hw(sc, key->keyidx, cipher,
+ key->key, key->keylen, key,
+ vif_priv, sta_priv);
+ }
+ if ((vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt)
+ && (vif_priv->group_key_idx > 0)) {
+ _set_aes_tkip_hw_crypto_group_key(sc,
+ &sc->vif_info[vif_priv->
+ vif_idx],
+ sta_priv->sta_info,
+ &vif_priv->group_key_idx);
+ }
+ return ret;
+}
+
+static int _set_group_key_tkip_ccmp(struct ssv_softc *sc,
+ struct ssv_vif_priv_data *vif_priv,
+ struct ssv_sta_priv_data *sta_priv,
+ enum SSV_CIPHER_E cipher,
+ struct ieee80211_key_conf *key)
+{
+ int ret = 0;
+ const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP";
+ bool tkip_use_sw_cipher = false;
+ vif_priv->group_cipher = cipher;
+ if (sc->sh->cfg.use_wpa2_only) {
+ dev_warn(sc->dev, "Group TKIP/CCMP: use WPA2 HW security mode only.\n");
+ }
+ if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) {
+ tkip_use_sw_cipher = true;
+ }
+ if (((vif_priv->vif_idx == 0) && (tkip_use_sw_cipher == false))
+ || ((cipher == SSV_CIPHER_CCMP)
+ && (sc->sh->cfg.use_wpa2_only == 1))) {
+ dev_dbg(sc->dev, "VIF %d uses HW %s cipher for group.\n",
+ vif_priv->vif_idx, cipher_name);
+#ifdef USE_MAC80211_DECRYPT_BROADCAST
+ vif_priv->has_hw_decrypt = false;
+ ret = -EOPNOTSUPP;
+#else
+ vif_priv->has_hw_decrypt = true;
+#endif
+ vif_priv->has_hw_encrypt = true;
+ vif_priv->need_sw_decrypt = false;
+ vif_priv->need_sw_encrypt = false;
+ vif_priv->use_mac80211_decrypt = false;
+ } else {
+ vif_priv->has_hw_decrypt = false;
+ vif_priv->has_hw_encrypt = false;
+ dev_err(sc->dev, "VIF %d uses MAC80211's %s cipher.\n",
+ vif_priv->vif_idx, cipher_name);
+ vif_priv->need_sw_encrypt = false;
+ vif_priv->need_sw_encrypt = false;
+ vif_priv->use_mac80211_decrypt = true;
+ ret = -EOPNOTSUPP;
+ }
+ if (vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt) {
+#ifdef USE_MAC80211_DECRYPT_BROADCAST
+ ssv6200_hw_set_group_type(sc->sh, ME_NONE);
+#else
+ ssv6200_hw_set_group_type(sc->sh, cipher);
+#endif
+ key->hw_key_idx = key->keyidx;
+ _write_group_key_to_hw(sc, key->keyidx, cipher,
+ key->key, key->keylen, key,
+ vif_priv, sta_priv);
+ }
+ vif_priv->is_security_valid = true;
+ {
+ int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
+ struct ssv_vif_priv_data *another_vif_priv =
+ (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].
+ vif_priv;
+ if (another_vif_priv != NULL) {
+ if (((SSV6XXX_USE_SW_DECRYPT(vif_priv)
+ && SSV6XXX_USE_HW_DECRYPT(another_vif_priv)))
+ || ((SSV6XXX_USE_HW_DECRYPT(vif_priv)
+ &&
+ (SSV6XXX_USE_SW_DECRYPT(another_vif_priv))))) {
+ u32 val;
+ SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
+ if (((val >> 4) & 0xF) != M_ENG_CPU) {
+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+ ((val & 0xf) |
+ (M_ENG_CPU << 4)
+ | (val & 0xfffffff0) <<
+ 4));
+ dev_dbg(sc->dev,
+ "orginal Rx_Flow %x , modified flow %x \n",
+ val,
+ ((val & 0xf) | (M_ENG_CPU << 4)
+ | (val & 0xfffffff0) << 4));
+ } else {
+ dev_dbg(sc->dev, " doesn't need to change rx flow\n");
+ }
+ }
+ }
+ }
+ return ret;
+}
+
+static int _set_key_tkip_ccmp(struct ssv_softc *sc,
+ struct ssv_vif_priv_data *vif_priv,
+ struct ssv_sta_priv_data *sta_priv,
+ enum SSV_CIPHER_E cipher,
+ struct ieee80211_key_conf *key)
+{
+ if (key->keyidx == 0)
+ return _set_pairwise_key_tkip_ccmp(sc, vif_priv, sta_priv,
+ cipher, key);
+ else
+ return _set_group_key_tkip_ccmp(sc, vif_priv, sta_priv, cipher,
+ key);
+}
+
+static int ssv6200_set_key(struct ieee80211_hw *hw,
+ enum set_key_cmd cmd,
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta,
+ struct ieee80211_key_conf *key)
+{
+ struct ssv_softc *sc = hw->priv;
+ int ret = 0;
+ enum SSV_CIPHER_E cipher = SSV_CIPHER_NONE;
+ int sta_idx = (-1);
+ struct ssv_sta_info *sta_info = NULL;
+ struct ssv_sta_priv_data *sta_priv = NULL;
+ struct ssv_vif_priv_data *vif_priv =
+ (struct ssv_vif_priv_data *)vif->drv_priv;
+ struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+ if (sta) {
+ sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ sta_idx = sta_priv->sta_idx;
+ sta_info = sta_priv->sta_info;
+ }
+ BUG_ON((cmd != SET_KEY) && (cmd != DISABLE_KEY));
+ if (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_SECURITY)) {
+ dev_warn(sc->dev, "HW does not support security.\n");
+ return -EOPNOTSUPP;
+ }
+ if (sta_info && (sta_info->hw_wsid == (-1))) {
+ dev_warn(sc->dev,
+ "Add STA without HW resource. Use MAC80211's solution.\n");
+ return -EOPNOTSUPP;
+ }
+ cipher = _prepare_key(key);
+ dev_dbg(sc->dev,
+ "Set key VIF %d VIF type %d STA %d algorithm = %d, key->keyidx = %d, cmd = %d\n",
+ vif_priv->vif_idx, vif->type, sta_idx, cipher, key->keyidx,
+ cmd);
+ if (cipher == SSV_CIPHER_INVALID) {
+ dev_warn(sc->dev, "Unsupported cipher type.\n");
+ return -EOPNOTSUPP;
+ }
+ mutex_lock(&sc->mutex);
+ switch (cmd) {
+ case SET_KEY:
+ {
+ switch (cipher) {
+ case SSV_CIPHER_WEP40:
+ case SSV_CIPHER_WEP104:
+ ret =
+ _set_key_wep(sc, vif_priv, sta_priv, cipher,
+ key);
+ break;
+ case SSV_CIPHER_TKIP:
+ case SSV_CIPHER_CCMP:
+ ret =
+ _set_key_tkip_ccmp(sc, vif_priv, sta_priv,
+ cipher, key);
+ break;
+ default:
+ break;
+ }
+ if (sta) {
+ struct ssv_sta_priv_data *first_sta_priv =
+ list_first_entry(&vif_priv->sta_list,
+ struct ssv_sta_priv_data,
+ list);
+ if (first_sta_priv->sta_idx ==
+ sta_priv->sta_idx) {
+ vif_priv->pair_cipher = cipher;
+ }
+ if (SSV6200_USE_HW_WSID(sta_idx)) {
+ if (SSV6XXX_USE_SW_DECRYPT(sta_priv)) {
+ u32 cipher_setting;
+ cipher_setting =
+ ssv6200_hw_get_pair_type
+ (sc->sh);
+ if (cipher_setting != ME_NONE) {
+ u32 val;
+ SMAC_REG_READ(sc->sh,
+ ADR_RX_FLOW_DATA,
+ &val);
+ if (((val >> 4) & 0xF)
+ != M_ENG_CPU) {
+ SMAC_REG_WRITE
+ (sc->sh,
+ ADR_RX_FLOW_DATA,
+ ((val &
+ 0xf) |
+ (M_ENG_CPU
+ << 4)
+ | (val &
+ 0xfffffff0)
+ << 4));
+ dev_dbg(sc->dev,
+ "orginal Rx_Flow %x , modified flow %x \n",
+ val,
+ ((val &
+ 0xf) |
+ (M_ENG_CPU
+ << 4)
+ | (val
+ &
+ 0xfffffff0)
+ << 4));
+ } else {
+ dev_dbg(sc->dev, " doesn't need to change rx flow\n");
+ }
+ }
+ }
+ if (sta_priv->has_hw_decrypt) {
+ hw_update_watch_wsid(sc, sta,
+ sta_info,
+ sta_idx,
+ SSV6XXX_WSID_SEC_HW,
+ SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE);
+ dev_info(sc->dev, "set hw wsid %d cipher mode to HW cipher for pairwise key\n", sta_idx);
+ }
+ }
+ } else {
+ if (vif_info->if_type == NL80211_IFTYPE_STATION) {
+ struct ssv_sta_priv_data *first_sta_priv
+ =
+ list_first_entry(&vif_priv->
+ sta_list,
+ struct
+ ssv_sta_priv_data,
+ list);
+ if (SSV6200_USE_HW_WSID
+ (first_sta_priv->sta_idx)) {
+ if (vif_priv->has_hw_decrypt) {
+ hw_update_watch_wsid(sc,
+ sta,
+ sta_info,
+ first_sta_priv->
+ sta_idx,
+ SSV6XXX_WSID_SEC_HW,
+ SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE);
+ dev_info(sc->dev, "set hw wsid %d cipher mode to HW cipher for group key\n", first_sta_priv->sta_idx);
+ }
+ }
+ }
+ }
+ }
+ break;
+ case DISABLE_KEY:
+ {
+ int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
+ struct ssv_vif_priv_data *another_vif_priv =
+ (struct ssv_vif_priv_data *)sc->
+ vif_info[another_vif_idx].vif_priv;
+ if (another_vif_priv != NULL) {
+ struct ssv_vif_info *vif_info =
+ &sc->vif_info[vif_priv->vif_idx];
+ if (vif_info->if_type != NL80211_IFTYPE_AP) {
+ if ((SSV6XXX_USE_SW_DECRYPT(vif_priv)
+ &&
+ SSV6XXX_USE_HW_DECRYPT
+ (another_vif_priv))
+ ||
+ (SSV6XXX_USE_SW_DECRYPT
+ (another_vif_priv)
+ &&
+ SSV6XXX_USE_HW_DECRYPT(vif_priv)))
+ {
+ SMAC_REG_WRITE(sc->sh,
+ ADR_RX_FLOW_DATA,
+ M_ENG_MACRX |
+ (M_ENG_ENCRYPT_SEC
+ << 4) |
+ (M_ENG_HWHCI <<
+ 8));
+ dev_dbg(sc->dev, "redirect Rx flow for disconnect\n");
+ }
+ } else {
+ if (sta == NULL) {
+ if (SSV6XXX_USE_SW_DECRYPT
+ (another_vif_priv)
+ &&
+ SSV6XXX_USE_HW_DECRYPT
+ (vif_priv)) {
+ SMAC_REG_WRITE(sc->sh,
+ ADR_RX_FLOW_DATA,
+ M_ENG_MACRX
+ |
+ (M_ENG_ENCRYPT_SEC
+ << 4) |
+ (M_ENG_HWHCI
+ << 8));
+ dev_dbg(sc->dev, "redirect Rx flow for disconnect\n");
+ }
+ }
+ }
+ }
+ if (sta == NULL) {
+ vif_priv->group_cipher = ME_NONE;
+ if ((another_vif_priv == NULL)
+ || ((another_vif_priv != NULL)
+ &&
+ (!SSV6XXX_USE_HW_DECRYPT
+ (another_vif_priv)))) {
+ ssv6200_hw_set_group_type(sc->sh,
+ ME_NONE);
+ }
+ } else {
+ struct ssv_vif_info *vif_info =
+ &sc->vif_info[vif_priv->vif_idx];
+ if ((vif_info->if_type != NL80211_IFTYPE_AP)
+ && (another_vif_priv == NULL)) {
+ struct ssv_sta_priv_data *first_sta_priv
+ =
+ list_first_entry(&vif_priv->
+ sta_list,
+ struct
+ ssv_sta_priv_data,
+ list);
+ if (sta_priv == first_sta_priv) {
+ ssv6200_hw_set_pair_type(sc->sh,
+ ME_NONE);
+ }
+ }
+ vif_priv->pair_cipher = ME_NONE;
+ }
+ if ((cipher == ME_TKIP) || (cipher == ME_CCMP)) {
+ dev_dbg(sc->dev, "Clear key %d VIF %d, STA %d\n",
+ key->keyidx, (vif != NULL),
+ (sta != NULL));
+ hw_crypto_key_clear(hw, key->keyidx, key,
+ vif_priv, sta_priv);
+ }
+ {
+ if ((key->keyidx == 0) && (sta_priv != NULL)) {
+ sta_priv->has_hw_decrypt = false;
+ sta_priv->has_hw_encrypt = false;
+ sta_priv->need_sw_encrypt = false;
+ sta_priv->use_mac80211_decrypt = false;
+ }
+ if ((vif_priv->is_security_valid)
+ && (key->keyidx != 0)) {
+ vif_priv->is_security_valid = false;
+ }
+ }
+ ret = 0;
+ }
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ mutex_unlock(&sc->mutex);
+ if (sta_priv != NULL) {
+ dev_info(sc->dev, "station mode: hardware encrypt:%d/decrypt:%d, software encrypt:%d/decrypt:%d\n",
+ (sta_priv->has_hw_encrypt == true),
+ (sta_priv->has_hw_decrypt == true),
+ (sta_priv->need_sw_encrypt == true),
+ (sta_priv->need_sw_decrypt == true));
+ }
+ if (vif_priv) {
+ dev_info
+ (sc->dev, "vif mode: hardware encrypt:%d/decrypt:%d, software encrypt:%d/decrypt:%d, mac80211 decrypt: %d, valid:%d\n",
+ (vif_priv->has_hw_encrypt == true),
+ (vif_priv->has_hw_decrypt == true),
+ (vif_priv->need_sw_encrypt == true),
+ (vif_priv->need_sw_decrypt == true),
+ (vif_priv->use_mac80211_decrypt == true),
+ (vif_priv->is_security_valid == true));
+ }
+ if (vif_priv->force_sw_encrypt
+ || (sta_info && (sta_info->hw_wsid != 1)
+ && (sta_info->hw_wsid != 0))) {
+ if (vif_priv->force_sw_encrypt == false)
+ vif_priv->force_sw_encrypt = true;
+ ret = -EOPNOTSUPP;
+ }
+ dev_dbg(sc->dev, "SET KEY %d\n", ret);
+ return ret;
+}
+
+u32 _process_tx_done(struct ssv_softc *sc)
+{
+ struct ieee80211_tx_info *tx_info;
+ struct sk_buff *skb;
+ while ((skb = skb_dequeue(&sc->tx_done_q))) {
+ struct ssv6200_tx_desc *tx_desc;
+ tx_info = IEEE80211_SKB_CB(skb);
+ tx_desc = (struct ssv6200_tx_desc *)skb->data;
+ if (tx_desc->c_type > M2_TXREQ) {
+ ssv_skb_free(skb);
+ dev_dbg(sc->dev, "free cmd skb!\n");
+ continue;
+ }
+ if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
+ ssv6200_ampdu_release_skb(skb, sc->hw);
+ continue;
+ }
+ skb_pull(skb, SSV6XXX_TX_DESC_LEN);
+ ieee80211_tx_info_clear_status(tx_info);
+ tx_info->flags |= IEEE80211_TX_STAT_ACK;
+ tx_info->status.ack_signal = 100;
+#ifdef REPORT_TX_DONE_IN_IRQ
+ ieee80211_tx_status_irqsafe(sc->hw, skb);
+#else
+ ieee80211_tx_status(sc->hw, skb);
+ if (skb_queue_len(&sc->rx_skb_q))
+ break;
+#endif
+ }
+ return skb_queue_len(&sc->tx_done_q);
+}
+
+#ifdef REPORT_TX_DONE_IN_IRQ
+void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args)
+{
+ struct ssv_softc *sc = (struct ssv_softc *)args;
+ _process_tx_done *(sc);
+}
+#else
+void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args)
+{
+ struct ssv_softc *sc = (struct ssv_softc *)args;
+ struct sk_buff *skb;
+ while ((skb = skb_dequeue(skb_head))) {
+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+ struct ssv6200_tx_desc *tx_desc;
+ tx_desc = (struct ssv6200_tx_desc *)skb->data;
+ if (tx_desc->c_type > M2_TXREQ) {
+ ssv_skb_free(skb);
+ dev_dbg(sc->dev, "free cmd skb!\n");
+ continue;
+ }
+ if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
+ ssv6xxx_ampdu_sent(sc->hw, skb);
+ skb_queue_tail(&sc->tx_done_q, skb);
+ }
+ wake_up_interruptible(&sc->rx_wait_q);
+}
+#endif
+void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args)
+{
+ struct ieee80211_hdr *hdr;
+ struct ssv_softc *sc = args;
+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+ struct ssv6200_tx_desc *tx_desc;
+ struct ssv_rate_info ssv_rate;
+ u32 nav = 0;
+ int ret = 0;
+ tx_desc = (struct ssv6200_tx_desc *)skb->data;
+ if (tx_desc->c_type > M2_TXREQ)
+ return;
+ if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) {
+ hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_TX_DESC_LEN);
+ if ((ieee80211_is_data_qos(hdr->frame_control)
+ || ieee80211_is_data(hdr->frame_control))
+ && (tx_desc->wsid < SSV_RC_MAX_HARDWARE_SUPPORT)) {
+ ret =
+ ssv6xxx_rc_hw_rate_update_check(skb, sc,
+ tx_desc->
+ do_rts_cts);
+ if (ret & RC_FIRMWARE_REPORT_FLAG) {
+ {
+ tx_desc->RSVD_0 = SSV6XXX_RC_REPORT;
+ tx_desc->tx_report = 1;
+ }
+ ret &= 0xf;
+ }
+ if (ret) {
+ ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
+ tx_desc->crate_idx = ssv_rate.crate_hw_idx;
+ tx_desc->drate_idx = ssv_rate.drate_hw_idx;
+ nav =
+ ssv6xxx_set_frame_duration(info, &ssv_rate,
+ skb->len +
+ FCS_LEN, tx_desc,
+ NULL, NULL);
+ if (tx_desc->tx_burst == 0) {
+ if (tx_desc->ack_policy != 0x01)
+ hdr->duration_id = nav;
+ }
+ }
+ }
+ } else {
+ }
+ return;
+}
+
+void ssv6xxx_update_txinfo(struct ssv_softc *sc, struct sk_buff *skb)
+{
+ struct ieee80211_hdr *hdr;
+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+ struct ieee80211_sta *sta;
+ struct ssv_sta_info *sta_info = NULL;
+ struct ssv_sta_priv_data *ssv_sta_priv = NULL;
+ struct ssv_vif_priv_data *vif_priv =
+ (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
+ struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data;
+ struct ieee80211_tx_rate *tx_drate;
+ struct ssv_rate_info ssv_rate;
+ int ac, hw_txqid;
+ u32 nav = 0;
+ if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+ struct ampdu_hdr_st *ampdu_hdr =
+ (struct ampdu_hdr_st *)skb->head;
+ sta = ampdu_hdr->ampdu_tid->sta;
+ hdr =
+ (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET +
+ AMPDU_DELIMITER_LEN);
+ } else {
+ struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+ sta = skb_info->sta;
+ hdr = (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET);
+ }
+ if (sta) {
+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ sta_info = ssv_sta_priv->sta_info;
+ }
+ if ((!sc->bq4_dtim) &&
+ (ieee80211_is_mgmt(hdr->frame_control) ||
+ ieee80211_is_nullfunc(hdr->frame_control) ||
+ ieee80211_is_qos_nullfunc(hdr->frame_control))) {
+ ac = 4;
+ hw_txqid = 4;
+ } else if ((sc->bq4_dtim) &&
+ info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
+ hw_txqid = 4;
+ ac = 4;
+ } else {
+ ac = skb_get_queue_mapping(skb);
+ hw_txqid = sc->tx.hw_txqid[ac];
+ }
+ tx_drate = &info->control.rates[0];
+ ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
+ tx_desc->len = skb->len;
+ tx_desc->c_type = M2_TXREQ;
+ tx_desc->f80211 = 1;
+ tx_desc->qos = (ieee80211_is_data_qos(hdr->frame_control)) ? 1 : 0;
+ if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
+ if (ieee80211_is_mgmt(hdr->frame_control) &&
+ ieee80211_has_order(hdr->frame_control))
+ tx_desc->ht = 1;
+ }
+ tx_desc->use_4addr = (ieee80211_has_a4(hdr->frame_control)) ? 1 : 0;
+ tx_desc->more_data =
+ (ieee80211_has_morefrags(hdr->frame_control)) ? 1 : 0;
+ tx_desc->stype_b5b4 = (cpu_to_le16(hdr->frame_control) >> 4) & 0x3;
+ tx_desc->frag = (tx_desc->more_data || (hdr->seq_ctrl & 0xf)) ? 1 : 0;
+ tx_desc->unicast = (is_multicast_ether_addr(hdr->addr1)) ? 0 : 1;
+ tx_desc->tx_burst = (tx_desc->frag) ? 1 : 0;
+ tx_desc->wsid = (!sta_info
+ || (sta_info->hw_wsid < 0)) ? 0x0F : sta_info->hw_wsid;
+ tx_desc->txq_idx = hw_txqid;
+ tx_desc->hdr_offset = TXPB_OFFSET;
+ tx_desc->hdr_len = ssv6xxx_frame_hdrlen(hdr, tx_desc->ht);
+ tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
+ if (info->control.use_rts)
+ tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS;
+ else if (info->control.use_cts_prot)
+ tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_CTS_PROTECT;
+ if (tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT)
+ tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS;
+ if (tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT) {
+ tx_desc->crate_idx = 0;
+ } else
+ tx_desc->crate_idx = ssv_rate.crate_hw_idx;
+ tx_desc->drate_idx = ssv_rate.drate_hw_idx;
+ if (tx_desc->unicast == 0)
+ tx_desc->ack_policy = 1;
+ else if (tx_desc->qos == 1)
+ tx_desc->ack_policy = (*ieee80211_get_qos_ctl(hdr) & 0x60) >> 5;
+ else if (ieee80211_is_ctl(hdr->frame_control))
+ tx_desc->ack_policy = 1;
+ tx_desc->security = 0;
+ tx_desc->fCmdIdx = 0;
+ tx_desc->fCmd = (hw_txqid + M_ENG_TX_EDCA0);
+ if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+#ifdef AMPDU_HAS_LEADING_FRAME
+ tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_CPU;
+#else
+ tx_desc->RSVD_1 = 1;
+#endif
+ tx_desc->aggregation = 1;
+ tx_desc->ack_policy = 0x01;
+ if ((tx_desc->do_rts_cts == 0)
+ && ((sc->hw->wiphy->rts_threshold == (-1))
+ || ((skb->len - sc->sh->tx_desc_len) >
+ sc->hw->wiphy->rts_threshold))) {
+ tx_drate->flags |= IEEE80211_TX_RC_USE_RTS_CTS;
+ tx_desc->do_rts_cts = 1;
+ }
+ }
+ if (ieee80211_has_protected(hdr->frame_control)
+ && (ieee80211_is_data_qos(hdr->frame_control)
+ || ieee80211_is_data(hdr->frame_control))) {
+ if ((tx_desc->unicast && ssv_sta_priv
+ && ssv_sta_priv->has_hw_encrypt)
+ || (!tx_desc->unicast && vif_priv
+ && vif_priv->has_hw_encrypt)) {
+ if (!tx_desc->unicast
+ && !list_empty(&vif_priv->sta_list)) {
+ struct ssv_sta_priv_data *one_sta_priv;
+ int hw_wsid;
+ one_sta_priv =
+ list_first_entry(&vif_priv->sta_list,
+ struct ssv_sta_priv_data,
+ list);
+ hw_wsid = one_sta_priv->sta_info->hw_wsid;
+ if (hw_wsid != (-1)) {
+ tx_desc->wsid = hw_wsid;
+ }
+ }
+ tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_ENCRYPT;
+ } else if (ssv_sta_priv->need_sw_encrypt) {
+ } else {
+ }
+ } else {
+ }
+ tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_HWHCI;
+ if (tx_desc->aggregation == 1) {
+ struct ampdu_hdr_st *ampdu_hdr =
+ (struct ampdu_hdr_st *)skb->head;
+ memcpy(&tx_desc->rc_params[0], ampdu_hdr->rates,
+ sizeof(tx_desc->rc_params));
+ nav =
+ ssv6xxx_set_frame_duration(info, &ssv_rate,
+ (skb->len + FCS_LEN), tx_desc,
+ &tx_desc->rc_params[0], sc);
+#ifdef FW_RC_RETRY_DEBUG
+ {
+ dev_dbg
+ (sc->dev, "[FW_RC]:param[0]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
+ tx_desc->rc_params[0].drate,
+ tx_desc->rc_params[0].count,
+ tx_desc->rc_params[0].crate,
+ tx_desc->rc_params[0].dl_length,
+ tx_desc->rc_params[0].frame_consume_time,
+ tx_desc->rc_params[0].rts_cts_nav);
+ dev_dbg
+ (sc->dev, "[FW_RC]:param[1]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
+ tx_desc->rc_params[1].drate,
+ tx_desc->rc_params[1].count,
+ tx_desc->rc_params[1].crate,
+ tx_desc->rc_params[1].dl_length,
+ tx_desc->rc_params[1].frame_consume_time,
+ tx_desc->rc_params[1].rts_cts_nav);
+ dev_dbg
+ (sc->dev, "[FW_RC]:param[2]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
+ tx_desc->rc_params[2].drate,
+ tx_desc->rc_params[2].count,
+ tx_desc->rc_params[2].crate,
+ tx_desc->rc_params[2].dl_length,
+ tx_desc->rc_params[2].frame_consume_time,
+ tx_desc->rc_params[2].rts_cts_nav);
+ }
+#endif
+ } else {
+ nav =
+ ssv6xxx_set_frame_duration(info, &ssv_rate,
+ (skb->len + FCS_LEN), tx_desc,
+ NULL, NULL);
+ }
+ if ((tx_desc->aggregation == 0)) {
+ if (tx_desc->tx_burst == 0) {
+ if (tx_desc->ack_policy != 0x01)
+ hdr->duration_id = nav;
+ } else {
+ }
+ }
+}
+
+void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb)
+{
+ struct ssv6200_tx_desc *tx_desc;
+ skb_push(skb, sc->sh->tx_desc_len);
+ tx_desc = (struct ssv6200_tx_desc *)skb->data;
+ memset((void *)tx_desc, 0, sc->sh->tx_desc_len);
+ ssv6xxx_update_txinfo(sc, skb);
+}
+
+int ssv6xxx_get_real_index(struct ssv_softc *sc, struct sk_buff *skb)
+{
+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+ struct ieee80211_tx_rate *tx_drate;
+ struct ssv_rate_info ssv_rate;
+ tx_drate = &info->control.rates[0];
+ ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
+ return ssv_rate.drate_hw_idx;
+}
+
+static void _ssv6xxx_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+ struct ieee80211_vif *vif = info->control.vif;
+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+ struct ssv6200_tx_desc *tx_desc;
+ int ret;
+ unsigned long flags;
+ bool send_hci = false;
+ do {
+ if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
+ if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
+ sc->tx.seq_no += 0x10;
+ hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
+ hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
+ }
+ if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+ if (ssv6xxx_get_real_index(sc, skb) <
+ SSV62XX_RATE_MCS_INDEX) {
+ info->flags &= (~IEEE80211_TX_CTL_AMPDU);
+ goto tx_mpdu;
+ }
+ if (ssv6200_ampdu_tx_handler(hw, skb)) {
+ break;
+ } else {
+ info->flags &= (~IEEE80211_TX_CTL_AMPDU);
+ }
+ }
+ tx_mpdu:
+ ssv6xxx_add_txinfo(sc, skb);
+ if (vif &&
+ vif->type == NL80211_IFTYPE_AP &&
+ (sc->bq4_dtim) &&
+ info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
+ struct ssv_vif_priv_data *priv_vif =
+ (struct ssv_vif_priv_data *)vif->drv_priv;
+ u8 buffered = 0;
+ spin_lock_irqsave(&sc->ps_state_lock, flags);
+ if (priv_vif->sta_asleep_mask) {
+ buffered =
+ ssv6200_bcast_enqueue(sc, &sc->bcast_txq,
+ skb);
+ if (1 == buffered) {
+ dev_dbg(sc->dev, "ssv6200_tx:ssv6200_bcast_start\n");
+ ssv6200_bcast_start(sc);
+ }
+ }
+ spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+ if (buffered)
+ break;
+ }
+ if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
+ struct ssv_vif_priv_data *vif_priv =
+ (struct ssv_vif_priv_data *)vif->drv_priv;
+ dev_dbg(sc->dev, "vif[%d] sc->bq4_dtim[%d]\n",
+ vif_priv->vif_idx, sc->bq4_dtim);
+ }
+ tx_desc = (struct ssv6200_tx_desc *)skb->data;
+ ret = HCI_SEND(sc->sh, skb, tx_desc->txq_idx);
+ send_hci = true;
+ } while (0);
+ if ((skb_queue_len(&sc->tx_skb_q) < LOW_TX_Q_LEN)
+ ) {
+ if (sc->tx.flow_ctrl_status != 0) {
+ int ac;
+ for (ac = 0; ac < sc->hw->queues; ac++) {
+ if ((sc->tx.flow_ctrl_status & BIT(ac)) == 0)
+ ieee80211_wake_queue(sc->hw, ac);
+ }
+ } else {
+ ieee80211_wake_queues(sc->hw);
+ }
+ }
+}
+
+static void ssv6200_tx(struct ieee80211_hw *hw,
+ struct ieee80211_tx_control *control,
+ struct sk_buff *skb)
+{
+ struct ssv_softc *sc = (struct ssv_softc *)hw->priv;
+ struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+ skb_info->sta = control ? control->sta : NULL;
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+ skb_info->timestamp = ktime_get();
+#endif
+ skb_queue_tail(&sc->tx_skb_q, skb);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (sc->max_tx_skb_q_len < skb_queue_len(&sc->tx_skb_q))
+ sc->max_tx_skb_q_len = skb_queue_len(&sc->tx_skb_q);
+#endif
+ wake_up_interruptible(&sc->tx_wait_q);
+ do {
+ if (skb_queue_len(&sc->tx_skb_q) >= MAX_TX_Q_LEN)
+ ieee80211_stop_queues(sc->hw);
+ } while (0);
+}
+
+int ssv6xxx_tx_task(void *data)
+{
+ struct ssv_softc *sc = (struct ssv_softc *)data;
+ u32 wait_period = SSV_AMPDU_timer_period / 2;
+ dev_info(sc->dev, "TX Task started\n");
+ while (!kthread_should_stop()) {
+ u32 before_timeout = (-1);
+ set_current_state(TASK_INTERRUPTIBLE);
+ before_timeout = wait_event_interruptible_timeout(sc->tx_wait_q,
+ (skb_queue_len
+ (&sc->
+ tx_skb_q)
+ ||
+ kthread_should_stop
+ ()
+ || sc->
+ tx_q_empty),
+ msecs_to_jiffies
+ (wait_period));
+ if (kthread_should_stop()) {
+ dev_dbg(sc->dev, "Quit TX task loop...\n");
+ break;
+ }
+ set_current_state(TASK_RUNNING);
+ do {
+ struct sk_buff *tx_skb = skb_dequeue(&sc->tx_skb_q);
+ if (tx_skb == NULL)
+ break;
+ _ssv6xxx_tx(sc->hw, tx_skb);
+ } while (1);
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+ {
+ struct ssv_hw_txq *hw_txq = NULL;
+ struct ieee80211_tx_info *tx_info = NULL;
+ struct sk_buff *skb = NULL;
+ int txqid;
+ unsigned int timeout;
+ u32 status;
+ for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
+ hw_txq = &ssv_dbg_ctrl_hci->hw_txq[txqid];
+ skb = skb_peek(&hw_txq->qhead);
+ if (skb != NULL) {
+ tx_info = IEEE80211_SKB_CB(skb);
+ if (tx_info->
+ flags & IEEE80211_TX_CTL_AMPDU)
+ timeout =
+ cal_duration_of_ampdu(skb,
+ SKB_DURATION_STAGE_IN_HWQ);
+ else
+ timeout =
+ cal_duration_of_mpdu(skb);
+ if (timeout > SKB_DURATION_TIMEOUT_MS) {
+ HCI_IRQ_STATUS(ssv_dbg_ctrl_hci,
+ &status);
+ dev_dbg(sc->dev, "hci int_mask: %08x\n",
+ ssv_dbg_ctrl_hci->
+ int_mask);
+ dev_dbg(sc->dev, "sdio status: %08x\n",
+ status);
+ dev_dbg(sc->dev, "hwq%d len: %d\n", txqid,
+ skb_queue_len(&hw_txq->
+ qhead));
+ }
+ }
+ }
+ }
+#endif
+ if (sc->tx_q_empty || (before_timeout == 0)) {
+ u32 flused_ampdu = ssv6xxx_ampdu_flush(sc->hw);
+ sc->tx_q_empty = false;
+ if (flused_ampdu == 0 && before_timeout == 0) {
+ wait_period *= 2;
+ if (wait_period > 1000)
+ wait_period = 1000;
+ }
+ } else
+ wait_period = SSV_AMPDU_timer_period / 2;
+ }
+ return 0;
+}
+
+int ssv6xxx_rx_task(void *data)
+{
+ struct ssv_softc *sc = (struct ssv_softc *)data;
+ unsigned long wait_period = msecs_to_jiffies(200);
+ unsigned long last_timeout_check_jiffies = jiffies;
+ unsigned long cur_jiffies;
+ dev_info(sc->dev, "RX Task started\n");
+ while (!kthread_should_stop()) {
+ u32 before_timeout = (-1);
+ set_current_state(TASK_INTERRUPTIBLE);
+ before_timeout = wait_event_interruptible_timeout(sc->rx_wait_q,
+ (skb_queue_len
+ (&sc->
+ rx_skb_q)
+ ||
+ skb_queue_len
+ (&sc->
+ tx_done_q)
+ ||
+ kthread_should_stop
+ ()),
+ wait_period);
+ if (kthread_should_stop()) {
+ dev_dbg(sc->dev, "Quit RX task loop...\n");
+ break;
+ }
+ set_current_state(TASK_RUNNING);
+ cur_jiffies = jiffies;
+ if ((before_timeout == 0)
+ || time_before((last_timeout_check_jiffies + wait_period),
+ cur_jiffies)) {
+ ssv6xxx_ampdu_check_timeout(sc->hw);
+ last_timeout_check_jiffies = cur_jiffies;
+ }
+ if (skb_queue_len(&sc->rx_skb_q))
+ _process_rx_q(sc, &sc->rx_skb_q, NULL);
+ if (skb_queue_len(&sc->tx_done_q))
+ _process_tx_done(sc);
+ }
+ return 0;
+}
+
+struct ssv6xxx_iqk_cfg init_iqk_cfg = {
+ SSV6XXX_IQK_CFG_XTAL_26M,
+#ifdef CONFIG_SSV_DPD
+ SSV6XXX_IQK_CFG_PA_LI_MPB,
+#else
+ SSV6XXX_IQK_CFG_PA_DEF,
+#endif
+ 0,
+ 0,
+ 26,
+ 3,
+ 0x75,
+ 0x75,
+ 0x80,
+ 0x80,
+ SSV6XXX_IQK_CMD_INIT_CALI,
+ {SSV6XXX_IQK_TEMPERATURE
+ + SSV6XXX_IQK_RXDC
+ + SSV6XXX_IQK_RXRC
+ + SSV6XXX_IQK_TXDC + SSV6XXX_IQK_TXIQ + SSV6XXX_IQK_RXIQ
+#ifdef CONFIG_SSV_DPD
+ + SSV6XXX_IQK_PAPD
+#endif
+ },
+};
+
+static int ssv6200_start(struct ieee80211_hw *hw)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ssv_hw *sh = sc->sh;
+ struct ieee80211_channel *chan;
+ int ret;
+
+ mutex_lock(&sc->mutex);
+ ret = ssv6xxx_init_mac(sc->sh);
+ if (ret != 0) {
+ dev_err(sc->dev, "Failed to initialize mac, ret=%d\n", ret);
+ ssv6xxx_deinit_mac(sc);
+ mutex_unlock(&sc->mutex);
+ return -1;
+ }
+#ifdef CONFIG_P2P_NOA
+ ssv6xxx_noa_reset(sc);
+#endif
+ HCI_START(sh);
+ ieee80211_wake_queues(hw);
+ ssv6200_ampdu_init(hw);
+ sc->watchdog_flag = WD_KICKED;
+ mutex_unlock(&sc->mutex);
+ mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
+#ifdef CONFIG_SSV_SMARTLINK
+ {
+ extern int ksmartlink_init(void);
+ (void)ksmartlink_init();
+ }
+#endif
+ ret = ssv6xxx_do_iq_calib(sc->sh, &init_iqk_cfg);
+ if (ret != 0) {
+ dev_err(sc->dev, "IQ Calibration failed, ret=%d\n", ret);
+ return ret;
+ }
+
+ dev_info(sc->dev, "Calibration successful\n");
+
+ SMAC_REG_WRITE(sc->sh, ADR_PHY_EN_1, 0x217f);
+ if ((sh->cfg.chip_identity == SSV6051Z)
+ || (sc->sh->cfg.chip_identity == SSV6051P)) {
+ int i;
+ for (i = 0; i < sh->ch_cfg_size; i++) {
+ SMAC_REG_READ(sh, sh->p_ch_cfg[i].reg_addr,
+ &sh->p_ch_cfg[i].ch1_12_value);
+ }
+ }
+ chan = hw->conf.chandef.chan;
+ sc->cur_channel = chan;
+ dev_dbg(sc->dev, "%s(): current channel: %d,sc->ps_status=%d\n", __FUNCTION__,
+ sc->cur_channel->hw_value, sc->ps_status);
+ ssv6xxx_set_channel(sc, chan->hw_value);
+ ssv6xxx_rf_enable(sh);
+ return 0;
+}
+
+static void ssv6200_stop(struct ieee80211_hw *hw)
+{
+ struct ssv_softc *sc = hw->priv;
+ u32 count = 0;
+ struct rssi_res_st *rssi_tmp0, *rssi_tmp1;
+ dev_dbg(sc->dev, "%s(): sc->ps_status=%d\n", __FUNCTION__,
+ sc->ps_status);
+ mutex_lock(&sc->mutex);
+ list_for_each_entry_safe(rssi_tmp0, rssi_tmp1, &rssi_res.rssi_list,
+ rssi_list) {
+ list_del(&rssi_tmp0->rssi_list);
+ kfree(rssi_tmp0);
+ }
+ ssv6200_ampdu_deinit(hw);
+ ssv6xxx_rf_disable(sc->sh);
+ HCI_STOP(sc->sh);
+#ifndef NO_USE_RXQ_LOCK
+ while (0) {
+#else
+ while (skb_queue_len(&sc->rx.rxq_head)) {
+#endif
+ dev_dbg(sc->dev, "sc->rx.rxq_count=%d\n", sc->rx.rxq_count);
+ count++;
+ if (count > 90000000) {
+ dev_err(sc->dev, "Could not empty RX queue during shutdown\n");
+ break;
+ }
+ }
+ HCI_TXQ_FLUSH(sc->sh, (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2 |
+ TXQ_EDCA_3 | TXQ_MGMT));
+ if ((sc->ps_status == PWRSV_PREPARE) || (sc->ps_status == PWRSV_ENABLE)) {
+ ssv6xxx_enable_ps(sc);
+ ssv6xxx_rf_enable(sc->sh);
+ }
+ sc->watchdog_flag = WD_SLEEP;
+ mutex_unlock(&sc->mutex);
+ del_timer_sync(&sc->watchdog_timeout);
+#ifdef CONFIG_SSV_SMARTLINK
+ {
+ extern void ksmartlink_exit(void);
+ ksmartlink_exit();
+ }
+#endif
+ dev_dbg(sc->dev, "%s(): leave\n", __FUNCTION__);
+}
+
+void inline ssv62xxx_set_bssid(struct ssv_softc *sc, u8 * bssid)
+{
+ memcpy(sc->bssid, bssid, 6);
+ SMAC_REG_WRITE(sc->sh, ADR_BSSID_0, *((u32 *) & sc->bssid[0]));
+ SMAC_REG_WRITE(sc->sh, ADR_BSSID_1, *((u32 *) & sc->bssid[4]));
+}
+
+struct ssv_vif_priv_data *ssv6xxx_config_vif_res(struct ssv_softc *sc,
+ struct ieee80211_vif *vif)
+{
+ int i;
+ struct ssv_vif_priv_data *priv_vif;
+ struct ssv_vif_info *vif_info;
+ lockdep_assert_held(&sc->mutex);
+ for (i = 0; i < SSV6200_MAX_VIF; i++) {
+ if (sc->vif_info[i].vif == NULL)
+ break;
+ }
+ BUG_ON(i >= SSV6200_MAX_VIF);
+ dev_dbg(sc->dev, "ssv6xxx_config_vif_res id[%d].\n", i);
+ priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
+ memset(priv_vif, 0, sizeof(struct ssv_vif_priv_data));
+ priv_vif->vif_idx = i;
+ memset(&sc->vif_info[i], 0, sizeof(sc->vif_info[0]));
+ sc->vif_info[i].vif = vif;
+ sc->vif_info[i].vif_priv = priv_vif;
+ INIT_LIST_HEAD(&priv_vif->sta_list);
+ priv_vif->pair_cipher = SSV_CIPHER_NONE;
+ priv_vif->group_cipher = SSV_CIPHER_NONE;
+ priv_vif->has_hw_decrypt = false;
+ priv_vif->has_hw_encrypt = false;
+ priv_vif->need_sw_encrypt = false;
+ priv_vif->need_sw_decrypt = false;
+ priv_vif->use_mac80211_decrypt = false;
+ priv_vif->is_security_valid = false;
+ priv_vif->force_sw_encrypt = (vif->type == NL80211_IFTYPE_AP);
+ vif_info = &sc->vif_info[priv_vif->vif_idx];
+ vif_info->if_type = vif->type;
+ vif_info->vif = vif;
+ return priv_vif;
+}
+
+static int ssv6200_add_interface(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif)
+{
+ struct ssv_softc *sc = hw->priv;
+ int ret = 0;
+ struct ssv_vif_priv_data *vif_priv = NULL;
+ dev_dbg(sc->dev, "[I] %s(): vif->type = %d, NL80211_IFTYPE_AP=%d\n", __FUNCTION__,
+ vif->type, NL80211_IFTYPE_AP);
+ if ((sc->nvif >= SSV6200_MAX_VIF)
+ || (((vif->type == NL80211_IFTYPE_AP)
+ || (vif->p2p))
+ && (sc->ap_vif != NULL))) {
+ dev_err(sc->dev, "Add interface of type %d (p2p: %d) failed.\n",
+ vif->type, vif->p2p);
+ return -EOPNOTSUPP;
+ }
+ mutex_lock(&sc->mutex);
+ vif_priv = ssv6xxx_config_vif_res(sc, vif);
+ if ((vif_priv->vif_idx == 0) && (vif->p2p == 0)
+ && (vif->type == NL80211_IFTYPE_AP)) {
+ dev_dbg(sc->dev, "VIF[0] set bssid and config opmode to ap\n");
+ ssv62xxx_set_bssid(sc, sc->sh->cfg.maddr[0]);
+ SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6200_OPMODE_AP,
+ OP_MODE_MSK);
+ }
+ if (vif->type == NL80211_IFTYPE_AP) {
+ BUG_ON(sc->ap_vif != NULL);
+ sc->ap_vif = vif;
+ if (!vif->p2p && (vif_priv->vif_idx == 0)) {
+ dev_dbg(sc->dev, "Normal AP mode. Config Q4 to DTIM Q.\n");
+ SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC,
+ MTX_HALT_MNG_UNTIL_DTIM_MSK,
+ MTX_HALT_MNG_UNTIL_DTIM_MSK);
+ sc->bq4_dtim = true;
+ }
+ }
+ sc->nvif++;
+ dev_dbg(sc->dev,
+ "VIF %02x:%02x:%02x:%02x:%02x:%02x of type %d is added.\n",
+ vif->addr[0], vif->addr[1], vif->addr[2], vif->addr[3],
+ vif->addr[4], vif->addr[5], vif->type);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ ssv6xxx_debugfs_add_interface(sc, vif);
+#endif
+ mutex_unlock(&sc->mutex);
+ return ret;
+}
+
+static void ssv6200_remove_interface(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ssv_vif_priv_data *vif_priv =
+ (struct ssv_vif_priv_data *)vif->drv_priv;
+ dev_err(sc->dev,
+ "Removing interface %02x:%02x:%02x:%02x:%02x:%02x. PS=%d\n",
+ vif->addr[0], vif->addr[1], vif->addr[2], vif->addr[3],
+ vif->addr[4], vif->addr[5], sc->ps_status);
+ mutex_lock(&sc->mutex);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ ssv6xxx_debugfs_remove_interface(sc, vif);
+#endif
+ if (vif->type == NL80211_IFTYPE_AP) {
+ if (sc->bq4_dtim) {
+ sc->bq4_dtim = false;
+ ssv6200_release_bcast_frame_res(sc, vif);
+ SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC,
+ 0, MTX_HALT_MNG_UNTIL_DTIM_MSK);
+ dev_dbg(sc->dev, "Config Q4 to normal Q \n");
+ }
+ ssv6xxx_beacon_release(sc);
+ sc->ap_vif = NULL;
+ }
+ memset(&sc->vif_info[vif_priv->vif_idx], 0,
+ sizeof(struct ssv_vif_info));
+ sc->nvif--;
+ mutex_unlock(&sc->mutex);
+}
+
+static int ssv6200_change_interface(struct ieee80211_hw *dev,
+ struct ieee80211_vif *vif,
+ enum nl80211_iftype new_type, bool p2p)
+{
+ struct ssv_softc *sc = dev->priv;
+ int ret = 0;
+
+ dev_dbg(sc->dev, "change_interface new: %d (%d), old: %d (%d)\n", new_type,
+ p2p, vif->type, vif->p2p);
+
+ if (new_type != vif->type || vif->p2p != p2p) {
+ ssv6200_remove_interface(dev, vif);
+ vif->type = new_type;
+ vif->p2p = p2p;
+ ret = ssv6200_add_interface(dev, vif);
+ }
+
+ return ret;
+}
+
+void ssv6xxx_ps_callback_func(unsigned long data)
+{
+ struct ssv_softc *sc = (struct ssv_softc *)data;
+ struct sk_buff *skb;
+ struct cfg_host_cmd *host_cmd;
+ int retry_cnt = 20;
+#ifdef SSV_WAKEUP_HOST
+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
+ M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+ M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + 6 * 4,
+ (sc->mac_deci_tbl[6] | 1));
+#else
+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
+ M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+ M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
+ M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
+#endif
+ skb = ssv_skb_alloc(sizeof(struct cfg_host_cmd));
+ skb->data_len = sizeof(struct cfg_host_cmd);
+ skb->len = skb->data_len;
+ host_cmd = (struct cfg_host_cmd *)skb->data;
+ host_cmd->c_type = HOST_CMD;
+ host_cmd->RSVD0 = 0;
+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_PS;
+ host_cmd->len = skb->data_len;
+#ifdef SSV_WAKEUP_HOST
+ host_cmd->dummy = sc->ps_aid;
+#else
+ host_cmd->dummy = 0;
+#endif
+ sc->ps_aid = 0;
+ while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
+ dev_warn(sc->dev, "PS cmd retry=%d!!\n", retry_cnt);
+ retry_cnt--;
+ }
+ ssv_skb_free(skb);
+ dev_dbg(sc->dev, "SSV6XXX_HOST_CMD_PS,ps_aid = %d,len=%d,tabl=0x%x\n",
+ host_cmd->dummy, skb->len, (sc->mac_deci_tbl[6] | 1));
+}
+
+void ssv6xxx_enable_ps(struct ssv_softc *sc)
+{
+ sc->ps_status = PWRSV_ENABLE;
+}
+
+void ssv6xxx_disable_ps(struct ssv_softc *sc)
+{
+ sc->ps_status = PWRSV_DISABLE;
+ dev_info(sc->dev, "Power saving disabled\n");
+}
+
+int ssv6xxx_watchdog_controller(struct ssv_hw *sh, u8 flag)
+{
+ struct sk_buff *skb;
+ struct cfg_host_cmd *host_cmd;
+ int ret = 0;
+ dev_dbg(sh->sc->dev, "ssv6xxx_watchdog_controller %d\n", flag);
+ skb = ssv_skb_alloc(HOST_CMD_HDR_LEN);
+ if (skb == NULL) {
+ dev_warn(sh->sc->dev, "init ssv6xxx_watchdog_controller fail!!!\n");
+ return (-1);
+ }
+ skb->data_len = HOST_CMD_HDR_LEN;
+ skb->len = skb->data_len;
+ host_cmd = (struct cfg_host_cmd *)skb->data;
+ host_cmd->c_type = HOST_CMD;
+ host_cmd->h_cmd = (u8) flag;
+ host_cmd->len = skb->data_len;
+ sh->hci.hci_ops->hci_send_cmd(skb);
+ ssv_skb_free(skb);
+ return ret;
+}
+
+static int ssv6200_config(struct ieee80211_hw *hw, u32 changed)
+{
+ struct ssv_softc *sc = hw->priv;
+ int ret = 0;
+ mutex_lock(&sc->mutex);
+ if (changed & IEEE80211_CONF_CHANGE_PS) {
+ struct ieee80211_conf *conf = &hw->conf;
+ if (conf->flags & IEEE80211_CONF_PS) {
+ dev_dbg(sc->dev, "Enable IEEE80211_CONF_PS ps_aid=%d\n",
+ sc->ps_aid);
+ } else {
+ dev_dbg(sc->dev, "Disable IEEE80211_CONF_PS ps_aid=%d\n",
+ sc->ps_aid);
+ }
+ }
+ if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
+ struct ieee80211_channel *chan;
+ chan = hw->conf.chandef.chan;
+#ifdef CONFIG_P2P_NOA
+ if (sc->p2p_noa.active_noa_vif) {
+ dev_dbg(sc->dev, "NOA operating-active vif[%02x] skip scan\n",
+ sc->p2p_noa.active_noa_vif);
+ goto out;
+ }
+#endif
+ if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) {
+ if ((sc->ap_vif == NULL)
+ ||
+ list_empty(&
+ ((struct ssv_vif_priv_data *)sc->ap_vif->
+ drv_priv)->sta_list)) {
+ HCI_PAUSE(sc->sh,
+ (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
+ | TXQ_EDCA_3 | TXQ_MGMT));
+ sc->sc_flags |= SC_OP_OFFCHAN;
+ ssv6xxx_set_channel(sc, chan->hw_value);
+ sc->hw_chan = chan->hw_value;
+ HCI_RESUME(sc->sh, TXQ_MGMT);
+ } else {
+ dev_dbg(sc->dev,
+ "Off-channel to %d is ignored when AP mode enabled.\n",
+ chan->hw_value);
+ }
+ } else {
+ if ((sc->cur_channel == NULL)
+ || (sc->sc_flags & SC_OP_OFFCHAN)
+ || (sc->hw_chan != chan->hw_value)) {
+ HCI_PAUSE(sc->sh,
+ (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
+ | TXQ_EDCA_3 | TXQ_MGMT));
+ ssv6xxx_set_channel(sc, chan->hw_value);
+ sc->cur_channel = chan;
+ HCI_RESUME(sc->sh,
+ (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
+ | TXQ_EDCA_3 | TXQ_MGMT));
+ sc->sc_flags &= ~SC_OP_OFFCHAN;
+ } else {
+ dev_dbg(sc->dev,
+ "Change to the same channel %d\n",
+ chan->hw_value);
+ }
+ }
+ }
+#ifdef CONFIG_P2P_NOA
+ out:
+#endif
+ mutex_unlock(&sc->mutex);
+ return ret;
+}
+
+#define SUPPORTED_FILTERS \
+ (FIF_ALLMULTI | \
+ FIF_CONTROL | \
+ FIF_PSPOLL | \
+ FIF_OTHER_BSS | \
+ FIF_BCN_PRBRESP_PROMISC | \
+ FIF_PROBE_REQ | \
+ FIF_FCSFAIL)
+static void ssv6200_config_filter(struct ieee80211_hw *hw,
+ unsigned int changed_flags,
+ unsigned int *total_flags, u64 multicast)
+{
+ changed_flags &= SUPPORTED_FILTERS;
+ *total_flags &= SUPPORTED_FILTERS;
+}
+
+static void ssv6200_bss_info_changed(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_bss_conf *info,
+ u64 changed)
+{
+ struct ssv_vif_priv_data *priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
+ struct ssv_softc *sc = hw->priv;
+#ifdef CONFIG_P2P_NOA
+ u8 null_address[6] = { 0 };
+#endif
+ mutex_lock(&sc->mutex);
+ if (changed & BSS_CHANGED_ERP_PREAMBLE) {
+ dev_dbg(sc->dev, "BSS Changed use_short_preamble[%d]\n",
+ info->use_short_preamble);
+ if (info->use_short_preamble)
+ sc->sc_flags |= SC_OP_SHORT_PREAMBLE;
+ else
+ sc->sc_flags &= ~SC_OP_SHORT_PREAMBLE;
+ }
+ if (!priv_vif->vif_idx) {
+ if (changed & BSS_CHANGED_BSSID) {
+#ifdef CONFIG_P2P_NOA
+ struct ssv_vif_priv_data *vif_priv;
+ vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+#endif
+ ssv62xxx_set_bssid(sc, (u8 *) info->bssid);
+ dev_dbg(sc->dev, "BSS_CHANGED_BSSID: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ info->bssid[0], info->bssid[1], info->bssid[2],
+ info->bssid[3], info->bssid[4], info->bssid[5]);
+#ifdef CONFIG_P2P_NOA
+ if (memcmp(info->bssid, null_address, 6))
+ ssv6xxx_noa_hdl_bss_change(sc,
+ MONITOR_NOA_CONF_ADD,
+ vif_priv->vif_idx);
+ else
+ ssv6xxx_noa_hdl_bss_change(sc,
+ MONITOR_NOA_CONF_REMOVE,
+ vif_priv->vif_idx);
+#endif
+ }
+ if (changed & BSS_CHANGED_ERP_SLOT) {
+ u32 regval = 0;
+ dev_dbg(sc->dev, "BSS_CHANGED_ERP_SLOT: use_short_slot[%d]\n",
+ info->use_short_slot);
+ if (info->use_short_slot) {
+ SMAC_REG_READ(sc->sh, ADR_MTX_DUR_IFS, &regval);
+ regval = regval & MTX_DUR_SLOT_I_MSK;
+ regval |= 9 << MTX_DUR_SLOT_SFT;
+ SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_IFS, regval);
+ SMAC_REG_READ(sc->sh, ADR_MTX_DUR_SIFS_G,
+ &regval);
+ regval = regval & MTX_DUR_BURST_SIFS_G_I_MSK;
+ regval |= 0xa << MTX_DUR_BURST_SIFS_G_SFT;
+ regval = regval & MTX_DUR_SLOT_G_I_MSK;
+ regval |= 9 << MTX_DUR_SLOT_G_SFT;
+ SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_SIFS_G,
+ regval);
+ } else {
+ SMAC_REG_READ(sc->sh, ADR_MTX_DUR_IFS, &regval);
+ regval = regval & MTX_DUR_SLOT_I_MSK;
+ regval |= 20 << MTX_DUR_SLOT_SFT;
+ SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_IFS, regval);
+ SMAC_REG_READ(sc->sh, ADR_MTX_DUR_SIFS_G,
+ &regval);
+ regval = regval & MTX_DUR_BURST_SIFS_G_I_MSK;
+ regval |= 0xa << MTX_DUR_BURST_SIFS_G_SFT;
+ regval = regval & MTX_DUR_SLOT_G_I_MSK;
+ regval |= 20 << MTX_DUR_SLOT_G_SFT;
+ SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_SIFS_G,
+ regval);
+ }
+ }
+ }
+ if (changed & BSS_CHANGED_HT) {
+ dev_dbg(sc->dev, "BSS_CHANGED_HT: Untreated!!\n");
+ }
+ if (changed & BSS_CHANGED_BASIC_RATES) {
+ dev_dbg(sc->dev, "ssv6xxx_rc_update_basic_rate!!\n");
+ ssv6xxx_rc_update_basic_rate(sc, info->basic_rates);
+ }
+ if (vif->type == NL80211_IFTYPE_STATION) {
+ dev_dbg(sc->dev, "NL80211_IFTYPE_STATION!!\n");
+ if ((changed & BSS_CHANGED_ASSOC) && (vif->p2p == 0)) {
+ sc->isAssoc = vif->cfg.assoc;
+ if (!sc->isAssoc) {
+ sc->channel_center_freq = 0;
+ sc->ps_aid = 0;
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x0400);
+#endif
+ SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_CONTROL,
+ 0x0);
+ } else {
+ struct ieee80211_channel *curchan;
+ curchan = hw->conf.chandef.chan;
+ sc->channel_center_freq = curchan->center_freq;
+ dev_dbg(sc->dev, "info->aid = %d\n", vif->cfg.aid);
+ sc->ps_aid = vif->cfg.aid;
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x1000);
+#endif
+ }
+ }
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+ else if ((changed & BSS_CHANGED_ASSOC) && vif->p2p == 1) {
+ if (info->assoc)
+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x0400);
+ else if (sc->ps_aid != 0)
+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x1000);
+ }
+#endif
+ }
+ if (vif->type == NL80211_IFTYPE_AP) {
+ if (changed & (BSS_CHANGED_BEACON
+ | BSS_CHANGED_SSID
+ | BSS_CHANGED_BSSID | BSS_CHANGED_BASIC_RATES)) {
+#ifdef BROADCAST_DEBUG
+ dev_dbg(sc->dev, "[A] ssv6200_bss_info_changed:beacon changed\n");
+#endif
+ queue_work(sc->config_wq, &sc->set_tim_work);
+ }
+ if (changed & BSS_CHANGED_BEACON_INT) {
+ dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_INT beacon_interval(%d)\n",
+ info->beacon_int);
+ if (sc->beacon_interval != info->beacon_int) {
+ sc->beacon_interval = info->beacon_int;
+ ssv6xxx_beacon_set_info(sc, sc->beacon_interval,
+ sc->beacon_dtim_cnt);
+ }
+ }
+ if (changed & BSS_CHANGED_BEACON_ENABLED) {
+#ifdef BEACON_DEBUG
+ dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_ENABLED (0x%x)\n",
+ info->enable_beacon);
+#endif
+ if (0 != ssv6xxx_beacon_enable(sc, info->enable_beacon)) {
+ dev_err(sc->dev, "Beacon enable %d error.\n",
+ info->enable_beacon);
+ }
+ }
+ }
+ mutex_unlock(&sc->mutex);
+ dev_dbg(sc->dev, "[I] %s(): leave\n", __FUNCTION__);
+}
+
+static int ssv6200_sta_add(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif, struct ieee80211_sta *sta)
+{
+ struct ssv_sta_priv_data *sta_priv_dat = NULL;
+ struct ssv_softc *sc = hw->priv;
+ struct ssv_sta_info *sta_info;
+ u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
+ int s, i;
+ u32 reg_wsid_tid0[] = { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ };
+ u32 reg_wsid_tid7[] = { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ };
+ unsigned long flags;
+ int ret = 0;
+ struct ssv_vif_priv_data *vif_priv =
+ (struct ssv_vif_priv_data *)vif->drv_priv;
+ int fw_sec_caps = SSV6XXX_WSID_SEC_NONE;
+ bool tdls_use_sw_cipher = false, tdls_link = false;
+ dev_dbg(sc->dev, "[I] %s(): vif[%d] ", __FUNCTION__, vif_priv->vif_idx);
+ if (sc->force_triger_reset == true) {
+ vif_priv->sta_asleep_mask = 0;
+ do {
+ spin_lock_irqsave(&sc->ps_state_lock, flags);
+ for (s = 0; s < SSV_NUM_STA; s++, sta_info++) {
+ sta_info = &sc->sta_info[s];
+ if ((sta_info->s_flags & STA_FLAG_VALID)) {
+ if (sta_info->sta == sta) {
+ dev_dbg
+ (sc->dev, "search stat %02x:%02x:%02x:%02x:%02x:%02x to wsid=%d\n",
+ sta->addr[0], sta->addr[1],
+ sta->addr[2], sta->addr[3],
+ sta->addr[4], sta->addr[5],
+ sta_info->hw_wsid);
+ spin_unlock_irqrestore(&sc->
+ ps_state_lock,
+ flags);
+ return ret;
+ }
+ }
+ }
+ spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+ if (s >= SSV_NUM_STA) {
+ break;
+ }
+ } while (0);
+ }
+ do {
+ spin_lock_irqsave(&sc->ps_state_lock, flags);
+ if (!list_empty(&vif_priv->sta_list)
+ && vif->type == NL80211_IFTYPE_STATION) {
+ tdls_link = true;
+ }
+ if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_NONE)
+ && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)
+ && (sc->sh->cfg.use_wpa2_only == false)) {
+ tdls_use_sw_cipher = true;
+ }
+ if (((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false))
+ || sc->sh->cfg.use_wpa2_only)
+ s = 0;
+ else
+ s = 2;
+ for (; s < SSV_NUM_STA; s++) {
+ sta_info = &sc->sta_info[s];
+ if ((sta_info->s_flags & STA_FLAG_VALID) == 0) {
+ sta_info->aid = sta->aid;
+ sta_info->sta = sta;
+ sta_info->vif = vif;
+ sta_info->s_flags = STA_FLAG_VALID;
+ sta_priv_dat =
+ (struct ssv_sta_priv_data *)sta->drv_priv;
+ sta_priv_dat->sta_idx = s;
+ sta_priv_dat->sta_info = sta_info;
+ sta_priv_dat->has_hw_encrypt = false;
+ sta_priv_dat->has_hw_decrypt = false;
+ sta_priv_dat->need_sw_decrypt = false;
+ sta_priv_dat->need_sw_encrypt = false;
+ sta_priv_dat->use_mac80211_decrypt = false;
+ if ((vif_priv->pair_cipher == SSV_CIPHER_WEP40)
+ || (vif_priv->pair_cipher ==
+ SSV_CIPHER_WEP104)) {
+ sta_priv_dat->has_hw_encrypt =
+ vif_priv->has_hw_encrypt;
+ sta_priv_dat->has_hw_decrypt =
+ vif_priv->has_hw_decrypt;
+ sta_priv_dat->need_sw_encrypt =
+ vif_priv->need_sw_encrypt;
+ sta_priv_dat->need_sw_decrypt =
+ vif_priv->need_sw_decrypt;
+ }
+ list_add_tail(&sta_priv_dat->list,
+ &vif_priv->sta_list);
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+ if (s >= SSV_NUM_STA) {
+ dev_err(sc->dev,
+ "Number of STA exceeds driver limitation %d\n.",
+ SSV_NUM_STA);
+ ret = -1;
+ break;
+ }
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ ssv6xxx_debugfs_add_sta(sc, sta_info);
+#endif
+ sta_info->hw_wsid = -1;
+ if (sta_priv_dat->sta_idx < SSV_NUM_HW_STA) {
+ SMAC_REG_WRITE(sc->sh, reg_wsid[s] + 4,
+ *((u32 *) & sta->addr[0]));
+ SMAC_REG_WRITE(sc->sh, reg_wsid[s] + 8,
+ *((u32 *) & sta->addr[4]));
+ SMAC_REG_WRITE(sc->sh, reg_wsid[s], 1);
+ for (i = reg_wsid_tid0[s]; i <= reg_wsid_tid7[s];
+ i += 4)
+ SMAC_REG_WRITE(sc->sh, i, 0);
+ ssv6xxx_rc_hw_reset(sc, sta_priv_dat->rc_idx, s);
+ sta_info->hw_wsid = sta_priv_dat->sta_idx;
+ } else if ((vif_priv->vif_idx == 0)
+ || sc->sh->cfg.use_wpa2_only) {
+ sta_info->hw_wsid = sta_priv_dat->sta_idx;
+ }
+ if ((sta_priv_dat->has_hw_encrypt
+ || sta_priv_dat->has_hw_decrypt)
+ && ((vif_priv->pair_cipher == SSV_CIPHER_WEP40)
+ || (vif_priv->pair_cipher == SSV_CIPHER_WEP104))) {
+ struct ssv_vif_info *vif_info =
+ &sc->vif_info[vif_priv->vif_idx];
+ struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey;
+ _set_wep_hw_crypto_pair_key(sc, vif_info, sta_info,
+ (void *)sramKey);
+ if (sramKey->sta_key[0].pair_key_idx != 0) {
+ _set_wep_hw_crypto_group_key(sc, vif_info,
+ sta_info,
+ (void *)sramKey);
+ }
+ }
+ ssv6200_ampdu_tx_add_sta(hw, sta);
+ if (sta_info->hw_wsid >= SSV_NUM_HW_STA) {
+ if (sta_priv_dat->has_hw_decrypt)
+ fw_sec_caps = SSV6XXX_WSID_SEC_PAIRWISE;
+ if (vif_priv->has_hw_decrypt)
+ fw_sec_caps |= SSV6XXX_WSID_SEC_GROUP;
+ hw_update_watch_wsid(sc, sta, sta_info,
+ sta_priv_dat->sta_idx, fw_sec_caps,
+ SSV6XXX_WSID_OPS_ADD);
+ } else if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx)) {
+ hw_update_watch_wsid(sc, sta, sta_info,
+ sta_priv_dat->sta_idx,
+ SSV6XXX_WSID_SEC_SW,
+ SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE);
+ hw_update_watch_wsid(sc, sta, sta_info,
+ sta_priv_dat->sta_idx,
+ SSV6XXX_WSID_SEC_SW,
+ SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE);
+ }
+ dev_dbg
+ (sc->dev, "Add %02x:%02x:%02x:%02x:%02x:%02x to VIF %d sw_idx=%d, wsid=%d\n",
+ sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+ sta->addr[4], sta->addr[5], vif_priv->vif_idx,
+ sta_priv_dat->sta_idx, sta_info->hw_wsid);
+ } while (0);
+ return ret;
+}
+
+void ssv6200_rx_flow_check(struct ssv_sta_priv_data *sta_priv_dat,
+ struct ssv_softc *sc)
+{
+ if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx)
+ && (sta_priv_dat->need_sw_decrypt)) {
+ int other_hw_wsid = (sta_priv_dat->sta_idx + 1) & 1;
+ struct ssv_sta_info *sta_info = &sc->sta_info[other_hw_wsid];
+ struct ieee80211_sta *sta = sta_info->sta;
+ struct ssv_sta_priv_data *sta_priv =
+ (struct ssv_sta_priv_data *)sta->drv_priv;
+ mutex_lock(&sc->mutex);
+ if ((sta_info->s_flags == 0)
+ || ((sta_info->s_flags && STA_FLAG_VALID)
+ && (sta_priv->has_hw_decrypt))) {
+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+ M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) |
+ (M_ENG_HWHCI << 8));
+ dev_dbg(sc->dev, "redirect Rx flow for sta %d disconnect\n",
+ sta_priv_dat->sta_idx);
+ }
+ mutex_unlock(&sc->mutex);
+ }
+}
+
+static int ssv6200_sta_remove(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta)
+{
+ u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
+ struct ssv_sta_priv_data *sta_priv_dat =
+ (struct ssv_sta_priv_data *)sta->drv_priv;
+ struct ssv_softc *sc = hw->priv;
+ struct ssv_sta_info *sta_info = sta_priv_dat->sta_info;
+ unsigned long flags;
+ u32 bit;
+ struct ssv_vif_priv_data *priv_vif =
+ (struct ssv_vif_priv_data *)vif->drv_priv;
+ u8 hw_wsid = -1;
+ BUG_ON(sta_priv_dat->sta_idx >= SSV_NUM_STA);
+ dev_notice(sc->dev,
+ "Removing STA %d (%02X:%02X:%02X:%02X:%02X:%02X) from VIF %d\n.",
+ sta_priv_dat->sta_idx, sta->addr[0], sta->addr[1],
+ sta->addr[2], sta->addr[3], sta->addr[4], sta->addr[5],
+ priv_vif->vif_idx);
+ ssv6200_rx_flow_check(sta_priv_dat, sc);
+ spin_lock_irqsave(&sc->ps_state_lock, flags);
+ bit = BIT(sta_priv_dat->sta_idx);
+ priv_vif->sta_asleep_mask &= ~bit;
+ if (sta_info->hw_wsid != -1) {
+ hw_wsid = sta_info->hw_wsid;
+ }
+ if (sta_info->hw_wsid >= SSV_NUM_HW_STA) {
+ spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+ hw_update_watch_wsid(sc, sta, sta_info, sta_info->hw_wsid, 0,
+ SSV6XXX_WSID_OPS_DEL);
+ spin_lock_irqsave(&sc->ps_state_lock, flags);
+ }
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ {
+ ssv6xxx_debugfs_remove_sta(sc, sta_info);
+ }
+#endif
+ memset(sta_info, 0, sizeof(*sta_info));
+ sta_priv_dat->sta_idx = -1;
+ list_del(&sta_priv_dat->list);
+ if (list_empty(&priv_vif->sta_list)
+ && vif->type == NL80211_IFTYPE_STATION) {
+ priv_vif->pair_cipher = 0;
+ priv_vif->group_cipher = 0;
+ }
+ spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+ if ((hw_wsid != -1) && (hw_wsid < SSV_NUM_HW_STA))
+ SMAC_REG_WRITE(sc->sh, reg_wsid[hw_wsid], 0x00);
+ return 0;
+}
+
+static void ssv6200_sta_notify(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ enum sta_notify_cmd cmd,
+ struct ieee80211_sta *sta)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ssv_vif_priv_data *priv_vif =
+ (struct ssv_vif_priv_data *)vif->drv_priv;
+ struct ssv_sta_priv_data *sta_priv_dat =
+ sta != NULL ? (struct ssv_sta_priv_data *)sta->drv_priv : NULL;
+ struct ssv_sta_info *sta_info;
+ u32 bit, prev;
+ unsigned long flags;
+ spin_lock_irqsave(&sc->ps_state_lock, flags);
+ if (sta_priv_dat != NULL) {
+ bit = BIT(sta_priv_dat->sta_idx);
+ prev = priv_vif->sta_asleep_mask & bit;
+ sta_info = sta_priv_dat->sta_info;
+ switch (cmd) {
+ case STA_NOTIFY_SLEEP:
+ if (!prev) {
+ sta_info->sleeping = true;
+ if ((vif->type == NL80211_IFTYPE_AP)
+ && sc->bq4_dtim
+ && !priv_vif->sta_asleep_mask
+ && ssv6200_bcast_queue_len(&sc->
+ bcast_txq)) {
+ dev_dbg(sc->dev, "%s(): ssv6200_bcast_start\n", __FUNCTION__);
+ ssv6200_bcast_start(sc);
+ }
+ priv_vif->sta_asleep_mask |= bit;
+ }
+ break;
+ case STA_NOTIFY_AWAKE:
+ if (prev) {
+ sta_info->sleeping = false;
+ priv_vif->sta_asleep_mask &= ~bit;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+}
+
+static u64 ssv6200_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
+{
+ return jiffies * 1000 * 1000 / HZ;
+}
+
+static u64 ssv6200_get_systime_us(void)
+{
+#if LINUX_VERSION_CODE > KERNEL_VERSION(4,19,0)
+ struct timespec64 ts;
+ ktime_get_boottime_ts64(&ts);
+#else
+ struct timespec ts;
+ get_monotonic_boottime(&ts);
+#endif
+ return ((u64) ts.tv_sec * 1000000) + ts.tv_nsec / 1000;
+}
+
+static u32 pre_11b_cca_control;
+static u32 pre_11b_cca_1;
+static void ssv6200_sw_scan_start(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ const u8 * mac_addr)
+{
+ ((struct ssv_softc *)(hw->priv))->bScanning = true;
+ SMAC_REG_READ(((struct ssv_softc *)(hw->priv))->sh,
+ ADR_RX_11B_CCA_CONTROL, &pre_11b_cca_control);
+ SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
+ ADR_RX_11B_CCA_CONTROL, 0x0);
+ SMAC_REG_READ(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
+ &pre_11b_cca_1);
+ SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
+ RX_11B_CCA_IN_SCAN);
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+ SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_MRX_FLT_EN3,
+ 0x0400);
+#endif
+}
+
+static void ssv6200_sw_scan_complete(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif)
+{
+
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+ bool is_p2p_assoc;
+#endif
+ ((struct ssv_softc *)(hw->priv))->bScanning = false;
+ SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
+ ADR_RX_11B_CCA_CONTROL, pre_11b_cca_control);
+ SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
+ pre_11b_cca_1);
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+ is_p2p_assoc =
+ ((struct ssv_softc *)(hw->priv))->vif_info[1].vif->bss_conf.assoc;
+ if (((struct ssv_softc *)(hw->priv))->ps_aid != 0 && (!is_p2p_assoc))
+ SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
+ ADR_MRX_FLT_EN3, 0x1000);
+#endif
+}
+
+static int ssv6200_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
+ bool set)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ssv_sta_info *sta_info = sta
+ ? ((struct ssv_sta_priv_data *)sta->drv_priv)->sta_info : NULL;
+ if (sta_info && (sta_info->tim_set ^ set)) {
+ dev_dbg(sc->dev, "[I] [A] ssvcabrio_set_tim");
+ sta_info->tim_set = set;
+ queue_work(sc->config_wq, &sc->set_tim_work);
+ }
+ return 0;
+}
+
+static int ssv6200_conf_tx(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif, u32 link_id, u16 queue,
+ const struct ieee80211_tx_queue_params *params)
+{
+ struct ssv_softc *sc = hw->priv;
+ u32 cw;
+ u8 hw_txqid = sc->tx.hw_txqid[queue];
+ struct ssv_vif_priv_data *priv_vif =
+ (struct ssv_vif_priv_data *)vif->drv_priv;
+ dev_dbg
+ (sc->dev, "[I] sv6200_conf_tx vif[%d] qos[%d] queue[%d] aifsn[%d] cwmin[%d] cwmax[%d] txop[%d] \n",
+ priv_vif->vif_idx, vif->bss_conf.qos, queue, params->aifs,
+ params->cw_min, params->cw_max, params->txop);
+ if (queue > NL80211_TXQ_Q_BK)
+ return 1;
+ if (priv_vif->vif_idx != 0) {
+ dev_warn(sc->dev,
+ "WMM setting applicable to primary interface only.\n");
+ return 1;
+ }
+ mutex_lock(&sc->mutex);
+ SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET,
+ (vif->bss_conf.qos << QOS_EN_SFT), QOS_EN_MSK);
+ cw = (params->aifs - 1) & 0xf;
+ cw |= ((ilog2(params->cw_min + 1)) & 0xf) << TXQ1_MTX_Q_ECWMIN_SFT;
+ cw |= ((ilog2(params->cw_max + 1)) & 0xf) << TXQ1_MTX_Q_ECWMAX_SFT;
+ cw |= ((params->txop) & 0xff) << TXQ1_MTX_Q_TXOP_LIMIT_SFT;
+ SMAC_REG_WRITE(sc->sh, ADR_TXQ0_MTX_Q_AIFSN + 0x100 * hw_txqid, cw);
+ mutex_unlock(&sc->mutex);
+ return 0;
+}
+
+static int ssv6200_ampdu_action(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_ampdu_params *params)
+{
+ struct ssv_softc *sc = hw->priv;
+ int ret = 0;
+ struct ieee80211_sta *sta = params->sta;
+ enum ieee80211_ampdu_mlme_action action = params->action;
+ u16 tid = params->tid;
+ u16 *ssn = &(params->ssn);
+ u8 buf_size = params->buf_size;
+ if (sta == NULL)
+ return ret;
+#if (!Enable_AMPDU_Rx)
+ if (action == IEEE80211_AMPDU_RX_START
+ || action == IEEE80211_AMPDU_RX_STOP) {
+ ampdu_db_log("Disable AMPDU_RX for test(1).\n");
+ return -EOPNOTSUPP;
+ }
+#endif
+#if (!Enable_AMPDU_Tx)
+ if (action == IEEE80211_AMPDU_TX_START
+ || action == IEEE80211_AMPDU_TX_STOP
+ || action == IEEE80211_AMPDU_TX_OPERATIONAL) {
+ ampdu_db_log("Disable AMPDU_TX for test(1).\n");
+ return -EOPNOTSUPP;
+ }
+#endif
+ if ((action == IEEE80211_AMPDU_RX_START
+ || action == IEEE80211_AMPDU_RX_STOP)
+ && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX))) {
+ ampdu_db_log("Disable AMPDU_RX(2).\n");
+ return -EOPNOTSUPP;
+ }
+ if ((action == IEEE80211_AMPDU_TX_START
+ || action == IEEE80211_AMPDU_TX_STOP_CONT
+ || action == IEEE80211_AMPDU_TX_STOP_FLUSH
+ || action == IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
+ || action == IEEE80211_AMPDU_TX_OPERATIONAL)
+ && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) {
+ ampdu_db_log("Disable AMPDU_TX(2).\n");
+ return -EOPNOTSUPP;
+ }
+ switch (action) {
+ case IEEE80211_AMPDU_RX_START:
+#ifdef WIFI_CERTIFIED
+ if (sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS) {
+ ieee80211_stop_rx_ba_session(vif,
+ (1 << (sc->ba_tid)),
+ sc->ba_ra_addr);
+ sc->rx_ba_session_count--;
+ }
+#else
+ if ((sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS)
+ && (sc->rx_ba_sta != sta)) {
+ ret = -EBUSY;
+ break;
+ } else
+ if ((sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS)
+ && (sc->rx_ba_sta == sta)) {
+ ieee80211_stop_rx_ba_session(vif, (1 << (sc->ba_tid)),
+ sc->ba_ra_addr);
+ sc->rx_ba_session_count--;
+ }
+#endif
+ dev_dbg(sc->dev, "IEEE80211_AMPDU_RX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+ sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+ sta->addr[4], sta->addr[5], tid);
+ sc->rx_ba_session_count++;
+ sc->rx_ba_sta = sta;
+ sc->ba_tid = tid;
+ sc->ba_ssn = *ssn;
+ memcpy(sc->ba_ra_addr, sta->addr, ETH_ALEN);
+ queue_work(sc->config_wq, &sc->set_ampdu_rx_add_work);
+ break;
+ case IEEE80211_AMPDU_RX_STOP:
+ sc->rx_ba_session_count--;
+ if (sc->rx_ba_session_count == 0)
+ sc->rx_ba_sta = NULL;
+ queue_work(sc->config_wq, &sc->set_ampdu_rx_del_work);
+ break;
+ case IEEE80211_AMPDU_TX_START:
+ dev_dbg(sc->dev, "AMPDU_TX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+ sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+ sta->addr[4], sta->addr[5], tid);
+ ssv6200_ampdu_tx_start(tid, sta, hw, ssn);
+ ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+ break;
+ case IEEE80211_AMPDU_TX_STOP_CONT:
+ case IEEE80211_AMPDU_TX_STOP_FLUSH:
+ case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
+ dev_dbg(sc->dev, "AMPDU_TX_STOP %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+ sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+ sta->addr[4], sta->addr[5], tid);
+ ssv6200_ampdu_tx_stop(tid, sta, hw);
+ ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+ break;
+ case IEEE80211_AMPDU_TX_OPERATIONAL:
+ dev_dbg(sc->dev, "AMPDU_TX_OPERATIONAL %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+ sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+ sta->addr[4], sta->addr[5], tid);
+ ssv6200_ampdu_tx_operation(tid, sta, hw, buf_size);
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+ return ret;
+}
+
+#ifdef CONFIG_PM
+int ssv6xxx_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan)
+{
+ return 0;
+}
+
+int ssv6xxx_resume(struct ieee80211_hw *hw)
+{
+ return 0;
+}
+#endif
+struct ieee80211_ops ssv6200_ops = {
+ .tx = ssv6200_tx,
+ .start = ssv6200_start,
+ .stop = ssv6200_stop,
+ .add_interface = ssv6200_add_interface,
+ .remove_interface = ssv6200_remove_interface,
+ .change_interface = ssv6200_change_interface,
+ .config = ssv6200_config,
+ .configure_filter = ssv6200_config_filter,
+ .bss_info_changed = ssv6200_bss_info_changed,
+ .sta_add = ssv6200_sta_add,
+ .sta_remove = ssv6200_sta_remove,
+ .sta_notify = ssv6200_sta_notify,
+ .set_key = ssv6200_set_key,
+ .sw_scan_start = ssv6200_sw_scan_start,
+ .sw_scan_complete = ssv6200_sw_scan_complete,
+ .get_tsf = ssv6200_get_tsf,
+ .set_tim = ssv6200_set_tim,
+ .conf_tx = ssv6200_conf_tx,
+ .ampdu_action = ssv6200_ampdu_action,
+ .wake_tx_queue = ieee80211_handle_wake_tx_queue,
+#ifdef CONFIG_PM
+ .suspend = ssv6xxx_suspend,
+ .resume = ssv6xxx_resume,
+#endif
+};
+
+int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug)
+{
+ struct ssv_softc *sc = dev;
+ int ac;
+ BUG_ON(hw_txqid > 4);
+ if (hw_txqid == 4)
+ return 0;
+ ac = sc->tx.ac_txqid[hw_txqid];
+ if (fc_en == false) {
+ if (sc->tx.flow_ctrl_status & (1 << ac)) {
+ ieee80211_wake_queue(sc->hw, ac);
+ sc->tx.flow_ctrl_status &= ~(1 << ac);
+ } else {
+ }
+ } else {
+ if ((sc->tx.flow_ctrl_status & (1 << ac)) == 0) {
+ ieee80211_stop_queue(sc->hw, ac);
+ sc->tx.flow_ctrl_status |= (1 << ac);
+ } else {
+ }
+ }
+ return 0;
+}
+
+void ssv6xxx_tx_q_empty_cb(u32 txq_no, void *cb_data)
+{
+ struct ssv_softc *sc = cb_data;
+ BUG_ON(sc == NULL);
+ sc->tx_q_empty = true;
+ smp_mb();
+ wake_up_interruptible(&sc->tx_wait_q);
+}
+
+struct ssv6xxx_b_cca_control {
+ u32 down_level;
+ u32 upper_level;
+ u32 adjust_cca_control;
+ u32 adjust_cca_1;
+};
+struct ssv6xxx_b_cca_control adjust_cci[] = {
+ {0, 43, 0x00162000, 0x20380050},
+ {40, 48, 0x00161000, 0x20380050},
+ {45, 53, 0x00160800, 0x20380050},
+ {50, 63, 0x00160400, 0x20380050},
+ {60, 68, 0x00160200, 0x20380050},
+ {65, 73, 0x00160100, 0x20380050},
+ {70, 128, 0x00000000, 0x20300050},
+};
+
+#define MAX_CCI_LEVEL 128
+static unsigned long last_jiffies = INITIAL_JIFFIES;
+static s32 size = sizeof(adjust_cci) / sizeof(adjust_cci[0]);
+static u32 current_level = MAX_CCI_LEVEL;
+static u32 current_gate = (sizeof(adjust_cci) / sizeof(adjust_cci[0])) - 1;
+void mitigate_cci(struct ssv_softc *sc, u32 input_level)
+{
+ s32 i;
+ if (input_level > MAX_CCI_LEVEL) {
+ dev_dbg(sc->dev, "mitigate_cci input error[%d]!!\n", input_level);
+ return;
+ }
+ if (time_after(jiffies, last_jiffies + msecs_to_jiffies(3000))) {
+ dev_dbg(sc->dev, "jiffies=%lu, input_level=%d\n", jiffies, input_level);
+ last_jiffies = jiffies;
+ if ((input_level >= adjust_cci[current_gate].down_level)
+ && (input_level <= adjust_cci[current_gate].upper_level)) {
+ current_level = input_level;
+#ifdef DEBUG_MITIGATE_CCI
+ dev_dbg(sc->dev, "Keep the 0xce0020a0[%x] 0xce002008[%x]!!\n",
+ adjust_cci[current_gate].adjust_cca_control,
+ adjust_cci[current_gate].adjust_cca_1);
+#endif
+ } else {
+ if (current_level < input_level) {
+ for (i = 0; i < size; i++) {
+ if (input_level <=
+ adjust_cci[i].upper_level) {
+#ifdef DEBUG_MITIGATE_CCI
+ dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].upper_level=%d, value=%08x\n",
+ current_gate, input_level,
+ i,
+ adjust_cci[i].upper_level,
+ adjust_cci[i].
+ adjust_cca_control);
+#endif
+ current_level = input_level;
+ current_gate = i;
+ SMAC_REG_WRITE(sc->sh,
+ ADR_RX_11B_CCA_CONTROL,
+ adjust_cci[i].
+ adjust_cca_control);
+ SMAC_REG_WRITE(sc->sh,
+ ADR_RX_11B_CCA_1,
+ adjust_cci[i].
+ adjust_cca_1);
+#ifdef DEBUG_MITIGATE_CCI
+ dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n",
+ adjust_cci[current_gate].
+ adjust_cca_control,
+ adjust_cci[current_gate].
+ adjust_cca_1);
+#endif
+ return;
+ }
+ }
+ } else {
+ for (i = (size - 1); i >= 0; i--) {
+ if (input_level >=
+ adjust_cci[i].down_level) {
+#ifdef DEBUG_MITIGATE_CCI
+ dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].down_level=%d, value=%08x\n",
+ current_gate, input_level,
+ i,
+ adjust_cci[i].down_level,
+ adjust_cci[i].
+ adjust_cca_control);
+#endif
+ current_level = input_level;
+ current_gate = i;
+ SMAC_REG_WRITE(sc->sh,
+ ADR_RX_11B_CCA_CONTROL,
+ adjust_cci[i].
+ adjust_cca_control);
+ SMAC_REG_WRITE(sc->sh,
+ ADR_RX_11B_CCA_1,
+ adjust_cci[i].
+ adjust_cca_1);
+#ifdef DEBUG_MITIGATE_CCI
+ dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n",
+ adjust_cci[current_gate].
+ adjust_cca_control,
+ adjust_cci[current_gate].
+ adjust_cca_1);
+#endif
+ return;
+ }
+ }
+ }
+ }
+ }
+}
+
+#define RSSI_SMOOTHING_SHIFT 5
+#define RSSI_DECIMAL_POINT_SHIFT 6
+static void _proc_data_rx_skb(struct ssv_softc *sc, struct sk_buff *rx_skb)
+{
+ struct ieee80211_rx_status *rxs;
+ struct ieee80211_hdr *hdr;
+ __le16 fc;
+ struct ssv6200_rx_desc *rxdesc;
+ struct ssv6200_rxphy_info_padding *rxphypad;
+ struct ssv6200_rxphy_info *rxphy;
+ struct ieee80211_channel *chan;
+ struct ieee80211_vif *vif = NULL;
+ struct ieee80211_sta *sta = NULL;
+ bool rx_hw_dec = false;
+ bool do_sw_dec = false;
+ struct ssv_sta_priv_data *sta_priv = NULL;
+ struct ssv_vif_priv_data *vif_priv = NULL;
+ SKB_info *skb_info = NULL;
+ u8 is_beacon;
+ u8 is_probe_resp;
+ s32 found = 0;
+#ifdef CONFIG_SSV_SMARTLINK
+ {
+ extern int ksmartlink_smartlink_started(void);
+ void smartlink_nl_send_msg(struct sk_buff *skb);
+ if (unlikely(ksmartlink_smartlink_started())) {
+ skb_pull(rx_skb, SSV6XXX_RX_DESC_LEN);
+ skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad);
+ smartlink_nl_send_msg(rx_skb);
+ return;
+ }
+ }
+#endif
+ rxdesc = (struct ssv6200_rx_desc *)rx_skb->data;
+ rxphy = (struct ssv6200_rxphy_info *)(rx_skb->data + sizeof(*rxdesc));
+ rxphypad =
+ (struct ssv6200_rxphy_info_padding *)(rx_skb->data + rx_skb->len -
+ sizeof(struct
+ ssv6200_rxphy_info_padding));
+ hdr = (struct ieee80211_hdr *)(rx_skb->data + SSV6XXX_RX_DESC_LEN);
+ fc = hdr->frame_control;
+ skb_info = (SKB_info *) rx_skb->head;
+ if (rxdesc->wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) {
+ if ((ieee80211_is_data(hdr->frame_control))
+ && (!(ieee80211_is_nullfunc(hdr->frame_control)))) {
+ ssv6xxx_rc_rx_data_handler(sc->hw, rx_skb,
+ rxdesc->rate_idx);
+ }
+ }
+ rxs = IEEE80211_SKB_RXCB(rx_skb);
+ memset(rxs, 0, sizeof(struct ieee80211_rx_status));
+ ssv6xxx_rc_mac8011_rate_idx(sc, rxdesc->rate_idx, rxs);
+
+ rxs->mactime = *((u32 *) & rx_skb->data[28]);
+ chan = sc->hw->conf.chandef.chan;
+ rxs->band = chan->band;
+ rxs->freq = chan->center_freq;
+ rxs->antenna = 1;
+ is_beacon = ieee80211_is_beacon(hdr->frame_control);
+ is_probe_resp = ieee80211_is_probe_resp(hdr->frame_control);
+ if (is_beacon) //+++
+ {
+ struct ieee80211_mgmt *mgmt_tmp = NULL;
+ mgmt_tmp =
+ (struct ieee80211_mgmt *)(rx_skb->data +
+ SSV6XXX_RX_DESC_LEN);
+ mgmt_tmp->u.beacon.timestamp =
+ cpu_to_le64(ssv6200_get_systime_us());
+ }
+ if (is_probe_resp) {
+ struct ieee80211_mgmt *mgmt_tmp = NULL;
+ mgmt_tmp =
+ (struct ieee80211_mgmt *)(rx_skb->data +
+ SSV6XXX_RX_DESC_LEN);
+ mgmt_tmp->u.probe_resp.timestamp =
+ cpu_to_le64(ssv6200_get_systime_us());
+ }
+
+ if (rxdesc->rate_idx < SSV62XX_G_RATE_INDEX && rxphypad->RSVD == 0) {
+ if (is_beacon || is_probe_resp) {
+ sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+ if (sta) {
+ sta_priv =
+ (struct ssv_sta_priv_data *)sta->drv_priv;
+#ifdef SSV_RSSI_DEBUG
+ dev_dbg(sc->dev, "b_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n",
+ hdr->addr2[0], hdr->addr2[1],
+ hdr->addr2[2], hdr->addr2[3],
+ hdr->addr2[4], hdr->addr2[5],
+ rxphypad->rpci, rxphypad->snr);
+#endif
+ if (sta_priv->beacon_rssi) {
+ sta_priv->beacon_rssi =
+ ((rxphypad->
+ rpci << RSSI_DECIMAL_POINT_SHIFT)
+ +
+ ((sta_priv->
+ beacon_rssi <<
+ RSSI_SMOOTHING_SHIFT) -
+ sta_priv->
+ beacon_rssi)) >>
+ RSSI_SMOOTHING_SHIFT;
+ rxphypad->rpci =
+ (sta_priv->
+ beacon_rssi >>
+ RSSI_DECIMAL_POINT_SHIFT);
+ } else
+ sta_priv->beacon_rssi =
+ (rxphypad->
+ rpci << RSSI_DECIMAL_POINT_SHIFT);
+#ifdef SSV_RSSI_DEBUG
+ dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n", rxphypad->rpci);
+#endif
+ mitigate_cci(sc, rxphypad->rpci);
+ } else {
+ mutex_lock(&sc->mutex);
+ list_for_each_entry(p_rssi_res,
+ &rssi_res.rssi_list,
+ rssi_list) {
+ if (!memcmp
+ (p_rssi_res->bssid, hdr->addr2,
+ ETH_ALEN)) {
+ {
+ p_rssi_res->rssi =
+ ((rxphypad->
+ rpci <<
+ RSSI_DECIMAL_POINT_SHIFT)
+ +
+ ((p_rssi_res->
+ rssi <<
+ RSSI_SMOOTHING_SHIFT)
+ -
+ p_rssi_res->
+ rssi)) >>
+ RSSI_SMOOTHING_SHIFT;
+ rxphypad->rpci =
+ (p_rssi_res->
+ rssi >>
+ RSSI_DECIMAL_POINT_SHIFT);
+ }
+ p_rssi_res->cache_jiffies =
+ jiffies;
+ found = 1;
+ break;
+ } else {
+ if (p_rssi_res->rssi) {
+ if (time_after
+ (jiffies,
+ p_rssi_res->
+ cache_jiffies +
+ msecs_to_jiffies
+ (40000))) {
+ p_rssi_res->
+ timeout = 1;
+ }
+ }
+ }
+ }
+ if (!found) {
+ p_rssi_res =
+ kmalloc(sizeof(struct rssi_res_st),
+ GFP_KERNEL);
+ memcpy(p_rssi_res->bssid, hdr->addr2,
+ ETH_ALEN);
+ p_rssi_res->cache_jiffies = jiffies;
+ p_rssi_res->rssi =
+ (rxphypad->
+ rpci << RSSI_DECIMAL_POINT_SHIFT);
+ p_rssi_res->timeout = 0;
+ INIT_LIST_HEAD(&p_rssi_res->rssi_list);
+ list_add_tail_rcu(&
+ (p_rssi_res->
+ rssi_list),
+ &(rssi_res.
+ rssi_list));
+ }
+ mutex_unlock(&sc->mutex);
+ }
+ if (rxphypad->rpci > 88)
+ rxphypad->rpci = 88;
+ }
+ if (sc->sh->cfg.rssi_ctl) {
+ rxs->signal = (-rxphypad->rpci) + sc->sh->cfg.rssi_ctl;
+ } else {
+ rxs->signal = (-rxphypad->rpci);
+ }
+ } else if (rxdesc->rate_idx >= SSV62XX_G_RATE_INDEX
+ && rxphy->service == 0) {
+ if (is_beacon || is_probe_resp) {
+ sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+ if (sta) {
+ sta_priv =
+ (struct ssv_sta_priv_data *)sta->drv_priv;
+#ifdef SSV_RSSI_DEBUG
+ dev_dbg(sc->dev, "gn_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n",
+ hdr->addr2[0], hdr->addr2[1],
+ hdr->addr2[2], hdr->addr2[3],
+ hdr->addr2[4], hdr->addr2[5], rxphy->rpci,
+ rxphy->snr);
+#endif
+ if (sta_priv->beacon_rssi) {
+ sta_priv->beacon_rssi =
+ ((rxphy->
+ rpci << RSSI_DECIMAL_POINT_SHIFT)
+ +
+ ((sta_priv->
+ beacon_rssi <<
+ RSSI_SMOOTHING_SHIFT) -
+ sta_priv->
+ beacon_rssi)) >>
+ RSSI_SMOOTHING_SHIFT;
+ rxphy->rpci =
+ (sta_priv->
+ beacon_rssi >>
+ RSSI_DECIMAL_POINT_SHIFT);
+ } else
+ sta_priv->beacon_rssi =
+ (rxphy->
+ rpci << RSSI_DECIMAL_POINT_SHIFT);
+#ifdef SSV_RSSI_DEBUG
+ dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n", rxphy->rpci);
+#endif
+ }
+ if (rxphy->rpci > 88)
+ rxphy->rpci = 88;
+ }
+ if (sc->sh->cfg.rssi_ctl) {
+ rxs->signal = (-rxphy->rpci) + sc->sh->cfg.rssi_ctl;
+ } else {
+ rxs->signal = (-rxphy->rpci);
+ }
+ } else {
+#ifdef SSV_RSSI_DEBUG
+ dev_dbg(sc->dev, "########unicast: %d, b_rssi/snr: %d/%d, gn_rssi/snr: %d/%d, rate:%d###############\n",
+ rxdesc->unicast, (-rxphy->rpci), rxphy->snr,
+ (-rxphypad->rpci), rxphypad->snr, rxdesc->rate_idx);
+ dev_dbg(sc->dev, "RSSI, %d, rate_idx, %d\n", rxs->signal,
+ rxdesc->rate_idx);
+ dev_dbg(sc->dev, "rxdesc->RxResult = %x,rxdesc->wsid = %d\n",
+ rxdesc->RxResult, rxdesc->wsid);
+#endif
+ sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+ if (sta) {
+ sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ rxs->signal =
+ -(sta_priv->
+ beacon_rssi >> RSSI_DECIMAL_POINT_SHIFT);
+ }
+#ifdef SSV_RSSI_DEBUG
+ dev_dbg(sc->dev, "Others signal %d\n", rxs->signal);
+#endif
+ }
+// rxs->flag = RX_FLAG_MACTIME_START; //+++
+ rxs->rx_flags = 0;
+ if (rxphy->aggregate)
+ rxs->flag |= RX_FLAG_NO_SIGNAL_VAL;
+ sc->hw_mng_used = rxdesc->mng_used;
+ if ((ieee80211_is_data(fc) || ieee80211_is_data_qos(fc))
+ && ieee80211_has_protected(fc)) {
+ sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+ if (sta == NULL)
+ goto drop_rx;
+ sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ vif = sta_priv->sta_info->vif;
+ if (vif == NULL)
+ goto drop_rx;
+ if (is_broadcast_ether_addr(hdr->addr1) || is_multicast_ether_addr(hdr->addr1)) {
+ vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+ rx_hw_dec = vif_priv->has_hw_decrypt;
+ do_sw_dec = vif_priv->need_sw_decrypt;
+ } else {
+ rx_hw_dec = sta_priv->has_hw_decrypt;
+ do_sw_dec = sta_priv->need_sw_decrypt;
+ }
+ }
+ skb_pull(rx_skb, SSV6XXX_RX_DESC_LEN);
+ skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad);
+#ifdef CONFIG_P2P_NOA
+ if (is_beacon)
+ ssv6xxx_noa_detect(sc, hdr, rx_skb->len);
+#endif
+ if (rx_hw_dec || do_sw_dec) {
+ hdr = (struct ieee80211_hdr *)rx_skb->data;
+ rxs = IEEE80211_SKB_RXCB(rx_skb);
+ hdr->frame_control =
+ hdr->
+ frame_control & ~(cpu_to_le16(IEEE80211_FCTL_PROTECTED));
+ rxs->flag |= (RX_FLAG_DECRYPTED | RX_FLAG_IV_STRIPPED);
+ }
+#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_RX_DATA)
+ local_bh_disable();
+ ieee80211_rx(sc->hw, rx_skb);
+ local_bh_enable();
+#else
+ ieee80211_rx_irqsafe(sc->hw, rx_skb);
+#endif
+ return;
+ drop_rx:
+ dev_kfree_skb_any(rx_skb);
+}
+
+#ifdef IRQ_PROC_RX_DATA
+static struct sk_buff *_proc_rx_skb(struct ssv_softc *sc,
+ struct sk_buff *rx_skb)
+{
+ struct ieee80211_hdr *hdr =
+ (struct ieee80211_hdr *)(rx_skb->data + SSV6XXX_RX_DESC_LEN);
+ struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)rx_skb->data;
+ if (ieee80211_is_back(hdr->frame_control)
+ || (rxdesc->c_type == HOST_EVENT))
+ return rx_skb;
+ _proc_data_rx_skb(sc, rx_skb);
+ return NULL;
+}
+#endif
+void _process_rx_q(struct ssv_softc *sc, struct sk_buff_head *rx_q,
+ spinlock_t * rx_q_lock)
+{
+ struct sk_buff *skb;
+ struct ieee80211_hdr *hdr;
+ struct ssv6200_rx_desc *rxdesc;
+ unsigned long flags = 0;
+#ifdef USE_FLUSH_RETRY
+ bool has_ba_processed = false;
+#endif
+ while (1) {
+ if (rx_q_lock != NULL) {
+ spin_lock_irqsave(rx_q_lock, flags);
+ skb = __skb_dequeue(rx_q);
+ } else
+ skb = skb_dequeue(rx_q);
+ if (!skb) {
+ if (rx_q_lock != NULL)
+ spin_unlock_irqrestore(rx_q_lock, flags);
+ break;
+ }
+ sc->rx.rxq_count--;
+ if (rx_q_lock != NULL)
+ spin_unlock_irqrestore(rx_q_lock, flags);
+ rxdesc = (struct ssv6200_rx_desc *)skb->data;
+ if (rxdesc->c_type == HOST_EVENT) {
+ struct cfg_host_event *h_evt =
+ (struct cfg_host_event *)rxdesc;
+ if (h_evt->h_event == SOC_EVT_NO_BA) {
+ ssv6200_ampdu_no_BA_handler(sc->hw, skb);
+#ifdef USE_FLUSH_RETRY
+ has_ba_processed = true;
+#endif
+ } else if (h_evt->h_event == SOC_EVT_RC_MPDU_REPORT) {
+ skb_queue_tail(&sc->rc_report_queue, skb);
+ if (sc->rc_sample_sechedule == 0)
+ queue_work(sc->rc_sample_workqueue,
+ &sc->rc_sample_work);
+ } else if (h_evt->h_event == SOC_EVT_SDIO_TEST_COMMAND) {
+ if (h_evt->evt_seq_no == 0) {
+ dev_dbg(sc->dev, "SOC_EVT_SDIO_TEST_COMMAND\n");
+ sc->sdio_rx_evt_size = h_evt->len;
+ sc->sdio_throughput_timestamp = jiffies;
+ } else {
+ sc->sdio_rx_evt_size += h_evt->len;
+ if (time_after
+ (jiffies,
+ sc->sdio_throughput_timestamp +
+ msecs_to_jiffies(1000))) {
+ dev_dbg(sc->dev, "data[%ld] SDIO RX throughput %ld Kbps\n",
+ sc->sdio_rx_evt_size,
+ (sc->
+ sdio_rx_evt_size << 3) /
+ jiffies_to_msecs(jiffies -
+ sc->
+ sdio_throughput_timestamp));
+ sc->sdio_throughput_timestamp =
+ jiffies;
+ sc->sdio_rx_evt_size = 0;
+ }
+ }
+ dev_kfree_skb_any(skb);
+ } else if (h_evt->h_event == SOC_EVT_WATCHDOG_TRIGGER) {
+ dev_kfree_skb_any(skb);
+// if(sc->watchdog_flag != WD_SLEEP) //+++
+ sc->watchdog_flag = WD_KICKED;
+ } else if (h_evt->h_event == SOC_EVT_RESET_HOST) {
+ dev_kfree_skb_any(skb);
+ if ((sc->ap_vif == NULL)
+ || !(sc->sh->cfg.ignore_reset_in_ap)) {
+ ssv6xxx_restart_hw(sc);
+ } else {
+ dev_warn(sc->dev,
+ "Reset event ignored.\n");
+ }
+ }
+#ifdef CONFIG_P2P_NOA
+ else if (h_evt->h_event == SOC_EVT_NOA) {
+ ssv6xxx_process_noa_event(sc, skb);
+ dev_kfree_skb_any(skb);
+ }
+#endif
+ else if (h_evt->h_event == SOC_EVT_SDIO_TXTPUT_RESULT) {
+ dev_dbg(sc->dev, "data SDIO TX throughput %d Kbps\n",
+ h_evt->evt_seq_no);
+ dev_kfree_skb_any(skb);
+ } else if (h_evt->h_event == SOC_EVT_TXLOOPBK_RESULT) {
+ if (h_evt->evt_seq_no == SSV6XXX_STATE_OK) {
+ dev_dbg(sc->dev, "FW TX LOOPBACK OK\n");
+ sc->iq_cali_done = IQ_CALI_OK;
+ } else {
+ dev_dbg(sc->dev, "FW TX LOOPBACK FAILED\n");
+ sc->iq_cali_done = IQ_CALI_FAILED;
+ }
+ dev_kfree_skb_any(skb);
+ wake_up_interruptible(&sc->fw_wait_q);
+ } else {
+ dev_warn(sc->dev, "Unkown event %d received\n",
+ h_evt->h_event);
+ dev_kfree_skb_any(skb);
+ }
+ continue;
+ }
+ hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_RX_DESC_LEN);
+ if (ieee80211_is_back(hdr->frame_control)) {
+ ssv6200_ampdu_BA_handler(sc->hw, skb);
+#ifdef USE_FLUSH_RETRY
+ has_ba_processed = true;
+#endif
+ continue;
+ }
+ _proc_data_rx_skb(sc, skb);
+ }
+#ifdef USE_FLUSH_RETRY
+ if (has_ba_processed) {
+ ssv6xxx_ampdu_postprocess_BA(sc->hw);
+ }
+#endif
+}
+
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args)
+#else
+int ssv6200_rx(struct sk_buff *rx_skb, void *args)
+#endif
+{
+ struct ssv_softc *sc = args;
+#ifdef IRQ_PROC_RX_DATA
+ struct sk_buff *skb;
+ skb = _proc_rx_skb(sc, rx_skb);
+ if (skb == NULL)
+ return 0;
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+ {
+ unsigned long flags;
+ spin_lock_irqsave(&sc->rx_skb_q.lock, flags);
+ while (skb_queue_len(rx_skb_q))
+ __skb_queue_tail(&sc->rx_skb_q,
+ __skb_dequeue(rx_skb_q));
+ spin_unlock_irqrestore(&sc->rx_skb_q.lock, flags);
+ }
+#else
+ skb_queue_tail(&sc->rx_skb_q, rx_skb);
+#endif
+ wake_up_interruptible(&sc->rx_wait_q);
+ return 0;
+}
+
+struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb(struct ssv_softc *sc,
+ struct sk_buff *skb)
+{
+ struct ieee80211_hdr *hdr =
+ (struct ieee80211_hdr *)(skb->data + SSV6XXX_RX_DESC_LEN);
+ struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)skb->data;;
+ if ((rxdesc->wsid >= 0) && (rxdesc->wsid < SSV_NUM_STA))
+ return sc->sta_info[rxdesc->wsid].sta;
+ else
+ return ssv6xxx_find_sta_by_addr(sc, hdr->addr2);
+}
+
+struct ieee80211_sta *ssv6xxx_find_sta_by_addr(struct ssv_softc *sc, u8 addr[6])
+{
+ struct ieee80211_sta *sta;
+ int i;
+ for (i = 0; i < SSV6200_MAX_VIF; i++) {
+ if (sc->vif_info[i].vif == NULL)
+ continue;
+ sta = ieee80211_find_sta(sc->vif_info[i].vif, addr);
+ if (sta != NULL)
+ return sta;
+ }
+ return NULL;
+}
+
+void ssv6xxx_foreach_sta(struct ssv_softc *sc,
+ void (*sta_func)(struct ssv_softc *,
+ struct ssv_sta_info *, void *),
+ void *param)
+{
+ int i;
+ BUG_ON(sta_func == NULL);
+ for (i = 0; i < SSV_NUM_STA; i++) {
+ if ((sc->sta_info[i].s_flags & STA_FLAG_VALID) == 0)
+ continue;
+ (*sta_func) (sc, &sc->sta_info[i], param);
+ }
+}
+
+void ssv6xxx_foreach_vif_sta(struct ssv_softc *sc,
+ struct ssv_vif_info *vif_info,
+ void (*sta_func)(struct ssv_softc *,
+ struct ssv_vif_info *,
+ struct ssv_sta_info *,
+ void *), void *param)
+{
+ struct ssv_vif_priv_data *vif_priv;
+ struct ssv_sta_priv_data *sta_priv_iter;
+ BUG_ON(vif_info == NULL);
+ BUG_ON((size_t)vif_info < 0x30000);
+ vif_priv = (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+ BUG_ON((size_t)vif_info->vif < 0x30000);
+ BUG_ON((size_t)vif_priv < 0x30000);
+ list_for_each_entry(sta_priv_iter, &vif_priv->sta_list, list) {
+ BUG_ON(sta_priv_iter == NULL);
+ BUG_ON((size_t)sta_priv_iter < 0x30000);
+ BUG_ON(sta_priv_iter->sta_info == NULL);
+ BUG_ON((size_t)sta_priv_iter->sta_info < 0x30000);
+ if ((sta_priv_iter->sta_info->s_flags & STA_FLAG_VALID) == 0)
+ continue;
+ (*sta_func) (sc, vif_info, sta_priv_iter->sta_info, param);
+ }
+}
+
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ssize_t ssv6xxx_tx_queue_status_dump(struct ssv_softc *sc, char *status_buf,
+ ssize_t length)
+{
+ ssize_t buf_size = length;
+ ssize_t prt_size;
+ prt_size =
+ snprintf(status_buf, buf_size, "\nSMAC driver queue status:.\n");
+ status_buf += prt_size;
+ buf_size -= prt_size;
+ prt_size = snprintf(status_buf, buf_size, "\tTX queue: %d\n",
+ skb_queue_len(&sc->tx_skb_q));
+ status_buf += prt_size;
+ buf_size -= prt_size;
+ prt_size = snprintf(status_buf, buf_size, "\tMax TX queue: %d\n",
+ sc->max_tx_skb_q_len);
+ status_buf += prt_size;
+ buf_size -= prt_size;
+ return (length - buf_size);
+}
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/dev.h b/drivers/net/wireless/ssv6051/smac/dev.h
new file mode 100644
index 000000000000..0a6357624b1c
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/dev.h
@@ -0,0 +1,445 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DEV_H_
+#define _DEV_H_
+#include <linux/version.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <net/mac80211.h>
+#include "ampdu.h"
+#include "ssv_rc_common.h"
+#include "drv_comm.h"
+#include "sec.h"
+#include "p2p.h"
+#include <linux/kthread.h>
+#define SSV6200_MAX_HW_MAC_ADDR 2
+#define SSV6200_MAX_VIF 2
+#define SSV6200_RX_BA_MAX_SESSIONS 1
+#define SSV6200_OPMODE_STA 0
+#define SSV6200_OPMODE_AP 1
+#define SSV6200_OPMODE_IBSS 2
+#define SSV6200_OPMODE_WDS 3
+#define SSV6200_USE_HW_WSID(_sta_idx) ((_sta_idx == 0) || (_sta_idx == 1))
+#define HW_MAX_RATE_TRIES 7
+#define MAC_DECITBL1_SIZE 16
+#define MAC_DECITBL2_SIZE 9
+#define RX_11B_CCA_IN_SCAN 0x20230050
+//#define WATCHDOG_TIMEOUT (10*HZ)
+#define WATCHDOG_TIMEOUT (99999*HZ)
+extern u16 generic_deci_tbl[];
+#define ap_deci_tbl generic_deci_tbl
+#define sta_deci_tbl generic_deci_tbl
+#define HT_SIGNAL_EXT 6
+#define HT_SIFS_TIME 10
+#define BITS_PER_BYTE 8
+#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
+#define ACK_LEN (14)
+#define BA_LEN (32)
+#define RTS_LEN (20)
+#define CTS_LEN (14)
+#define L_STF 8
+#define L_LTF 8
+#define L_SIG 4
+#define HT_SIG 8
+#define HT_STF 4
+#define HT_LTF(_ns) (4 * (_ns))
+#define SYMBOL_TIME(_ns) ((_ns) << 2)
+#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5)
+#define CCK_SIFS_TIME 10
+#define CCK_PREAMBLE_BITS 144
+#define CCK_PLCP_BITS 48
+#define OFDM_SIFS_TIME 16
+#define OFDM_PREAMBLE_TIME 20
+#define OFDM_PLCP_BITS 22
+#define OFDM_SYMBOL_TIME 4
+#define WMM_AC_VO 0
+#define WMM_AC_VI 1
+#define WMM_AC_BE 2
+#define WMM_AC_BK 3
+#define WMM_NUM_AC 4
+#define WMM_TID_NUM 8
+#define TXQ_EDCA_0 0x01
+#define TXQ_EDCA_1 0x02
+#define TXQ_EDCA_2 0x04
+#define TXQ_EDCA_3 0x08
+#define TXQ_MGMT 0x10
+#define IS_SSV_HT(dsc) ((dsc)->rate_idx >= 15)
+#define IS_SSV_SHORT_GI(dsc) ((dsc)->rate_idx>=23 && (dsc)->rate_idx<=30)
+#define IS_SSV_HT_GF(dsc) ((dsc)->rate_idx >= 31)
+#define IS_SSV_SHORT_PRE(dsc) ((dsc)->rate_idx>=4 && (dsc)->rate_idx<=14)
+#define SMAC_REG_WRITE(_s,_r,_v) \
+ (_s)->hci.hci_ops->hci_write_word(_r,_v)
+#define SMAC_REG_READ(_s,_r,_v) \
+ (_s)->hci.hci_ops->hci_read_word(_r, _v)
+#define SMAC_LOAD_FW(_s,_r,_v) \
+ (_s)->hci.hci_ops->hci_load_fw(_r, _v)
+#define SMAC_IFC_RESET(_s) (_s)->hci.hci_ops->hci_interface_reset()
+#define SMAC_REG_CONFIRM(_s,_r,_v) \
+{ \
+ u32 _regval; \
+ SMAC_REG_READ(_s, _r, &_regval); \
+ if (_regval != (_v)) { \
+ printk("ERROR!!Please check interface!\n"); \
+ printk("[0x%08x]: 0x%08x!=0x%08x\n", \
+ (_r), (_v), _regval); \
+ printk("SOS!SOS!\n"); \
+ return -1; \
+ } \
+}
+#define SMAC_REG_SET_BITS(_sh,_reg,_set,_clr) \
+({ \
+ int ret; \
+ u32 _regval; \
+ ret = SMAC_REG_READ(_sh, _reg, &_regval); \
+ _regval &= ~(_clr); \
+ _regval |= (_set); \
+ if (ret == 0) \
+ ret = SMAC_REG_WRITE(_sh, _reg, _regval); \
+ ret; \
+})
+#define HCI_START(_sh) \
+ (_sh)->hci.hci_ops->hci_start()
+#define HCI_STOP(_sh) \
+ (_sh)->hci.hci_ops->hci_stop()
+#define HCI_SEND(_sh,_sk,_q) \
+ (_sh)->hci.hci_ops->hci_tx(_sk, _q, 0)
+#define HCI_PAUSE(_sh,_mk) \
+ (_sh)->hci.hci_ops->hci_tx_pause(_mk)
+#define HCI_RESUME(_sh,_mk) \
+ (_sh)->hci.hci_ops->hci_tx_resume(_mk)
+#define HCI_TXQ_FLUSH(_sh,_mk) \
+ (_sh)->hci.hci_ops->hci_txq_flush(_mk)
+#define HCI_TXQ_FLUSH_BY_STA(_sh,_aid) \
+ (_sh)->hci.hci_ops->hci_txq_flush_by_sta(_aid)
+#define HCI_TXQ_EMPTY(_sh,_txqid) \
+ (_sh)->hci.hci_ops->hci_txq_empty(_txqid)
+#define HCI_WAKEUP_PMU(_sh) \
+ (_sh)->hci.hci_ops->hci_pmu_wakeup()
+#define HCI_SEND_CMD(_sh,_sk) \
+ (_sh)->hci.hci_ops->hci_send_cmd(_sk)
+#define SSV6XXX_SET_HW_TABLE(sh_,tbl_) \
+({ \
+ int ret = 0; \
+ u32 i=0; \
+ for(; i<sizeof(tbl_)/sizeof(struct ssv6xxx_dev_table); i++) { \
+ ret = SMAC_REG_WRITE(sh_, tbl_[i].address, tbl_[i].data); \
+ if (ret) break; \
+ } \
+ ret; \
+})
+#define SSV6XXX_USE_HW_DECRYPT(_priv) (_priv->has_hw_decrypt)
+#define SSV6XXX_USE_SW_DECRYPT(_priv) (SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) || SSV6XXX_USE_MAC80211_DECRYPT(_priv))
+#define SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) (_priv->need_sw_decrypt)
+#define SSV6XXX_USE_MAC80211_DECRYPT(_priv) (_priv->use_mac80211_decrypt)
+struct ssv_softc;
+#ifdef CONFIG_P2P_NOA
+struct ssv_p2p_noa;
+#endif
+#define SSV6200_HT_TX_STREAMS 1
+#define SSV6200_HT_RX_STREAMS 1
+#define SSV6200_RX_HIGHEST_RATE 72
+enum PWRSV_STATUS {
+ PWRSV_DISABLE,
+ PWRSV_ENABLE,
+ PWRSV_PREPARE,
+};
+struct rssi_res_st {
+ struct list_head rssi_list;
+ unsigned long cache_jiffies;
+ s32 rssi;
+ s32 timeout;
+ u8 bssid[ETH_ALEN];
+};
+struct ssv_hw {
+ struct ssv_softc *sc;
+ struct ssv6xxx_platform_data *priv;
+ struct ssv6xxx_hci_info hci;
+ char chip_id[24];
+ u64 chip_tag;
+ u32 tx_desc_len;
+ u32 rx_desc_len;
+ u32 rx_pinfo_pad;
+ u32 tx_page_available;
+ u32 ampdu_divider;
+ u8 page_count[SSV6200_ID_NUMBER];
+ u32 hw_buf_ptr[SSV_RC_MAX_STA];
+ u32 hw_sec_key[SSV_RC_MAX_STA];
+ u32 hw_pinfo;
+ struct ssv6xxx_cfg cfg;
+ u32 n_addresses;
+ struct mac_address maddr[SSV6200_MAX_HW_MAC_ADDR];
+ u8 ipd_channel_touch;
+ struct ssv6xxx_ch_cfg *p_ch_cfg;
+ u32 ch_cfg_size;
+};
+struct ssv_tx {
+ u16 seq_no;
+ int hw_txqid[WMM_NUM_AC];
+ int ac_txqid[WMM_NUM_AC];
+ u32 flow_ctrl_status;
+ u32 tx_pkt[SSV_HW_TXQ_NUM];
+ u32 tx_frag[SSV_HW_TXQ_NUM];
+ struct list_head ampdu_tx_que;
+ spinlock_t ampdu_tx_que_lock;
+ u16 ampdu_tx_group_id;
+};
+struct ssv_rx {
+ struct sk_buff *rx_buf;
+ spinlock_t rxq_lock;
+ struct sk_buff_head rxq_head;
+ u32 rxq_count;
+};
+#define SSV6XXX_GET_STA_INFO(_sc,_s) \
+ &(_sc)->sta_info[((struct ssv_sta_priv_data *)((_s)->drv_priv))->sta_idx]
+#define STA_FLAG_VALID 0x00001
+#define STA_FLAG_QOS 0x00002
+#define STA_FLAG_AMPDU 0x00004
+#define STA_FLAG_ENCRYPT 0x00008
+struct ssv_sta_info {
+ u16 aid;
+ u16 s_flags;
+ int hw_wsid;
+ struct ieee80211_sta *sta;
+ struct ieee80211_vif *vif;
+ bool sleeping;
+ bool tim_set;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct dentry *debugfs_dir;
+#endif
+};
+struct ssv_vif_info {
+ struct ieee80211_vif *vif;
+ struct ssv_vif_priv_data *vif_priv;
+ enum nl80211_iftype if_type;
+ struct ssv6xxx_hw_sec sramKey;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct dentry *debugfs_dir;
+#endif
+};
+struct ssv_sta_priv_data {
+ int sta_idx;
+ int rc_idx;
+ int rx_data_rate;
+ struct ssv_sta_info *sta_info;
+ struct list_head list;
+ u32 ampdu_mib_total_BA_counter;
+ AMPDU_TID ampdu_tid[WMM_TID_NUM];
+ bool has_hw_encrypt;
+ bool need_sw_encrypt;
+ bool has_hw_decrypt;
+ bool need_sw_decrypt;
+ bool use_mac80211_decrypt;
+ u8 group_key_idx;
+ u32 beacon_rssi;
+};
+struct ssv_vif_priv_data {
+ int vif_idx;
+ struct list_head sta_list;
+ u32 sta_asleep_mask;
+ u32 pair_cipher;
+ u32 group_cipher;
+ bool is_security_valid;
+ bool has_hw_encrypt;
+ bool need_sw_encrypt;
+ bool has_hw_decrypt;
+ bool need_sw_decrypt;
+ bool use_mac80211_decrypt;
+ bool force_sw_encrypt;
+ u8 group_key_idx;
+};
+#define SC_OP_INVALID 0x00000001
+#define SC_OP_HW_RESET 0x00000002
+#define SC_OP_OFFCHAN 0x00000004
+#define SC_OP_FIXED_RATE 0x00000008
+#define SC_OP_SHORT_PREAMBLE 0x00000010
+struct ssv6xxx_beacon_info {
+ u32 pubf_addr;
+ u16 len;
+ u8 tim_offset;
+ u8 tim_cnt;
+};
+#define SSV6200_MAX_BCAST_QUEUE_LEN 16
+struct ssv6xxx_bcast_txq {
+ spinlock_t txq_lock;
+ struct sk_buff_head qhead;
+ int cur_qsize;
+};
+#ifdef DEBUG_AMPDU_FLUSH
+typedef struct AMPDU_TID_st AMPDU_TID;
+#define MAX_TID (24)
+#endif
+struct ssv_softc {
+ struct ieee80211_hw *hw;
+ struct device *dev;
+ u32 restart_counter;
+ bool force_triger_reset;
+ unsigned long sdio_throughput_timestamp;
+ unsigned long sdio_rx_evt_size;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
+ struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
+#else
+ struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
+#endif
+ struct ieee80211_channel *cur_channel;
+ u16 hw_chan;
+ struct mutex mutex;
+ struct ssv_hw *sh;
+ struct ssv_tx tx;
+ struct ssv_rx rx;
+ struct ssv_vif_info vif_info[SSV_NUM_VIF];
+ struct ssv_sta_info sta_info[SSV_NUM_STA];
+ struct ieee80211_vif *ap_vif;
+ u8 nvif;
+ u32 sc_flags;
+ void *rc;
+ int max_rate_idx;
+ struct workqueue_struct *rc_sample_workqueue;
+ struct sk_buff_head rc_report_queue;
+ struct work_struct rc_sample_work;
+#ifdef DEBUG_AMPDU_FLUSH
+ struct AMPDU_TID_st *tid[MAX_TID];
+#endif
+ u16 rc_sample_sechedule;
+ u16 *mac_deci_tbl;
+ struct workqueue_struct *config_wq;
+ bool bq4_dtim;
+ struct work_struct set_tim_work;
+ u8 enable_beacon;
+ u8 beacon_interval;
+ u8 beacon_dtim_cnt;
+ u8 beacon_usage;
+ struct ssv6xxx_beacon_info beacon_info[2];
+ struct sk_buff *beacon_buf;
+ struct work_struct bcast_start_work;
+ struct delayed_work bcast_stop_work;
+ struct delayed_work bcast_tx_work;
+ struct delayed_work thermal_monitor_work;
+ struct workqueue_struct *thermal_wq;
+ int is_sar_enabled;
+ bool aid0_bit_set;
+ u8 hw_mng_used;
+ struct ssv6xxx_bcast_txq bcast_txq;
+ int bcast_interval;
+ u8 bssid[6];
+ struct mutex mem_mutex;
+ spinlock_t ps_state_lock;
+ u8 hw_wsid_bit;
+ int rx_ba_session_count;
+ struct ieee80211_sta *rx_ba_sta;
+ u8 rx_ba_bitmap;
+ u8 ba_ra_addr[ETH_ALEN];
+ u16 ba_tid;
+ u16 ba_ssn;
+ struct work_struct set_ampdu_rx_add_work;
+ struct work_struct set_ampdu_rx_del_work;
+ bool isAssoc;
+ u16 channel_center_freq;
+ bool bScanning;
+ int ps_status;
+ u16 ps_aid;
+ u16 tx_wait_q_woken;
+ wait_queue_head_t tx_wait_q;
+ struct sk_buff_head tx_skb_q;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ u32 max_tx_skb_q_len;
+#endif
+ struct task_struct *tx_task;
+ bool tx_q_empty;
+ struct sk_buff_head tx_done_q;
+ u16 rx_wait_q_woken;
+ wait_queue_head_t rx_wait_q;
+ struct sk_buff_head rx_skb_q;
+ struct task_struct *rx_task;
+ bool dbg_rx_frame;
+ bool dbg_tx_frame;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct dentry *debugfs_dir;
+#endif
+#ifdef CONFIG_P2P_NOA
+ struct ssv_p2p_noa p2p_noa;
+#endif
+ struct timer_list watchdog_timeout;
+ u32 watchdog_flag;
+ wait_queue_head_t fw_wait_q;
+ u32 iq_cali_done;
+ u32 sr_bhvr;
+};
+enum {
+ IQ_CALI_RUNNING,
+ IQ_CALI_OK,
+ IQ_CALI_FAILED
+};
+enum {
+ WD_SLEEP,
+ WD_BARKING,
+ WD_KICKED,
+ WD_MAX
+};
+void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args);
+void ssv6200_rx_process(struct work_struct *work);
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args);
+#else
+int ssv6200_rx(struct sk_buff *rx_skb, void *args);
+#endif
+void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args);
+void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args);
+int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug);
+void ssv6xxx_tx_q_empty_cb(u32 txq_no, void *);
+int ssv6xxx_rf_disable(struct ssv_hw *sh);
+int ssv6xxx_rf_enable(struct ssv_hw *sh);
+int ssv6xxx_set_channel(struct ssv_softc *sc, int ch);
+#ifdef CONFIG_SSV_SMARTLINK
+int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch);
+int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept);
+int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept);
+#endif
+int ssv6xxx_tx_task(void *data);
+int ssv6xxx_rx_task(void *data);
+u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type);
+bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr);
+void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb);
+void ssv6xxx_update_txinfo(struct ssv_softc *sc, struct sk_buff *skb);
+int ssv6xxx_update_decision_table(struct ssv_softc *sc);
+void ssv6xxx_ps_callback_func(unsigned long data);
+void ssv6xxx_enable_ps(struct ssv_softc *sc);
+void ssv6xxx_disable_ps(struct ssv_softc *sc);
+int ssv6xxx_watchdog_controller(struct ssv_hw *sh, u8 flag);
+int ssv6xxx_skb_encrypt(struct sk_buff *mpdu, struct ssv_softc *sc);
+int ssv6xxx_skb_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta,
+ struct ssv_softc *sc);
+void ssv6200_sync_hw_key_sequence(struct ssv_softc *sc,
+ struct ssv_sta_info *sta_info, bool bWrite);
+struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb(struct ssv_softc *sc,
+ struct sk_buff *skb);
+struct ieee80211_sta *ssv6xxx_find_sta_by_addr(struct ssv_softc *sc,
+ u8 addr[6]);
+void ssv6xxx_foreach_sta(struct ssv_softc *sc,
+ void (*sta_func)(struct ssv_softc *,
+ struct ssv_sta_info *, void *),
+ void *param);
+void ssv6xxx_foreach_vif_sta(struct ssv_softc *sc,
+ struct ssv_vif_info *vif_info,
+ void (*sta_func)(struct ssv_softc *,
+ struct ssv_vif_info *,
+ struct ssv_sta_info *, void *),
+ void *param);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ssize_t ssv6xxx_tx_queue_status_dump(struct ssv_softc *sc, char *status_buf,
+ ssize_t buf_size);
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/dev_tbl.h b/drivers/net/wireless/ssv6051/smac/dev_tbl.h
new file mode 100644
index 000000000000..5c49d0bde6a6
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/dev_tbl.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DEV_TBL_H_
+#define _DEV_TBL_H_
+#include "ssv6200_configuration.h"
+#include "drv_comm.h"
+struct ssv6xxx_dev_table {
+ u32 address;
+ u32 data;
+};
+#define ssv6200_phy_tbl phy_setting
+#define ssv6200_rf_tbl asic_rf_setting
+#define ACTION_DO_NOTHING 0
+#define ACTION_UPDATE_NAV 1
+#define ACTION_RESET_NAV 2
+#define ACTION_SIGNAL_ACK 3
+#define FRAME_ACCEPT 0
+#define FRAME_DROP 1
+#define SET_DEC_TBL(_type,_mask,_action,_drop) \
+ (_type<<9| \
+ _mask <<3| \
+ _action<<1| \
+ _drop)
+u16 generic_deci_tbl[] = {
+ SET_DEC_TBL(0x1e, 0x3e, ACTION_RESET_NAV, FRAME_DROP),
+ SET_DEC_TBL(0x18, 0x3e, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+ SET_DEC_TBL(0x1a, 0x3f, ACTION_DO_NOTHING, FRAME_ACCEPT),
+ SET_DEC_TBL(0x10, 0x38, ACTION_DO_NOTHING, FRAME_DROP),
+ 0,
+ 0,
+ 0,
+ SET_DEC_TBL(0x05, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+ SET_DEC_TBL(0x0b, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+ SET_DEC_TBL(0x01, 0x3d, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+ SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_ACCEPT),
+ SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+ SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_DROP),
+ SET_DEC_TBL(0x00, 0x00, ACTION_UPDATE_NAV, FRAME_DROP),
+ SET_DEC_TBL(0x00, 0x00, ACTION_RESET_NAV, FRAME_DROP),
+ SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_DROP),
+ 0x2008,
+ 0x1001,
+ 0x0400,
+ 0x0400,
+ 0x2000,
+ 0x800E,
+ 0x0800,
+ 0x0B88,
+ 0x0800,
+};
+
+#define SET_PHY_INFO(_ctsdur,_ba_rate_idx,_ack_rate_idx,_llength_idx,_llength_enable) \
+ (_ctsdur<<16| \
+ _ba_rate_idx <<10| \
+ _ack_rate_idx<<4| \
+ _llength_idx<<1| \
+ _llength_enable)
+#define SET_PHY_L_LENGTH(_l_ba,_l_rts,_l_cts_ack) (_l_ba<<12|_l_rts<<6 |_l_cts_ack)
+static u32 phy_info_6051z[] = {
+ 0x18000000, 0x18000100, 0x18000200, 0x18000300, 0x18000140,
+ 0x18000240, 0x18000340, 0x0C000001, 0x0C000101, 0x0C000201,
+ 0x0C000301, 0x18000401, 0x18000501, 0x18000601, 0x18000701,
+ 0x0C030002, 0x0C030102, 0x0C030202, 0x18030302, 0x18030402,
+ 0x18030502, 0x18030602, 0x1C030702, 0x0C030082, 0x0C030182,
+ 0x0C030282, 0x18030382, 0x18030482, 0x18030582, 0x18030682,
+ 0x1C030782, 0x0C030042, 0x0C030142, 0x0C030242, 0x18030342,
+ 0x18030442, 0x18030542, 0x18030642, 0x1C030742
+};
+
+static u32 phy_info_tbl[] = {
+ 0x0C000000, 0x0C000100, 0x0C000200, 0x0C000300, 0x0C000140,
+ 0x0C000240, 0x0C000340, 0x00000001, 0x00000101, 0x00000201,
+ 0x00000301, 0x0C000401, 0x0C000501, 0x0C000601, 0x0C000701,
+ 0x00030002, 0x00030102, 0x00030202, 0x0C030302, 0x0C030402,
+ 0x0C030502, 0x0C030602, 0x10030702, 0x00030082, 0x00030182,
+ 0x00030282, 0x0C030382, 0x0C030482, 0x0C030582, 0x0C030682,
+ 0x10030782, 0x00030042, 0x00030142, 0x00030242, 0x0C030342,
+ 0x0C030442, 0x0C030542, 0x0C030642, 0x10030742,
+ SET_PHY_INFO(314, 0, 0, 0, 0),
+ SET_PHY_INFO(258, 0, 1, 0, 0),
+ SET_PHY_INFO(223, 0, 1, 0, 0),
+ SET_PHY_INFO(213, 0, 1, 0, 0),
+ SET_PHY_INFO(162, 0, 4, 0, 0),
+ SET_PHY_INFO(127, 0, 4, 0, 0),
+ SET_PHY_INFO(117, 0, 4, 0, 0),
+ SET_PHY_INFO(60, 7, 7, 0, 0),
+ SET_PHY_INFO(52, 7, 7, 0, 0),
+ SET_PHY_INFO(48, 9, 9, 0, 0),
+ SET_PHY_INFO(44, 9, 9, 0, 0),
+ SET_PHY_INFO(44, 11, 11, 0, 0),
+ SET_PHY_INFO(40, 11, 11, 0, 0),
+ SET_PHY_INFO(40, 11, 11, 0, 0),
+ SET_PHY_INFO(40, 11, 11, 0, 0),
+ SET_PHY_INFO(76, 7, 7, 0, 1),
+ SET_PHY_INFO(64, 9, 9, 1, 1),
+ SET_PHY_INFO(60, 9, 9, 2, 1),
+ SET_PHY_INFO(60, 11, 11, 3, 1),
+ SET_PHY_INFO(56, 11, 11, 4, 1),
+ SET_PHY_INFO(56, 11, 11, 5, 1),
+ SET_PHY_INFO(56, 11, 11, 5, 1),
+ SET_PHY_INFO(56, 11, 11, 5, 1),
+ SET_PHY_INFO(76, 7, 7, 6, 1),
+ SET_PHY_INFO(64, 9, 9, 1, 1),
+ SET_PHY_INFO(60, 9, 9, 2, 1),
+ SET_PHY_INFO(60, 11, 11, 3, 1),
+ SET_PHY_INFO(56, 11, 11, 4, 1),
+ SET_PHY_INFO(56, 11, 11, 5, 1),
+ SET_PHY_INFO(56, 11, 11, 5, 1),
+ SET_PHY_INFO(56, 11, 11, 5, 1),
+ SET_PHY_INFO(64, 7, 7, 0, 0),
+ SET_PHY_INFO(52, 9, 9, 0, 0),
+ SET_PHY_INFO(48, 9, 9, 0, 0),
+ SET_PHY_INFO(48, 11, 11, 0, 0),
+ SET_PHY_INFO(44, 11, 11, 0, 0),
+ SET_PHY_INFO(44, 11, 11, 0, 0),
+ SET_PHY_INFO(44, 11, 11, 0, 0),
+ SET_PHY_INFO(44, 11, 11, 0, 0),
+ SET_PHY_L_LENGTH(50, 38, 35),
+ SET_PHY_L_LENGTH(35, 29, 26),
+ SET_PHY_L_LENGTH(29, 26, 23),
+ SET_PHY_L_LENGTH(26, 23, 23),
+ SET_PHY_L_LENGTH(23, 23, 20),
+ SET_PHY_L_LENGTH(23, 20, 20),
+ SET_PHY_L_LENGTH(47, 38, 35),
+ SET_PHY_L_LENGTH(0, 0, 0),
+};
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/drv_comm.h b/drivers/net/wireless/ssv6051/smac/drv_comm.h
new file mode 100644
index 000000000000..f04fbae004c3
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/drv_comm.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DRV_COMM_H_
+#define _DRV_COMM_H_
+#define PHY_INFO_TBL1_SIZE 39
+#define PHY_INFO_TBL2_SIZE 39
+#define PHY_INFO_TBL3_SIZE 8
+#define ampdu_fw_rate_info_status_no_use BIT(0)
+#define ampdu_fw_rate_info_status_in_use BIT(1)
+#define ampdu_fw_rate_info_status_reset BIT(2)
+#define SSV_NUM_STA 8
+#define SSV_NUM_VIF 2
+#define SECURITY_KEY_LEN (32)
+enum SSV_CIPHER_E {
+ SSV_CIPHER_NONE,
+ SSV_CIPHER_WEP40,
+ SSV_CIPHER_WEP104,
+ SSV_CIPHER_TKIP,
+ SSV_CIPHER_CCMP,
+ SSV_CIPHER_SMS4,
+ SSV_CIPHER_INVALID = (-1)
+};
+#define ME_NONE 0
+#define ME_WEP40 1
+#define ME_WEP104 2
+#define ME_TKIP 3
+#define ME_CCMP 4
+#define ME_SMS4 5
+struct ssv6xxx_hw_key {
+ u8 key[SECURITY_KEY_LEN];
+ u32 tx_pn_l;
+ u32 tx_pn_h;
+ u32 rx_pn_l;
+ u32 rx_pn_h;
+} __attribute__((packed));
+struct ssv6xxx_hw_sta_key {
+ u8 pair_key_idx:4;
+ u8 group_key_idx:4;
+ u8 valid;
+ u8 reserve[2];
+ struct ssv6xxx_hw_key pair;
+} __attribute__((packed));
+struct ssv6xxx_hw_sec {
+ struct ssv6xxx_hw_key group_key[3];
+ struct ssv6xxx_hw_sta_key sta_key[8];
+} __attribute__((packed));
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/efuse.c b/drivers/net/wireless/ssv6051/smac/efuse.c
new file mode 100644
index 000000000000..9a1f3f5488f2
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/efuse.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/etherdevice.h>
+#include <ssv6200.h>
+#include "efuse.h"
+
+struct file *openFile(char *path, int flag, int mode)
+{
+ struct file *fp = NULL;
+ fp = filp_open(path, flag, 0);
+ if (IS_ERR(fp))
+ return NULL;
+ else
+ return fp;
+}
+
+int readFile(struct file *fp, char *buf, int readlen)
+{
+ if (fp->f_op && fp->f_op->read)
+ return fp->f_op->read(fp, buf, readlen, &fp->f_pos);
+ else
+ return -1;
+}
+
+int closeFile(struct file *fp)
+{
+ filp_close(fp, NULL);
+ return 0;
+}
+
+void initKernelEnv(void)
+{
+}
+
+void parseMac(char *mac, u_int8_t addr[])
+{
+ long b;
+ int i;
+ for (i = 0; i < 6; i++) {
+ b = simple_strtol(mac + (3 * i), (char **)NULL, 16);
+ addr[i] = (char)b;
+ }
+}
+
+static int readfile_mac(u8 * path, u8 * mac_addr)
+{
+ char buf[128];
+ struct file *fp = NULL;
+ int ret = 0;
+ fp = openFile(path, O_RDONLY, 0);
+ if (fp != NULL) {
+ initKernelEnv();
+ memset(buf, 0, 128);
+ if ((ret = readFile(fp, buf, 128)) > 0) {
+ parseMac(buf, (uint8_t *) mac_addr);
+ } else
+ pr_err("read file error %d=[%s]\n", ret, path);
+ closeFile(fp);
+ } else
+ pr_err("Read open File fail[%s]!!!! \n", path);
+ return ret;
+}
+
+static int write_mac_to_file(u8 * mac_path, u8 * mac_addr)
+{
+ char buf[128];
+ struct file *fp = NULL;
+ int ret = 0, len;
+ fp = openFile(mac_path, O_WRONLY | O_CREAT, 0640);
+ if (fp != NULL) {
+ initKernelEnv();
+ memset(buf, 0, 128);
+ sprintf(buf, "%x:%x:%x:%x:%x:%x", mac_addr[0], mac_addr[1],
+ mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
+ len = strlen(buf) + 1;
+ fp->f_op->write(fp, (char *)buf, len, &fp->f_pos);
+ closeFile(fp);
+ } else
+ pr_err("Write open File fail!!!![%s] \n", mac_path);
+ return ret;
+}
+
+static struct efuse_map SSV_EFUSE_ITEM_TABLE[] = {
+ {4, 0, 0},
+ {4, 8, 0},
+ {4, 8, 0},
+ {4, 48, 0},
+ {4, 8, 0},
+ {4, 8, 0},
+ {4, 8, 0},
+};
+
+static u8 read_efuse(struct ssv_hw *sh, u8 * pbuf)
+{
+ extern struct ssv6xxx_cfg ssv_cfg;
+ u32 val, i;
+ u32 *temp = (u32 *) pbuf;
+ SMAC_REG_WRITE(sh, 0xC0000328, 0x11);
+ SMAC_REG_WRITE(sh, SSV_EFUSE_ID_READ_SWITCH, 0x1);
+ SMAC_REG_READ(sh, SSV_EFUSE_ID_RAW_DATA_BASE, &val);
+ ssv_cfg.chip_identity = val;
+ SMAC_REG_WRITE(sh, SSV_EFUSE_READ_SWITCH, 0x1);
+ SMAC_REG_READ(sh, SSV_EFUSE_RAW_DATA_BASE, &val);
+ if (val == 0x00) {
+ return 0;
+ }
+ for (i = 0; i < (EFUSE_MAX_SECTION_MAP); i++) {
+ SMAC_REG_WRITE(sh, SSV_EFUSE_READ_SWITCH + i * 4, 0x1);
+ SMAC_REG_READ(sh, SSV_EFUSE_RAW_DATA_BASE + i * 4, &val);
+ *temp++ = val;
+ }
+ SMAC_REG_WRITE(sh, 0xC0000328, 0x1800000a);
+ return 1;
+}
+
+static u16 parser_efuse(u8 * pbuf, u8 * mac_addr)
+{
+ u8 *rtemp8, idx = 0;
+ u16 shift = 0, i;
+ u16 efuse_real_content_len = 0;
+ rtemp8 = pbuf;
+ if (*rtemp8 == 0x00) {
+ return efuse_real_content_len;
+ }
+ do {
+ idx = (*(rtemp8) >> shift) & 0xf;
+ switch (idx) {
+ case EFUSE_R_CALIBRATION_RESULT:
+ case EFUSE_CRYSTAL_FREQUENCY_OFFSET:
+ case EFUSE_TX_POWER_INDEX_1:
+ case EFUSE_TX_POWER_INDEX_2:
+ case EFUSE_SAR_RESULT:
+ if (shift) {
+ rtemp8++;
+ SSV_EFUSE_ITEM_TABLE[idx].value =
+ (u16) ((u8) (*((u16 *) rtemp8)) &
+ ((1 <<
+ SSV_EFUSE_ITEM_TABLE
+ [idx].byte_cnts) - 1));
+ } else {
+ SSV_EFUSE_ITEM_TABLE[idx].value =
+ (u16) ((u8) (*((u16 *) rtemp8) >> 4) &
+ ((1 <<
+ SSV_EFUSE_ITEM_TABLE
+ [idx].byte_cnts) - 1));
+ }
+ efuse_real_content_len +=
+ (SSV_EFUSE_ITEM_TABLE[idx].offset +
+ SSV_EFUSE_ITEM_TABLE[idx].byte_cnts);
+ break;
+ case EFUSE_MAC:
+ if (shift) {
+ rtemp8++;
+ memcpy(mac_addr, rtemp8, 6);
+ } else {
+ for (i = 0; i < 6; i++) {
+ mac_addr[i] =
+ (u16) (*((u16 *) rtemp8) >> 4) &
+ 0xff;
+ rtemp8++;
+ }
+ }
+ efuse_real_content_len +=
+ (SSV_EFUSE_ITEM_TABLE[idx].offset +
+ SSV_EFUSE_ITEM_TABLE[idx].byte_cnts);
+ break;
+ default:
+ idx = 0;
+ break;
+ }
+ shift = efuse_real_content_len % 8;
+ rtemp8 = &pbuf[efuse_real_content_len / 8];
+ } while (idx != 0);
+ return efuse_real_content_len;
+}
+
+void addr_increase_copy(u8 * dst, u8 * src)
+{
+ u8 *a = (u8 *) dst;
+ const u8 *b = (const u8 *)src;
+ a[0] = b[0];
+ a[1] = b[1];
+ a[2] = b[2];
+ a[3] = b[3];
+ a[4] = b[4];
+ if (b[5] & 0x1)
+ a[5] = b[5] - 1;
+ else
+ a[5] = b[5] + 1;
+}
+
+static u8 key_char2num(u8 ch)
+{
+ if ((ch >= '0') && (ch <= '9'))
+ return ch - '0';
+ else if ((ch >= 'a') && (ch <= 'f'))
+ return ch - 'a' + 10;
+ else if ((ch >= 'A') && (ch <= 'F'))
+ return ch - 'A' + 10;
+ else
+ return 0xff;
+}
+
+u8 key_2char2num(u8 hch, u8 lch)
+{
+ return ((key_char2num(hch) << 4) | key_char2num(lch));
+}
+
+extern struct ssv6xxx_cfg ssv_cfg;
+extern char *ssv_initmac;
+void efuse_read_all_map(struct ssv_hw *sh)
+{
+ u8 mac[ETH_ALEN] = { 0 };
+ int jj, kk;
+ u8 efuse_mapping_table[EFUSE_HWSET_MAX_SIZE / 8];
+#ifndef CONFIG_SSV_RANDOM_MAC
+ u8 pseudo_mac0[ETH_ALEN] = { 0x00, 0x33, 0x33, 0x33, 0x33, 0x33 };
+#endif
+ u8 rom_mac0[ETH_ALEN];
+ memset(rom_mac0, 0x00, ETH_ALEN);
+ memset(efuse_mapping_table, 0x00, EFUSE_HWSET_MAX_SIZE / 8);
+ read_efuse(sh, efuse_mapping_table);
+ parser_efuse(efuse_mapping_table, rom_mac0);
+ ssv_cfg.r_calbration_result =
+ (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_R_CALIBRATION_RESULT].value;
+ ssv_cfg.sar_result = (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_SAR_RESULT].value;
+ ssv_cfg.crystal_frequency_offset =
+ (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_CRYSTAL_FREQUENCY_OFFSET].value;
+ ssv_cfg.tx_power_index_1 =
+ (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_TX_POWER_INDEX_1].value;
+ ssv_cfg.tx_power_index_2 =
+ (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_TX_POWER_INDEX_2].value;
+ if (!is_valid_ether_addr(&sh->cfg.maddr[0][0])) {
+ if (!sh->cfg.ignore_efuse_mac) {
+ if (is_valid_ether_addr(rom_mac0)) {
+ dev_info(sh->sc->dev, "Using MAC address from e-fuse\n");
+ memcpy(&sh->cfg.maddr[0][0], rom_mac0,
+ ETH_ALEN);
+ addr_increase_copy(&sh->cfg.maddr[1][0],
+ rom_mac0);
+ goto Done;
+ }
+ }
+ if (ssv_initmac != NULL) {
+ for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) {
+ mac[jj] =
+ key_2char2num(ssv_initmac[kk],
+ ssv_initmac[kk + 1]);
+ }
+ if (is_valid_ether_addr(mac)) {
+ dev_info(sh->sc->dev, "Using MAC address from module option\n");
+ memcpy(&sh->cfg.maddr[0][0], mac, ETH_ALEN);
+ addr_increase_copy(&sh->cfg.maddr[1][0], mac);
+ goto Done;
+ }
+ }
+ if (sh->cfg.mac_address_path[0] != 0x00) {
+ if ((readfile_mac
+ (sh->cfg.mac_address_path, &sh->cfg.maddr[0][0]))
+ && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
+ dev_info
+ (sh->sc->dev, "Using MAC address from configuration file\n");
+ addr_increase_copy(&sh->cfg.maddr[1][0],
+ &sh->cfg.maddr[0][0]);
+ goto Done;
+ }
+ }
+ switch (sh->cfg.mac_address_mode) {
+ case 1:
+ get_random_bytes(&sh->cfg.maddr[0][0], ETH_ALEN);
+ sh->cfg.maddr[0][0] = sh->cfg.maddr[0][0] & 0xF0;
+ addr_increase_copy(&sh->cfg.maddr[1][0],
+ &sh->cfg.maddr[0][0]);
+ break;
+ case 2:
+ if ((readfile_mac
+ (sh->cfg.mac_output_path, &sh->cfg.maddr[0][0]))
+ && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
+ addr_increase_copy(&sh->cfg.maddr[1][0],
+ &sh->cfg.maddr[0][0]);
+ } else {
+ {
+ get_random_bytes(&sh->cfg.maddr[0][0],
+ ETH_ALEN);
+ sh->cfg.maddr[0][0] =
+ sh->cfg.maddr[0][0] & 0xF0;
+ addr_increase_copy(&sh->cfg.maddr[1][0],
+ &sh->
+ cfg.maddr[0][0]);
+ if (sh->cfg.mac_output_path[0] != 0x00)
+ write_mac_to_file(sh->
+ cfg.mac_output_path,
+ &sh->
+ cfg.maddr[0]
+ [0]);
+ }
+ }
+ break;
+ default:
+ memcpy(&sh->cfg.maddr[0][0], pseudo_mac0, ETH_ALEN);
+ addr_increase_copy(&sh->cfg.maddr[1][0], pseudo_mac0);
+ break;
+ }
+ dev_info(sh->sc->dev, "MAC address from Software MAC mode[%d]\n",
+ sh->cfg.mac_address_mode);
+ }
+ Done:
+ dev_info(sh->sc->dev, "Chip identity from efuse: %08x\n", ssv_cfg.chip_identity);
+ dev_dbg(sh->sc->dev, "r_calbration_result- %x\n", ssv_cfg.r_calbration_result);
+ dev_dbg(sh->sc->dev, "sar_result- %x\n", ssv_cfg.sar_result);
+ dev_dbg(sh->sc->dev, "crystal_frequency_offset- %x\n",
+ ssv_cfg.crystal_frequency_offset);
+ dev_dbg(sh->sc->dev, "tx_power_index_1- %x\n", ssv_cfg.tx_power_index_1);
+ dev_dbg(sh->sc->dev, "tx_power_index_2- %x\n", ssv_cfg.tx_power_index_2);
+ dev_dbg(sh->sc->dev, "MAC address - %pM\n", rom_mac0);
+ sh->cfg.crystal_frequency_offset = ssv_cfg.crystal_frequency_offset;
+ sh->cfg.tx_power_index_1 = ssv_cfg.tx_power_index_1;
+ sh->cfg.tx_power_index_2 = ssv_cfg.tx_power_index_2;
+ sh->cfg.chip_identity = ssv_cfg.chip_identity;
+}
diff --git a/drivers/net/wireless/ssv6051/smac/efuse.h b/drivers/net/wireless/ssv6051/smac/efuse.h
new file mode 100644
index 000000000000..c25280c5abad
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/efuse.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_EFUSE_H_
+#define _SSV_EFUSE_H_
+#include "dev.h"
+struct efuse_map {
+ u8 offset;
+ u8 byte_cnts;
+ u16 value;
+};
+enum efuse_data_item {
+ EFUSE_R_CALIBRATION_RESULT = 1,
+ EFUSE_SAR_RESULT,
+ EFUSE_MAC,
+ EFUSE_CRYSTAL_FREQUENCY_OFFSET,
+ EFUSE_TX_POWER_INDEX_1,
+ EFUSE_TX_POWER_INDEX_2
+};
+#define EFUSE_HWSET_MAX_SIZE (256-32)
+#define EFUSE_MAX_SECTION_MAP (EFUSE_HWSET_MAX_SIZE>>5)
+#define SSV_EFUSE_ID_READ_SWITCH 0xC2000128
+#define SSV_EFUSE_ID_RAW_DATA_BASE 0xC200014C
+#define SSV_EFUSE_READ_SWITCH 0xC200012C
+#define SSV_EFUSE_RAW_DATA_BASE 0xC2000150
+void efuse_read_all_map(struct ssv_hw *sh);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/init.c b/drivers/net/wireless/ssv6051/smac/init.c
new file mode 100644
index 000000000000..592c52a28381
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/init.c
@@ -0,0 +1,1347 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/nl80211.h>
+#include <linux/kthread.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+#include <crypto/hash.h>
+#else
+#include <linux/crypto.h>
+#endif
+#include <ssv6200.h>
+#include <hci/hctrl.h>
+#include <ssv_firmware_version.h>
+#include "dev_tbl.h"
+#include "dev.h"
+#include "lib.h"
+#include "ssv_rc.h"
+#include "ap.h"
+#include "efuse.h"
+#include "sar.h"
+#include "ssv_cfgvendor.h"
+
+#include "linux_80211.h"
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+#include "ssv6xxx_debugfs.h"
+#endif
+
+#define WIFI_FIRMWARE_NAME "ssv6051-sw.bin"
+static const struct ieee80211_iface_limit ssv6xxx_p2p_limits[] = {
+ {
+ .max = 2,
+ .types = BIT(NL80211_IFTYPE_STATION),
+ },
+ {
+ .max = 1,
+ .types = BIT(NL80211_IFTYPE_P2P_GO) |
+ BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_AP),
+ },
+};
+
+static const struct ieee80211_iface_combination
+ ssv6xxx_iface_combinations_p2p[] = {
+ {.num_different_channels = 1,
+ .max_interfaces = SSV6200_MAX_VIF,
+ .beacon_int_infra_match = true,
+ .limits = ssv6xxx_p2p_limits,
+ .n_limits = ARRAY_SIZE(ssv6xxx_p2p_limits),
+ },
+};
+
+#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
+ (((a) & 0xff00ff00) >> 8))
+#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
+#define CHAN2G(_freq,_idx) { \
+ .band = INDEX_80211_BAND_2GHZ, \
+ .center_freq = (_freq), \
+ .hw_value = (_idx), \
+ .max_power = 20, \
+}
+#ifndef WLAN_CIPHER_SUITE_SMS4
+#define WLAN_CIPHER_SUITE_SMS4 0x00147201
+#endif
+#define SHPCHECK(__hw_rate,__flags) \
+ ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate +3 ) : 0)
+#define RATE(_bitrate,_hw_rate,_flags) { \
+ .bitrate = (_bitrate), \
+ .flags = (_flags), \
+ .hw_value = (_hw_rate), \
+ .hw_value_short = SHPCHECK(_hw_rate,_flags) \
+}
+extern struct ssv6xxx_cfg ssv_cfg;
+static const struct ieee80211_channel ssv6200_2ghz_chantable[] = {
+ CHAN2G(2412, 1),
+ CHAN2G(2417, 2),
+ CHAN2G(2422, 3),
+ CHAN2G(2427, 4),
+ CHAN2G(2432, 5),
+ CHAN2G(2437, 6),
+ CHAN2G(2442, 7),
+ CHAN2G(2447, 8),
+ CHAN2G(2452, 9),
+ CHAN2G(2457, 10),
+ CHAN2G(2462, 11),
+ CHAN2G(2467, 12),
+ CHAN2G(2472, 13),
+ CHAN2G(2484, 14),
+};
+
+static struct ieee80211_rate ssv6200_legacy_rates[] = {
+ RATE(10, 0x00, 0),
+ RATE(20, 0x01, IEEE80211_RATE_SHORT_PREAMBLE),
+ RATE(55, 0x02, IEEE80211_RATE_SHORT_PREAMBLE),
+ RATE(110, 0x03, IEEE80211_RATE_SHORT_PREAMBLE),
+ RATE(60, 0x07, 0),
+ RATE(90, 0x08, 0),
+ RATE(120, 0x09, 0),
+ RATE(180, 0x0a, 0),
+ RATE(240, 0x0b, 0),
+ RATE(360, 0x0c, 0),
+ RATE(480, 0x0d, 0),
+ RATE(540, 0x0e, 0),
+};
+
+struct ssv6xxx_ch_cfg ch_cfg_z[] = {
+ {ADR_ABB_REGISTER_1, 0, 0x151559fc},
+ {ADR_LDO_REGISTER, 0, 0x00eb7c1c},
+ {ADR_RX_ADC_REGISTER, 0, 0x20d000d2}
+};
+
+struct ssv6xxx_ch_cfg ch_cfg_p[] = {
+ {ADR_ABB_REGISTER_1, 0, 0x151559fc},
+ {ADR_RX_ADC_REGISTER, 0, 0x20d000d2}
+};
+
+int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg)
+{
+ struct sk_buff *skb;
+ struct cfg_host_cmd *host_cmd;
+ int ret = 0;
+ dev_dbg(sh->sc->dev, "# Do init_cali (iq)\n");
+ skb =
+ ssv_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE +
+ RF_SETTING_SIZE);
+ if (skb == NULL) {
+ dev_err(sh->sc->dev, "init ssv6xxx_do_iq_calib failure\n");
+ return (-1);
+ }
+ if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) ||
+ (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) {
+ dev_warn(sh->sc->dev, "wrong RF or PHY table size\n");
+ WARN_ON(1);
+ return (-1);
+ }
+ skb->data_len =
+ HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE;
+ skb->len = skb->data_len;
+ host_cmd = (struct cfg_host_cmd *)skb->data;
+ host_cmd->c_type = HOST_CMD;
+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_INIT_CALI;
+ host_cmd->len = skb->data_len;
+ p_cfg->phy_tbl_size = PHY_SETTING_SIZE;
+ p_cfg->rf_tbl_size = RF_SETTING_SIZE;
+ memcpy(host_cmd->dat32, p_cfg, IQK_CFG_LEN);
+ memcpy(host_cmd->dat8 + IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE);
+ memcpy(host_cmd->dat8 + IQK_CFG_LEN + PHY_SETTING_SIZE, ssv6200_rf_tbl,
+ RF_SETTING_SIZE);
+ sh->hci.hci_ops->hci_send_cmd(skb);
+ ssv_skb_free(skb);
+ {
+ u32 timeout;
+ sh->sc->iq_cali_done = IQ_CALI_RUNNING;
+ set_current_state(TASK_INTERRUPTIBLE);
+ timeout = wait_event_interruptible_timeout(sh->sc->fw_wait_q,
+ sh->sc->iq_cali_done,
+ msecs_to_jiffies
+ (500));
+ set_current_state(TASK_RUNNING);
+ if (timeout == 0)
+ return -ETIME;
+ if (sh->sc->iq_cali_done != IQ_CALI_OK)
+ return (-1);
+ }
+ return ret;
+}
+
+#define HT_CAP_RX_STBC_ONE_STREAM 0x1
+#if defined(CONFIG_PM)
+static const struct wiphy_wowlan_support wowlan_support = {
+#ifdef SSV_WAKEUP_HOST
+ .flags = WIPHY_WOWLAN_ANY,
+#else
+ .flags = WIPHY_WOWLAN_DISCONNECT,
+#endif
+ .n_patterns = 0,
+ .pattern_max_len = 0,
+ .pattern_min_len = 0,
+ .max_pkt_offset = 0,
+};
+#endif
+static void ssv6xxx_set_80211_hw_capab(struct ssv_softc *sc)
+{
+ struct ieee80211_hw *hw = sc->hw;
+ struct ssv_hw *sh = sc->sh;
+ struct ieee80211_sta_ht_cap *ht_info;
+ ieee80211_hw_set(hw, SIGNAL_DBM);
+ hw->rate_control_algorithm = "ssv6xxx_rate_control";
+ //hw->rate_control_algorithm = NULL; // NULL selects default
+ ht_info = &sc->sbands[INDEX_80211_BAND_2GHZ].ht_cap;
+ ampdu_db_log("sh->cfg.hw_caps = 0x%x\n", sh->cfg.hw_caps);
+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_HT) {
+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX) {
+ ieee80211_hw_set(hw, AMPDU_AGGREGATION);
+ ampdu_db_log("set IEEE80211_HW_AMPDU_AGGREGATION(%d)\n",
+ ieee80211_hw_check(hw, AMPDU_AGGREGATION));
+ }
+ ht_info->cap = IEEE80211_HT_CAP_SM_PS;
+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_GF) {
+ ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
+ ht_info->cap |=
+ HT_CAP_RX_STBC_ONE_STREAM <<
+ IEEE80211_HT_CAP_RX_STBC_SHIFT;
+ }
+ if (sh->cfg.hw_caps & SSV6200_HT_CAP_SGI_20)
+ ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
+ ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_32K;
+ ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
+ memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
+ ht_info->mcs.rx_mask[0] = 0xff;
+ ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
+ ht_info->mcs.rx_highest = cpu_to_le16(SSV6200_RX_HIGHEST_RATE);
+ ht_info->ht_supported = true;
+ }
+ hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) {
+ hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_CLIENT);
+ hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_GO);
+ hw->wiphy->iface_combinations = ssv6xxx_iface_combinations_p2p;
+ hw->wiphy->n_iface_combinations =
+ ARRAY_SIZE(ssv6xxx_iface_combinations_p2p);
+ }
+ hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_AP) {
+ hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
+ hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
+ }
+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_TDLS) {
+ hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
+ hw->wiphy->flags |= WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
+ dev_info(sc->dev, "TDLS function enabled in sta.cfg\n");
+ }
+ hw->queues = 4;
+ hw->max_rates = 4;
+ hw->max_listen_interval = 1;
+ hw->max_rate_tries = HW_MAX_RATE_TRIES;
+ hw->extra_tx_headroom = TXPB_OFFSET + AMPDU_DELIMITER_LEN;
+ if (sizeof(struct ampdu_hdr_st) > SSV_SKB_info_size)
+ hw->extra_tx_headroom += sizeof(struct ampdu_hdr_st);
+ else
+ hw->extra_tx_headroom += SSV_SKB_info_size;
+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
+ hw->wiphy->bands[INDEX_80211_BAND_2GHZ] =
+ &sc->sbands[INDEX_80211_BAND_2GHZ];
+ }
+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX)
+#ifdef PREFER_RX
+ hw->max_rx_aggregation_subframes = 64;
+#else
+ hw->max_rx_aggregation_subframes = 16;
+#endif
+ else
+ hw->max_rx_aggregation_subframes = 12;
+ hw->max_tx_aggregation_subframes = 64;
+ hw->sta_data_size = sizeof(struct ssv_sta_priv_data);
+ hw->vif_data_size = sizeof(struct ssv_vif_priv_data);
+ memcpy(sh->maddr[0].addr, &sh->cfg.maddr[0][0], ETH_ALEN);
+ hw->wiphy->addresses = sh->maddr;
+ hw->wiphy->n_addresses = 1;
+ if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) {
+ int i;
+ for (i = 1; i < SSV6200_MAX_HW_MAC_ADDR; i++) {
+ memcpy(sh->maddr[i].addr, sh->maddr[i - 1].addr,
+ ETH_ALEN);
+ sh->maddr[i].addr[5]++;
+ hw->wiphy->n_addresses++;
+ }
+ }
+ if (!is_zero_ether_addr(sh->cfg.maddr[1])) {
+ memcpy(sh->maddr[1].addr, sh->cfg.maddr[1], ETH_ALEN);
+ if (hw->wiphy->n_addresses < 2)
+ hw->wiphy->n_addresses = 2;
+ }
+#if defined(CONFIG_PM)
+ hw->wiphy->wowlan = &wowlan_support;
+#endif
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) && defined(CONFIG_SSV_VENDOR_EXT_SUPPORT)
+ {
+ int err = 0;
+ struct ssv_softc *softc = (struct ssv_softc *)hw->priv;
+ if (softc)
+ {
+ set_wiphy_dev(hw->wiphy, softc->dev);
+ *((struct ssv_softc **)wiphy_priv(hw->wiphy)) = softc;
+ }
+ dev_dbg(sc->dev, "Registering Vendor80211\n");
+ err = ssv_cfgvendor_attach(hw->wiphy);
+ if (unlikely(err < 0)) {
+ dev_err(sc->dev, "Couldn not attach vendor commands (%d)\n", err);
+ }
+ }
+#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) || defined(WL_VENDOR_EXT_SUPPORT) */
+}
+
+void ssv6xxx_watchdog_restart_hw(struct ssv_softc *sc)
+{
+ dev_dbg(sc->dev, "%s()\n", __FUNCTION__);
+ sc->restart_counter++;
+ sc->force_triger_reset = true;
+ sc->beacon_info[0].pubf_addr = 0x00;
+ sc->beacon_info[1].pubf_addr = 0x00;
+ ieee80211_restart_hw(sc->hw);
+}
+
+extern struct rssi_res_st rssi_res;
+void ssv6200_watchdog_timeout(struct timer_list *t)
+{
+ static u32 count = 0;
+ struct rssi_res_st *rssi_tmp0 = NULL, *rssi_tmp1 = NULL;
+ struct ssv_softc *sc = from_timer(sc, t, watchdog_timeout);
+ if (sc->watchdog_flag == WD_BARKING) {
+ ssv6xxx_watchdog_restart_hw(sc);
+ mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
+ return;
+ }
+ if (sc->watchdog_flag != WD_SLEEP)
+ sc->watchdog_flag = WD_BARKING;
+ count++;
+ if (count == 6) {
+ count = 0;
+ if (list_empty(&rssi_res.rssi_list)) {
+ return;
+ }
+ list_for_each_entry_safe(rssi_tmp0, rssi_tmp1,
+ &rssi_res.rssi_list, rssi_list) {
+ if (rssi_tmp0->timeout) {
+ list_del_rcu(&rssi_tmp0->rssi_list);
+ kfree(rssi_tmp0);
+ }
+ }
+ }
+ mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
+ return;
+}
+
+static void ssv6xxx_preload_sw_cipher(void)
+{
+}
+
+static int ssv6xxx_init_softc(struct ssv_softc *sc)
+{
+ void *channels;
+ int ret = 0;
+ sc->sc_flags = SC_OP_INVALID;
+ mutex_init(&sc->mutex);
+ mutex_init(&sc->mem_mutex);
+ sc->config_wq = create_singlethread_workqueue("ssv6xxx_cong_wq");
+ sc->thermal_wq = create_singlethread_workqueue("ssv6xxx_thermal_wq");
+ INIT_DELAYED_WORK(&sc->thermal_monitor_work, thermal_monitor);
+ INIT_WORK(&sc->set_tim_work, ssv6200_set_tim_work);
+ INIT_WORK(&sc->bcast_start_work, ssv6200_bcast_start_work);
+ INIT_DELAYED_WORK(&sc->bcast_stop_work, ssv6200_bcast_stop_work);
+ INIT_DELAYED_WORK(&sc->bcast_tx_work, ssv6200_bcast_tx_work);
+ INIT_WORK(&sc->set_ampdu_rx_add_work, ssv6xxx_set_ampdu_rx_add_work);
+ INIT_WORK(&sc->set_ampdu_rx_del_work, ssv6xxx_set_ampdu_rx_del_work);
+ sc->mac_deci_tbl = sta_deci_tbl;
+ memset((void *)&sc->tx, 0, sizeof(struct ssv_tx));
+ sc->tx.hw_txqid[WMM_AC_VO] = 3;
+ sc->tx.ac_txqid[3] = WMM_AC_VO;
+ sc->tx.hw_txqid[WMM_AC_VI] = 2;
+ sc->tx.ac_txqid[2] = WMM_AC_VI;
+ sc->tx.hw_txqid[WMM_AC_BE] = 1;
+ sc->tx.ac_txqid[1] = WMM_AC_BE;
+ sc->tx.hw_txqid[WMM_AC_BK] = 0;
+ sc->tx.ac_txqid[0] = WMM_AC_BK;
+ INIT_LIST_HEAD(&sc->tx.ampdu_tx_que);
+ spin_lock_init(&sc->tx.ampdu_tx_que_lock);
+ memset((void *)&sc->rx, 0, sizeof(struct ssv_rx));
+ spin_lock_init(&sc->rx.rxq_lock);
+ skb_queue_head_init(&sc->rx.rxq_head);
+ sc->rx.rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
+ if (sc->rx.rx_buf == NULL)
+ return -ENOMEM;
+ memset(&sc->bcast_txq, 0, sizeof(struct ssv6xxx_bcast_txq));
+ spin_lock_init(&sc->bcast_txq.txq_lock);
+ skb_queue_head_init(&sc->bcast_txq.qhead);
+ spin_lock_init(&sc->ps_state_lock);
+#ifdef CONFIG_P2P_NOA
+ spin_lock_init(&sc->p2p_noa.p2p_config_lock);
+#endif
+ if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
+ channels = kmemdup(ssv6200_2ghz_chantable,
+ sizeof(ssv6200_2ghz_chantable), GFP_KERNEL);
+ if (!channels) {
+ kfree(sc->rx.rx_buf);
+ return -ENOMEM;
+ }
+ sc->sbands[INDEX_80211_BAND_2GHZ].channels = channels;
+ sc->sbands[INDEX_80211_BAND_2GHZ].band = INDEX_80211_BAND_2GHZ;
+ sc->sbands[INDEX_80211_BAND_2GHZ].n_channels =
+ ARRAY_SIZE(ssv6200_2ghz_chantable);
+ sc->sbands[INDEX_80211_BAND_2GHZ].bitrates =
+ ssv6200_legacy_rates;
+ sc->sbands[INDEX_80211_BAND_2GHZ].n_bitrates =
+ ARRAY_SIZE(ssv6200_legacy_rates);
+ }
+ sc->cur_channel = NULL;
+ sc->hw_chan = (-1);
+ ssv6xxx_set_80211_hw_capab(sc);
+ ret = ssv6xxx_rate_control_register();
+ if (ret != 0) {
+ dev_warn(sc->dev, "%s(): Failed to register rc algorithm.\n",__FUNCTION__);
+ }
+ init_waitqueue_head(&sc->tx_wait_q);
+ sc->tx_wait_q_woken = 0;
+ skb_queue_head_init(&sc->tx_skb_q);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ sc->max_tx_skb_q_len = 0;
+#endif
+ sc->tx_task = kthread_run(ssv6xxx_tx_task, sc, "ssv6xxx_tx_task");
+ sc->tx_q_empty = false;
+ skb_queue_head_init(&sc->tx_done_q);
+ init_waitqueue_head(&sc->rx_wait_q);
+ sc->rx_wait_q_woken = 0;
+ skb_queue_head_init(&sc->rx_skb_q);
+ sc->rx_task = kthread_run(ssv6xxx_rx_task, sc, "ssv6xxx_rx_task");
+ ssv6xxx_preload_sw_cipher();
+ timer_setup(&sc->watchdog_timeout, ssv6200_watchdog_timeout, 0);
+ init_waitqueue_head(&sc->fw_wait_q);
+ INIT_LIST_HEAD(&rssi_res.rssi_list);
+ rssi_res.rssi = 0;
+ mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
+ //add_timer(&sc->watchdog_timeout);
+ //if(get_flash_info(sc) == 1)
+ sc->is_sar_enabled = get_flash_info(sc);
+ if (sc->is_sar_enabled)
+ queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
+ THERMAL_MONITOR_TIME);
+ //schedule_delayed_work(&sc->thermal_monitor_work, THERMAL_MONITOR_TIME);
+ return ret;
+}
+
+static int ssv6xxx_deinit_softc(struct ssv_softc *sc)
+{
+ void *channels;
+ struct sk_buff *skb;
+ u8 remain_size;
+ dev_dbg(sc->dev, "%s():\n", __FUNCTION__);
+ if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
+ channels = sc->sbands[INDEX_80211_BAND_2GHZ].channels;
+ kfree(channels);
+ }
+ ssv_skb_free(sc->rx.rx_buf);
+ sc->rx.rx_buf = NULL;
+ ssv6xxx_rate_control_unregister();
+ cancel_delayed_work_sync(&sc->bcast_tx_work);
+ //ssv6xxx_watchdog_controller(sc->sh ,(u8)SSV6XXX_HOST_CMD_WATCHDOG_STOP);
+ del_timer_sync(&sc->watchdog_timeout);
+ cancel_delayed_work(&sc->thermal_monitor_work);
+ sc->ps_status = PWRSV_PREPARE;
+ flush_workqueue(sc->thermal_wq);
+ destroy_workqueue(sc->thermal_wq);
+ do {
+ skb = ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size);
+ if (skb)
+ ssv6xxx_txbuf_free_skb(skb, (void *)sc);
+ else
+ break;
+ } while (remain_size);
+ if (sc->tx_task != NULL) {
+ dev_dbg(sc->dev, "Stopping TX task...\n");
+ kthread_stop(sc->tx_task);
+ sc->tx_task = NULL;
+ dev_dbg(sc->dev, "Stopped TX task.\n");
+ }
+ if (sc->rx_task != NULL) {
+ dev_dbg(sc->dev, "Stopping RX task...\n");
+ kthread_stop(sc->rx_task);
+ sc->rx_task = NULL;
+ dev_dbg(sc->dev, "Stopped RX task.\n");
+ }
+ destroy_workqueue(sc->config_wq);
+ return 0;
+}
+
+static void ssv6xxx_hw_set_replay_ignore(struct ssv_hw *sh, u8 ignore)
+{
+ u32 temp;
+ SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
+ temp = temp & SCRT_RPLY_IGNORE_I_MSK;
+ temp |= (ignore << SCRT_RPLY_IGNORE_SFT);
+ SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
+}
+
+int ssv6xxx_init_mac(struct ssv_hw *sh)
+{
+ struct ssv_softc *sc = sh->sc;
+ int i = 0, ret = 0;
+
+ u32 *ptr, id_len, regval, temp[0x8];
+ char *chip_id = sh->chip_id;
+ SMAC_REG_READ(sh, ADR_IC_TIME_TAG_1, &regval);
+ sh->chip_tag = ((u64) regval << 32);
+ SMAC_REG_READ(sh, ADR_IC_TIME_TAG_0, &regval);
+ sh->chip_tag |= (regval);
+ SMAC_REG_READ(sh, ADR_CHIP_ID_3, &regval);
+ *((u32 *) & chip_id[0]) = (u32) LONGSWAP(regval);
+ SMAC_REG_READ(sh, ADR_CHIP_ID_2, &regval);
+ *((u32 *) & chip_id[4]) = (u32) LONGSWAP(regval);
+ SMAC_REG_READ(sh, ADR_CHIP_ID_1, &regval);
+ *((u32 *) & chip_id[8]) = (u32) LONGSWAP(regval);
+ SMAC_REG_READ(sh, ADR_CHIP_ID_0, &regval);
+ *((u32 *) & chip_id[12]) = (u32) LONGSWAP(regval);
+ chip_id[12 + sizeof(u32)] = 0;
+ dev_info(sh->sc->dev, "chip id: %s, tag: %llx\n", chip_id, sh->chip_tag);
+ if (sc->ps_status == PWRSV_ENABLE) {
+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA,
+ M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) |
+ (M_ENG_HWHCI << 8));
+ SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
+ M_ENG_MACRX | (M_ENG_HWHCI << 4));
+#if Enable_AMPDU_FW_Retry
+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
+ M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI <<
+ 8));
+#else
+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
+ M_ENG_MACRX | (M_ENG_HWHCI << 4));
+#endif
+ SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + 6 * 4,
+ (sc->mac_deci_tbl[6]));
+ return ret;
+ }
+ SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (0 << RG_PHY_MD_EN_SFT),
+ RG_PHY_MD_EN_MSK);
+ SMAC_REG_WRITE(sh, ADR_BRG_SW_RST, 1 << MAC_SW_RST_SFT);
+ do {
+ SMAC_REG_READ(sh, ADR_BRG_SW_RST, &regval);
+ i++;
+ if (i > 10000) {
+ dev_err(sh->sc->dev, "MAC reset fail !!!!\n");
+ WARN_ON(1);
+ ret = 1;
+ goto exit;
+ }
+ } while (regval != 0);
+ SMAC_REG_WRITE(sc->sh, ADR_TXQ4_MTX_Q_AIFSN, 0xffff2101);
+ SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC, 0,
+ MTX_HALT_MNG_UNTIL_DTIM_MSK);
+ SMAC_REG_WRITE(sh, ADR_CONTROL, 0x12000006);
+ SMAC_REG_WRITE(sh, ADR_RX_TIME_STAMP_CFG,
+ ((28 << MRX_STP_OFST_SFT) | 0x01));
+ SMAC_REG_WRITE(sh, ADR_HCI_TX_RX_INFO_SIZE,
+ ((u32) (TXPB_OFFSET) << TX_PBOFFSET_SFT) |
+ ((u32) (sh->tx_desc_len) << TX_INFO_SIZE_SFT) |
+ ((u32) (sh->rx_desc_len) << RX_INFO_SIZE_SFT) |
+ ((u32) (sh->rx_pinfo_pad) << RX_LAST_PHY_SIZE_SFT)
+ );
+ SMAC_REG_READ(sh, ADR_MMU_CTRL, &regval);
+ regval |= (0xff << MMU_SHARE_MCU_SFT);
+ SMAC_REG_WRITE(sh, ADR_MMU_CTRL, regval);
+ SMAC_REG_READ(sh, ADR_MRX_WATCH_DOG, &regval);
+ regval &= 0xfffffff0;
+ SMAC_REG_WRITE(sh, ADR_MRX_WATCH_DOG, regval);
+ SMAC_REG_READ(sh, ADR_TRX_ID_THRESHOLD, &id_len);
+ id_len = (id_len & 0xffff0000) |
+ (SSV6200_ID_TX_THRESHOLD << TX_ID_THOLD_SFT) |
+ (SSV6200_ID_RX_THRESHOLD << RX_ID_THOLD_SFT);
+ SMAC_REG_WRITE(sh, ADR_TRX_ID_THRESHOLD, id_len);
+ SMAC_REG_READ(sh, ADR_ID_LEN_THREADSHOLD1, &id_len);
+ id_len = (id_len & 0x0f) |
+ (SSV6200_PAGE_TX_THRESHOLD << ID_TX_LEN_THOLD_SFT) |
+ (SSV6200_PAGE_RX_THRESHOLD << ID_RX_LEN_THOLD_SFT);
+ SMAC_REG_WRITE(sh, ADR_ID_LEN_THREADSHOLD1, id_len);
+#ifdef CONFIG_SSV_CABRIO_MB_DEBUG
+ SMAC_REG_READ(sh, ADR_MB_DBG_CFG3, &regval);
+ regval |= (debug_buffer << 0);
+ SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG3, regval);
+ SMAC_REG_READ(sh, ADR_MB_DBG_CFG2, &regval);
+ regval |= (DEBUG_SIZE << 16);
+ SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG2, regval);
+ SMAC_REG_READ(sh, ADR_MB_DBG_CFG1, &regval);
+ regval |= (1 << MB_DBG_EN_SFT);
+ SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG1, regval);
+ SMAC_REG_READ(sh, ADR_MBOX_HALT_CFG, &regval);
+ regval |= (1 << MB_ERR_AUTO_HALT_EN_SFT);
+ SMAC_REG_WRITE(sh, ADR_MBOX_HALT_CFG, regval);
+#endif
+ SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, &regval);
+ regval |= (1 << MTX_TSF_TIMER_EN_SFT);
+ SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval);
+ SMAC_REG_WRITE(sh, 0xcd010004, 0x1213);
+ for (i = 0; i < SSV_RC_MAX_STA; i++) {
+ if (i == 0) {
+ sh->hw_buf_ptr[i] =
+ ssv6xxx_pbuf_alloc(sc,
+ sizeof(phy_info_tbl) +
+ sizeof(struct ssv6xxx_hw_sec),
+ NOTYPE_BUF);
+ if ((sh->hw_buf_ptr[i] >> 28) != 8) {
+ dev_err(sh->sc->dev, "opps allocate pbuf error\n");
+ WARN_ON(1);
+ ret = 1;
+ goto exit;
+ }
+ } else {
+ sh->hw_buf_ptr[i] =
+ ssv6xxx_pbuf_alloc(sc,
+ sizeof(struct ssv6xxx_hw_sec),
+ NOTYPE_BUF);
+ if ((sh->hw_buf_ptr[i] >> 28) != 8) {
+ dev_err(sh->sc->dev, "opps allocate pbuf error\n");
+ WARN_ON(1);
+ ret = 1;
+ goto exit;
+ }
+ }
+ }
+ for (i = 0; i < 0x8; i++) {
+ temp[i] = 0;
+ temp[i] = ssv6xxx_pbuf_alloc(sc, 256, NOTYPE_BUF);
+ }
+ for (i = 0; i < 0x8; i++) {
+ if (temp[i] == 0x800e0000)
+ dev_dbg(sh->sc->dev, "Found 0x800e0000 at position %d\n", i);
+ else
+ ssv6xxx_pbuf_free(sc, temp[i]);
+ }
+ for (i = 0; i < SSV_RC_MAX_STA; i++)
+ sh->hw_sec_key[i] = sh->hw_buf_ptr[i];
+ for (i = 0; i < SSV_RC_MAX_STA; i++) {
+ int x;
+ for (x = 0; x < sizeof(struct ssv6xxx_hw_sec); x += 4) {
+ SMAC_REG_WRITE(sh, sh->hw_sec_key[i] + x, 0);
+ }
+ }
+ SMAC_REG_READ(sh, ADR_SCRT_SET, &regval);
+ regval &= SCRT_PKT_ID_I_MSK;
+ regval |= ((sh->hw_sec_key[0] >> 16) << SCRT_PKT_ID_SFT);
+ SMAC_REG_WRITE(sh, ADR_SCRT_SET, regval);
+ sh->hw_pinfo = sh->hw_sec_key[0] + sizeof(struct ssv6xxx_hw_sec);
+ for (i = 0, ptr = phy_info_tbl; i < PHY_INFO_TBL1_SIZE; i++, ptr++) {
+ SMAC_REG_WRITE(sh, ADR_INFO0 + i * 4, *ptr);
+ SMAC_REG_CONFIRM(sh, ADR_INFO0 + i * 4, *ptr);
+ }
+ for (i = 0; i < PHY_INFO_TBL2_SIZE; i++, ptr++) {
+ SMAC_REG_WRITE(sh, sh->hw_pinfo + i * 4, *ptr);
+ SMAC_REG_CONFIRM(sh, sh->hw_pinfo + i * 4, *ptr);
+ }
+ for (i = 0; i < PHY_INFO_TBL3_SIZE; i++, ptr++) {
+ SMAC_REG_WRITE(sh, sh->hw_pinfo +
+ (PHY_INFO_TBL2_SIZE << 2) + i * 4, *ptr);
+ SMAC_REG_CONFIRM(sh, sh->hw_pinfo +
+ (PHY_INFO_TBL2_SIZE << 2) + i * 4, *ptr);
+ }
+ SMAC_REG_WRITE(sh, ADR_INFO_RATE_OFFSET, 0x00040000);
+ SMAC_REG_WRITE(sh, ADR_INFO_IDX_ADDR, sh->hw_pinfo);
+ SMAC_REG_WRITE(sh, ADR_INFO_LEN_ADDR,
+ sh->hw_pinfo + (PHY_INFO_TBL2_SIZE) * 4);
+ dev_dbg(sh->sc->dev, "ADR_INFO_IDX_ADDR[%08x] ADR_INFO_LEN_ADDR[%08x]\n",
+ sh->hw_pinfo, sh->hw_pinfo + (PHY_INFO_TBL2_SIZE) * 4);
+ SMAC_REG_WRITE(sh, ADR_GLBLE_SET,
+ (0 << OP_MODE_SFT) | (0 << SNIFFER_MODE_SFT) | (1 <<
+ DUP_FLT_SFT)
+ | (SSV6200_TX_PKT_RSVD_SETTING << TX_PKT_RSVD_SFT) |
+ ((u32) (RXPB_OFFSET) << PB_OFFSET_SFT)
+ );
+ SMAC_REG_WRITE(sh, ADR_STA_MAC_0, *((u32 *) & sh->cfg.maddr[0][0]));
+ SMAC_REG_WRITE(sh, ADR_STA_MAC_1, *((u32 *) & sh->cfg.maddr[0][4]));
+ SMAC_REG_WRITE(sh, ADR_BSSID_0, *((u32 *) & sc->bssid[0]));
+ SMAC_REG_WRITE(sh, ADR_BSSID_1, *((u32 *) & sc->bssid[4]));
+ SMAC_REG_WRITE(sh, ADR_TX_ETHER_TYPE_0, 0x00000000);
+ SMAC_REG_WRITE(sh, ADR_TX_ETHER_TYPE_1, 0x00000000);
+ SMAC_REG_WRITE(sh, ADR_RX_ETHER_TYPE_0, 0x00000000);
+ SMAC_REG_WRITE(sh, ADR_RX_ETHER_TYPE_1, 0x00000000);
+ SMAC_REG_WRITE(sh, ADR_REASON_TRAP0, 0x7FBC7F87);
+ SMAC_REG_WRITE(sh, ADR_REASON_TRAP1, 0x0000003F);
+ SMAC_REG_WRITE(sh, ADR_TRAP_HW_ID, M_ENG_CPU);
+ SMAC_REG_WRITE(sh, ADR_WSID0, 0x00000000);
+ SMAC_REG_WRITE(sh, ADR_WSID1, 0x00000000);
+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA,
+ M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) | (M_ENG_HWHCI <<
+ 8));
+#if defined(CONFIG_P2P_NOA) || defined(CONFIG_RX_MGMT_CHECK)
+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG,
+ M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
+#else
+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG, M_ENG_MACRX | (M_ENG_HWHCI << 4));
+#endif
+#if Enable_AMPDU_FW_Retry
+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
+ M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
+#else
+ SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL, M_ENG_MACRX | (M_ENG_HWHCI << 4));
+#endif
+ ssv6xxx_hw_set_replay_ignore(sh, 1);
+ ssv6xxx_update_decision_table(sc);
+ SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6200_OPMODE_STA,
+ OP_MODE_MSK);
+ SMAC_REG_WRITE(sh, ADR_SDIO_MASK, 0xfffe1fff);
+ SMAC_REG_WRITE(sh, ADR_TX_LIMIT_INTR, 0x80000000 |
+ SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER << 16 |
+ SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER);
+#ifdef CONFIG_SSV_SUPPORT_BTCX
+ SMAC_REG_WRITE(sh, ADR_BTCX0,
+ COEXIST_EN_MSK | (WIRE_MODE_SZ << WIRE_MODE_SFT)
+ | WIFI_TX_SW_POL_MSK | BT_SW_POL_MSK);
+ SMAC_REG_WRITE(sh, ADR_BTCX1,
+ SSV6200_BT_PRI_SMP_TIME | (SSV6200_BT_STA_SMP_TIME <<
+ BT_STA_SMP_TIME_SFT)
+ | (SSV6200_WLAN_REMAIN_TIME << WLAN_REMAIN_TIME_SFT));
+ SMAC_REG_WRITE(sh, ADR_SWITCH_CTL, BT_2WIRE_EN_MSK);
+ SMAC_REG_WRITE(sh, ADR_PAD7, 1);
+ SMAC_REG_WRITE(sh, ADR_PAD8, 0);
+ SMAC_REG_WRITE(sh, ADR_PAD9, 1);
+ SMAC_REG_WRITE(sh, ADR_PAD25, 1);
+ SMAC_REG_WRITE(sh, ADR_PAD27, 8);
+ SMAC_REG_WRITE(sh, ADR_PAD28, 8);
+#endif
+ dev_info(sh->sc->dev, "attempt to load firmware %s\n", WIFI_FIRMWARE_NAME);
+ ret = SMAC_LOAD_FW(sh, WIFI_FIRMWARE_NAME, 0);
+
+ SMAC_REG_READ(sh, FW_VERSION_REG, &regval);
+ if (regval == ssv_firmware_version) {
+ SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (1 << RG_PHY_MD_EN_SFT),
+ RG_PHY_MD_EN_MSK);
+ dev_info(sh->sc->dev, "Firmware version %d\n", regval);
+ } else {
+ dev_err(sh->sc->dev, "Firmware version not mapping %d\n", regval);
+ ret = -1;
+ }
+ ssv6xxx_watchdog_controller(sh, (u8) SSV6XXX_HOST_CMD_WATCHDOG_START);
+ exit:
+ return ret;
+}
+
+void ssv6xxx_deinit_mac(struct ssv_softc *sc)
+{
+ int i;
+ for (i = 0; i < SSV_RC_MAX_STA; i++) {
+ if (sc->sh->hw_buf_ptr[i])
+ ssv6xxx_pbuf_free(sc, sc->sh->hw_buf_ptr[i]);
+ }
+}
+
+void inline ssv6xxx_deinit_hw(struct ssv_softc *sc)
+{
+ dev_dbg(sc->dev, "%s(): \n", __FUNCTION__);
+ ssv6xxx_deinit_mac(sc);
+}
+
+void ssv6xxx_restart_hw(struct ssv_softc *sc)
+{
+ dev_info(sc->dev, "Software MAC reset\n");
+ sc->restart_counter++;
+ sc->force_triger_reset = true;
+ HCI_STOP(sc->sh);
+ SMAC_REG_WRITE(sc->sh, 0xce000004, 0x0);
+ sc->beacon_info[0].pubf_addr = 0x00;
+ sc->beacon_info[1].pubf_addr = 0x00;
+ ieee80211_restart_hw(sc->hw);
+}
+
+extern struct ssv6xxx_iqk_cfg init_iqk_cfg;
+static int ssv6xxx_init_hw(struct ssv_hw *sh)
+{
+ int ret = 0, i = 0, x = 0;
+ u32 regval;
+ sh->tx_desc_len = SSV6XXX_TX_DESC_LEN;
+ sh->rx_desc_len = SSV6XXX_RX_DESC_LEN;
+ sh->rx_pinfo_pad = 0x04;
+ sh->tx_page_available = SSV6200_PAGE_TX_THRESHOLD;
+ sh->ampdu_divider = SSV6XXX_AMPDU_DIVIDER;
+ memset(sh->page_count, 0, sizeof(sh->page_count));
+ if (sh->cfg.force_chip_identity) {
+ dev_info(sh->sc->dev, "Force use external RF setting [%08x]\n",
+ sh->cfg.force_chip_identity);
+ sh->cfg.chip_identity = sh->cfg.force_chip_identity;
+ }
+ if (sh->cfg.chip_identity == SSV6051Z) {
+ sh->p_ch_cfg = &ch_cfg_z[0];
+ sh->ch_cfg_size =
+ sizeof(ch_cfg_z) / sizeof(struct ssv6xxx_ch_cfg);
+ memcpy(phy_info_tbl, phy_info_6051z, sizeof(phy_info_6051z));
+ } else if (sh->cfg.chip_identity == SSV6051P) {
+ sh->p_ch_cfg = &ch_cfg_p[0];
+ sh->ch_cfg_size =
+ sizeof(ch_cfg_p) / sizeof(struct ssv6xxx_ch_cfg);
+ }
+ switch (sh->cfg.chip_identity) {
+ case SSV6051Q_P1:
+ case SSV6051Q_P2:
+ case SSV6051Q:
+ dev_info(sh->sc->dev, "Using SSV6051Q setting\n");
+ for (i = 0;
+ i <
+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+ i++) {
+ if (ssv6200_rf_tbl[i].address == 0xCE010008)
+ ssv6200_rf_tbl[i].data = 0x008DF61B;
+ if (ssv6200_rf_tbl[i].address == 0xCE010014)
+ ssv6200_rf_tbl[i].data = 0x3D3E84FE;
+ if (ssv6200_rf_tbl[i].address == 0xCE010018)
+ ssv6200_rf_tbl[i].data = 0x01457D79;
+ if (ssv6200_rf_tbl[i].address == 0xCE01001C)
+ ssv6200_rf_tbl[i].data = 0x000103A7;
+ if (ssv6200_rf_tbl[i].address == 0xCE010020)
+ ssv6200_rf_tbl[i].data = 0x000103A6;
+ if (ssv6200_rf_tbl[i].address == 0xCE01002C)
+ ssv6200_rf_tbl[i].data = 0x00032CA8;
+ if (ssv6200_rf_tbl[i].address == 0xCE010048)
+ ssv6200_rf_tbl[i].data = 0xFCCCCF27;
+ if (ssv6200_rf_tbl[i].address == 0xCE010050)
+ ssv6200_rf_tbl[i].data = 0x0047C000;
+ }
+ break;
+ case SSV6051Z:
+ dev_info(sh->sc->dev, "Using SSV6051Z setting\n");
+ for (i = 0;
+ i <
+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+ i++) {
+ if (ssv6200_rf_tbl[i].address == 0xCE010008)
+ ssv6200_rf_tbl[i].data = 0x004D561C;
+ if (ssv6200_rf_tbl[i].address == 0xCE010014)
+ ssv6200_rf_tbl[i].data = 0x3D9E84FE;
+ if (ssv6200_rf_tbl[i].address == 0xCE010018)
+ ssv6200_rf_tbl[i].data = 0x00457D79;
+ if (ssv6200_rf_tbl[i].address == 0xCE01001C)
+ ssv6200_rf_tbl[i].data = 0x000103EB;
+ if (ssv6200_rf_tbl[i].address == 0xCE010020)
+ ssv6200_rf_tbl[i].data = 0x000103EA;
+ if (ssv6200_rf_tbl[i].address == 0xCE01002C)
+ ssv6200_rf_tbl[i].data = 0x00062CA8;
+ if (ssv6200_rf_tbl[i].address == 0xCE010048)
+ ssv6200_rf_tbl[i].data = 0xFCCCCF27;
+ if (ssv6200_rf_tbl[i].address == 0xCE010050)
+ ssv6200_rf_tbl[i].data = 0x0047C000;
+ }
+ break;
+ case SSV6051P:
+ dev_info(sh->sc->dev, "Using SSV6051P setting\n");
+ for (i = 0;
+ i <
+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+ i++) {
+ if (ssv6200_rf_tbl[i].address == 0xCE010008)
+ ssv6200_rf_tbl[i].data = 0x008B7C1C;
+ if (ssv6200_rf_tbl[i].address == 0xCE010014)
+ ssv6200_rf_tbl[i].data = 0x3D7E84FE;
+ if (ssv6200_rf_tbl[i].address == 0xCE010018)
+ ssv6200_rf_tbl[i].data = 0x01457D79;
+ if (ssv6200_rf_tbl[i].address == 0xCE01001C)
+ ssv6200_rf_tbl[i].data = 0x000103EB;
+ if (ssv6200_rf_tbl[i].address == 0xCE010020)
+ ssv6200_rf_tbl[i].data = 0x000103EA;
+ if (ssv6200_rf_tbl[i].address == 0xCE01002C)
+ ssv6200_rf_tbl[i].data = 0x00032CA8;
+ if (ssv6200_rf_tbl[i].address == 0xCE010048)
+ ssv6200_rf_tbl[i].data = 0xFCCCCC27;
+ if (ssv6200_rf_tbl[i].address == 0xCE010050)
+ ssv6200_rf_tbl[i].data = 0x0047C000;
+ if (ssv6200_rf_tbl[i].address == 0xC0001D00)
+ ssv6200_rf_tbl[i].data = 0x5E000040;
+ }
+ break;
+ default:
+ dev_err(sh->sc->dev, "No RF setting\n");
+ break;
+ }
+ if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M) {
+ init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_26M;
+ dev_info(sh->sc->dev, "Crystal frequency: 26 Mhz\n");
+ } else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) {
+ init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_40M;
+ dev_info(sh->sc->dev, "Crystal frequency: 40 Mhz\n");
+ } else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M) {
+ init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_24M;
+ dev_info(sh->sc->dev, "Crystal frequency: 24 Mhz\n");
+ for (i = 0;
+ i <
+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+ i++) {
+ if (ssv6200_rf_tbl[i].address == ADR_SX_ENABLE_REGISTER)
+ ssv6200_rf_tbl[i].data = 0x0003E07C;
+ if (ssv6200_rf_tbl[i].address ==
+ ADR_DPLL_DIVIDER_REGISTER)
+ ssv6200_rf_tbl[i].data = 0x00406000;
+ if (ssv6200_rf_tbl[i].address ==
+ ADR_DPLL_FB_DIVIDER_REGISTERS_I)
+ ssv6200_rf_tbl[i].data = 0x00000028;
+ if (ssv6200_rf_tbl[i].address ==
+ ADR_DPLL_FB_DIVIDER_REGISTERS_II)
+ ssv6200_rf_tbl[i].data = 0x00000000;
+ }
+ } else {
+ dev_warn(sh->sc->dev, "Illegal crystal setting, using default value of 26 Mhz\n");
+ }
+ for (i = 0;
+ i < sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+ i++) {
+ if (ssv6200_rf_tbl[i].address ==
+ ADR_SYN_KVCO_XO_FINE_TUNE_CBANK) {
+ if (sh->cfg.crystal_frequency_offset) {
+ ssv6200_rf_tbl[i].data &=
+ RG_XOSC_CBANK_XO_I_MSK;
+ ssv6200_rf_tbl[i].data |=
+ (sh->cfg.
+ crystal_frequency_offset <<
+ RG_XOSC_CBANK_XO_SFT);
+ }
+ }
+ }
+ for (i = 0; i < sizeof(phy_setting) / sizeof(struct ssv6xxx_dev_table);
+ i++) {
+ if (phy_setting[i].address == ADR_TX_GAIN_FACTOR) {
+ switch (sh->cfg.chip_identity) {
+ case SSV6051Q_P1:
+ case SSV6051Q_P2:
+ case SSV6051Q:
+ dev_dbg(sh->sc->dev, "SSV6051Q setting [0x5B606C72]\n");
+ phy_setting[i].data = 0x5B606C72;
+ break;
+ case SSV6051Z:
+ dev_dbg(sh->sc->dev, "SSV6051Z setting [0x60606060]\n");
+ phy_setting[i].data = 0x60606060;
+ break;
+ case SSV6051P:
+ dev_dbg(sh->sc->dev, "SSV6051P setting [0x6C726C72]\n");
+ phy_setting[i].data = 0x6C726C72;
+ break;
+ default:
+ dev_dbg(sh->sc->dev, "Use default power setting\n");
+ break;
+ }
+ if (sh->cfg.wifi_tx_gain_level_b) {
+ phy_setting[i].data &= 0xffff0000;
+ phy_setting[i].data |=
+ wifi_tx_gain[sh->cfg.
+ wifi_tx_gain_level_b] &
+ 0x0000ffff;
+ }
+ if (sh->cfg.wifi_tx_gain_level_gn) {
+ phy_setting[i].data &= 0x0000ffff;
+ phy_setting[i].data |=
+ wifi_tx_gain[sh->cfg.
+ wifi_tx_gain_level_gn] &
+ 0xffff0000;
+ }
+ dev_dbg(sh->sc->dev, "TX power setting 0x%x\n", phy_setting[i].data);
+ init_iqk_cfg.cfg_def_tx_scale_11b =
+ (phy_setting[i].data >> 0) & 0xff;
+ init_iqk_cfg.cfg_def_tx_scale_11b_p0d5 =
+ (phy_setting[i].data >> 8) & 0xff;
+ init_iqk_cfg.cfg_def_tx_scale_11g =
+ (phy_setting[i].data >> 16) & 0xff;
+ init_iqk_cfg.cfg_def_tx_scale_11g_p0d5 =
+ (phy_setting[i].data >> 24) & 0xff;
+ break;
+ }
+ }
+ if (sh->cfg.volt_regulator == SSV6XXX_VOLT_LDO_CONVERT) {
+ dev_info(sh->sc->dev, "Using LDO voltage regulator\n");
+ for (i = 0;
+ i <
+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+ i++) {
+ if (ssv6200_rf_tbl[i].address == ADR_PMU_2) {
+ ssv6200_rf_tbl[i].data &= 0xFFFFFFFE;
+ ssv6200_rf_tbl[i].data |= 0x00000000;
+ }
+ }
+ } else if (sh->cfg.volt_regulator == SSV6XXX_VOLT_DCDC_CONVERT) {
+ dev_info(sh->sc->dev, "Using DCDC buck regulator\n");
+ for (i = 0;
+ i <
+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+ i++) {
+ if (ssv6200_rf_tbl[i].address == ADR_PMU_2) {
+ ssv6200_rf_tbl[i].data &= 0xFFFFFFFE;
+ ssv6200_rf_tbl[i].data |= 0x00000001;
+ }
+ }
+ } else {
+ dev_warn(sh->sc->dev, "Illegal regulator setting, using DCDC buck as default\n");
+ }
+ while (ssv_cfg.configuration[x][0]) {
+ for (i = 0;
+ i <
+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+ i++) {
+ if (ssv6200_rf_tbl[i].address ==
+ ssv_cfg.configuration[x][0]) {
+ ssv6200_rf_tbl[i].data =
+ ssv_cfg.configuration[x][1];
+ break;
+ }
+ }
+ for (i = 0;
+ i < sizeof(phy_setting) / sizeof(struct ssv6xxx_dev_table);
+ i++) {
+ if (phy_setting[i].address ==
+ ssv_cfg.configuration[x][0]) {
+ phy_setting[i].data =
+ ssv_cfg.configuration[x][1];
+ break;
+ }
+ }
+ x++;
+ };
+ if (ret == 0)
+ ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_rf_tbl);
+ if (ret == 0)
+ ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1, 0x00000000);
+ SMAC_REG_READ(sh, ADR_PHY_EN_0, &regval);
+ if (regval & (1 << RG_RF_BB_CLK_SEL_SFT)) {
+ dev_dbg(sh->sc->dev, "already do clock switch\n");
+ } else {
+ dev_dbg(sh->sc->dev, "reset PLL\n");
+ SMAC_REG_READ(sh, ADR_DPLL_CP_PFD_REGISTER, &regval);
+ regval |=
+ ((1 << RG_DP_BBPLL_PD_SFT) |
+ (1 << RG_DP_BBPLL_SDM_EDGE_SFT));
+ SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval);
+ regval &=
+ ~((1 << RG_DP_BBPLL_PD_SFT) |
+ (1 << RG_DP_BBPLL_SDM_EDGE_SFT));
+ SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval);
+ mdelay(10);
+ }
+ if (ret == 0)
+ ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_phy_tbl);
+ if (ret == 0)
+ ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xEAAAAAAA);
+ SMAC_REG_READ(sh, ADR_TRX_DUMMY_REGISTER, &regval);
+ if (regval != 0xEAAAAAAA) {
+ dev_warn(sh->sc->dev, "Unexpected register value\n");
+ WARN_ON(1);
+ }
+ if (ret == 0)
+ ret = SMAC_REG_WRITE(sh, ADR_PAD53, 0x21);
+ if (ret == 0)
+ ret = SMAC_REG_WRITE(sh, ADR_PAD54, 0x3000);
+ if (ret == 0)
+ ret = SMAC_REG_WRITE(sh, ADR_PIN_SEL_0, 0x4000);
+ if (ret == 0)
+ ret = SMAC_REG_WRITE(sh, 0xc0000304, 0x01);
+ if (ret == 0)
+ ret = SMAC_REG_WRITE(sh, 0xc0000308, 0x01);
+ if (ret == 0)
+ ret = SMAC_REG_WRITE(sh, ADR_CLOCK_SELECTION, 0x3);
+ if (ret == 0)
+ ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xAAAAAAAA);
+ if ((ret = ssv6xxx_set_channel(sh->sc, sh->cfg.def_chan)))
+ return ret;
+ if (ret == 0)
+ ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1,
+ (RG_PHYRX_MD_EN_MSK | RG_PHYTX_MD_EN_MSK |
+ RG_PHY11GN_MD_EN_MSK | RG_PHY11B_MD_EN_MSK
+ | RG_PHYRXFIFO_MD_EN_MSK |
+ RG_PHYTXFIFO_MD_EN_MSK |
+ RG_PHY11BGN_MD_EN_MSK));
+ return ret;
+}
+
+static void ssv6xxx_check_mac2(struct ssv_hw *sh)
+{
+ const u8 addr_mask[6] = { 0xfd, 0xff, 0xff, 0xff, 0xff, 0xfc };
+ u8 i;
+ bool invalid = false;
+ for (i = 0; i < 6; i++) {
+ if ((ssv_cfg.maddr[0][i] & addr_mask[i]) !=
+ (ssv_cfg.maddr[1][i] & addr_mask[i])) {
+ invalid = true;
+ dev_dbg(sh->sc->dev, " i %d , mac1[i] %x, mac2[i] %x, mask %x \n", i,
+ ssv_cfg.maddr[0][i], ssv_cfg.maddr[1][i],
+ addr_mask[i]);
+ break;
+ }
+ }
+ if (invalid) {
+ memcpy(&ssv_cfg.maddr[1][0], &ssv_cfg.maddr[0][0], 6);
+ ssv_cfg.maddr[1][5] ^= 0x01;
+ if (ssv_cfg.maddr[1][5] < ssv_cfg.maddr[0][5]) {
+ u8 temp;
+ temp = ssv_cfg.maddr[0][5];
+ ssv_cfg.maddr[0][5] = ssv_cfg.maddr[1][5];
+ ssv_cfg.maddr[1][5] = temp;
+ sh->cfg.maddr[0][5] = ssv_cfg.maddr[0][5];
+ }
+ dev_warn(sh->sc->dev, "MAC 2 address invalid!!\n");
+ dev_warn(sh->sc->dev, "After modification, MAC1 %pM, MAC2 %pM\n",
+ ssv_cfg.maddr[0], ssv_cfg.maddr[1]);
+ }
+}
+
+static int ssv6xxx_read_configuration(struct ssv_hw *sh)
+{
+ extern u32 sdio_sr_bhvr;
+ if (is_valid_ether_addr(&ssv_cfg.maddr[0][0]))
+ memcpy(&sh->cfg.maddr[0][0], &ssv_cfg.maddr[0][0], ETH_ALEN);
+ if (is_valid_ether_addr(&ssv_cfg.maddr[1][0])) {
+ ssv6xxx_check_mac2(sh);
+ memcpy(&sh->cfg.maddr[1][0], &ssv_cfg.maddr[1][0], ETH_ALEN);
+ }
+ if (ssv_cfg.hw_caps)
+ sh->cfg.hw_caps = ssv_cfg.hw_caps;
+ else
+ sh->cfg.hw_caps = SSV6200_HW_CAP_HT |
+ SSV6200_HW_CAP_2GHZ |
+ SSV6200_HW_CAP_SECURITY |
+ SSV6200_HW_CAP_P2P |
+ SSV6200_HT_CAP_SGI_20 |
+ SSV6200_HW_CAP_AMPDU_RX |
+ SSV6200_HW_CAP_AMPDU_TX | SSV6200_HW_CAP_AP;
+ if (ssv_cfg.def_chan)
+ sh->cfg.def_chan = ssv_cfg.def_chan;
+ else
+ sh->cfg.def_chan = 6;
+ sh->cfg.use_wpa2_only = ssv_cfg.use_wpa2_only;
+ if (ssv_cfg.crystal_type == 26)
+ sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_26M;
+ else if (ssv_cfg.crystal_type == 40)
+ sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_40M;
+ else if (ssv_cfg.crystal_type == 24)
+ sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_24M;
+ else {
+ dev_warn(sh->sc->dev, "Please redefine xtal_clock(wifi.cfg)!!\n");
+ WARN_ON(1);
+ return 1;
+ }
+ if (ssv_cfg.volt_regulator < 2)
+ sh->cfg.volt_regulator = ssv_cfg.volt_regulator;
+ else {
+ dev_warn(sh->sc->dev, "Please redefine volt_regulator(wifi.cfg)!!\n");
+ WARN_ON(1);
+ return 1;
+ }
+ sh->cfg.wifi_tx_gain_level_gn = ssv_cfg.wifi_tx_gain_level_gn;
+ sh->cfg.wifi_tx_gain_level_b = ssv_cfg.wifi_tx_gain_level_b;
+ sh->cfg.rssi_ctl = ssv_cfg.rssi_ctl;
+ sh->cfg.sr_bhvr = ssv_cfg.sr_bhvr;
+ sdio_sr_bhvr = ssv_cfg.sr_bhvr;
+ sh->cfg.force_chip_identity = ssv_cfg.force_chip_identity;
+ strncpy(sh->cfg.firmware_path, ssv_cfg.firmware_path,
+ sizeof(sh->cfg.firmware_path) - 1);
+ strncpy(sh->cfg.flash_bin_path, ssv_cfg.flash_bin_path,
+ sizeof(sh->cfg.flash_bin_path) - 1);
+ strncpy(sh->cfg.mac_address_path, ssv_cfg.mac_address_path,
+ sizeof(sh->cfg.mac_address_path) - 1);
+ strncpy(sh->cfg.mac_output_path, ssv_cfg.mac_output_path,
+ sizeof(sh->cfg.mac_output_path) - 1);
+ sh->cfg.ignore_efuse_mac = ssv_cfg.ignore_efuse_mac;
+ sh->cfg.mac_address_mode = ssv_cfg.mac_address_mode;
+ return 0;
+}
+
+static int ssv6xxx_read_hw_info(struct ssv_softc *sc)
+{
+ struct ssv_hw *sh;
+ sh = kzalloc(sizeof(struct ssv_hw), GFP_KERNEL);
+ if (sh == NULL)
+ return -ENOMEM;
+ memset((void *)sh, 0, sizeof(struct ssv_hw));
+ sc->sh = sh;
+ sh->sc = sc;
+ sh->priv = sc->dev->platform_data;
+ if (ssv6xxx_read_configuration(sh))
+ return -ENOMEM;
+ sh->hci.dev = sc->dev;
+ sh->hci.hci_ops = NULL;
+ sh->hci.hci_rx_cb = ssv6200_rx;
+ sh->hci.rx_cb_args = (void *)sc;
+ sh->hci.hci_tx_cb = ssv6xxx_tx_cb;
+ sh->hci.tx_cb_args = (void *)sc;
+ sh->hci.hci_skb_update_cb = ssv6xxx_tx_rate_update;
+ sh->hci.skb_update_args = (void *)sc;
+ sh->hci.hci_tx_flow_ctrl_cb = ssv6200_tx_flow_control;
+ sh->hci.tx_fctrl_cb_args = (void *)sc;
+ sh->hci.hci_tx_q_empty_cb = ssv6xxx_tx_q_empty_cb;
+ sh->hci.tx_q_empty_args = (void *)sc;
+ sh->hci.if_ops = sh->priv->ops;
+ sh->hci.hci_tx_buf_free_cb = ssv6xxx_txbuf_free_skb;
+ sh->hci.tx_buf_free_args = (void *)sc;
+ return 0;
+}
+
+static int ssv6xxx_init_device(struct ssv_softc *sc, const char *name)
+{
+ struct ieee80211_hw *hw = sc->hw;
+ struct ssv_hw *sh;
+ int error = 0;
+ BUG_ON(!sc->dev->platform_data);
+ if ((error = ssv6xxx_read_hw_info(sc)) != 0) {
+ return error;
+ }
+ sh = sc->sh;
+ if (sh->cfg.hw_caps == 0)
+ return -1;
+ ssv6xxx_hci_register(&sh->hci);
+ efuse_read_all_map(sh);
+ if ((error = ssv6xxx_init_softc(sc)) != 0) {
+ ssv6xxx_deinit_softc(sc);
+ ssv6xxx_hci_deregister();
+ kfree(sh);
+ return error;
+ }
+ if ((error = ssv6xxx_init_hw(sc->sh)) != 0) {
+ ssv6xxx_deinit_hw(sc);
+ ssv6xxx_deinit_softc(sc);
+ ssv6xxx_hci_deregister();
+ kfree(sh);
+ return error;
+ }
+ if ((error = ieee80211_register_hw(hw)) != 0) {
+ dev_err(sc->dev, "Failed to register ieee80211 wireless device. ret=%d.\n", error);
+ ssv6xxx_deinit_hw(sc);
+ ssv6xxx_deinit_softc(sc);
+ ssv6xxx_hci_deregister();
+ kfree(sh);
+ return error;
+ }
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ ssv6xxx_init_debugfs(sc, name);
+#endif
+ return 0;
+}
+
+static void ssv6xxx_deinit_device(struct ssv_softc *sc)
+{
+ dev_dbg(sc->dev, "%s(): \n", __FUNCTION__);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ ssv6xxx_deinit_debugfs(sc);
+#endif
+ ssv6xxx_rf_disable(sc->sh);
+ ieee80211_unregister_hw(sc->hw);
+ ssv6xxx_deinit_hw(sc);
+ ssv6xxx_deinit_softc(sc);
+ ssv6xxx_hci_deregister();
+ kfree(sc->sh);
+}
+
+extern struct ieee80211_ops ssv6200_ops;
+int ssv6xxx_dev_probe(struct platform_device *pdev)
+{
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+ extern struct ssv_softc *ssv_dbg_sc;
+#endif
+#ifdef CONFIG_SSV_SMARTLINK
+ extern struct ssv_softc *ssv_smartlink_sc;
+#endif
+ struct ssv_softc *softc;
+ struct ieee80211_hw *hw;
+ int ret;
+ if (!pdev->dev.platform_data) {
+ dev_err(&pdev->dev, "no platform data specified!\n");
+ return -EINVAL;
+ }
+ hw = ieee80211_alloc_hw(sizeof(struct ssv_softc), &ssv6200_ops);
+ if (hw == NULL) {
+ dev_err(&pdev->dev, "Could not allocate memory for ieee80211 wireless device\n");
+ return -ENOMEM;
+ }
+ SET_IEEE80211_DEV(hw, &pdev->dev);
+ dev_set_drvdata(&pdev->dev, hw);
+ memset((void *)hw->priv, 0, sizeof(struct ssv_softc));
+ softc = hw->priv;
+ softc->hw = hw;
+ softc->dev = &pdev->dev;
+ //SET_IEEE80211_PERM_ADDR(hw, (const u8 *)&softc->sh->maddr[0]);
+ ret = ssv6xxx_init_device(softc, pdev->name);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to initialize device\n");
+ ieee80211_free_hw(hw);
+ return ret;
+ }
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+ ssv_dbg_sc = softc;
+#endif
+#ifdef CONFIG_SSV_SMARTLINK
+ ssv_smartlink_sc = softc;
+#endif
+ wiphy_info(hw->wiphy, "%s\n", "SSV6200 of South Silicon Valley");
+ return 0;
+}
+
+EXPORT_SYMBOL(ssv6xxx_dev_probe);
+int ssv6xxx_dev_remove(struct platform_device *pdev)
+{
+ struct ieee80211_hw *hw = dev_get_drvdata(&pdev->dev);
+ struct ssv_softc *softc = hw->priv;
+ dev_dbg(&pdev->dev, "ssv6xxx_dev_remove(): pdev=%p, hw=%p\n", pdev, hw);
+ ssv6xxx_deinit_device(softc);
+ dev_dbg(&pdev->dev, "ieee80211_free_hw(): \n");
+ ieee80211_free_hw(hw);
+ dev_info(&pdev->dev, "driver unloaded\n");
+ return 0;
+}
+
+EXPORT_SYMBOL(ssv6xxx_dev_remove);
+static const struct platform_device_id ssv6xxx_id_table[] = {
+ {
+ .name = "ssv6200",
+ .driver_data = 0x00,
+ },
+ {},
+};
+
+MODULE_DEVICE_TABLE(platform, ssv6xxx_id_table);
+static struct platform_driver ssv6xxx_driver = {
+ .probe = ssv6xxx_dev_probe,
+ .remove = ssv6xxx_dev_remove,
+ .id_table = ssv6xxx_id_table,
+ .driver = {
+ .name = "SSV WLAN driver",
+ .owner = THIS_MODULE,
+ }
+};
+
+int ssv6xxx_init(void)
+{
+ extern void *ssv_dbg_phy_table;
+ extern u32 ssv_dbg_phy_len;
+ extern void *ssv_dbg_rf_table;
+ extern u32 ssv_dbg_rf_len;
+ ssv_dbg_phy_table = (void *)ssv6200_phy_tbl;
+ ssv_dbg_phy_len =
+ sizeof(ssv6200_phy_tbl) / sizeof(struct ssv6xxx_dev_table);
+ ssv_dbg_rf_table = (void *)ssv6200_rf_tbl;
+ ssv_dbg_rf_len =
+ sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+ return platform_driver_register(&ssv6xxx_driver);
+}
+
+void ssv6xxx_exit(void)
+{
+ platform_driver_unregister(&ssv6xxx_driver);
+}
+
+EXPORT_SYMBOL(ssv6xxx_init);
+EXPORT_SYMBOL(ssv6xxx_exit);
diff --git a/drivers/net/wireless/ssv6051/smac/init.h b/drivers/net/wireless/ssv6051/smac/init.h
new file mode 100644
index 000000000000..97994d00d4da
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/init.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _INIT_H_
+#define _INIT_H_
+int ssv6xxx_init_mac(struct ssv_hw *sh);
+int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg);
+void ssv6xxx_deinit_mac(struct ssv_softc *sc);
+void ssv6xxx_restart_hw(struct ssv_softc *sc);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/lib.c b/drivers/net/wireless/ssv6051/smac/lib.c
new file mode 100644
index 000000000000..ccf0974b0f20
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/lib.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200.h>
+#include "lib.h"
+struct sk_buff *ssv_skb_alloc(s32 len)
+{
+ struct sk_buff *skb;
+ skb = __dev_alloc_skb(len + 128, GFP_KERNEL);
+ if (skb != NULL) {
+ skb_put(skb, 0x20);
+ skb_pull(skb, 0x20);
+ }
+ return skb;
+}
+
+void ssv_skb_free(struct sk_buff *skb)
+{
+ dev_kfree_skb_any(skb);
+}
diff --git a/drivers/net/wireless/ssv6051/smac/lib.h b/drivers/net/wireless/ssv6051/smac/lib.h
new file mode 100644
index 000000000000..266cf7afac95
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/lib.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _LIB_H_
+#define _LIB_H_
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+struct sk_buff *ssv_skb_alloc(s32 len);
+void ssv_skb_free(struct sk_buff *skb);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/linux_80211.h b/drivers/net/wireless/ssv6051/smac/linux_80211.h
new file mode 100644
index 000000000000..e268808e3c93
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/linux_80211.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _LINUX_80211_H_
+#define _LINUX_80211_H_
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
+#define INDEX_80211_BAND_2GHZ IEEE80211_BAND_2GHZ
+#else
+#define INDEX_80211_BAND_2GHZ NL80211_BAND_2GHZ
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/p2p.c b/drivers/net/wireless/ssv6051/smac/p2p.c
new file mode 100644
index 000000000000..60fd8effd6ec
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/p2p.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200.h>
+#include <linux/types.h>
+#include <linux/nl80211.h>
+#include <net/mac80211.h>
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <linux/kthread.h>
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include "p2p.h"
+#include "dev.h"
+#include "lib.h"
+#ifdef CONFIG_P2P_NOA
+#define P2P_IE_VENDOR_TYPE 0x506f9a09
+#define P2P_NOA_DETECT_INTERVAL (5 * HZ)
+#ifndef MAC2STR
+#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
+#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
+#define COMPACT_MACSTR "%02x%02x%02x%02x%02x%02x"
+#endif
+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
+ struct ssv6xxx_p2p_noa_param *p2p_noa_param);
+static inline u32 WPA_GET_BE32(const u8 * a)
+{
+ return (a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3];
+}
+
+static inline u16 WPA_GET_LE16(const u8 * a)
+{
+ return (a[1] << 8) | a[0];
+}
+
+static inline u32 WPA_GET_LE32(const u8 * a)
+{
+ return (a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0];
+}
+
+#define IEEE80211_HDRLEN 24
+enum p2p_attr_id {
+ P2P_ATTR_STATUS = 0,
+ P2P_ATTR_MINOR_REASON_CODE = 1,
+ P2P_ATTR_CAPABILITY = 2,
+ P2P_ATTR_DEVICE_ID = 3,
+ P2P_ATTR_GROUP_OWNER_INTENT = 4,
+ P2P_ATTR_CONFIGURATION_TIMEOUT = 5,
+ P2P_ATTR_LISTEN_CHANNEL = 6,
+ P2P_ATTR_GROUP_BSSID = 7,
+ P2P_ATTR_EXT_LISTEN_TIMING = 8,
+ P2P_ATTR_INTENDED_INTERFACE_ADDR = 9,
+ P2P_ATTR_MANAGEABILITY = 10,
+ P2P_ATTR_CHANNEL_LIST = 11,
+ P2P_ATTR_NOTICE_OF_ABSENCE = 12,
+ P2P_ATTR_DEVICE_INFO = 13,
+ P2P_ATTR_GROUP_INFO = 14,
+ P2P_ATTR_GROUP_ID = 15,
+ P2P_ATTR_INTERFACE = 16,
+ P2P_ATTR_OPERATING_CHANNEL = 17,
+ P2P_ATTR_INVITATION_FLAGS = 18,
+ P2P_ATTR_OOB_GO_NEG_CHANNEL = 19,
+ P2P_ATTR_VENDOR_SPECIFIC = 221
+};
+struct ssv6xxx_p2p_noa_attribute {
+ u8 index;
+ u16 ctwindows_oppps;
+ struct ssv6xxx_p2p_noa_param noa_param;
+};
+extern void _ssv6xxx_hexdump(const char *title, const u8 * buf, size_t len);
+bool p2p_find_noa(const u8 * ies, struct ssv6xxx_p2p_noa_attribute *noa_attr)
+{
+ const u8 *end, *pos, *ie;
+ u32 len;
+ len = ie[1] - 4;
+ pos = ie + 6;
+ end = pos + len;
+ while (pos < end) {
+ u16 attr_len;
+ if (pos + 2 >= end) {
+ return false;
+ }
+ attr_len = WPA_GET_LE16(pos + 1);
+ if (pos + 3 + attr_len > end) {
+ return false;
+ }
+ if (pos[0] != P2P_ATTR_NOTICE_OF_ABSENCE) {
+ pos += 3 + attr_len;
+ continue;
+ }
+ if (attr_len < 15) {
+ printk
+ ("*********************NOA descriptor does not exist len[%d]\n",
+ attr_len);
+ break;
+ }
+ if (attr_len > 15)
+ printk("More than one NOA descriptor\n");
+ noa_attr->index = pos[3];
+ noa_attr->ctwindows_oppps = pos[4];
+ noa_attr->noa_param.count = pos[5];
+ noa_attr->noa_param.duration = WPA_GET_LE32(&pos[6]);
+ noa_attr->noa_param.interval = WPA_GET_LE32(&pos[10]);
+ noa_attr->noa_param.start_time = WPA_GET_LE32(&pos[14]);
+ return true;
+ }
+ return false;
+}
+
+bool p2p_get_attribute_noa(const u8 * ies, u32 oui_type,
+ struct ssv6xxx_p2p_noa_attribute *noa_attr)
+{
+ const u8 *end, *pos, *ie;
+ u32 len;
+ pos = ies;
+ end = ies + ies_len;
+ ie = NULL;
+ while (pos + 1 < end) {
+ if (pos + 2 + pos[1] > end)
+ return false;
+ if (pos[0] == WLAN_EID_VENDOR_SPECIFIC && pos[1] >= 4 &&
+ WPA_GET_BE32(&pos[2]) == oui_type) {
+ ie = pos;
+ if (p2p_find_noa(ie, 0, noa_attr) == true)
+ return true;
+ }
+ pos += 2 + pos[1];
+ }
+ return false;
+}
+
+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb)
+{
+ struct cfg_host_event *host_event;
+ struct ssv62xx_noa_evt *noa_evt;
+ host_event = (struct cfg_host_event *)skb->data;
+ noa_evt = (struct ssv62xx_noa_evt *)&host_event->dat[0];
+ switch (noa_evt->evt_id) {
+ case SSV6XXX_NOA_START:
+ sc->p2p_noa.active_noa_vif |= (1 << noa_evt->vif);
+ printk("SSV6XXX_NOA_START===>[%08x]\n",
+ sc->p2p_noa.active_noa_vif);
+ break;
+ case SSV6XXX_NOA_STOP:
+ sc->p2p_noa.active_noa_vif &= ~(1 << noa_evt->vif);
+ printk("SSV6XXX_NOA_STOP===>[%08x]\n",
+ sc->p2p_noa.active_noa_vif);
+ break;
+ default:
+ printk("--------->NOA wrong command<---------\n");
+ break;
+ }
+}
+
+void ssv6xxx_noa_reset(struct ssv_softc *sc)
+{
+ unsigned long flags;
+ printk("Reset NOA param...\n");
+ spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
+ memset(&sc->p2p_noa.noa_detect, 0,
+ sizeof(struct ssv_p2p_noa_detect) * SSV_NUM_VIF);
+ sc->p2p_noa.active_noa_vif = 0;
+ sc->p2p_noa.monitor_noa_vif = 0;
+ spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
+}
+
+void ssv6xxx_noa_host_stop_noa(struct ssv_softc *sc, u8 vif_id)
+{
+ struct ssv6xxx_p2p_noa_attribute noa_attr;
+ if (sc->p2p_noa.noa_detect[vif_id].p2p_noa_index >= 0) {
+ sc->p2p_noa.noa_detect[vif_id].p2p_noa_index = -1;
+ sc->p2p_noa.active_noa_vif &= ~(1 << vif_id);
+ memset(&sc->p2p_noa.noa_detect[vif_id].noa_param_cmd, 0,
+ sizeof(struct ssv6xxx_p2p_noa_param));
+ printk("->remove NOA operating vif[%d]\n", vif_id);
+ noa_attr.noa_param.enable = 0;
+ noa_attr.noa_param.vif_id = vif_id;
+ ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param);
+ }
+}
+
+void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr *hdr,
+ u32 len)
+{
+ int i;
+ unsigned long flags;
+ struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
+ struct ssv6xxx_p2p_noa_attribute noa_attr;
+ spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
+ if (sc->p2p_noa.monitor_noa_vif == 0)
+ goto out;
+ for (i = 0; i < SSV_NUM_VIF; i++) {
+ if (sc->p2p_noa.noa_detect[i].noa_addr == NULL)
+ continue;
+ if (memcmp(mgmt->bssid, sc->p2p_noa.noa_detect[i].noa_addr, 6)
+ != 0)
+ continue;
+ if (sc->p2p_noa.active_noa_vif &&
+ ((sc->p2p_noa.active_noa_vif & 1 << i) == 0))
+ continue;
+ sc->p2p_noa.noa_detect[i].last_rx = jiffies;
+ if (p2p_get_attribute_noa((const u8 *)mgmt->u.beacon.variable,
+ len - (IEEE80211_HDRLEN +
+ sizeof(mgmt->u.beacon)),
+ P2P_IE_VENDOR_TYPE,
+ &noa_attr) == false) {
+ continue;
+ }
+ if (sc->p2p_noa.noa_detect[i].p2p_noa_index == noa_attr.index) {
+ goto out;
+ }
+ printk(MACSTR "->set NOA element\n", MAC2STR(mgmt->bssid));
+ sc->p2p_noa.active_noa_vif |= (1 << i);
+ sc->p2p_noa.noa_detect[i].p2p_noa_index = noa_attr.index;
+ memcpy(&sc->p2p_noa.noa_detect[i].noa_param_cmd,
+ &noa_attr.noa_param,
+ sizeof(struct ssv6xxx_p2p_noa_param));
+ noa_attr.noa_param.enable = 1;
+ noa_attr.noa_param.vif_id = i;
+ memcpy(noa_attr.noa_param.addr, hdr->addr2, 6);
+ ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param);
+ }
+ out:
+ spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
+}
+
+void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc,
+ enum ssv6xxx_noa_conf conf, u8 vif_idx)
+{
+ unsigned long flags;
+ if (sc->vif_info[vif_idx].vif->type != NL80211_IFTYPE_STATION ||
+ sc->vif_info[vif_idx].vif->p2p != true)
+ return;
+ spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
+ printk("====>[NOA]ssv6xxx_noa_hdl_bss_change conf[%d] vif_idx[%d]\n",
+ conf, vif_idx);
+ switch (conf) {
+ case MONITOR_NOA_CONF_ADD:
+ memset(&sc->p2p_noa.noa_detect[vif_idx], 0,
+ sizeof(struct ssv_p2p_noa_detect));
+ sc->p2p_noa.noa_detect[vif_idx].noa_addr =
+ sc->vif_info[vif_idx].vif->bss_conf.bssid;
+ sc->p2p_noa.noa_detect[vif_idx].p2p_noa_index = -1;
+ sc->p2p_noa.noa_detect[vif_idx].last_rx = jiffies;
+ sc->p2p_noa.monitor_noa_vif |= 1 << vif_idx;
+ break;
+ case MONITOR_NOA_CONF_REMOVE:
+ sc->p2p_noa.monitor_noa_vif &= ~(1 << vif_idx);
+ sc->p2p_noa.noa_detect[vif_idx].noa_addr = NULL;
+ ssv6xxx_noa_host_stop_noa(sc, vif_idx);
+ break;
+ default:
+ break;
+ }
+ spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
+}
+
+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
+ struct ssv6xxx_p2p_noa_param *p2p_noa_param)
+{
+ struct sk_buff *skb;
+ struct cfg_host_cmd *host_cmd;
+ int retry_cnt = 5;
+ skb =
+ ssv_skb_alloc(HOST_CMD_HDR_LEN +
+ sizeof(struct ssv6xxx_p2p_noa_param));
+ skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param);
+ skb->len = skb->data_len;
+ host_cmd = (struct cfg_host_cmd *)skb->data;
+ host_cmd->c_type = HOST_CMD;
+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_SET_NOA;
+ host_cmd->len = skb->data_len;
+ memcpy(host_cmd->dat32, p2p_noa_param,
+ sizeof(struct ssv6xxx_p2p_noa_param));
+ printk
+ ("Noa cmd NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]vif[%d]\n\n",
+ p2p_noa_param->enable, p2p_noa_param->interval,
+ p2p_noa_param->duration, p2p_noa_param->start_time,
+ p2p_noa_param->count, p2p_noa_param->addr[0],
+ p2p_noa_param->addr[1], p2p_noa_param->addr[2],
+ p2p_noa_param->addr[3], p2p_noa_param->addr[4],
+ p2p_noa_param->addr[5], p2p_noa_param->vif_id);
+ while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
+ printk(KERN_INFO "NOA cmd retry=%d!!\n", retry_cnt);
+ retry_cnt--;
+ }
+ ssv_skb_free(skb);
+}
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/p2p.h b/drivers/net/wireless/ssv6051/smac/p2p.h
new file mode 100644
index 000000000000..a5bb99c61bb0
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/p2p.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _P2P_H_
+#define _P2P_H_
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include "drv_comm.h"
+#ifdef CONFIG_P2P_NOA
+#define P2P_MAX_NOA_INTERFACE 1
+struct ssv_p2p_noa_detect {
+ const u8 *noa_addr;
+ s16 p2p_noa_index;
+ unsigned long last_rx;
+ struct ssv6xxx_p2p_noa_param noa_param_cmd;
+};
+struct ssv_p2p_noa {
+ spinlock_t p2p_config_lock;
+ struct ssv_p2p_noa_detect noa_detect[SSV_NUM_VIF];
+ u8 active_noa_vif;
+ u8 monitor_noa_vif;
+};
+enum ssv_cmd_state {
+ SSC_CMD_STATE_IDLE,
+ SSC_CMD_STATE_WAIT_RSP,
+};
+struct ssv_cmd_Info {
+ struct sk_buff_head cmd_que;
+ struct sk_buff_head evt_que;
+ enum ssv_cmd_state state;
+};
+enum ssv6xxx_noa_conf {
+ MONITOR_NOA_CONF_ADD,
+ MONITOR_NOA_CONF_REMOVE,
+};
+struct ssv_softc;
+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);
+void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc,
+ enum ssv6xxx_noa_conf conf, u8 vif_idx);
+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);
+void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr *hdr,
+ u32 len);
+void ssv6xxx_noa_reset(struct ssv_softc *sc);
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/sar.c b/drivers/net/wireless/ssv6051/smac/sar.c
new file mode 100644
index 000000000000..44a47a5c7a0f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/sar.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200_reg.h>
+#include <ssv6200_aux.h>
+#include <linux/fs.h>
+#include "dev.h"
+#include "sar.h"
+
+WIFI_FLASH_CCFG flash_cfg = {
+ //16bytes
+ 0x6051, 0x3009, 0x20170519, 0x1, 0x0, 0x0,
+ { //16bytes
+ {0x47c000, 0x47c000, 0x47c000, 0x9, 0x1d, 0x0},
+ //16bytes
+ {0x79807980, 0x79807980, 0x79807980, 0x9, 0x1d, 0x0}
+ }
+};
+
+WIFI_FLASH_CCFG *pflash_cfg;
+
+struct t_sar_info sar_info[] = {
+ {SAR_LVL_INVALID, 0x0047c000, NULL},
+ {SAR_LVL_INVALID, 0x79807980, NULL}
+};
+
+int sar_info_size = sizeof(sar_info) / sizeof(sar_info[0]);
+
+static u8 get_sar_lvl(u32 sar)
+{
+ static u32 prev_sar = 0;
+ int i;
+ u8 changed = 0x0;
+
+ if (sar == prev_sar)
+ return changed;
+
+ pr_debug("[thermal_sar] %d\n", (int)sar);
+
+ for (i = 0; i < sar_info_size; i++) {
+ if (sar_info[i].lvl == SAR_LVL_INVALID) { //if driver loaded under LT/HT env, it would cause wrong settings at this time.
+ sar_info[i].lvl = SAR_LVL_RT;
+ sar_info[i].value = sar_info[i].p->rt;
+ changed |= BIT(i);
+ } else if (sar_info[i].lvl == SAR_LVL_RT) {
+ if (sar < prev_sar) {
+ if (sar <= (u32) (sar_info[i].p->lt_ts - 2)) { //we need check if (g_tt_lt - 1) < SAR_MIN
+ sar_info[i].lvl = SAR_LVL_LT;
+ sar_info[i].value = sar_info[i].p->lt;
+ changed |= BIT(i);
+ }
+ } else if (sar > prev_sar) {
+ if (sar >= (u32) (sar_info[i].p->ht_ts + 2)) { //we need check if (g_tt_lt + 1) > SAR_MAX
+ sar_info[i].lvl = SAR_LVL_HT;
+ sar_info[i].value = sar_info[i].p->ht;
+ changed |= BIT(i);
+ }
+ }
+ } else if (sar_info[i].lvl == SAR_LVL_LT) {
+ if (sar >= (u32) (sar_info[i].p->lt_ts + 2)) {
+ sar_info[i].lvl = SAR_LVL_RT;
+ sar_info[i].value = sar_info[i].p->rt;
+ changed |= BIT(i);
+ }
+ } else if (sar_info[i].lvl == SAR_LVL_HT) {
+ if (sar <= (u32) (sar_info[i].p->ht_ts - 2)) {
+ sar_info[i].lvl = SAR_LVL_RT;
+ sar_info[i].value = sar_info[i].p->rt;
+ changed |= BIT(i);
+ }
+ }
+ }
+ if (changed) {
+ pr_debug("changed: 0x%x\n", changed);
+ }
+ prev_sar = sar;
+ return changed;
+}
+
+void sar_monitor(u32 curr_sar, struct ssv_softc *sc)
+{
+ //static u32 prev_sar_lvl = SAR_LVL_INVALID; //sar = 0, temparature < -25C
+ u8 changed;
+ changed = get_sar_lvl(curr_sar);
+
+ if (changed & BIT(SAR_TXGAIN_INDEX)) {
+ dev_dbg(sc->dev, "TXGAIN: 0x%08x\n", sar_info[SAR_TXGAIN_INDEX].value);
+ SMAC_REG_WRITE(sc->sh, ADR_TX_GAIN_FACTOR,
+ sar_info[SAR_TXGAIN_INDEX].value);
+ }
+ if (changed & BIT(SAR_XTAL_INDEX)) {
+ dev_dbg(sc->dev, "XTAL: 0x%08x\n", sar_info[SAR_XTAL_INDEX].value);
+ SMAC_REG_WRITE(sc->sh, ADR_SYN_KVCO_XO_FINE_TUNE_CBANK,
+ sar_info[SAR_XTAL_INDEX].value);
+ }
+}
+
+/*
+ SET_RG_SARADC_THERMAL(1); //ce010030[26]
+ SET_RG_EN_SARADC(1); //ce010030[30]
+ while(!GET_SAR_ADC_FSM_RDY); //ce010094[23]
+ sar_code = GET_RG_SARADC_BIT; //ce010094[21:16]
+ SET_RG_SARADC_THERMAL(0);
+ SET_RG_EN_SARADC(0);
+*/
+void thermal_monitor(struct work_struct *work)
+{
+ struct ssv_softc *sc =
+ container_of(work, struct ssv_softc, thermal_monitor_work.work);
+ u32 curr_sar;
+
+ u32 temp;
+ if (sc->ps_status == PWRSV_PREPARE) {
+ dev_dbg(sc->dev, "sar PWRSV_PREPARE\n");
+ return;
+ }
+
+ mutex_lock(&sc->mutex);
+ SMAC_REG_READ(sc->sh, ADR_RX_11B_CCA_1, &temp);
+ if (temp == RX_11B_CCA_IN_SCAN) {
+ dev_dbg(sc->dev, "in scan\n");
+ mutex_unlock(&sc->mutex);
+ queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
+ THERMAL_MONITOR_TIME);
+ return;
+ }
+ SMAC_REG_READ(sc->sh, ADR_RX_ADC_REGISTER, &temp);
+ //printk("ori %08x:%08x\n", ADR_RX_ADC_REGISTER, temp);
+ SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER,
+ (1 << RG_SARADC_THERMAL_SFT), RG_SARADC_THERMAL_MSK);
+ SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, (1 << RG_EN_SARADC_SFT),
+ RG_EN_SARADC_MSK);
+
+ do {
+ msleep(1);
+ SMAC_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1, &temp);
+ } while (((temp & SAR_ADC_FSM_RDY_MSK) >> SAR_ADC_FSM_RDY_SFT) != 1);
+ //printk("SAR_ADC_FSM_RDY_STAT %d\n", (temp & SAR_ADC_FSM_RDY_MSK) >> SAR_ADC_FSM_RDY_SFT);
+ curr_sar = (temp & RG_SARADC_BIT_MSK) >> RG_SARADC_BIT_SFT;
+ SMAC_REG_READ(sc->sh, ADR_RX_ADC_REGISTER, &temp);
+
+ //printk("new %08x:%08x\n", ADR_RX_ADC_REGISTER, temp);
+
+ SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER,
+ (0 << RG_SARADC_THERMAL_SFT), RG_SARADC_THERMAL_MSK);
+ SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, (0 << RG_EN_SARADC_SFT),
+ RG_EN_SARADC_MSK);
+ sar_monitor(curr_sar, sc);
+
+ mutex_unlock(&sc->mutex);
+
+ queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
+ THERMAL_MONITOR_TIME);
+}
+
+int get_flash_info(struct ssv_softc *sc)
+{
+ struct file *fp = (struct file *)NULL;
+ int i, ret;
+
+ pflash_cfg = &flash_cfg;
+
+ if (sc->sh->cfg.flash_bin_path[0] != 0x00) {
+ fp = filp_open(sc->sh->cfg.flash_bin_path, O_RDONLY, 0);
+ if (IS_ERR(fp) || fp == NULL) {
+ fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0);
+ }
+ } else {
+ fp = filp_open(DEFAULT_CFG_BIN_NAME, O_RDONLY, 0);
+ if (IS_ERR(fp) || fp == NULL) {
+ fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0);
+ }
+ }
+ if (IS_ERR(fp) || fp == NULL) {
+ dev_info(sc->dev, "flash_file %s not found, disable sar\n",
+ DEFAULT_CFG_BIN_NAME);
+ //WARN_ON(1);
+ ret = 0;
+ return ret;
+ }
+
+ fp->f_op->read(fp, (char *)pflash_cfg, sizeof(flash_cfg), &fp->f_pos);
+
+ filp_close(fp, NULL);
+ ret = 1;
+
+ for (i = 0; i < sar_info_size; i++) {
+ sar_info[i].p = &flash_cfg.sar_rlh[i];
+ dev_dbg(sc->dev, "rt = %x, lt = %x, ht = %x\n", sar_info[i].p->rt,
+ sar_info[i].p->lt, sar_info[i].p->ht);
+ dev_dbg(sc->dev, "lt_ts = %x, ht_ts = %x\n", sar_info[i].p->lt_ts,
+ sar_info[i].p->ht_ts);
+ }
+ return ret;
+}
diff --git a/drivers/net/wireless/ssv6051/smac/sar.h b/drivers/net/wireless/ssv6051/smac/sar.h
new file mode 100644
index 000000000000..291d58f236eb
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/sar.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _CFG_H_
+#define _CFG_H_
+#include <linux/kthread.h>
+
+#define SAR_XTAL_INDEX (0)
+#define SAR_TXGAIN_INDEX (1)
+#define THERMAL_MONITOR_TIME (10 * HZ)
+#define DEFAULT_CFG_BIN_NAME "/lib/firmware/ssv6051_sar.bin"
+#define SEC_CFG_BIN_NAME "/lib/firmware/ssv6xxx_sar.bin"
+enum {
+ SAR_LVL_LT,
+ SAR_LVL_RT,
+ SAR_LVL_HT,
+ SAR_LVL_INVALID
+};
+
+struct flash_thermal_info {
+ u32 rt;
+ u32 lt;
+ u32 ht;
+ u8 lt_ts;
+ u8 ht_ts;
+ u16 reserve;
+};
+typedef struct t_WIFI_FLASH_CCFG {
+ //16bytes
+ u16 chip_id;
+ u16 sid;
+ u32 date;
+ u16 version;
+ u16 reserve_1;
+ u32 reserve_2;
+ //16bytes
+ struct flash_thermal_info sar_rlh[2];
+} WIFI_FLASH_CCFG;
+
+struct t_sar_info {
+ u32 lvl;
+ u32 value;
+ struct flash_thermal_info *p;
+};
+
+void thermal_monitor(struct work_struct *work);
+int get_flash_info(struct ssv_softc *sc);
+void flash_hexdump(void);
+
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/sec.h b/drivers/net/wireless/ssv6051/smac/sec.h
new file mode 100644
index 000000000000..04a0f47c8ce2
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/sec.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SEC_H
+#define SEC_H
+#include <linux/types.h>
+#include <linux/ieee80211.h>
+#include <net/mac80211.h>
+#define CCMP_TK_LEN 16
+#define TKIP_KEY_LEN 32
+#define WEP_KEY_LEN 13
+struct ssv_crypto_ops {
+ const char *name;
+ struct list_head list;
+ void *(*init)(int keyidx);
+ void (*deinit)(void *priv);
+ int (*encrypt_mpdu)(struct sk_buff * skb, int hdr_len, void *priv);
+ int (*decrypt_mpdu)(struct sk_buff * skb, int hdr_len, void *priv);
+ int (*encrypt_msdu)(struct sk_buff * skb, int hdr_len, void *priv);
+ int (*decrypt_msdu)(struct sk_buff * skb, int keyidx, int hdr_len,
+ void *priv);
+ int (*set_tx_pn)(u8 * seq, void *priv);
+ int (*set_key)(void *key, int len, u8 * seq, void *priv);
+ int (*get_key)(void *key, int len, u8 * seq, void *priv);
+ char *(*print_stats)(char *p, void *priv);
+ unsigned long (*get_flags)(void *priv);
+ unsigned long (*set_flags)(unsigned long flags, void *priv);
+ int extra_mpdu_prefix_len, extra_mpdu_postfix_len;
+ int extra_msdu_prefix_len, extra_msdu_postfix_len;
+};
+struct ssv_crypto_data {
+ struct ssv_crypto_ops *ops;
+ void *priv;
+ rwlock_t lock;
+};
+struct ssv_crypto_ops *get_crypto_ccmp_ops(void);
+struct ssv_crypto_ops *get_crypto_tkip_ops(void);
+struct ssv_crypto_ops *get_crypto_wep_ops(void);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/smartlink.c b/drivers/net/wireless/ssv6051/smac/smartlink.c
new file mode 100644
index 000000000000..69e8d5118e09
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/smartlink.c
@@ -0,0 +1,340 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <net/sock.h>
+#include <linux/socket.h>
+#include <linux/net.h>
+#include <asm/types.h>
+#include <linux/netlink.h>
+#include <linux/skbuff.h>
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "lib.h"
+#include "dev.h"
+#define NETLINK_SMARTLINK (31)
+#define MAX_PAYLOAD (2048)
+static struct sock *nl_sk = NULL;
+struct ssv_softc *ssv_smartlink_sc = NULL;
+EXPORT_SYMBOL(ssv_smartlink_sc);
+u32 ssv_smartlink_status = 0;
+static int _ksmartlink_start_smartlink(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+ u32 * pOutBufLen)
+{
+#ifdef KSMARTLINK_DEBUG
+ printk(KERN_INFO "%s\n", __FUNCTION__);
+#endif
+ ssv_smartlink_status = 1;
+ *pOutBufLen = 0;
+ return 0;
+}
+
+int ksmartlink_smartlink_started(void)
+{
+ return ssv_smartlink_status;
+}
+
+EXPORT_SYMBOL(ksmartlink_smartlink_started);
+static int _ksmartlink_stop_smartlink(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+ u32 * pOutBufLen)
+{
+#ifdef KSMARTLINK_DEBUG
+ printk(KERN_INFO "%s\n", __FUNCTION__);
+#endif
+ ssv_smartlink_status = 0;
+ *pOutBufLen = 0;
+ return 0;
+}
+
+static int _ksmartlink_set_channel(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+ u32 * pOutBufLen)
+{
+ int ret = -10;
+ int ch = (int)(*pInBuf);
+ struct ssv_softc *sc = ssv_smartlink_sc;
+#ifdef KSMARTLINK_DEBUG
+ printk(KERN_INFO "%s %d\n", __FUNCTION__, ch);
+#endif
+ if (!sc) {
+ goto out;
+ }
+ mutex_lock(&sc->mutex);
+ ret = ssv6xxx_set_channel(sc, ch);
+ mutex_unlock(&sc->mutex);
+ *pOutBufLen = 0;
+ out:
+ return ret;
+}
+
+static int _ksmartlink_get_channel(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+ u32 * pOutBufLen)
+{
+ int ret = -10;
+ int ch = 0;
+ struct ssv_softc *sc = ssv_smartlink_sc;
+#ifdef KSMARTLINK_DEBUG
+ printk(KERN_INFO "%s\n", __FUNCTION__);
+#endif
+ if (!sc) {
+ goto out;
+ }
+ mutex_lock(&sc->mutex);
+ ret = ssv6xxx_get_channel(sc, &ch);
+ mutex_unlock(&sc->mutex);
+ *pOutBuf = ch;
+ *pOutBufLen = 1;
+#ifdef KSMARTLINK_DEBUG
+ printk(KERN_INFO "%s %d\n", __FUNCTION__, ch);
+#endif
+ out:
+ return ret;
+}
+
+static int _ksmartlink_set_promisc(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+ u32 * pOutBufLen)
+{
+ int ret = -10;
+ int accept = (int)(*pInBuf);
+ struct ssv_softc *sc = ssv_smartlink_sc;
+#ifdef KSMARTLINK_DEBUG
+ printk(KERN_INFO "%s %d\n", __FUNCTION__, accept);
+#endif
+ if (!sc) {
+ goto out;
+ }
+ mutex_lock(&sc->mutex);
+ ret = ssv6xxx_set_promisc(sc, accept);
+ mutex_unlock(&sc->mutex);
+ *pOutBufLen = 0;
+ out:
+ return ret;
+}
+
+static int _ksmartlink_get_promisc(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+ u32 * pOutBufLen)
+{
+ int ret = -10;
+ int accept = (int)(*pInBuf);
+ struct ssv_softc *sc = ssv_smartlink_sc;
+#ifdef KSMARTLINK_DEBUG
+ printk(KERN_INFO "%s\n", __FUNCTION__);
+#endif
+ if (!sc) {
+ goto out;
+ }
+ mutex_lock(&sc->mutex);
+ ret = ssv6xxx_get_promisc(sc, &accept);
+ mutex_unlock(&sc->mutex);
+ *pOutBuf = accept;
+ *pOutBufLen = 1;
+#ifdef KSMARTLINK_DEBUG
+ printk(KERN_INFO "%s %d\n", __FUNCTION__, accept);
+#endif
+ out:
+ return ret;
+}
+
+#define SMARTLINK_CMD_FIXED_LEN (10)
+#define SMARTLINK_CMD_FIXED_TOT_LEN (SMARTLINK_CMD_FIXED_LEN+1)
+#define SMARTLINK_RES_FIXED_LEN (SMARTLINK_CMD_FIXED_LEN)
+#define SMARTLINK_RES_FIXED_TOT_LEN (SMARTLINK_RES_FIXED_LEN+2)
+struct ksmartlink_cmd {
+ char *cmd;
+ int (*process_func)(u8 *, u32, u8 *, u32 *);
+};
+static struct ksmartlink_cmd _ksmartlink_cmd_table[] = {
+ {"startairki", _ksmartlink_start_smartlink},
+ {"stopairkis", _ksmartlink_stop_smartlink},
+ {"setchannel", _ksmartlink_set_channel},
+ {"getchannel", _ksmartlink_get_channel},
+ {"setpromisc", _ksmartlink_set_promisc},
+ {"getpromisc", _ksmartlink_get_promisc},
+};
+
+static u32 _ksmartlink_cmd_table_size =
+ sizeof(_ksmartlink_cmd_table) / sizeof(struct ksmartlink_cmd);
+#ifdef KSMARTLINK_DEBUG
+static void _ksmartlink_hex_dump(u8 * pInBuf, u32 inBufLen)
+{
+ u32 i = 0;
+ printk(KERN_INFO "\nKernel Hex Dump(len=%d):\n", inBufLen);
+ printk(KERN_INFO ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
+ for (i = 0; i < inBufLen; i++) {
+ if ((i) && ((i & 0xf) == 0)) {
+ printk("\n");
+ }
+ printk("%02x ", pInBuf[i]);
+ }
+ printk(KERN_INFO "<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
+}
+#endif
+static int _ksmartlink_process_msg(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+ u32 * pOutBufLen)
+{
+ int ret = 0;
+ u32 i = 0;
+ struct ksmartlink_cmd *pCmd;
+ if (!pInBuf || !pOutBuf || !pOutBufLen) {
+ printk(KERN_ERR "NULL pointer\n");
+ return -1;
+ }
+ for (i = 0; i < _ksmartlink_cmd_table_size; i++) {
+ if (!strncmp
+ (_ksmartlink_cmd_table[i].cmd, pInBuf,
+ SMARTLINK_CMD_FIXED_LEN)) {
+ break;
+ }
+ }
+ if (i < _ksmartlink_cmd_table_size) {
+ pCmd = &_ksmartlink_cmd_table[i];
+ if (!pCmd->process_func) {
+ printk(KERN_ERR "CMD %s has NULL process_func\n",
+ pCmd->cmd);
+ return -3;
+ }
+ ret =
+ pCmd->process_func(pInBuf + SMARTLINK_CMD_FIXED_LEN,
+ inBufLen, pOutBuf, pOutBufLen);
+#ifdef CONFIG_SSV_NETLINK_RESPONSE
+ if (ret < 0) {
+ *pOutBufLen = SMARTLINK_RES_FIXED_TOT_LEN;
+ } else {
+ if (*pOutBufLen > 0) {
+ pOutBuf[SMARTLINK_RES_FIXED_LEN] = (u8) ret;
+ pOutBuf[SMARTLINK_RES_FIXED_LEN + 1] = *pOutBuf;
+ } else {
+ pOutBuf[SMARTLINK_RES_FIXED_LEN] = (u8) ret;
+ pOutBuf[SMARTLINK_RES_FIXED_LEN + 1] = 0;
+ }
+ *pOutBufLen = SMARTLINK_RES_FIXED_TOT_LEN;
+ }
+ memcpy(pOutBuf, pCmd->cmd, SMARTLINK_RES_FIXED_LEN);
+#else
+ (void)pOutBuf;
+ (void)pOutBufLen;
+#endif
+ return 0;
+ } else {
+ printk(KERN_INFO "Unknow CMD or Packet?\n");
+ }
+ return 0;
+}
+static u8 gkBuf[MAX_PAYLOAD] = { 0 };
+
+static int ssv_usr_pid = 0;
+void smartlink_nl_recv_msg(struct sk_buff *skb)
+{
+ struct nlmsghdr *nlh;
+#ifdef CONFIG_SSV_NETLINK_RESPONSE
+ struct sk_buff *skb_out;
+#endif
+ int ret = 0;
+ u8 *pInBuf = NULL;
+ u32 inBufLen = 0;
+ u32 outBufLen = 0;
+ nlh = (struct nlmsghdr *)skb->data;
+ ssv_usr_pid = nlh->nlmsg_pid;
+ pInBuf = (u8 *) nlmsg_data(nlh);
+ inBufLen = nlmsg_len(nlh);
+#ifdef KSMARTLINK_DEBUG
+ _ksmartlink_hex_dump(pInBuf, inBufLen);
+#endif
+ outBufLen = 0;
+ memset(gkBuf, 0, MAX_PAYLOAD);
+ ret = _ksmartlink_process_msg(pInBuf, inBufLen, gkBuf, &outBufLen);
+#ifdef CONFIG_SSV_NETLINK_RESPONSE
+ if (outBufLen == 0) {
+ memcpy(gkBuf, "Nothing", 8);
+ outBufLen = strlen(gkBuf);
+ }
+ skb_out = nlmsg_new(outBufLen, 0);
+ if (!skb_out) {
+ printk(KERN_ERR "Failed to allocate new skb\n");
+ return;
+ }
+ nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, outBufLen, 0);
+ NETLINK_CB(skb_out).dst_group = 0;
+ memcpy(nlmsg_data(nlh), gkBuf, outBufLen);
+ ret = nlmsg_unicast(nl_sk, skb_out, ssv_usr_pid);
+ if (ret < 0) {
+ printk(KERN_ERR "Error while sending bak to user\n");
+ }
+#endif
+ return;
+}
+
+void smartlink_nl_send_msg(struct sk_buff *skb)
+{
+ struct nlmsghdr *nlh;
+ struct sk_buff *skb_out;
+ int ret = 0;
+ u8 *pOutBuf = skb->data;
+ u32 outBufLen = skb->len;
+#ifdef KSMARTLINK_DEBUG
+#endif
+ skb_out = nlmsg_new(outBufLen, 0);
+ if (!skb_out) {
+ printk(KERN_ERR "Allocate new skb failed!\n");
+ return;
+ }
+ nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, outBufLen, 0);
+ NETLINK_CB(skb_out).dst_group = 0;
+ memcpy(nlmsg_data(nlh), pOutBuf, outBufLen);
+ ret = nlmsg_unicast(nl_sk, skb_out, ssv_usr_pid);
+ if (ret < 0) {
+ printk(KERN_ERR "nlmsg_unicast failed!\n");
+ }
+ kfree_skb(skb);
+ return;
+}
+
+EXPORT_SYMBOL(smartlink_nl_send_msg);
+int ksmartlink_init(void)
+{
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)
+ nl_sk = netlink_kernel_create(&init_net,
+ NETLINK_SMARTLINK,
+ 0,
+ smartlink_nl_recv_msg, NULL, THIS_MODULE);
+#else
+ struct netlink_kernel_cfg cfg = {
+ .groups = 0,
+ .input = smartlink_nl_recv_msg,
+ };
+ nl_sk = netlink_kernel_create(&init_net, NETLINK_SMARTLINK, &cfg);
+#endif
+ printk(KERN_INFO "***************SmartLink Init-S**************\n");
+ if (!nl_sk) {
+ printk(KERN_ERR "Error creating socket.\n");
+ return -10;
+ }
+ printk(KERN_INFO "***************SmartLink Init-E**************\n");
+ return 0;
+}
+
+void ksmartlink_exit(void)
+{
+ printk(KERN_INFO "%s\n", __FUNCTION__);
+ if (nl_sk) {
+ netlink_kernel_release(nl_sk);
+ nl_sk = NULL;
+ }
+}
+
+EXPORT_SYMBOL(ksmartlink_init);
+EXPORT_SYMBOL(ksmartlink_exit);
diff --git a/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
new file mode 100644
index 000000000000..9be5ea96e7f9
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ssv6xxx_debugfs.h"
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+#define QUEUE_STATUS_BUF_SIZE (4096)
+static ssize_t queue_status_read(struct file *file,
+ char __user * user_buf, size_t count,
+ loff_t * ppos)
+{
+ struct ssv_softc *sc = (struct ssv_softc *)file->private_data;
+ char *status_buf = kzalloc(QUEUE_STATUS_BUF_SIZE, GFP_KERNEL);
+ ssize_t status_size;
+ ssize_t ret;
+ if (!status_buf)
+ return -ENOMEM;
+ status_size = ssv6xxx_tx_queue_status_dump(sc, status_buf,
+ QUEUE_STATUS_BUF_SIZE);
+ ret = simple_read_from_buffer(user_buf, count, ppos, status_buf,
+ status_size);
+ kfree(status_buf);
+ return ret;
+}
+
+static int queue_status_open(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+static const struct file_operations queue_status_fops
+ = {.read = queue_status_read,
+ .open = queue_status_open
+};
+#endif
+int ssv6xxx_init_debugfs(struct ssv_softc *sc, const char *name)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct ieee80211_hw *hw = sc->hw;
+ struct dentry *phy_debugfs_dir = hw->wiphy->debugfsdir;
+ struct dentry *drv_debugfs_dir;
+ drv_debugfs_dir = debugfs_create_dir(name, phy_debugfs_dir);
+ if (!drv_debugfs_dir) {
+ dev_err(sc->dev, "Failed to create debugfs.\n");
+ return -ENOMEM;
+ }
+ sc->debugfs_dir = drv_debugfs_dir;
+ sc->sh->hci.hci_ops->hci_init_debugfs(sc->debugfs_dir);
+ debugfs_create_file("queue_status", 00444, drv_debugfs_dir,
+ sc, &queue_status_fops);
+#endif
+ return 0;
+}
+
+void ssv6xxx_deinit_debugfs(struct ssv_softc *sc)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ if (!sc->debugfs_dir)
+ return;
+ sc->sh->hci.hci_ops->hci_deinit_debugfs();
+ debugfs_remove_recursive(sc->debugfs_dir);
+ sc->debugfs_dir = NULL;
+#endif
+}
+
+int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc,
+ struct ieee80211_vif *vif)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct dentry *drv_debugfs_dir = sc->debugfs_dir;
+ struct dentry *vif_debugfs_dir;
+ char vif_addr[18];
+ struct ssv_vif_priv_data *vif_priv =
+ (struct ssv_vif_priv_data *)vif->drv_priv;
+ struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+ snprintf(vif_addr, sizeof(vif_addr), "%02X-%02X-%02X-%02X-%02X-%02X",
+ vif->addr[0], vif->addr[1], vif->addr[2],
+ vif->addr[3], vif->addr[4], vif->addr[5]);
+ vif_debugfs_dir = debugfs_create_dir(vif_addr, drv_debugfs_dir);
+ if (!vif_debugfs_dir) {
+ dev_err(sc->dev, "Failed to create interface debugfs for %s.\n",
+ vif_addr);
+ return -ENOMEM;
+ }
+ sc->debugfs_dir = drv_debugfs_dir;
+ vif_info->debugfs_dir = vif_debugfs_dir;
+#endif
+ return 0;
+}
+
+int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc,
+ struct ieee80211_vif *vif)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct ssv_vif_priv_data *vif_priv =
+ (struct ssv_vif_priv_data *)vif->drv_priv;
+ struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+ if ((vif_info->debugfs_dir == NULL) || (sc->debugfs_dir == NULL))
+ return 0;
+ debugfs_remove_recursive(vif_info->debugfs_dir);
+ vif_info->debugfs_dir = NULL;
+#endif
+ return 0;
+}
+
+int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct ssv_vif_priv_data *vif_priv =
+ (struct ssv_vif_priv_data *)sta->vif->drv_priv;
+ struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+ if ((sc->debugfs_dir == NULL) || (vif_info->debugfs_dir == NULL)
+ || (sta->debugfs_dir == NULL))
+ return 0;
+ debugfs_remove_recursive(sta->debugfs_dir);
+ sta->debugfs_dir = NULL;
+#endif
+ return 0;
+}
+
+int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ struct ssv_vif_priv_data *vif_priv =
+ (struct ssv_vif_priv_data *)sta->vif->drv_priv;
+ struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+ struct dentry *vif_debugfs_dir = vif_info->debugfs_dir;
+ struct dentry *sta_debugfs_dir;
+ char sta_addr[18];
+ if (vif_debugfs_dir == NULL)
+ return 0;
+ snprintf(sta_addr, sizeof(sta_addr), "%02X-%02X-%02X-%02X-%02X-%02X",
+ sta->sta->addr[0], sta->sta->addr[1], sta->sta->addr[2],
+ sta->sta->addr[3], sta->sta->addr[4], sta->sta->addr[5]);
+ sta_debugfs_dir = debugfs_create_dir(sta_addr, vif_debugfs_dir);
+ if (!sta_debugfs_dir) {
+ dev_err(sc->dev, "Failed to create interface debugfs for %s.\n",
+ sta_addr);
+ return -ENOMEM;
+ }
+ sta->debugfs_dir = sta_debugfs_dir;
+#endif
+ return 0;
+}
+
+#define DEBUGFS_ADD_FILE(name,parent,mode) do { \
+ if (!debugfs_create_file(#name, mode, parent, priv, \
+ &ssv_dbgfs_##name##_ops)) \
+ goto err; \
+} while (0)
+#define DEBUGFS_ADD_BOOL(name,parent,ptr) do { \
+ struct dentry *__tmp; \
+ __tmp = debugfs_create_bool(#name, S_IWUSR | S_IRUSR, \
+ parent, ptr); \
+ if (IS_ERR(__tmp) || !__tmp) \
+ goto err; \
+} while (0)
+#define DEBUGFS_ADD_X32(name,parent,ptr) do { \
+ struct dentry *__tmp; \
+ __tmp = debugfs_create_x32(#name, S_IWUSR | S_IRUSR, \
+ parent, ptr); \
+ if (IS_ERR(__tmp) || !__tmp) \
+ goto err; \
+} while (0)
+#define DEBUGFS_ADD_U32(name,parent,ptr,mode) do { \
+ struct dentry *__tmp; \
+ __tmp = debugfs_create_u32(#name, mode, \
+ parent, ptr); \
+ if (IS_ERR(__tmp) || !__tmp) \
+ goto err; \
+} while (0)
+#define DEBUGFS_READ_FUNC(name) \
+static ssize_t ssv_dbgfs_##name##_read(struct file *file, \
+ char __user *user_buf, \
+ size_t count, loff_t *ppos);
+#define DEBUGFS_WRITE_FUNC(name) \
+static ssize_t ssv_dbgfs_##name##_write(struct file *file, \
+ const char __user *user_buf, \
+ size_t count, loff_t *ppos);
+#define DEBUGFS_READ_FILE_OPS(name) \
+ DEBUGFS_READ_FUNC(name); \
+static const struct file_operations ssv_dbgfs_##name##_ops = { \
+ .read = ssv_dbgfs_##name##_read, \
+ .open = ssv_dbgfs_open_file_generic, \
+ .llseek = generic_file_llseek, \
+};
+#define DEBUGFS_WRITE_FILE_OPS(name) \
+ DEBUGFS_WRITE_FUNC(name); \
+static const struct file_operations ssv_dbgfs_##name##_ops = { \
+ .write = ssv_dbgfs_##name##_write, \
+ .open = ssv_dbgfs_open_file_generic, \
+ .llseek = generic_file_llseek, \
+};
+#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
+ DEBUGFS_READ_FUNC(name); \
+ DEBUGFS_WRITE_FUNC(name); \
+static const struct file_operations ssv_dbgfs_##name##_ops = { \
+ .write = ssv_dbgfs_##name##_write, \
+ .read = ssv_dbgfs_##name##_read, \
+ .open = ssv_dbgfs_open_file_generic, \
+ .llseek = generic_file_llseek, \
+};
diff --git a/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
new file mode 100644
index 000000000000..39caceadda4a
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SSV6XXX_DBGFS_H__
+#define __SSV6XXX_DBGFS_H__
+int ssv6xxx_init_debugfs(struct ssv_softc *sc, const char *name);
+void ssv6xxx_deinit_debugfs(struct ssv_softc *sc);
+int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc,
+ struct ieee80211_vif *vif);
+int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc,
+ struct ieee80211_vif *vif);
+int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);
+int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
new file mode 100644
index 000000000000..f0135447b1f3
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
@@ -0,0 +1,1384 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2018 icomm Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#include "dev.h"
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(CONFIG_SSV_VENDOR_EXT_SUPPORT)
+
+#include <linux/kernel.h>
+#include <linux/if_arp.h>
+#include <asm/uaccess.h>
+
+#include <linux/kernel.h>
+#include <linux/kthread.h>
+#include <linux/netdevice.h>
+#include <linux/sched.h>
+#include <linux/etherdevice.h>
+#include <linux/wireless.h>
+#include <linux/ieee80211.h>
+#include <linux/wait.h>
+#include <net/cfg80211.h>
+
+#include <net/rtnetlink.h>
+#include "ssv_cfgvendor.h"
+
+#define wiphy_to_softc(x) (*((struct ssv_softc**)wiphy_priv(x)))
+#define FUNC_NDEV_FMT "%s"
+#define FUNC_NDEV_ARG(ndev) __func__
+
+#define _drv_always_ 1
+#define _drv_emerg_ 2
+#define _drv_alert_ 3
+#define _drv_crit_ 4
+#define _drv_err_ 5
+#define _drv_warning_ 6
+#define _drv_notice_ 7
+#define _drv_info_ 8
+#define _drv_dump_ 9
+#define _drv_debug_ 10
+
+struct sk_buff *ssv_cfg80211_vendor_event_alloc(struct wiphy *wiphy, int len,
+ int event_id, gfp_t gfp)
+{
+ struct sk_buff *skb;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))
+ skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp);
+#else
+ skb = cfg80211_vendor_event_alloc(wiphy, NULL, len, event_id, gfp);
+#endif
+ return skb;
+}
+
+#define ssv_cfg80211_vendor_event(skb, gfp) \
+ cfg80211_vendor_event(skb, gfp)
+
+#define ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \
+ cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len)
+
+#define ssv_cfg80211_vendor_cmd_reply(skb) \
+ cfg80211_vendor_cmd_reply(skb)
+
+/*
+ * This API is to be used for asynchronous vendor events. This
+ * shouldn't be used in response to a vendor command from its
+ * do_it handler context (instead ssv_cfgvendor_send_cmd_reply should
+ * be used).
+ */
+int ssv_cfgvendor_send_async_event(struct wiphy *wiphy,
+ struct net_device *dev, int event_id,
+ const void *data, int len)
+{
+ u16 kflags;
+ struct sk_buff *skb;
+
+ kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
+
+ /* Alloc the SKB for vendor_event */
+ skb = ssv_cfg80211_vendor_event_alloc(wiphy, len, event_id, kflags);
+ if (!skb) {
+ dev_err(&wiphy->dev, "skb alloc failed\n");
+ return -ENOMEM;
+ }
+
+ /* Push the data to the skb */
+ nla_put_nohdr(skb, len, data);
+
+ ssv_cfg80211_vendor_event(skb, kflags);
+
+ return 0;
+}
+
+static int ssv_cfgvendor_send_cmd_reply(struct wiphy *wiphy,
+ struct net_device *dev,
+ const void *data, int len)
+{
+ struct sk_buff *skb;
+
+ /* Alloc the SKB for vendor_event */
+ skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);
+ if (unlikely(!skb)) {
+ dev_err(&wiphy->dev, "skb alloc failed");
+ return -ENOMEM;
+ }
+
+ /* Push the data to the skb */
+ nla_put_nohdr(skb, len, data);
+
+ return ssv_cfg80211_vendor_cmd_reply(skb);
+}
+
+#define WIFI_FEATURE_INFRA 0x0001 /* Basic infrastructure mode */
+#define WIFI_FEATURE_INFRA_5G 0x0002 /* Support for 5 GHz Band */
+#define WIFI_FEATURE_HOTSPOT 0x0004 /* Support for GAS/ANQP */
+#define WIFI_FEATURE_P2P 0x0008 /* Wifi-Direct */
+#define WIFI_FEATURE_SOFT_AP 0x0010 /* Soft AP */
+#define WIFI_FEATURE_GSCAN 0x0020 /* Google-Scan APIs */
+#define WIFI_FEATURE_NAN 0x0040 /* Neighbor Awareness Networking */
+#define WIFI_FEATURE_D2D_RTT 0x0080 /* Device-to-device RTT */
+#define WIFI_FEATURE_D2AP_RTT 0x0100 /* Device-to-AP RTT */
+#define WIFI_FEATURE_BATCH_SCAN 0x0200 /* Batched Scan (legacy) */
+#define WIFI_FEATURE_PNO 0x0400 /* Preferred network offload */
+#define WIFI_FEATURE_ADDITIONAL_STA 0x0800 /* Support for two STAs */
+#define WIFI_FEATURE_TDLS 0x1000 /* Tunnel directed link setup */
+#define WIFI_FEATURE_TDLS_OFFCHANNEL 0x2000 /* Support for TDLS off channel */
+#define WIFI_FEATURE_EPR 0x4000 /* Enhanced power reporting */
+#define WIFI_FEATURE_AP_STA 0x8000 /* Support for AP STA Concurrency */
+
+#define MAX_FEATURE_SET_CONCURRRENT_GROUPS 3
+
+int ssv_dev_get_feature_set(struct net_device *dev)
+{
+ int feature_set = 0;
+
+ feature_set |= WIFI_FEATURE_INFRA;
+
+ feature_set |= WIFI_FEATURE_P2P;
+ feature_set |= WIFI_FEATURE_SOFT_AP;
+
+#if defined(GSCAN_SUPPORT)
+ feature_set |= WIFI_FEATURE_GSCAN;
+#endif
+
+#if defined(RTT_SUPPORT)
+ feature_set |= WIFI_FEATURE_NAN;
+ feature_set |= WIFI_FEATURE_D2D_RTT;
+ feature_set |= WIFI_FEATURE_D2AP_RTT;
+#endif
+
+ return feature_set;
+}
+
+int *ssv_dev_get_feature_set_matrix(struct net_device *dev, int *num)
+{
+ int feature_set_full, mem_needed;
+ int *ret;
+
+ *num = 0;
+ mem_needed = sizeof(int) * MAX_FEATURE_SET_CONCURRRENT_GROUPS;
+ ret =
+ (int *)kmalloc(mem_needed, in_interrupt()? GFP_ATOMIC : GFP_KERNEL);
+
+ if (!ret) {
+ dev_err(&dev->dev, "failed to allocate %d bytes\n", mem_needed);
+ return ret;
+ }
+
+ feature_set_full = ssv_dev_get_feature_set(dev);
+
+ ret[0] = (feature_set_full & WIFI_FEATURE_INFRA) |
+ (feature_set_full & WIFI_FEATURE_INFRA_5G) |
+ (feature_set_full & WIFI_FEATURE_NAN) |
+ (feature_set_full & WIFI_FEATURE_D2D_RTT) |
+ (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
+ (feature_set_full & WIFI_FEATURE_PNO) |
+ (feature_set_full & WIFI_FEATURE_BATCH_SCAN) |
+ (feature_set_full & WIFI_FEATURE_GSCAN) |
+ (feature_set_full & WIFI_FEATURE_HOTSPOT) |
+ (feature_set_full & WIFI_FEATURE_ADDITIONAL_STA) |
+ (feature_set_full & WIFI_FEATURE_EPR);
+
+ ret[1] = (feature_set_full & WIFI_FEATURE_INFRA) |
+ (feature_set_full & WIFI_FEATURE_INFRA_5G) |
+ /* Not yet verified NAN with P2P */
+ /* (feature_set_full & WIFI_FEATURE_NAN) | */
+ (feature_set_full & WIFI_FEATURE_P2P) |
+ (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
+ (feature_set_full & WIFI_FEATURE_D2D_RTT) |
+ (feature_set_full & WIFI_FEATURE_EPR);
+
+ ret[2] = (feature_set_full & WIFI_FEATURE_INFRA) |
+ (feature_set_full & WIFI_FEATURE_INFRA_5G) |
+ (feature_set_full & WIFI_FEATURE_NAN) |
+ (feature_set_full & WIFI_FEATURE_D2D_RTT) |
+ (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
+ (feature_set_full & WIFI_FEATURE_TDLS) |
+ (feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL) |
+ (feature_set_full & WIFI_FEATURE_EPR);
+ *num = MAX_FEATURE_SET_CONCURRRENT_GROUPS;
+
+ return ret;
+}
+
+#define wdev_to_ndev(wdev) NULL
+
+static int ssv_cfgvendor_get_feature_set(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ const void *data, int len)
+{
+ int err = 0;
+ int reply;
+
+ reply = ssv_dev_get_feature_set(wdev_to_ndev(wdev));
+
+ err =
+ ssv_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &reply,
+ sizeof(int));
+
+ if (unlikely(err))
+ dev_err(&wiphy->dev, "vendor Command reply failed, ret:%d\n", err);
+
+ return err;
+}
+
+static int ssv_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ const void *data, int len)
+{
+ int err = 0;
+ struct sk_buff *skb;
+ int *reply;
+ int num, mem_needed, i;
+
+ reply = ssv_dev_get_feature_set_matrix(wdev_to_ndev(wdev), &num);
+
+ if (!reply) {
+ dev_err(&wiphy->dev, "could not get feature list matrix\n");
+ err = -EINVAL;
+ return err;
+ }
+
+ mem_needed = VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * num) +
+ ATTRIBUTE_U32_LEN;
+
+ /* Alloc the SKB for vendor_event */
+ skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
+ if (unlikely(!skb)) {
+ dev_err(&wiphy->dev, "skb alloc failed\n");
+ err = -ENOMEM;
+ goto exit;
+ }
+
+ nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, num);
+ for (i = 0; i < num; i++) {
+ nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_FEATURE_SET, reply[i]);
+ }
+
+ err = ssv_cfg80211_vendor_cmd_reply(skb);
+
+ if (unlikely(err))
+ dev_err(&wiphy->dev, "vendor Command reply failed, ret=%d\n", err);
+ exit:
+ kfree((void *)reply);
+ return err;
+}
+
+#if defined(GSCAN_SUPPORT) && 0
+int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
+ struct net_device *dev, void *data, int len,
+ wl_vendor_event_t event)
+{
+ u16 kflags;
+ const void *ptr;
+ struct sk_buff *skb;
+ int malloc_len, total, iter_cnt_to_send, cnt;
+ gscan_results_cache_t *cache = (gscan_results_cache_t *) data;
+
+ total = len / sizeof(wifi_gscan_result_t);
+ while (total > 0) {
+ malloc_len =
+ (total * sizeof(wifi_gscan_result_t)) +
+ VENDOR_DATA_OVERHEAD;
+ if (malloc_len > NLMSG_DEFAULT_SIZE) {
+ malloc_len = NLMSG_DEFAULT_SIZE;
+ }
+ iter_cnt_to_send =
+ (malloc_len -
+ VENDOR_DATA_OVERHEAD) / sizeof(wifi_gscan_result_t);
+ total = total - iter_cnt_to_send;
+
+ kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
+
+ /* Alloc the SKB for vendor_event */
+ skb =
+ ssv_cfg80211_vendor_event_alloc(wiphy, malloc_len, event,
+ kflags);
+ if (!skb) {
+ WL_ERR(("skb alloc failed"));
+ return -ENOMEM;
+ }
+
+ while (cache && iter_cnt_to_send) {
+ ptr =
+ (const void *)&cache->results[cache->tot_consumed];
+
+ if (iter_cnt_to_send <
+ (cache->tot_count - cache->tot_consumed))
+ cnt = iter_cnt_to_send;
+ else
+ cnt = (cache->tot_count - cache->tot_consumed);
+
+ iter_cnt_to_send -= cnt;
+ cache->tot_consumed += cnt;
+ /* Push the data to the skb */
+ nla_append(skb, cnt * sizeof(wifi_gscan_result_t), ptr);
+ if (cache->tot_consumed == cache->tot_count)
+ cache = cache->next;
+
+ }
+
+ ssv_cfg80211_vendor_event(skb, kflags);
+ }
+
+ return 0;
+}
+
+static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ const void *data, int len)
+{
+ int err = 0;
+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+ dhd_pno_gscan_capabilities_t *reply = NULL;
+ uint32 reply_len = 0;
+
+ reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
+ DHD_PNO_GET_CAPABILITIES, NULL,
+ &reply_len);
+ if (!reply) {
+ WL_ERR(("Could not get capabilities\n"));
+ err = -EINVAL;
+ return err;
+ }
+
+ err = ssv_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
+ reply, reply_len);
+
+ if (unlikely(err))
+ WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+
+ kfree(reply);
+ return err;
+}
+
+static int wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ const void *data, int len)
+{
+ int err = 0, type, band;
+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+ uint16 *reply = NULL;
+ uint32 reply_len = 0, num_channels, mem_needed;
+ struct sk_buff *skb;
+
+ type = nla_type(data);
+
+ if (type == GSCAN_ATTRIBUTE_BAND) {
+ band = nla_get_u32(data);
+ } else {
+ return -1;
+ }
+
+ reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
+ DHD_PNO_GET_CHANNEL_LIST, &band,
+ &reply_len);
+
+ if (!reply) {
+ WL_ERR(("Could not get channel list\n"));
+ err = -EINVAL;
+ return err;
+ }
+ num_channels = reply_len / sizeof(uint32);
+ mem_needed =
+ reply_len + VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 2);
+
+ /* Alloc the SKB for vendor_event */
+ skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
+ if (unlikely(!skb)) {
+ WL_ERR(("skb alloc failed"));
+ err = -ENOMEM;
+ goto exit;
+ }
+
+ nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_CHANNELS, num_channels);
+ nla_put(skb, GSCAN_ATTRIBUTE_CHANNEL_LIST, reply_len, reply);
+
+ err = ssv_cfg80211_vendor_cmd_reply(skb);
+
+ if (unlikely(err))
+ WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+ exit:
+ kfree(reply);
+ return err;
+}
+
+static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ const void *data, int len)
+{
+ int err = 0;
+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+ gscan_results_cache_t *results, *iter;
+ uint32 reply_len, complete = 0, num_results_iter;
+ int32 mem_needed;
+ wifi_gscan_result_t *ptr;
+ uint16 num_scan_ids, num_results;
+ struct sk_buff *skb;
+ struct nlattr *scan_hdr;
+
+ dhd_dev_wait_batch_results_complete(bcmcfg_to_prmry_ndev(cfg));
+ dhd_dev_pno_lock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
+ results = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
+ DHD_PNO_GET_BATCH_RESULTS, NULL,
+ &reply_len);
+
+ if (!results) {
+ WL_ERR(("No results to send %d\n", err));
+ err =
+ ssv_cfgvendor_send_cmd_reply(wiphy,
+ bcmcfg_to_prmry_ndev(cfg),
+ results, 0);
+
+ if (unlikely(err))
+ WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+ dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev
+ (cfg));
+ return err;
+ }
+ num_scan_ids = reply_len & 0xFFFF;
+ num_results = (reply_len & 0xFFFF0000) >> 16;
+ mem_needed = (num_results * sizeof(wifi_gscan_result_t)) +
+ (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) +
+ VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN;
+
+ if (mem_needed > (int32) NLMSG_DEFAULT_SIZE) {
+ mem_needed = (int32) NLMSG_DEFAULT_SIZE;
+ complete = 0;
+ } else {
+ complete = 1;
+ }
+
+ WL_TRACE(("complete %d mem_needed %d max_mem %d\n", complete,
+ mem_needed, (int)NLMSG_DEFAULT_SIZE));
+ /* Alloc the SKB for vendor_event */
+ skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
+ if (unlikely(!skb)) {
+ WL_ERR(("skb alloc failed"));
+ dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev
+ (cfg));
+ return -ENOMEM;
+ }
+ iter = results;
+
+ nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE, complete);
+
+ mem_needed =
+ mem_needed - (SCAN_RESULTS_COMPLETE_FLAG_LEN +
+ VENDOR_REPLY_OVERHEAD);
+
+ while (iter && ((mem_needed - GSCAN_BATCH_RESULT_HDR_LEN) > 0)) {
+ scan_hdr = nla_nest_start(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS);
+ nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_ID, iter->scan_id);
+ nla_put_u8(skb, GSCAN_ATTRIBUTE_SCAN_FLAGS, iter->flag);
+ num_results_iter =
+ (mem_needed -
+ GSCAN_BATCH_RESULT_HDR_LEN) / sizeof(wifi_gscan_result_t);
+
+ if ((iter->tot_count - iter->tot_consumed) < num_results_iter)
+ num_results_iter = iter->tot_count - iter->tot_consumed;
+
+ nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_OF_RESULTS,
+ num_results_iter);
+ if (num_results_iter) {
+ ptr = &iter->results[iter->tot_consumed];
+ iter->tot_consumed += num_results_iter;
+ nla_put(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS,
+ num_results_iter * sizeof(wifi_gscan_result_t),
+ ptr);
+ }
+ nla_nest_end(skb, scan_hdr);
+ mem_needed -= GSCAN_BATCH_RESULT_HDR_LEN +
+ (num_results_iter * sizeof(wifi_gscan_result_t));
+ iter = iter->next;
+ }
+
+ dhd_dev_gscan_batch_cache_cleanup(bcmcfg_to_prmry_ndev(cfg));
+ dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
+
+ return ssv_cfg80211_vendor_cmd_reply(skb);
+}
+
+static int wl_cfgvendor_initiate_gscan(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ const void *data, int len)
+{
+ int err = 0;
+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+ int type, tmp = len;
+ int run = 0xFF;
+ int flush = 0;
+ const struct nlattr *iter;
+
+ nla_for_each_attr(iter, data, len, tmp) {
+ type = nla_type(iter);
+ if (type == GSCAN_ATTRIBUTE_ENABLE_FEATURE)
+ run = nla_get_u32(iter);
+ else if (type == GSCAN_ATTRIBUTE_FLUSH_FEATURE)
+ flush = nla_get_u32(iter);
+ }
+
+ if (run != 0xFF) {
+ err =
+ dhd_dev_pno_run_gscan(bcmcfg_to_prmry_ndev(cfg), run,
+ flush);
+
+ if (unlikely(err))
+ WL_ERR(("Could not run gscan:%d \n", err));
+ return err;
+ } else {
+ return -1;
+ }
+
+}
+
+static int wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ const void *data, int len)
+{
+ int err = 0;
+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+ int type;
+ bool real_time = FALSE;
+
+ type = nla_type(data);
+
+ if (type == GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS) {
+ real_time = nla_get_u32(data);
+
+ err =
+ dhd_dev_pno_enable_full_scan_result(bcmcfg_to_prmry_ndev
+ (cfg), real_time);
+
+ if (unlikely(err))
+ WL_ERR(("Could not run gscan:%d \n", err));
+
+ } else {
+ err = -1;
+ }
+
+ return err;
+}
+
+static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ const void *data, int len)
+{
+ int err = 0;
+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+ gscan_scan_params_t *scan_param;
+ int j = 0;
+ int type, tmp, tmp1, tmp2, k = 0;
+ const struct nlattr *iter, *iter1, *iter2;
+ struct dhd_pno_gscan_channel_bucket *ch_bucket;
+
+ scan_param = kzalloc(sizeof(gscan_scan_params_t), GFP_KERNEL);
+ if (!scan_param) {
+ WL_ERR(("Could not set GSCAN scan cfg, mem alloc failure\n"));
+ err = -EINVAL;
+ return err;
+
+ }
+
+ scan_param->scan_fr = PNO_SCAN_MIN_FW_SEC;
+ nla_for_each_attr(iter, data, len, tmp) {
+ type = nla_type(iter);
+
+ if (j >= GSCAN_MAX_CH_BUCKETS)
+ break;
+
+ switch (type) {
+ case GSCAN_ATTRIBUTE_BASE_PERIOD:
+ scan_param->scan_fr = nla_get_u32(iter) / 1000;
+ break;
+ case GSCAN_ATTRIBUTE_NUM_BUCKETS:
+ scan_param->nchannel_buckets = nla_get_u32(iter);
+ break;
+ case GSCAN_ATTRIBUTE_CH_BUCKET_1:
+ case GSCAN_ATTRIBUTE_CH_BUCKET_2:
+ case GSCAN_ATTRIBUTE_CH_BUCKET_3:
+ case GSCAN_ATTRIBUTE_CH_BUCKET_4:
+ case GSCAN_ATTRIBUTE_CH_BUCKET_5:
+ case GSCAN_ATTRIBUTE_CH_BUCKET_6:
+ case GSCAN_ATTRIBUTE_CH_BUCKET_7:
+ nla_for_each_nested(iter1, iter, tmp1) {
+ type = nla_type(iter1);
+ ch_bucket = scan_param->channel_bucket;
+
+ switch (type) {
+ case GSCAN_ATTRIBUTE_BUCKET_ID:
+ break;
+ case GSCAN_ATTRIBUTE_BUCKET_PERIOD:
+ ch_bucket[j].bucket_freq_multiple =
+ nla_get_u32(iter1) / 1000;
+ break;
+ case GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS:
+ ch_bucket[j].num_channels =
+ nla_get_u32(iter1);
+ break;
+ case GSCAN_ATTRIBUTE_BUCKET_CHANNELS:
+ nla_for_each_nested(iter2, iter1, tmp2) {
+ if (k >=
+ PFN_SWC_RSSI_WINDOW_MAX)
+ break;
+ ch_bucket[j].chan_list[k] =
+ nla_get_u32(iter2);
+ k++;
+ }
+ k = 0;
+ break;
+ case GSCAN_ATTRIBUTE_BUCKETS_BAND:
+ ch_bucket[j].band = (uint16)
+ nla_get_u32(iter1);
+ break;
+ case GSCAN_ATTRIBUTE_REPORT_EVENTS:
+ ch_bucket[j].report_flag = (uint8)
+ nla_get_u32(iter1);
+ break;
+ }
+ }
+ j++;
+ break;
+ }
+ }
+
+ if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+ DHD_PNO_SCAN_CFG_ID, scan_param, 0) < 0) {
+ WL_ERR(("Could not set GSCAN scan cfg\n"));
+ err = -EINVAL;
+ }
+
+ kfree(scan_param);
+ return err;
+
+}
+
+static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy,
+ struct wireless_dev *wdev, const void *data,
+ int len)
+{
+ int err = 0;
+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+ gscan_hotlist_scan_params_t *hotlist_params;
+ int tmp, tmp1, tmp2, type, j = 0, dummy;
+ const struct nlattr *outer, *inner, *iter;
+ uint8 flush = 0;
+ struct bssid_t *pbssid;
+
+ hotlist_params =
+ (gscan_hotlist_scan_params_t *) kzalloc(len, GFP_KERNEL);
+ if (!hotlist_params) {
+ WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len));
+ return -1;
+ }
+
+ hotlist_params->lost_ap_window = GSCAN_LOST_AP_WINDOW_DEFAULT;
+
+ nla_for_each_attr(iter, data, len, tmp2) {
+ type = nla_type(iter);
+ switch (type) {
+ case GSCAN_ATTRIBUTE_HOTLIST_BSSIDS:
+ pbssid = hotlist_params->bssid;
+ nla_for_each_nested(outer, iter, tmp) {
+ nla_for_each_nested(inner, outer, tmp1) {
+ type = nla_type(inner);
+
+ switch (type) {
+ case GSCAN_ATTRIBUTE_BSSID:
+ memcpy(&(pbssid[j].macaddr),
+ nla_data(inner),
+ ETHER_ADDR_LEN);
+ break;
+ case GSCAN_ATTRIBUTE_RSSI_LOW:
+ pbssid[j].
+ rssi_reporting_threshold =
+ (int8) nla_get_u8(inner);
+ break;
+ case GSCAN_ATTRIBUTE_RSSI_HIGH:
+ dummy =
+ (int8) nla_get_u8(inner);
+ break;
+ }
+ }
+ j++;
+ }
+ hotlist_params->nbssid = j;
+ break;
+ case GSCAN_ATTRIBUTE_HOTLIST_FLUSH:
+ flush = nla_get_u8(iter);
+ break;
+ case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
+ hotlist_params->lost_ap_window = nla_get_u32(iter);
+ break;
+ }
+
+ }
+
+ if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+ DHD_PNO_GEOFENCE_SCAN_CFG_ID,
+ hotlist_params, flush) < 0) {
+ WL_ERR(("Could not set GSCAN HOTLIST cfg\n"));
+ err = -EINVAL;
+ goto exit;
+ }
+ exit:
+ kfree(hotlist_params);
+ return err;
+}
+
+static int wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ const void *data, int len)
+{
+ int err = 0, tmp, type;
+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+ gscan_batch_params_t batch_param;
+ const struct nlattr *iter;
+
+ batch_param.mscan = batch_param.bestn = 0;
+ batch_param.buffer_threshold = GSCAN_BATCH_NO_THR_SET;
+
+ nla_for_each_attr(iter, data, len, tmp) {
+ type = nla_type(iter);
+
+ switch (type) {
+ case GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN:
+ batch_param.bestn = nla_get_u32(iter);
+ break;
+ case GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE:
+ batch_param.mscan = nla_get_u32(iter);
+ break;
+ case GSCAN_ATTRIBUTE_REPORT_THRESHOLD:
+ batch_param.buffer_threshold = nla_get_u32(iter);
+ break;
+ }
+ }
+
+ if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+ DHD_PNO_BATCH_SCAN_CFG_ID, &batch_param,
+ 0) < 0) {
+ WL_ERR(("Could not set batch cfg\n"));
+ err = -EINVAL;
+ return err;
+ }
+
+ return err;
+}
+
+static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ const void *data, int len)
+{
+ int err = 0;
+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+ gscan_swc_params_t *significant_params;
+ int tmp, tmp1, tmp2, type, j = 0;
+ const struct nlattr *outer, *inner, *iter;
+ uint8 flush = 0;
+ wl_pfn_significant_bssid_t *pbssid;
+
+ significant_params = (gscan_swc_params_t *) kzalloc(len, GFP_KERNEL);
+ if (!significant_params) {
+ WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len));
+ return -1;
+ }
+
+ nla_for_each_attr(iter, data, len, tmp2) {
+ type = nla_type(iter);
+
+ switch (type) {
+ case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH:
+ flush = nla_get_u8(iter);
+ break;
+ case GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE:
+ significant_params->rssi_window = nla_get_u16(iter);
+ break;
+ case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
+ significant_params->lost_ap_window = nla_get_u16(iter);
+ break;
+ case GSCAN_ATTRIBUTE_MIN_BREACHING:
+ significant_params->swc_threshold = nla_get_u16(iter);
+ break;
+ case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS:
+ pbssid = significant_params->bssid_elem_list;
+ nla_for_each_nested(outer, iter, tmp) {
+ nla_for_each_nested(inner, outer, tmp1) {
+ switch (nla_type(inner)) {
+ case GSCAN_ATTRIBUTE_BSSID:
+ memcpy(&(pbssid[j].macaddr),
+ nla_data(inner),
+ ETHER_ADDR_LEN);
+ break;
+ case GSCAN_ATTRIBUTE_RSSI_HIGH:
+ pbssid[j].rssi_high_threshold =
+ (int8) nla_get_u8(inner);
+ break;
+ case GSCAN_ATTRIBUTE_RSSI_LOW:
+ pbssid[j].rssi_low_threshold =
+ (int8) nla_get_u8(inner);
+ break;
+ }
+ }
+ j++;
+ }
+ break;
+ }
+ }
+ significant_params->nbssid = j;
+
+ if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+ DHD_PNO_SIGNIFICANT_SCAN_CFG_ID,
+ significant_params, flush) < 0) {
+ WL_ERR(("Could not set GSCAN significant cfg\n"));
+ err = -EINVAL;
+ goto exit;
+ }
+ exit:
+ kfree(significant_params);
+ return err;
+}
+#endif /* GSCAN_SUPPORT */
+
+#if defined(RTT_SUPPORT) && 0
+void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data)
+{
+ struct wireless_dev *wdev = (struct wireless_dev *)ctx;
+ struct wiphy *wiphy;
+ struct sk_buff *skb;
+ uint32 tot_len = NLMSG_DEFAULT_SIZE, entry_len = 0;
+ gfp_t kflags;
+ rtt_report_t *rtt_report = NULL;
+ rtt_result_t *rtt_result = NULL;
+ struct list_head *rtt_list;
+ wiphy = wdev->wiphy;
+
+ WL_DBG(("In\n"));
+ /* Push the data to the skb */
+ if (!rtt_data) {
+ WL_ERR(("rtt_data is NULL\n"));
+ goto exit;
+ }
+ rtt_list = (struct list_head *)rtt_data;
+ kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
+ /* Alloc the SKB for vendor_event */
+ skb =
+ ssv_cfg80211_vendor_event_alloc(wiphy, tot_len,
+ GOOGLE_RTT_COMPLETE_EVENT, kflags);
+ if (!skb) {
+ WL_ERR(("skb alloc failed"));
+ goto exit;
+ }
+ /* fill in the rtt results on each entry */
+ list_for_each_entry(rtt_result, rtt_list, list) {
+ entry_len = 0;
+ if (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) {
+ entry_len = sizeof(rtt_report_t);
+ rtt_report = kzalloc(entry_len, kflags);
+ if (!rtt_report) {
+ WL_ERR(("rtt_report alloc failed"));
+ goto exit;
+ }
+ rtt_report->addr = rtt_result->peer_mac;
+ rtt_report->num_measurement = 1; /* ONE SHOT */
+ rtt_report->status = rtt_result->err_code;
+ rtt_report->type =
+ (rtt_result->TOF_type ==
+ TOF_TYPE_ONE_WAY) ? RTT_ONE_WAY : RTT_TWO_WAY;
+ rtt_report->peer = rtt_result->target_info->peer;
+ rtt_report->channel = rtt_result->target_info->channel;
+ rtt_report->rssi = rtt_result->avg_rssi;
+ /* tx_rate */
+ rtt_report->tx_rate = rtt_result->tx_rate;
+ /* RTT */
+ rtt_report->rtt = rtt_result->meanrtt;
+ rtt_report->rtt_sd = rtt_result->sdrtt;
+ /* convert to centi meter */
+ if (rtt_result->distance != 0xffffffff)
+ rtt_report->distance =
+ (rtt_result->distance >> 2) * 25;
+ else /* invalid distance */
+ rtt_report->distance = -1;
+
+ rtt_report->ts = rtt_result->ts;
+ nla_append(skb, entry_len, rtt_report);
+ kfree(rtt_report);
+ }
+ }
+ ssv_cfg80211_vendor_event(skb, kflags);
+ exit:
+ return;
+}
+
+static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ const void *data, int len)
+{
+ int err = 0, rem, rem1, rem2, type;
+ rtt_config_params_t rtt_param;
+ rtt_target_info_t *rtt_target = NULL;
+ const struct nlattr *iter, *iter1, *iter2;
+ int8 eabuf[ETHER_ADDR_STR_LEN];
+ int8 chanbuf[CHANSPEC_STR_LEN];
+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+
+ WL_DBG(("In\n"));
+ err =
+ dhd_dev_rtt_register_noti_callback(wdev->netdev, wdev,
+ wl_cfgvendor_rtt_evt);
+ if (err < 0) {
+ WL_ERR(("failed to register rtt_noti_callback\n"));
+ goto exit;
+ }
+ memset(&rtt_param, 0, sizeof(rtt_param));
+ nla_for_each_attr(iter, data, len, rem) {
+ type = nla_type(iter);
+ switch (type) {
+ case RTT_ATTRIBUTE_TARGET_CNT:
+ rtt_param.rtt_target_cnt = nla_get_u8(iter);
+ if (rtt_param.rtt_target_cnt > RTT_MAX_TARGET_CNT) {
+ WL_ERR(("exceed max target count : %d\n",
+ rtt_param.rtt_target_cnt));
+ err = BCME_RANGE;
+ }
+ break;
+ case RTT_ATTRIBUTE_TARGET_INFO:
+ rtt_target = rtt_param.target_info;
+ nla_for_each_nested(iter1, iter, rem1) {
+ nla_for_each_nested(iter2, iter1, rem2) {
+ type = nla_type(iter2);
+ switch (type) {
+ case RTT_ATTRIBUTE_TARGET_MAC:
+ memcpy(&rtt_target->addr,
+ nla_data(iter2),
+ ETHER_ADDR_LEN);
+ break;
+ case RTT_ATTRIBUTE_TARGET_TYPE:
+ rtt_target->type =
+ nla_get_u8(iter2);
+ break;
+ case RTT_ATTRIBUTE_TARGET_PEER:
+ rtt_target->peer =
+ nla_get_u8(iter2);
+ break;
+ case RTT_ATTRIBUTE_TARGET_CHAN:
+ memcpy(&rtt_target->channel,
+ nla_data(iter2),
+ sizeof(rtt_target->
+ channel));
+ break;
+ case RTT_ATTRIBUTE_TARGET_MODE:
+ rtt_target->continuous =
+ nla_get_u8(iter2);
+ break;
+ case RTT_ATTRIBUTE_TARGET_INTERVAL:
+ rtt_target->interval =
+ nla_get_u32(iter2);
+ break;
+ case RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT:
+ rtt_target->measure_cnt =
+ nla_get_u32(iter2);
+ break;
+ case RTT_ATTRIBUTE_TARGET_NUM_PKT:
+ rtt_target->ftm_cnt =
+ nla_get_u32(iter2);
+ break;
+ case RTT_ATTRIBUTE_TARGET_NUM_RETRY:
+ rtt_target->retry_cnt =
+ nla_get_u32(iter2);
+ }
+ }
+ /* convert to chanspec value */
+ rtt_target->chanspec =
+ dhd_rtt_convert_to_chspec(rtt_target->
+ channel);
+ if (rtt_target->chanspec == 0) {
+ WL_ERR(("Channel is not valid \n"));
+ goto exit;
+ }
+ WL_INFORM(("Target addr %s, Channel : %s for RTT \n", bcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr, eabuf), wf_chspec_ntoa(rtt_target->chanspec, chanbuf)));
+ rtt_target++;
+ }
+ break;
+ }
+ }
+ WL_DBG(("leave :target_cnt : %d\n", rtt_param.rtt_target_cnt));
+ if (dhd_dev_rtt_set_cfg(bcmcfg_to_prmry_ndev(cfg), &rtt_param) < 0) {
+ WL_ERR(("Could not set RTT configuration\n"));
+ err = -EINVAL;
+ }
+ exit:
+ return err;
+}
+
+static int wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ const void *data, int len)
+{
+ int err = 0, rem, type, target_cnt = 0;
+ const struct nlattr *iter;
+ struct ether_addr *mac_list = NULL, *mac_addr = NULL;
+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+
+ nla_for_each_attr(iter, data, len, rem) {
+ type = nla_type(iter);
+ switch (type) {
+ case RTT_ATTRIBUTE_TARGET_CNT:
+ target_cnt = nla_get_u8(iter);
+ mac_list =
+ (struct ether_addr *)kzalloc(target_cnt *
+ ETHER_ADDR_LEN,
+ GFP_KERNEL);
+ if (mac_list == NULL) {
+ WL_ERR(("failed to allocate mem for mac list\n"));
+ goto exit;
+ }
+ mac_addr = &mac_list[0];
+ break;
+ case RTT_ATTRIBUTE_TARGET_MAC:
+ if (mac_addr)
+ memcpy(mac_addr++, nla_data(iter),
+ ETHER_ADDR_LEN);
+ else {
+ WL_ERR(("mac_list is NULL\n"));
+ goto exit;
+ }
+ break;
+ }
+ if (dhd_dev_rtt_cancel_cfg
+ (bcmcfg_to_prmry_ndev(cfg), mac_list, target_cnt) < 0) {
+ WL_ERR(("Could not cancel RTT configuration\n"));
+ err = -EINVAL;
+ goto exit;
+ }
+ }
+ exit:
+ if (mac_list)
+ kfree(mac_list);
+ return err;
+}
+
+static int wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ const void *data, int len)
+{
+ int err = 0;
+ struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+ rtt_capabilities_t capability;
+
+ err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);
+ if (unlikely(err)) {
+ WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+ goto exit;
+ }
+ err = ssv_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
+ &capability, sizeof(capability));
+
+ if (unlikely(err)) {
+ WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+ }
+ exit:
+ return err;
+}
+
+#endif /* RTT_SUPPORT */
+static int wl_cfgvendor_priv_string_handler(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ const void *data, int len)
+{
+ int err = 0;
+ u8 resp[1] = { '\0' };
+
+ dev_dbg(&wiphy->dev, "%s\n", (char *)data);
+ err = ssv_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), resp, 1);
+ if (unlikely(err))
+ dev_err(&wiphy->dev, "vendor Command reply failed, ret=:%d\n", err);
+
+ return err;
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+static const struct wiphy_vendor_command ssv_vendor_cmds[] = {
+ {
+ {
+ .vendor_id = OUI_SSV,
+ .subcmd = RTK_VENDOR_SCMD_PRIV_STR},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_priv_string_handler,
+ .policy = VENDOR_CMD_RAW_DATA},
+#if defined(GSCAN_SUPPORT) && 0
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_gscan_get_capabilities,
+ .policy = VENDOR_CMD_RAW_DATA},
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_SET_CONFIG},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_set_scan_cfg,
+ .policy = VENDOR_CMD_RAW_DATA},
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_set_batch_scan_cfg,
+ .policy = VENDOR_CMD_RAW_DATA},
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_initiate_gscan,
+ .policy = VENDOR_CMD_RAW_DATA},
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_enable_full_scan_result,
+ .policy = VENDOR_CMD_RAW_DATA},
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_SET_HOTLIST},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_hotlist_cfg,
+ .policy = VENDOR_CMD_RAW_DATA},
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_significant_change_cfg,
+ .policy = VENDOR_CMD_RAW_DATA},
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_gscan_get_batch_results,
+ .policy = VENDOR_CMD_RAW_DATA},
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_gscan_get_channel_list,
+ .policy = VENDOR_CMD_RAW_DATA},
+#endif /* GSCAN_SUPPORT */
+#if defined(RTT_SUPPORT) && 0
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = RTT_SUBCMD_SET_CONFIG},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_rtt_set_config,
+ .policy = VENDOR_CMD_RAW_DATA},
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = RTT_SUBCMD_CANCEL_CONFIG},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_rtt_cancel_config,
+ .policy = VENDOR_CMD_RAW_DATA},
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = RTT_SUBCMD_GETCAPABILITY},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_rtt_get_capability,
+ .policy = VENDOR_CMD_RAW_DATA},
+#endif /* RTT_SUPPORT */
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = ssv_cfgvendor_get_feature_set,
+ .policy = VENDOR_CMD_RAW_DATA},
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = ssv_cfgvendor_get_feature_set_matrix,
+ .policy = VENDOR_CMD_RAW_DATA}
+};
+#else
+static const struct wiphy_vendor_command ssv_vendor_cmds[] = {
+ {
+ {
+ .vendor_id = OUI_SSV,
+ .subcmd = RTK_VENDOR_SCMD_PRIV_STR},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_priv_string_handler
+ },
+#if defined(GSCAN_SUPPORT) && 0
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_gscan_get_capabilities
+ },
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_SET_CONFIG},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_set_scan_cfg
+ },
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_set_batch_scan_cfg
+ },
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_initiate_gscan
+ },
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_enable_full_scan_result
+ },
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_SET_HOTLIST},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_hotlist_cfg
+ },
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_significant_change_cfg
+ },
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_gscan_get_batch_results
+ },
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_gscan_get_channel_list
+ },
+#endif /* GSCAN_SUPPORT */
+#if defined(RTT_SUPPORT) && 0
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = RTT_SUBCMD_SET_CONFIG},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_rtt_set_config
+ },
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = RTT_SUBCMD_CANCEL_CONFIG},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_rtt_cancel_config
+ },
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = RTT_SUBCMD_GETCAPABILITY},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = wl_cfgvendor_rtt_get_capability
+ },
+#endif /* RTT_SUPPORT */
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = ssv_cfgvendor_get_feature_set
+ },
+ {
+ {
+ .vendor_id = OUI_GOOGLE,
+ .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX},
+ .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+ .doit = ssv_cfgvendor_get_feature_set_matrix
+ }
+};
+#endif
+
+static const struct nl80211_vendor_cmd_info ssv_vendor_events[] = {
+ {OUI_SSV, RTK_VENDOR_EVENT_UNSPEC},
+ {OUI_SSV, RTK_VENDOR_EVENT_PRIV_STR},
+#if defined(GSCAN_SUPPORT) && 0
+ {OUI_GOOGLE, GOOGLE_GSCAN_SIGNIFICANT_EVENT},
+ {OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT},
+ {OUI_GOOGLE, GOOGLE_GSCAN_BATCH_SCAN_EVENT},
+ {OUI_GOOGLE, GOOGLE_SCAN_FULL_RESULTS_EVENT},
+#endif /* GSCAN_SUPPORT */
+#if defined(RTT_SUPPORT) && 0
+ {OUI_GOOGLE, GOOGLE_RTT_COMPLETE_EVENT},
+#endif /* RTT_SUPPORT */
+#if defined(GSCAN_SUPPORT) && 0
+ {OUI_GOOGLE, GOOGLE_SCAN_COMPLETE_EVENT},
+ {OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_LOST_EVENT}
+#endif /* GSCAN_SUPPORT */
+};
+
+int ssv_cfgvendor_attach(struct wiphy *wiphy)
+{
+
+ dev_info(&wiphy->dev, "register SSV cfg80211 vendor cmd(0x%x) interface\n",
+ NL80211_CMD_VENDOR);
+
+ wiphy->vendor_commands = ssv_vendor_cmds;
+ wiphy->n_vendor_commands = ARRAY_SIZE(ssv_vendor_cmds);
+ wiphy->vendor_events = ssv_vendor_events;
+ wiphy->n_vendor_events = ARRAY_SIZE(ssv_vendor_events);
+
+ return 0;
+}
+
+int ssv_cfgvendor_detach(struct wiphy *wiphy)
+{
+ dev_info(&wiphy->dev, "unregister SSV cfg80211 vendor interface\n");
+
+ wiphy->vendor_commands = NULL;
+ wiphy->vendor_events = NULL;
+ wiphy->n_vendor_commands = 0;
+ wiphy->n_vendor_events = 0;
+
+ return 0;
+}
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(SSV_VENDOR_EXT_SUPPORT) */
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
new file mode 100644
index 000000000000..6d8696fcd220
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
@@ -0,0 +1,247 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef _RTW_CFGVENDOR_H_
+#define _RTW_CFGVENDOR_H_
+
+#define OUI_SSV 0x00E04C
+#define OUI_GOOGLE 0x001A11
+#define ATTRIBUTE_U32_LEN (NLA_HDRLEN + 4)
+#define VENDOR_ID_OVERHEAD ATTRIBUTE_U32_LEN
+#define VENDOR_SUBCMD_OVERHEAD ATTRIBUTE_U32_LEN
+#define VENDOR_DATA_OVERHEAD (NLA_HDRLEN)
+
+#define SCAN_RESULTS_COMPLETE_FLAG_LEN ATTRIBUTE_U32_LEN
+#define SCAN_INDEX_HDR_LEN (NLA_HDRLEN)
+#define SCAN_ID_HDR_LEN ATTRIBUTE_U32_LEN
+#define SCAN_FLAGS_HDR_LEN ATTRIBUTE_U32_LEN
+#define GSCAN_NUM_RESULTS_HDR_LEN ATTRIBUTE_U32_LEN
+#define GSCAN_RESULTS_HDR_LEN (NLA_HDRLEN)
+#define GSCAN_BATCH_RESULT_HDR_LEN (SCAN_INDEX_HDR_LEN + SCAN_ID_HDR_LEN + \
+ SCAN_FLAGS_HDR_LEN + \
+ GSCAN_NUM_RESULTS_HDR_LEN + \
+ GSCAN_RESULTS_HDR_LEN)
+
+#define VENDOR_REPLY_OVERHEAD (VENDOR_ID_OVERHEAD + \
+ VENDOR_SUBCMD_OVERHEAD + \
+ VENDOR_DATA_OVERHEAD)
+typedef enum {
+ /* don't use 0 as a valid subcommand */
+ VENDOR_NL80211_SUBCMD_UNSPECIFIED,
+
+ /* define all vendor startup commands between 0x0 and 0x0FFF */
+ VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001,
+ VENDOR_NL80211_SUBCMD_RANGE_END = 0x0FFF,
+
+ /* define all GScan related commands between 0x1000 and 0x10FF */
+ ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000,
+ ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END = 0x10FF,
+
+ /* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */
+ ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100,
+ ANDROID_NL80211_SUBCMD_NBD_RANGE_END = 0x11FF,
+
+ /* define all RTT related commands between 0x1100 and 0x11FF */
+ ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100,
+ ANDROID_NL80211_SUBCMD_RTT_RANGE_END = 0x11FF,
+
+ ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200,
+ ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END = 0x12FF,
+
+ ANDROID_NL80211_SUBCMD_TDLS_RANGE_START = 0x1300,
+ ANDROID_NL80211_SUBCMD_TDLS_RANGE_END = 0x13FF,
+ /* This is reserved for future usage */
+
+} ANDROID_VENDOR_SUB_COMMAND;
+
+enum wl_vendor_subcmd {
+ RTK_VENDOR_SCMD_UNSPEC,
+ RTK_VENDOR_SCMD_PRIV_STR,
+ GSCAN_SUBCMD_GET_CAPABILITIES =
+ ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START,
+ GSCAN_SUBCMD_SET_CONFIG,
+ GSCAN_SUBCMD_SET_SCAN_CONFIG,
+ GSCAN_SUBCMD_ENABLE_GSCAN,
+ GSCAN_SUBCMD_GET_SCAN_RESULTS,
+ GSCAN_SUBCMD_SCAN_RESULTS,
+ GSCAN_SUBCMD_SET_HOTLIST,
+ GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG,
+ GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS,
+ GSCAN_SUBCMD_GET_CHANNEL_LIST,
+ ANDR_WIFI_SUBCMD_GET_FEATURE_SET,
+ ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX,
+ RTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START,
+ RTT_SUBCMD_CANCEL_CONFIG,
+ RTT_SUBCMD_GETCAPABILITY,
+ /* Add more sub commands here */
+ VENDOR_SUBCMD_MAX
+};
+
+enum gscan_attributes {
+ GSCAN_ATTRIBUTE_NUM_BUCKETS = 10,
+ GSCAN_ATTRIBUTE_BASE_PERIOD,
+ GSCAN_ATTRIBUTE_BUCKETS_BAND,
+ GSCAN_ATTRIBUTE_BUCKET_ID,
+ GSCAN_ATTRIBUTE_BUCKET_PERIOD,
+ GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS,
+ GSCAN_ATTRIBUTE_BUCKET_CHANNELS,
+ GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN,
+ GSCAN_ATTRIBUTE_REPORT_THRESHOLD,
+ GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE,
+ GSCAN_ATTRIBUTE_BAND = GSCAN_ATTRIBUTE_BUCKETS_BAND,
+
+ GSCAN_ATTRIBUTE_ENABLE_FEATURE = 20,
+ GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE,
+ GSCAN_ATTRIBUTE_FLUSH_FEATURE,
+ GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS,
+ GSCAN_ATTRIBUTE_REPORT_EVENTS,
+ /* remaining reserved for additional attributes */
+ GSCAN_ATTRIBUTE_NUM_OF_RESULTS = 30,
+ GSCAN_ATTRIBUTE_FLUSH_RESULTS,
+ GSCAN_ATTRIBUTE_SCAN_RESULTS, /* flat array of wifi_scan_result */
+ GSCAN_ATTRIBUTE_SCAN_ID, /* indicates scan number */
+ GSCAN_ATTRIBUTE_SCAN_FLAGS, /* indicates if scan was aborted */
+ GSCAN_ATTRIBUTE_AP_FLAGS, /* flags on significant change event */
+ GSCAN_ATTRIBUTE_NUM_CHANNELS,
+ GSCAN_ATTRIBUTE_CHANNEL_LIST,
+
+ /* remaining reserved for additional attributes */
+
+ GSCAN_ATTRIBUTE_SSID = 40,
+ GSCAN_ATTRIBUTE_BSSID,
+ GSCAN_ATTRIBUTE_CHANNEL,
+ GSCAN_ATTRIBUTE_RSSI,
+ GSCAN_ATTRIBUTE_TIMESTAMP,
+ GSCAN_ATTRIBUTE_RTT,
+ GSCAN_ATTRIBUTE_RTTSD,
+
+ /* remaining reserved for additional attributes */
+
+ GSCAN_ATTRIBUTE_HOTLIST_BSSIDS = 50,
+ GSCAN_ATTRIBUTE_RSSI_LOW,
+ GSCAN_ATTRIBUTE_RSSI_HIGH,
+ GSCAN_ATTRIBUTE_HOSTLIST_BSSID_ELEM,
+ GSCAN_ATTRIBUTE_HOTLIST_FLUSH,
+
+ /* remaining reserved for additional attributes */
+ GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE = 60,
+ GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE,
+ GSCAN_ATTRIBUTE_MIN_BREACHING,
+ GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS,
+ GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH,
+ GSCAN_ATTRIBUTE_MAX
+};
+
+enum gscan_bucket_attributes {
+ GSCAN_ATTRIBUTE_CH_BUCKET_1,
+ GSCAN_ATTRIBUTE_CH_BUCKET_2,
+ GSCAN_ATTRIBUTE_CH_BUCKET_3,
+ GSCAN_ATTRIBUTE_CH_BUCKET_4,
+ GSCAN_ATTRIBUTE_CH_BUCKET_5,
+ GSCAN_ATTRIBUTE_CH_BUCKET_6,
+ GSCAN_ATTRIBUTE_CH_BUCKET_7
+};
+
+enum gscan_ch_attributes {
+ GSCAN_ATTRIBUTE_CH_ID_1,
+ GSCAN_ATTRIBUTE_CH_ID_2,
+ GSCAN_ATTRIBUTE_CH_ID_3,
+ GSCAN_ATTRIBUTE_CH_ID_4,
+ GSCAN_ATTRIBUTE_CH_ID_5,
+ GSCAN_ATTRIBUTE_CH_ID_6,
+ GSCAN_ATTRIBUTE_CH_ID_7
+};
+
+enum rtt_attributes {
+ RTT_ATTRIBUTE_TARGET_CNT,
+ RTT_ATTRIBUTE_TARGET_INFO,
+ RTT_ATTRIBUTE_TARGET_MAC,
+ RTT_ATTRIBUTE_TARGET_TYPE,
+ RTT_ATTRIBUTE_TARGET_PEER,
+ RTT_ATTRIBUTE_TARGET_CHAN,
+ RTT_ATTRIBUTE_TARGET_MODE,
+ RTT_ATTRIBUTE_TARGET_INTERVAL,
+ RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT,
+ RTT_ATTRIBUTE_TARGET_NUM_PKT,
+ RTT_ATTRIBUTE_TARGET_NUM_RETRY
+};
+
+typedef enum wl_vendor_event {
+ RTK_VENDOR_EVENT_UNSPEC,
+ RTK_VENDOR_EVENT_PRIV_STR,
+ GOOGLE_GSCAN_SIGNIFICANT_EVENT,
+ GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT,
+ GOOGLE_GSCAN_BATCH_SCAN_EVENT,
+ GOOGLE_SCAN_FULL_RESULTS_EVENT,
+ GOOGLE_RTT_COMPLETE_EVENT,
+ GOOGLE_SCAN_COMPLETE_EVENT,
+ GOOGLE_GSCAN_GEOFENCE_LOST_EVENT
+} wl_vendor_event_t;
+
+enum andr_wifi_feature_set_attr {
+ ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET,
+ ANDR_WIFI_ATTRIBUTE_FEATURE_SET
+};
+
+typedef enum wl_vendor_gscan_attribute {
+ ATTR_START_GSCAN,
+ ATTR_STOP_GSCAN,
+ ATTR_SET_SCAN_BATCH_CFG_ID, /* set batch scan params */
+ ATTR_SET_SCAN_GEOFENCE_CFG_ID, /* set list of bssids to track */
+ ATTR_SET_SCAN_SIGNIFICANT_CFG_ID, /* set list of bssids, rssi threshold etc.. */
+ ATTR_SET_SCAN_CFG_ID, /* set common scan config params here */
+ ATTR_GET_GSCAN_CAPABILITIES_ID,
+ /* Add more sub commands here */
+ ATTR_GSCAN_MAX
+} wl_vendor_gscan_attribute_t;
+
+typedef enum gscan_batch_attribute {
+ ATTR_GSCAN_BATCH_BESTN,
+ ATTR_GSCAN_BATCH_MSCAN,
+ ATTR_GSCAN_BATCH_BUFFER_THRESHOLD
+} gscan_batch_attribute_t;
+
+typedef enum gscan_geofence_attribute {
+ ATTR_GSCAN_NUM_HOTLIST_BSSID,
+ ATTR_GSCAN_HOTLIST_BSSID
+} gscan_geofence_attribute_t;
+
+typedef enum gscan_complete_event {
+ WIFI_SCAN_BUFFER_FULL,
+ WIFI_SCAN_COMPLETE
+} gscan_complete_event_t;
+
+/* Capture the RTK_VENDOR_SUBCMD_PRIV_STRINGS* here */
+#define RTK_VENDOR_SCMD_CAPA "cap"
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(SSV_VENDOR_EXT_SUPPORT)
+extern int ssv_cfgvendor_attach(struct wiphy *wiphy);
+extern int ssv_cfgvendor_detach(struct wiphy *wiphy);
+extern int ssv_cfgvendor_send_async_event(struct wiphy *wiphy,
+ struct net_device *dev, int event_id,
+ const void *data, int len);
+#if defined(GSCAN_SUPPORT) && 0
+extern int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
+ struct net_device *dev, void *data,
+ int len, wl_vendor_event_t event);
+#endif
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */
+
+#endif /* _RTW_CFGVENDOR_H_ */
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
new file mode 100644
index 000000000000..fae819c43400
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
@@ -0,0 +1,546 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ssv_ht_rc.h"
+#include "ssv_rc.h"
+#define SAMPLE_COUNT 4
+#define HT_CW_MIN 15
+#define HT_SEGMENT_SIZE 6000
+#define AVG_PKT_SIZE 12000
+#define SAMPLE_COLUMNS 10
+#define EWMA_LEVEL 75
+#define MCS_NBITS (AVG_PKT_SIZE << 3)
+#define MCS_NSYMS(bps) ((MCS_NBITS + (bps) - 1) / (bps))
+#define MCS_SYMBOL_TIME(sgi,syms) \
+ (sgi ? \
+ ((syms) * 18 + 4) / 5 : \
+ (syms) << 2 \
+ )
+#define MCS_DURATION(streams,sgi,bps) MCS_SYMBOL_TIME(sgi, MCS_NSYMS((streams) * (bps)))
+#define MCS_GROUP(_streams,_sgi,_ht40) { \
+ .duration = { \
+ MCS_DURATION(_streams, _sgi, _ht40 ? 54 : 26), \
+ MCS_DURATION(_streams, _sgi, _ht40 ? 108 : 52), \
+ MCS_DURATION(_streams, _sgi, _ht40 ? 162 : 78), \
+ MCS_DURATION(_streams, _sgi, _ht40 ? 216 : 104), \
+ MCS_DURATION(_streams, _sgi, _ht40 ? 324 : 156), \
+ MCS_DURATION(_streams, _sgi, _ht40 ? 432 : 208), \
+ MCS_DURATION(_streams, _sgi, _ht40 ? 486 : 234), \
+ MCS_DURATION(_streams, _sgi, _ht40 ? 540 : 260) \
+ } \
+}
+const struct mcs_group minstrel_mcs_groups_ssv[] = {
+ MCS_GROUP(1, 0, 0),
+ MCS_GROUP(1, 1, 0),
+};
+
+const u16 ampdu_max_transmit_length[RATE_TABLE_SIZE] = {
+ 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 4600, 9200, 13800, 18500, 27700, 37000, 41600, 46200,
+ 5100, 10200, 15400, 20500, 30800, 41100, 46200, 51300,
+ 4600, 9200, 13800, 18500, 27700, 37000, 41600, 46200
+};
+
+static u8 sample_table[SAMPLE_COLUMNS][MCS_GROUP_RATES];
+static int minstrel_ewma(int old, int new, int weight)
+{
+ return (new * (100 - weight) + old * weight) / 100;
+}
+
+static inline struct minstrel_rate_stats *minstrel_get_ratestats(struct
+ ssv62xx_ht *mi,
+ int index)
+{
+ return &mi->groups.rates[index % MCS_GROUP_RATES];
+}
+
+static void minstrel_calc_rate_ewma(struct minstrel_rate_stats *mr)
+{
+ if (unlikely(mr->attempts > 0)) {
+ mr->sample_skipped = 0;
+ mr->cur_prob = MINSTREL_FRAC(mr->success, mr->attempts);
+ if (!mr->att_hist)
+ mr->probability = mr->cur_prob;
+ else
+ mr->probability = minstrel_ewma(mr->probability,
+ mr->cur_prob,
+ EWMA_LEVEL);
+ mr->att_hist += mr->attempts;
+ mr->succ_hist += mr->success;
+ } else {
+ mr->sample_skipped++;
+ }
+ mr->last_success = mr->success;
+ mr->last_attempts = mr->attempts;
+ mr->success = 0;
+ mr->attempts = 0;
+}
+
+static void minstrel_ht_calc_tp(struct ssv62xx_ht *mi,
+ struct ssv_sta_rc_info *rc_sta, int rate)
+{
+ struct minstrel_rate_stats *mr;
+ unsigned int usecs, group_id;
+ if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
+ group_id = 0;
+ else
+ group_id = 1;
+ mr = &mi->groups.rates[rate];
+ if (mr->probability < MINSTREL_FRAC(1, 10)) {
+ mr->cur_tp = 0;
+ return;
+ }
+ usecs = mi->overhead / MINSTREL_TRUNC(mi->avg_ampdu_len);
+ usecs += minstrel_mcs_groups_ssv[group_id].duration[rate];
+ mr->cur_tp = MINSTREL_TRUNC((1000000 / usecs) * mr->probability);
+}
+
+static void rate_control_ht_sample(struct ssv62xx_ht *mi,
+ struct ssv_sta_rc_info *rc_sta)
+{
+ struct minstrel_mcs_group_data *mg;
+ struct minstrel_rate_stats *mr;
+ int cur_prob, cur_prob_tp, cur_tp, cur_tp2;
+ int i, index;
+ if (mi->ampdu_packets > 0) {
+ mi->avg_ampdu_len = minstrel_ewma(mi->avg_ampdu_len,
+ MINSTREL_FRAC(mi->ampdu_len,
+ mi->
+ ampdu_packets),
+ EWMA_LEVEL);
+ mi->ampdu_len = 0;
+ mi->ampdu_packets = 0;
+ } else
+ return;
+ mi->sample_slow = 0;
+ mi->sample_count = 0;
+ {
+ cur_prob = 0;
+ cur_prob_tp = 0;
+ cur_tp = 0;
+ cur_tp2 = 0;
+ mg = &mi->groups;
+ mg->max_tp_rate = 0;
+ mg->max_tp_rate2 = 0;
+ mg->max_prob_rate = 0;
+ for (i = 0; i < MCS_GROUP_RATES; i++) {
+ if (!(rc_sta->ht_supp_rates & BIT(i)))
+ continue;
+ mr = &mg->rates[i];
+ index = i;
+ minstrel_calc_rate_ewma(mr);
+ minstrel_ht_calc_tp(mi, rc_sta, i);
+#ifdef RATE_CONTROL_HT_PARAMETER_DEBUG
+ if (mr->cur_prob)
+ pr_debug
+ ("rate[%d]probability[%08d]cur_prob[%08d]TP[%04d]\n",
+ i, mr->probability, mr->cur_prob,
+ mr->cur_tp);
+#endif
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+ pr_debug
+ ("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n",
+ mg->max_tp_rate, mg->max_tp_rate2,
+ mg->max_prob_rate);
+ pr_debug("rate[%d]probability[%08d]TP[%d]\n", i,
+ mr->probability, mr->cur_tp);
+#endif
+ if (!mr->cur_tp)
+ continue;
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+ pr_debug("HT--1 mr->cur_tp[%d]cur_prob_tp[%d]\n",
+ mr->cur_tp, cur_prob_tp);
+#endif
+ if ((mr->cur_tp > cur_prob_tp && mr->probability >
+ MINSTREL_FRAC(3, 4))
+ || mr->probability > cur_prob) {
+ mg->max_prob_rate = index;
+ cur_prob = mr->probability;
+ cur_prob_tp = mr->cur_tp;
+ }
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+ pr_debug("HT--2 mr->cur_tp[%d]cur_tp[%d]\n", mr->cur_tp,
+ cur_tp);
+#endif
+ if (mr->cur_tp > cur_tp) {
+ swap(index, mg->max_tp_rate);
+ cur_tp = mr->cur_tp;
+ mr = minstrel_get_ratestats(mi, index);
+ }
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+ if (index != i)
+ pr_debug
+ ("HT--3 index[%d]i[%d]mg->max_tp_rate[%d]\n",
+ index, i, mg->max_tp_rate);
+#endif
+ if (index >= mg->max_tp_rate)
+ continue;
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+ if (index != i)
+ pr_debug("HT--4 mr->cur_tp[%d]cur_tp2[%d]\n",
+ mr->cur_tp, cur_tp2);
+#endif
+ if (mr->cur_tp > cur_tp2) {
+ mg->max_tp_rate2 = index;
+ cur_tp2 = mr->cur_tp;
+ }
+ }
+ }
+ mi->sample_count = SAMPLE_COUNT;
+ mi->max_tp_rate = mg->max_tp_rate;
+ mi->max_tp_rate2 = mg->max_tp_rate2;
+ mi->max_prob_rate = mg->max_prob_rate;
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+ pr_debug
+ ("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n",
+ mi->max_tp_rate, mi->max_tp_rate2, mi->max_prob_rate);
+#endif
+ mi->stats_update = jiffies;
+}
+
+static void minstrel_ht_set_rate(struct ssv62xx_ht *mi,
+ struct fw_rc_retry_params *rate, int index,
+ bool sample, bool rtscts,
+ struct ssv_sta_rc_info *rc_sta,
+ struct ssv_rate_ctrl *ssv_rc)
+{
+ struct minstrel_rate_stats *mr;
+ mr = minstrel_get_ratestats(mi, index);
+ rate->drate = ssv_rc->rc_table[mr->rc_index].hw_rate_idx;
+ rate->crate = ssv_rc->rc_table[mr->rc_index].ctrl_rate_idx;
+}
+
+static inline int minstrel_get_duration(int index,
+ struct ssv_sta_rc_info *rc_sta)
+{
+ unsigned int group_id;
+ const struct mcs_group *group;
+ if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
+ group_id = 0;
+ else
+ group_id = 1;
+ group = &minstrel_mcs_groups_ssv[group_id];
+ return group->duration[index % MCS_GROUP_RATES];
+}
+
+static void minstrel_next_sample_idx(struct ssv62xx_ht *mi)
+{
+ struct minstrel_mcs_group_data *mg;
+ for (;;) {
+ mg = &mi->groups;
+ if (++mg->index >= MCS_GROUP_RATES) {
+ mg->index = 0;
+ if (++mg->column >= ARRAY_SIZE(sample_table))
+ mg->column = 0;
+ }
+ break;
+ }
+}
+
+static int minstrel_get_sample_rate(struct ssv62xx_ht *mi,
+ struct ssv_sta_rc_info *rc_sta)
+{
+ struct minstrel_rate_stats *mr;
+ struct minstrel_mcs_group_data *mg;
+ int sample_idx = 0;
+ if (mi->sample_wait > 0) {
+ mi->sample_wait--;
+ return -1;
+ }
+ if (!mi->sample_tries)
+ return -1;
+ mi->sample_tries--;
+ mg = &mi->groups;
+ sample_idx = sample_table[mg->column][mg->index];
+ mr = &mg->rates[sample_idx];
+ minstrel_next_sample_idx(mi);
+ if (minstrel_get_duration(sample_idx, rc_sta) >
+ minstrel_get_duration(mi->max_tp_rate, rc_sta)) {
+ if (mr->sample_skipped < 20) {
+ return -1;
+ }
+ if (mi->sample_slow++ > 2) {
+ return -1;
+ }
+ }
+ return sample_idx;
+}
+
+static void _fill_txinfo_rates(struct ssv_rate_ctrl *ssv_rc,
+ struct sk_buff *skb,
+ struct fw_rc_retry_params *ar)
+{
+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+ info->control.rates[0].idx =
+ ssv_rc->rc_table[ar[0].drate].dot11_rate_idx;
+ info->control.rates[0].count = 1;
+ info->control.rates[SSV_DRATE_IDX].count = ar[0].drate;
+ info->control.rates[SSV_CRATE_IDX].count = ar[0].crate;
+}
+
+extern const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13];
+s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc,
+ struct fw_rc_retry_params *ar)
+{
+ struct ssv_rate_ctrl *ssv_rc = sc->rc;
+ struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+ struct ieee80211_sta *sta = skb_info->sta;
+ struct ssv62xx_ht *mi = NULL;
+ int sample_idx;
+ bool sample = false;
+ struct ssv_sta_rc_info *rc_sta;
+ struct ssv_sta_priv_data *sta_priv;
+ struct rc_pid_sta_info *spinfo;
+ int ret = 0;
+ if (sc->sc_flags & SC_OP_FIXED_RATE) {
+ ar[0].count = 3;
+ ar[0].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+ ar[0].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
+ ar[1].count = 2;
+ ar[1].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+ ar[1].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
+ ar[2].count = 2;
+ ar[2].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+ ar[2].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
+ _fill_txinfo_rates(ssv_rc, skb, ar);
+ return ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+ }
+ if (sta == NULL) {
+ dev_err(sc->dev, "Station NULL\n");
+ BUG_ON(1);
+ }
+ sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx];
+ spinfo = &rc_sta->spinfo;
+ if ((rc_sta->rc_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT)
+ || (rc_sta->rc_wsid < 0)) {
+ struct ssv_sta_priv_data *ssv_sta_priv;
+ int rateidx = 99;
+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ {
+ if ((rc_sta->ht_rc_type >= RC_TYPE_HT_SGI_20) &&
+ (ssv_sta_priv->rx_data_rate <
+ SSV62XX_RATE_MCS_INDEX)) {
+ if (ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0]
+ == 12)
+ rateidx =
+ (int)rc_sta->pinfo.rinfo[4].
+ rc_index;
+ else
+ rateidx =
+ (int)rc_sta->pinfo.rinfo[0].
+ rc_index;
+ } else {
+ rateidx = (int)ssv_sta_priv->rx_data_rate;
+ rateidx -= SSV62XX_RATE_MCS_INDEX;
+ rateidx %= 8;
+ if (rc_sta->ht_rc_type == RC_TYPE_HT_SGI_20)
+ rateidx += SSV62XX_RATE_MCS_SGI_INDEX;
+ else if (rc_sta->ht_rc_type ==
+ RC_TYPE_HT_LGI_20)
+ rateidx += SSV62XX_RATE_MCS_LGI_INDEX;
+ else
+ rateidx +=
+ SSV62XX_RATE_MCS_GREENFIELD_INDEX;
+ }
+ }
+ ar[0].count = 3;
+ ar[2].drate = ar[1].drate = ar[0].drate =
+ ssv_rc->rc_table[rateidx].hw_rate_idx;
+ ar[2].crate = ar[1].crate = ar[0].crate =
+ ssv_rc->rc_table[rateidx].ctrl_rate_idx;
+ ar[1].count = 2;
+ ar[2].count = 2;
+ _fill_txinfo_rates(ssv_rc, skb, ar);
+ return rateidx;
+ }
+ mi = &rc_sta->ht;
+ sample_idx = minstrel_get_sample_rate(mi, rc_sta);
+ if (sample_idx >= 0) {
+ sample = true;
+ minstrel_ht_set_rate(mi, &ar[0], sample_idx,
+ true, false, rc_sta, ssv_rc);
+ } else {
+ minstrel_ht_set_rate(mi, &ar[0], mi->max_tp_rate,
+ false, false, rc_sta, ssv_rc);
+ }
+ ar[0].count = mi->first_try_count;
+ ret = ar[0].drate;
+ {
+ if (sample_idx >= 0)
+ minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate,
+ false, false, rc_sta, ssv_rc);
+ else
+ minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate2,
+ false, true, rc_sta, ssv_rc);
+ ar[1].count = mi->second_try_count;
+ if (ret > ar[1].drate)
+ ret = ar[1].drate;
+ minstrel_ht_set_rate(mi, &ar[2], mi->max_prob_rate,
+ false, !sample, rc_sta, ssv_rc);
+ ar[2].count = mi->other_try_count;
+ if (ret > ar[2].drate)
+ ret = ar[2].drate;
+ }
+ mi->total_packets++;
+ if (mi->total_packets == ~0) {
+ mi->total_packets = 0;
+ mi->sample_packets = 0;
+ }
+ if (spinfo->real_hw_index < SSV62XX_RATE_MCS_INDEX)
+ return spinfo->real_hw_index;
+ _fill_txinfo_rates(ssv_rc, skb, ar);
+ return ret;
+}
+
+static void init_sample_table(void)
+{
+ int col, i, new_idx;
+ u8 rnd[MCS_GROUP_RATES];
+ memset(sample_table, 0xff, sizeof(sample_table));
+ for (col = 0; col < SAMPLE_COLUMNS; col++) {
+ for (i = 0; i < MCS_GROUP_RATES; i++) {
+ get_random_bytes(rnd, sizeof(rnd));
+ new_idx = (i + rnd[i]) % MCS_GROUP_RATES;
+ while (sample_table[col][new_idx] != 0xff)
+ new_idx = (new_idx + 1) % MCS_GROUP_RATES;
+ sample_table[col][new_idx] = i;
+ }
+ }
+}
+
+void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],
+ struct ssv_sta_rc_info *rc_sta)
+{
+ struct ssv62xx_ht *mi = &rc_sta->ht;
+ int ack_dur;
+ int i;
+ unsigned int group_id;
+ if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
+ group_id = 0;
+ else
+ group_id = 1;
+ for (i = 0; i < MCS_GROUP_RATES; i++) {
+ pr_debug("[RC]HT duration[%d][%d]\n", i,
+ minstrel_mcs_groups_ssv[group_id].duration[i]);
+ }
+ init_sample_table();
+ memset(mi, 0, sizeof(*mi));
+ mi->stats_update = jiffies;
+ ack_dur = pide_frame_duration(10, 60, 0, 0);
+ mi->overhead = pide_frame_duration(0, 60, 0, 0) + ack_dur;
+ mi->overhead_rtscts = mi->overhead + 2 * ack_dur;
+ mi->avg_ampdu_len = MINSTREL_FRAC(1, 1);
+ mi->sample_count = 16;
+ mi->sample_wait = 0;
+ mi->sample_tries = 4;
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+ mi->max_tp_rate = MCS_GROUP_RATES - 1;
+ mi->max_tp_rate2 = MCS_GROUP_RATES - 1;
+ mi->max_prob_rate = MCS_GROUP_RATES - 1;
+#endif
+#if (HW_MAX_RATE_TRIES == 7)
+ {
+ mi->first_try_count = 3;
+ mi->second_try_count = 2;
+ mi->other_try_count = 2;
+ }
+#else
+ {
+ mi->first_try_count = 2;
+ mi->second_try_count = 1;
+ mi->other_try_count = 1;
+ }
+#endif
+ for (i = 0; i < MCS_GROUP_RATES; i++) {
+ mi->groups.rates[i].rc_index =
+ ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][i + 1];
+ }
+}
+
+static bool minstrel_ht_txstat_valid(struct ssv62xx_tx_rate *rate)
+{
+ if (!rate->count)
+ return false;
+ if (rate->data_rate < 0)
+ return false;
+ return true;
+}
+
+void ssv6xxx_ht_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
+ struct ssv_sta_rc_info *rc_sta)
+{
+ struct cfg_host_event *host_event;
+ struct firmware_rate_control_report_data *report_data;
+ struct ssv62xx_ht *mi;
+ struct minstrel_rate_stats *rate;
+ bool last = false;
+ int i = 0;
+ u16 report_ampdu_packets = 0;
+ unsigned long period;
+ host_event = (struct cfg_host_event *)skb->data;
+ report_data =
+ (struct firmware_rate_control_report_data *)&host_event->dat[0];
+ if (host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) {
+ report_ampdu_packets = 1;
+ } else if (host_event->h_event == SOC_EVT_RC_MPDU_REPORT) {
+ report_data->ampdu_len = 1;
+ report_ampdu_packets = report_data->ampdu_len;
+ } else {
+ dev_warn(sc->dev, "rate control report handler got garbage\n");
+ return;
+ }
+ mi = &rc_sta->ht;
+ mi->ampdu_packets += report_ampdu_packets;
+ mi->ampdu_len += report_data->ampdu_len;
+ if (!mi->sample_wait && !mi->sample_tries && mi->sample_count > 0) {
+ mi->sample_wait = 16 + 2 * MINSTREL_TRUNC(mi->avg_ampdu_len);
+ mi->sample_tries = 2;
+ mi->sample_count--;
+ }
+ for (i = 0; !last; i++) {
+ last = (i == SSV62XX_TX_MAX_RATES - 1) ||
+ !minstrel_ht_txstat_valid(&report_data->rates[i + 1]);
+ if (!minstrel_ht_txstat_valid(&report_data->rates[i]))
+ break;
+#ifdef RATE_CONTROL_DEBUG
+ if ((report_data->rates[i].data_rate < SSV62XX_RATE_MCS_INDEX)
+ || (report_data->rates[i].data_rate >=
+ SSV62XX_RATE_MCS_GREENFIELD_INDEX)) {
+ dev_dbg
+ (sc->dev, "[RC]ssv6xxx_ht_report_handler get error report rate[%d]\n",
+ report_data->rates[i].data_rate);
+ break;
+ }
+#endif
+ rate =
+ &mi->groups.
+ rates[(report_data->rates[i].data_rate -
+ SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES];
+ if (last)
+ rate->success += report_data->ampdu_ack_len;
+ rate->attempts +=
+ report_data->rates[i].count * report_data->ampdu_len;
+ }
+ period = msecs_to_jiffies(SSV_RC_HT_INTERVAL / 2);
+ if (time_after(jiffies, mi->stats_update + period)) {
+ rate_control_ht_sample(mi, rc_sta);
+ }
+}
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
new file mode 100644
index 000000000000..275c3356e036
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_RC_HT_H_
+#define _SSV_RC_HT_H_
+#include "ssv_rc_common.h"
+#define MINSTREL_SCALE 16
+#define MINSTREL_FRAC(val,div) (((val) << MINSTREL_SCALE) / div)
+#define MINSTREL_TRUNC(val) ((val) >> MINSTREL_SCALE)
+#define SSV_RC_HT_INTERVAL 100
+extern const u16 ampdu_max_transmit_length[];
+s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc,
+ struct fw_rc_retry_params *ar);
+void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],
+ struct ssv_sta_rc_info *rc_sta);
+void ssv6xxx_ht_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
+ struct ssv_sta_rc_info *rc_sta);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_pm.c b/drivers/net/wireless/ssv6051/smac/ssv_pm.c
new file mode 100644
index 000000000000..fc3be2013f61
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_pm.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200.h>
+#include "dev.h"
+#include "sar.h"
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_pm.h b/drivers/net/wireless/ssv6051/smac/ssv_pm.h
new file mode 100644
index 000000000000..9be260dd904e
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_pm.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_PM_H_
+#define _SSV_PM_H_
+#include <linux/version.h>
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc.c b/drivers/net/wireless/ssv6051/smac/ssv_rc.c
new file mode 100644
index 000000000000..9c3574285364
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_rc.c
@@ -0,0 +1,1716 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ssv_ht_rc.h"
+#include "ssv_rc.h"
+#include "ssv_rc_common.h"
+static struct ssv_rc_rate ssv_11bgn_rate_table[] = {
+ [0] = {.rc_flags = RC_FLAG_LEGACY,
+ .phy_type = WLAN_RC_PHY_CCK,
+ .rate_kbps = 1000,
+ .dot11_rate_idx = 0,
+ .ctrl_rate_idx = 0,
+ .hw_rate_idx = 0,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [1] = {.rc_flags = RC_FLAG_LEGACY,
+ .phy_type = WLAN_RC_PHY_CCK,
+ .rate_kbps = 2000,
+ .dot11_rate_idx = 1,
+ .ctrl_rate_idx = 1,
+ .hw_rate_idx = 1,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [2] = {.rc_flags = RC_FLAG_LEGACY,
+ .phy_type = WLAN_RC_PHY_CCK,
+ .rate_kbps = 5500,
+ .dot11_rate_idx = 2,
+ .ctrl_rate_idx = 1,
+ .hw_rate_idx = 2,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [3] = {.rc_flags = RC_FLAG_LEGACY,
+ .phy_type = WLAN_RC_PHY_CCK,
+ .rate_kbps = 11000,
+ .dot11_rate_idx = 3,
+ .ctrl_rate_idx = 1,
+ .hw_rate_idx = 3,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [4] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
+ .phy_type = WLAN_RC_PHY_CCK,
+ .rate_kbps = 2000,
+ .dot11_rate_idx = 1,
+ .ctrl_rate_idx = 4,
+ .hw_rate_idx = 4,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [5] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
+ .phy_type = WLAN_RC_PHY_CCK,
+ .rate_kbps = 5500,
+ .dot11_rate_idx = 2,
+ .ctrl_rate_idx = 4,
+ .hw_rate_idx = 5,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [6] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
+ .phy_type = WLAN_RC_PHY_CCK,
+ .rate_kbps = 11000,
+ .dot11_rate_idx = 3,
+ .ctrl_rate_idx = 4,
+ .hw_rate_idx = 6,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [7] = {.rc_flags = RC_FLAG_LEGACY,
+ .phy_type = WLAN_RC_PHY_OFDM,
+ .rate_kbps = 6000,
+ .dot11_rate_idx = 4,
+ .ctrl_rate_idx = 7,
+ .hw_rate_idx = 7,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [8] = {.rc_flags = RC_FLAG_LEGACY,
+ .phy_type = WLAN_RC_PHY_OFDM,
+ .rate_kbps = 9000,
+ .dot11_rate_idx = 5,
+ .ctrl_rate_idx = 7,
+ .hw_rate_idx = 8,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [9] = {.rc_flags = RC_FLAG_LEGACY,
+ .phy_type = WLAN_RC_PHY_OFDM,
+ .rate_kbps = 12000,
+ .dot11_rate_idx = 6,
+ .ctrl_rate_idx = 9,
+ .hw_rate_idx = 9,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [10] = {.rc_flags = RC_FLAG_LEGACY,
+ .phy_type = WLAN_RC_PHY_OFDM,
+ .rate_kbps = 18000,
+ .dot11_rate_idx = 7,
+ .ctrl_rate_idx = 9,
+ .hw_rate_idx = 10,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [11] = {.rc_flags = RC_FLAG_LEGACY,
+ .phy_type = WLAN_RC_PHY_OFDM,
+ .rate_kbps = 24000,
+ .dot11_rate_idx = 8,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 11,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [12] = {.rc_flags = RC_FLAG_LEGACY,
+ .phy_type = WLAN_RC_PHY_OFDM,
+ .rate_kbps = 36000,
+ .dot11_rate_idx = 9,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 12,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [13] = {.rc_flags = RC_FLAG_LEGACY,
+ .phy_type = WLAN_RC_PHY_OFDM,
+ .rate_kbps = 48000,
+ .dot11_rate_idx = 10,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 13,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [14] = {.rc_flags = RC_FLAG_LEGACY,
+ .phy_type = WLAN_RC_PHY_OFDM,
+ .rate_kbps = 54000,
+ .dot11_rate_idx = 11,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 14,
+ .arith_shift = 8,
+ .target_pf = 8},
+ [15] = {.rc_flags = RC_FLAG_HT,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+ .rate_kbps = 6500,
+ .dot11_rate_idx = 0,
+ .ctrl_rate_idx = 7,
+ .hw_rate_idx = 15,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [16] = {.rc_flags = RC_FLAG_HT,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+ .rate_kbps = 13000,
+ .dot11_rate_idx = 1,
+ .ctrl_rate_idx = 9,
+ .hw_rate_idx = 16,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [17] = {.rc_flags = RC_FLAG_HT,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+ .rate_kbps = 19500,
+ .dot11_rate_idx = 2,
+ .ctrl_rate_idx = 9,
+ .hw_rate_idx = 17,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [18] = {.rc_flags = RC_FLAG_HT,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+ .rate_kbps = 26000,
+ .dot11_rate_idx = 3,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 18,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [19] = {.rc_flags = RC_FLAG_HT,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+ .rate_kbps = 39000,
+ .dot11_rate_idx = 4,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 19,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [20] = {.rc_flags = RC_FLAG_HT,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+ .rate_kbps = 52000,
+ .dot11_rate_idx = 5,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 20,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [21] = {.rc_flags = RC_FLAG_HT,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+ .rate_kbps = 58500,
+ .dot11_rate_idx = 6,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 21,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [22] = {.rc_flags = RC_FLAG_HT,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+ .rate_kbps = 65000,
+ .dot11_rate_idx = 7,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 22,
+ .arith_shift = 8,
+ .target_pf = 8},
+ [23] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+ .rate_kbps = 7200,
+ .dot11_rate_idx = 0,
+ .ctrl_rate_idx = 7,
+ .hw_rate_idx = 23,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [24] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+ .rate_kbps = 14400,
+ .dot11_rate_idx = 1,
+ .ctrl_rate_idx = 9,
+ .hw_rate_idx = 24,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [25] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+ .rate_kbps = 21700,
+ .dot11_rate_idx = 2,
+ .ctrl_rate_idx = 9,
+ .hw_rate_idx = 25,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [26] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+ .rate_kbps = 28900,
+ .dot11_rate_idx = 3,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 26,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [27] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+ .rate_kbps = 43300,
+ .dot11_rate_idx = 4,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 27,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [28] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+ .rate_kbps = 57800,
+ .dot11_rate_idx = 5,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 28,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [29] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+ .rate_kbps = 65000,
+ .dot11_rate_idx = 6,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 29,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [30] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+ .rate_kbps = 72200,
+ .dot11_rate_idx = 7,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 30,
+ .arith_shift = 8,
+ .target_pf = 8},
+ [31] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+ .rate_kbps = 6500,
+ .dot11_rate_idx = 0,
+ .ctrl_rate_idx = 7,
+ .hw_rate_idx = 31,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [32] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+ .rate_kbps = 13000,
+ .dot11_rate_idx = 1,
+ .ctrl_rate_idx = 9,
+ .hw_rate_idx = 32,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [33] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+ .rate_kbps = 19500,
+ .dot11_rate_idx = 2,
+ .ctrl_rate_idx = 9,
+ .hw_rate_idx = 33,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [34] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+ .rate_kbps = 26000,
+ .dot11_rate_idx = 3,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 34,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [35] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+ .rate_kbps = 39000,
+ .dot11_rate_idx = 4,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 35,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [36] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+ .rate_kbps = 52000,
+ .dot11_rate_idx = 5,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 36,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [37] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+ .rate_kbps = 58500,
+ .dot11_rate_idx = 6,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 37,
+ .arith_shift = 8,
+ .target_pf = 26,
+ },
+ [38] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+ .phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+ .rate_kbps = 65000,
+ .dot11_rate_idx = 7,
+ .ctrl_rate_idx = 11,
+ .hw_rate_idx = 38,
+ .arith_shift = 8,
+ .target_pf = 8},
+};
+
+const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13] = {
+ [RC_TYPE_B_ONLY] = {4, 0, 1, 2, 3},
+ [RC_TYPE_LEGACY_GB] = {12, 0, 1, 2, 7, 8, 3, 9, 10, 11, 12, 13, 14},
+ [RC_TYPE_SGI_20] = {8, 23, 24, 25, 26, 27, 28, 29, 30},
+ [RC_TYPE_LGI_20] = {8, 15, 16, 17, 18, 19, 20, 21, 22},
+ [RC_TYPE_HT_SGI_20] = {8, 23, 24, 25, 26, 27, 28, 29, 30},
+ [RC_TYPE_HT_LGI_20] = {8, 15, 16, 17, 18, 19, 20, 21, 22},
+ [RC_TYPE_HT_GF] = {8, 31, 32, 33, 34, 35, 36, 37, 38},
+};
+
+static u32 ssv6xxx_rate_supported(struct ssv_sta_rc_info *rc_sta, u32 index)
+{
+ return (rc_sta->rc_supp_rates & BIT(index));
+}
+
+static u8 ssv6xxx_rate_lowest_index(struct ssv_sta_rc_info *rc_sta)
+{
+ int i;
+ for (i = 0; i < rc_sta->rc_num_rate; i++)
+ if (ssv6xxx_rate_supported(rc_sta, i))
+ return i;
+ return 0;
+}
+
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+static u8 ssv6xxx_rate_highest_index(struct ssv_sta_rc_info *rc_sta)
+{
+ int i;
+ for (i = rc_sta->rc_num_rate - 1; i >= 0; i--)
+ if (ssv6xxx_rate_supported(rc_sta, i))
+ return i;
+ return 0;
+}
+#endif
+static void rate_control_pid_adjust_rate(struct ssv_sta_rc_info *rc_sta,
+ struct rc_pid_sta_info *spinfo,
+ int adj, struct rc_pid_rateinfo *rinfo)
+{
+ int cur_sorted, new_sorted, probe, tmp, n_bitrates;
+ int cur = spinfo->txrate_idx;
+ n_bitrates = rc_sta->rc_num_rate;
+ cur_sorted = rinfo[cur].index;
+ new_sorted = cur_sorted + adj;
+ if (new_sorted < 0)
+ new_sorted = rinfo[0].index;
+ else if (new_sorted >= n_bitrates)
+ new_sorted = rinfo[n_bitrates - 1].index;
+ tmp = new_sorted;
+ if (adj < 0) {
+ for (probe = cur_sorted; probe >= new_sorted; probe--)
+ if (rinfo[probe].diff <= rinfo[cur_sorted].diff &&
+ ssv6xxx_rate_supported(rc_sta, rinfo[probe].index))
+ tmp = probe;
+ } else {
+ for (probe = new_sorted + 1; probe < n_bitrates; probe++)
+ if (rinfo[probe].diff <= rinfo[new_sorted].diff &&
+ ssv6xxx_rate_supported(rc_sta, rinfo[probe].index))
+ tmp = probe;
+ }
+ BUG_ON(tmp < 0 || tmp >= n_bitrates);
+ do {
+ if (ssv6xxx_rate_supported(rc_sta, rinfo[tmp].index)) {
+ spinfo->tmp_rate_idx = rinfo[tmp].index;
+ break;
+ }
+ if (adj < 0)
+ tmp--;
+ else
+ tmp++;
+ } while (tmp < n_bitrates && tmp >= 0);
+ spinfo->oldrate = spinfo->txrate_idx;
+ if (spinfo->tmp_rate_idx != spinfo->txrate_idx) {
+ spinfo->monitoring = 1;
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+ pr_debug("Trigger monitor tmp_rate_idx=[%d]\n",
+ spinfo->tmp_rate_idx);
+#endif
+ spinfo->probe_cnt = MAXPROBES;
+ }
+}
+
+static void rate_control_pid_normalize(struct rc_pid_info *pinfo, int l)
+{
+ int i, norm_offset = RC_PID_NORM_OFFSET;
+ struct rc_pid_rateinfo *r = pinfo->rinfo;
+ if (r[0].diff > norm_offset)
+ r[0].diff -= norm_offset;
+ else if (r[0].diff < -norm_offset)
+ r[0].diff += norm_offset;
+ for (i = 0; i < l - 1; i++)
+ if (r[i + 1].diff > r[i].diff + norm_offset)
+ r[i + 1].diff -= norm_offset;
+ else if (r[i + 1].diff <= r[i].diff)
+ r[i + 1].diff += norm_offset;
+}
+
+#ifdef RATE_CONTROL_DEBUG
+unsigned int txrate_dlr = 0;
+#endif
+static void rate_control_pid_sample(struct ssv_rate_ctrl *ssv_rc,
+ struct rc_pid_info *pinfo,
+ struct ssv_sta_rc_info *rc_sta,
+ struct rc_pid_sta_info *spinfo)
+{
+ struct rc_pid_rateinfo *rinfo = pinfo->rinfo;
+ u8 pf;
+ s32 err_avg;
+ s32 err_prop;
+ s32 err_int;
+ s32 err_der;
+ int adj, i, j, tmp;
+ struct ssv_rc_rate *rc_table;
+ unsigned int dlr;
+ unsigned int perfect_time = 0;
+ unsigned int this_thp, ewma_thp;
+ struct rc_pid_rateinfo *rate;
+ if (!spinfo->monitoring) {
+ if (spinfo->tx_num_xmit == 0)
+ return;
+ spinfo->last_sample = jiffies;
+ pf = spinfo->tx_num_failed * 100 / spinfo->tx_num_xmit;
+ if (pinfo->rinfo[spinfo->txrate_idx].this_attempt > 0) {
+ rate = &pinfo->rinfo[spinfo->txrate_idx];
+ rc_table = &ssv_rc->rc_table[spinfo->txrate_idx];
+ dlr = 100 - rate->this_fail * 100 / rate->this_attempt;
+ perfect_time = rate->perfect_tx_time;
+ if (!perfect_time)
+ perfect_time = 1000000;
+ this_thp = dlr * (1000000 / perfect_time);
+ ewma_thp = rate->throughput;
+ if (ewma_thp == 0)
+ rate->throughput = this_thp;
+ else
+ rate->throughput = (ewma_thp + this_thp) >> 1;
+ rate->attempt += rate->this_attempt;
+ rate->success += rate->this_success;
+ rate->fail += rate->this_fail;
+ spinfo->tx_num_xmit = 0;
+ spinfo->tx_num_failed = 0;
+ rate->this_fail = 0;
+ rate->this_success = 0;
+ rate->this_attempt = 0;
+ if (pinfo->oldrate < 0
+ || pinfo->oldrate >= rc_sta->rc_num_rate) {
+ WARN_ON(1);
+ }
+ if (spinfo->txrate_idx < 0
+ || spinfo->txrate_idx >= rc_sta->rc_num_rate) {
+ WARN_ON(1);
+ }
+ if (pinfo->oldrate != spinfo->txrate_idx) {
+ i = rinfo[pinfo->oldrate].index;
+ j = rinfo[spinfo->txrate_idx].index;
+ tmp = (pf - spinfo->last_pf);
+ tmp =
+ RC_PID_DO_ARITH_RIGHT_SHIFT(tmp,
+ rc_table->arith_shift);
+ rinfo[j].diff = rinfo[i].diff + tmp;
+ pinfo->oldrate = spinfo->txrate_idx;
+ }
+ rate_control_pid_normalize(pinfo, rc_sta->rc_num_rate);
+ err_prop =
+ (rc_table->target_pf - pf) << rc_table->arith_shift;
+ err_avg = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT;
+ spinfo->err_avg_sc =
+ spinfo->err_avg_sc - err_avg + err_prop;
+ err_int = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT;
+ err_der = pf - spinfo->last_pf;
+ spinfo->last_pf = pf;
+ spinfo->last_dlr = dlr;
+ spinfo->oldrate = spinfo->txrate_idx;
+ adj =
+ (err_prop * RC_PID_COEFF_P +
+ err_int * RC_PID_COEFF_I +
+ err_der * RC_PID_COEFF_D);
+ adj =
+ RC_PID_DO_ARITH_RIGHT_SHIFT(adj,
+ rc_table->arith_shift <<
+ 1);
+ if (adj) {
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+ if ((spinfo->txrate_idx != 11)
+ || ((spinfo->txrate_idx == 11)
+ && (adj < 0)))
+ pr_debug
+ ("[RC]Probe adjust[%d] dlr[%d%%] this_thp[%d] ewma_thp[%d] index[%d]\n",
+ adj, dlr, this_thp, ewma_thp,
+ spinfo->txrate_idx);
+#endif
+ rate_control_pid_adjust_rate(rc_sta, spinfo,
+ adj, rinfo);
+ }
+ }
+ } else {
+ if ((spinfo->feedback_probes >= MAXPROBES)
+ || (spinfo->feedback_probes && spinfo->probe_cnt)) {
+ rate = &pinfo->rinfo[spinfo->txrate_idx];
+ spinfo->last_sample = jiffies;
+ if (rate->this_attempt > 0) {
+ dlr =
+ 100 -
+ rate->this_fail * 100 / rate->this_attempt;
+#ifdef RATE_CONTROL_DEBUG
+#ifdef PROBE
+ txrate_dlr = dlr;
+#endif
+#endif
+ spinfo->last_dlr = dlr;
+ perfect_time = rate->perfect_tx_time;
+ if (!perfect_time)
+ perfect_time = 1000000;
+ this_thp = dlr * (1000000 / perfect_time);
+ ewma_thp = rate->throughput;
+ if (ewma_thp == 0)
+ rate->throughput = this_thp;
+ else
+ rate->throughput =
+ (ewma_thp + this_thp) >> 1;
+ rate->attempt += rate->this_attempt;
+ rate->success += rate->this_success;
+ rinfo[spinfo->txrate_idx].fail +=
+ rate->this_fail;
+ rate->this_fail = 0;
+ rate->this_success = 0;
+ rate->this_attempt = 0;
+ } else {
+#ifdef RATE_CONTROL_DEBUG
+#ifdef PROBE
+ txrate_dlr = 0;
+#endif
+#endif
+ }
+ rate = &pinfo->rinfo[spinfo->tmp_rate_idx];
+ if (rate->this_attempt > 0) {
+ dlr =
+ 100 -
+ ((rate->this_fail * 100) /
+ rate->this_attempt);
+ {
+ perfect_time = rate->perfect_tx_time;
+ if (!perfect_time)
+ perfect_time = 1000000;
+ if (dlr)
+ this_thp =
+ dlr * (1000000 /
+ perfect_time);
+ else
+ this_thp = 0;
+ ewma_thp = rate->throughput;
+ if (ewma_thp == 0)
+ rate->throughput = this_thp;
+ else
+ rate->throughput =
+ (ewma_thp + this_thp) >> 1;
+ if (rate->throughput >
+ pinfo->rinfo[spinfo->
+ txrate_idx].throughput)
+ {
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+ pr_debug
+ ("[RC]UPDATE probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n",
+ spinfo->tmp_rate_idx,
+ rate->throughput, dlr,
+ spinfo->txrate_idx,
+ pinfo->
+ rinfo
+ [spinfo->txrate_idx].throughput,
+ txrate_dlr,
+ spinfo->feedback_probes);
+#endif
+ spinfo->txrate_idx =
+ spinfo->tmp_rate_idx;
+ } else {
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+ pr_debug
+ ("[RC]Fail probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n",
+ spinfo->tmp_rate_idx,
+ rate->throughput, dlr,
+ spinfo->txrate_idx,
+ pinfo->
+ rinfo
+ [spinfo->txrate_idx].throughput,
+ txrate_dlr,
+ spinfo->feedback_probes);
+#endif
+ ;
+ }
+ rate->attempt += rate->this_attempt;
+ rate->success += rate->this_success;
+ rate->fail += rate->this_fail;
+ rate->this_fail = 0;
+ rate->this_success = 0;
+ rate->this_attempt = 0;
+ spinfo->oldrate = spinfo->txrate_idx;
+ }
+ }
+#ifdef RATE_CONTROL_DEBUG
+ else
+ pr_err("Unexpected error\n");
+#endif
+ spinfo->feedback_probes = 0;
+ spinfo->tx_num_xmit = 0;
+ spinfo->tx_num_failed = 0;
+ spinfo->monitoring = 0;
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+ pr_debug("Disable monitor\n");
+#endif
+ spinfo->probe_report_flag = 0;
+ spinfo->probe_wating_times = 0;
+ } else {
+ spinfo->probe_wating_times++;
+#ifdef RATE_CONTROL_DEBUG
+ if (spinfo->probe_wating_times > 3) {
+ pr_debug
+ ("[RC]@@@@@ PROBE LOSE @@@@@ feedback=[%d] need=[%d] probe_cnt=[%d] wating times[%d]\n",
+ spinfo->feedback_probes, MAXPROBES,
+ spinfo->probe_cnt,
+ spinfo->probe_wating_times);
+ spinfo->feedback_probes = 0;
+ spinfo->tx_num_xmit = 0;
+ spinfo->tx_num_failed = 0;
+ spinfo->monitoring = 0;
+ spinfo->probe_report_flag = 0;
+ spinfo->probe_wating_times = 0;
+ }
+#else
+ if (spinfo->probe_wating_times > 3) {
+ spinfo->feedback_probes = 0;
+ spinfo->tx_num_xmit = 0;
+ spinfo->tx_num_failed = 0;
+ spinfo->monitoring = 0;
+ spinfo->probe_report_flag = 0;
+ spinfo->probe_wating_times = 0;
+ }
+#endif
+ }
+ }
+}
+
+#ifdef RATE_CONTROL_PERCENTAGE_TRACE
+int percentage = 0;
+int percentageCounter = 0;
+#endif
+void ssv6xxx_legacy_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
+ struct ssv_sta_rc_info *rc_sta)
+{
+ struct ssv_rate_ctrl *ssv_rc = sc->rc;
+ struct cfg_host_event *host_event;
+ struct firmware_rate_control_report_data *report_data;
+ struct rc_pid_info *pinfo;
+ struct rc_pid_sta_info *spinfo;
+ struct rc_pid_rateinfo *pidrate;
+ struct rc_pid_rateinfo *rate;
+ s32 report_data_index = 0;
+ unsigned long period;
+ host_event = (struct cfg_host_event *)skb->data;
+ report_data =
+ (struct firmware_rate_control_report_data *)&host_event->dat[0];
+ if ((report_data->wsid != (-1))
+ && sc->sta_info[report_data->wsid].sta == NULL) {
+ dev_warn(sc->dev, "RC report has no valid STA.(%d)\n",
+ report_data->wsid);
+ return;
+ }
+ pinfo = &rc_sta->pinfo;
+ spinfo = &rc_sta->spinfo;
+ pidrate = rc_sta->pinfo.rinfo;
+ if (host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) {
+ period = msecs_to_jiffies(HT_RC_UPDATE_INTERVAL);
+ if (time_after(jiffies, spinfo->last_sample + period)) {
+ if (rc_sta->rc_num_rate == 12)
+ spinfo->txrate_idx = rc_sta->ht.max_tp_rate + 4;
+ else
+ spinfo->txrate_idx = rc_sta->ht.max_tp_rate;
+#ifdef RATE_CONTROL_DEBUG
+ pr_debug("MPDU rate update time txrate_idx[%d]!!\n",
+ spinfo->txrate_idx);
+#endif
+ spinfo->last_sample = jiffies;
+ }
+ return;
+ } else if (host_event->h_event == SOC_EVT_RC_MPDU_REPORT) {
+ ;
+ } else {
+ dev_warn(sc->dev, "RC report handler got garbage\n");
+ return;
+ }
+ if (report_data->rates[0].data_rate < 7) {
+ if (report_data->rates[0].data_rate > 3) {
+ report_data->rates[0].data_rate -= 3;
+ }
+ }
+ if (ssv_rc->
+ rc_table[rc_sta->pinfo.rinfo[spinfo->txrate_idx].
+ rc_index].hw_rate_idx == report_data->rates[0].data_rate) {
+ report_data_index =
+ rc_sta->pinfo.rinfo[spinfo->txrate_idx].index;
+ } else
+ if (ssv_rc->rc_table
+ [rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].
+ rc_index].hw_rate_idx == report_data->rates[0].data_rate) {
+ report_data_index =
+ rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].index;
+ }
+ if ((report_data_index != spinfo->tmp_rate_idx)
+ && (report_data_index != spinfo->txrate_idx)) {
+#ifdef RATE_CONTROL_DEBUG
+ dev_dbg
+ (sc->dev, "Rate control report mismatch report_rate_idx[%d] tmp_rate_idx[%d]rate[%d] txrate_idx[%d]rate[%d]!!\n",
+ report_data->rates[0].data_rate, spinfo->tmp_rate_idx,
+ ssv_rc->rc_table[rc_sta->pinfo.
+ rinfo[spinfo->tmp_rate_idx].rc_index].
+ hw_rate_idx, spinfo->txrate_idx,
+ ssv_rc->rc_table[rc_sta->pinfo.
+ rinfo[spinfo->txrate_idx].rc_index].
+ hw_rate_idx);
+#endif
+ return;
+ }
+ if (report_data_index == spinfo->txrate_idx) {
+ spinfo->tx_num_xmit += report_data->rates[0].count;
+ spinfo->tx_num_failed +=
+ (report_data->rates[0].count - report_data->ampdu_ack_len);
+ rate = &pidrate[spinfo->txrate_idx];
+ rate->this_fail +=
+ (report_data->rates[0].count - report_data->ampdu_ack_len);
+ rate->this_attempt += report_data->rates[0].count;
+ rate->this_success += report_data->ampdu_ack_len;
+ }
+ if (report_data_index != spinfo->txrate_idx
+ && report_data_index == spinfo->tmp_rate_idx) {
+ spinfo->feedback_probes += report_data->ampdu_len;
+ rate = &pidrate[spinfo->tmp_rate_idx];
+ rate->this_fail +=
+ (report_data->rates[0].count - report_data->ampdu_ack_len);
+ rate->this_attempt += report_data->rates[0].count;
+ rate->this_success += report_data->ampdu_ack_len;
+ }
+ period = msecs_to_jiffies(RC_PID_INTERVAL);
+ if (time_after(jiffies, spinfo->last_sample + period)) {
+#ifdef RATE_CONTROL_PERCENTAGE_TRACE
+ rate = &pidrate[spinfo->txrate_idx];
+ if (rate->this_success > rate->this_attempt) {
+ dev_dbg(sc->dev, "this_success[%ld] this_attempt[%ld]\n",
+ rate->this_success, rate->this_attempt);
+ } else {
+ if (percentage == 0)
+ percentage =
+ (int)((rate->this_success * 100) /
+ rate->this_attempt);
+ else
+ percentage =
+ (percentage +
+ (int)((rate->this_success * 100) /
+ rate->this_attempt)) / 2;
+ deb_dbg(sc->dev, "Percentage[%d]\n", percentage);
+ if ((percentageCounter % 16) == 1)
+ percentage = 0;
+ }
+#endif
+#ifdef RATE_CONTROL_STUPID_DEBUG
+ if (spinfo->txrate_idx != spinfo->tmp_rate_idx) {
+ rate = &pidrate[spinfo->tmp_rate_idx];
+ if (spinfo->monitoring && ((rate->this_attempt == 0)
+ || (rate->this_attempt !=
+ MAXPROBES))) {
+ dev_dbg(sc->dev, "Probe result a[%ld]s[%ld]f[%ld]",
+ rate->this_attempt, rate->this_success,
+ rate->this_fail);
+ }
+ rate = &pidrate[spinfo->txrate_idx];
+ dev_dbg(sc->dev, "New a[%ld]s[%ld]f[%ld] \n", rate->this_attempt,
+ rate->this_success, rate->this_fail);
+ } else {
+ rate = &pidrate[spinfo->txrate_idx];
+ dev_dbg(sc->dev, "New a[%ld]s[%ld]f[%ld] \n", rate->this_attempt,
+ rate->this_success, rate->this_fail);
+ }
+ dev_dbg(sc->dev, "w[%d]x%03d-f%03d\n", rc_sta->rc_wsid,
+ spinfo->tx_num_xmit, spinfo->tx_num_failed);
+#endif
+ rate_control_pid_sample(sc->rc, pinfo, rc_sta, spinfo);
+ }
+}
+
+void ssv6xxx_sample_work(struct work_struct *work)
+{
+ struct ssv_softc *sc =
+ container_of(work, struct ssv_softc, rc_sample_work);
+ struct ssv_rate_ctrl *ssv_rc = sc->rc;
+ struct sk_buff *skb;
+ struct cfg_host_event *host_event;
+ struct ssv_sta_rc_info *rc_sta = NULL;
+ struct firmware_rate_control_report_data *report_data;
+ struct ssv_sta_info *ssv_sta;
+ u8 hw_wsid = 0;
+ sc->rc_sample_sechedule = 1;
+ while (1) {
+ skb = skb_dequeue(&sc->rc_report_queue);
+ if (skb == NULL)
+ break;
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+ {
+ dev_kfree_skb_any(skb);
+ continue;
+ }
+#endif
+ host_event = (struct cfg_host_event *)skb->data;
+ if ((host_event->h_event == SOC_EVT_RC_AMPDU_REPORT)
+ || (host_event->h_event == SOC_EVT_RC_MPDU_REPORT)) {
+ report_data =
+ (struct firmware_rate_control_report_data *)
+ &host_event->dat[0];
+ hw_wsid = report_data->wsid;
+ } else {
+ dev_warn(sc->dev, "rate control sampling got garbage\n");
+ dev_kfree_skb_any(skb);
+ continue;
+ }
+ if (hw_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) {
+#ifdef RATE_CONTROL_DEBUG
+ dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-0!!\n");
+#endif
+ dev_kfree_skb_any(skb);
+ continue;
+ }
+ ssv_sta = &sc->sta_info[hw_wsid];
+ if (ssv_sta->sta == NULL) {
+ dev_err(sc->dev, "Null STA %d for RC report.\n",
+ hw_wsid);
+ rc_sta = NULL;
+ } else {
+ struct ssv_sta_priv_data *ssv_sta_priv =
+ (struct ssv_sta_priv_data *)ssv_sta->sta->drv_priv;
+ rc_sta = &ssv_rc->sta_rc_info[ssv_sta_priv->rc_idx];
+ if (rc_sta->rc_wsid != hw_wsid) {
+ rc_sta = NULL;
+ }
+ }
+ if (rc_sta == NULL) {
+ dev_err(sc->dev,
+ "[RC]rc_sta is NULL pointer Check-1!!\n");
+ dev_kfree_skb_any(skb);
+ continue;
+ }
+ if (rc_sta == NULL) {
+#ifdef RATE_CONTROL_DEBUG
+ dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-2!!\n");
+#endif
+ dev_kfree_skb_any(skb);
+ continue;
+ }
+ if (rc_sta->is_ht) {
+ ssv6xxx_legacy_report_handler(sc, skb, rc_sta);
+ ssv6xxx_ht_report_handler(sc, skb, rc_sta);
+ } else
+ ssv6xxx_legacy_report_handler(sc, skb, rc_sta);
+ dev_kfree_skb_any(skb);
+ }
+ sc->rc_sample_sechedule = 0;
+}
+
+static void ssv6xxx_tx_status(void *priv,
+ struct ieee80211_supported_band *sband,
+ struct ieee80211_sta *sta, void *priv_sta,
+ struct sk_buff *skb)
+{
+ struct ssv_softc *sc;
+ struct ieee80211_hdr *hdr;
+ __le16 fc;
+ hdr = (struct ieee80211_hdr *)skb->data;
+ fc = hdr->frame_control;
+ if (!priv_sta || !ieee80211_is_data_qos(fc))
+ return;
+ sc = (struct ssv_softc *)priv;
+ if (conf_is_ht(&sc->hw->conf)
+ && (!(skb->protocol == cpu_to_be16(ETH_P_PAE)))) {
+ if (skb_get_queue_mapping(skb) != IEEE80211_AC_VO)
+ ssv6200_ampdu_tx_update_state(priv, sta, skb);
+ }
+ return;
+}
+
+static void rateControlGetRate(u8 rateIndex, char *pointer)
+{
+ switch (rateIndex) {
+ case 0:
+ sprintf(pointer, "1Mbps");
+ return;
+ case 1:
+ case 4:
+ sprintf(pointer, "2Mbps");
+ return;
+ case 2:
+ case 5:
+ sprintf(pointer, "5.5Mbps");
+ return;
+ case 3:
+ case 6:
+ sprintf(pointer, "11Mbps");
+ return;
+ case 7:
+ sprintf(pointer, "6Mbps");
+ return;
+ case 8:
+ sprintf(pointer, "9Mbps");
+ return;
+ case 9:
+ sprintf(pointer, "12Mbps");
+ return;
+ case 10:
+ sprintf(pointer, "18Mbps");
+ return;
+ case 11:
+ sprintf(pointer, "24Mbps");
+ return;
+ case 12:
+ sprintf(pointer, "36Mbps");
+ return;
+ case 13:
+ sprintf(pointer, "48Mbps");
+ return;
+ case 14:
+ sprintf(pointer, "54Mbps");
+ return;
+ case 15:
+ case 31:
+ sprintf(pointer, "MCS0-l");
+ return;
+ case 16:
+ case 32:
+ sprintf(pointer, "MCS1-l");
+ return;
+ case 17:
+ case 33:
+ sprintf(pointer, "MCS2-l");
+ return;
+ case 18:
+ case 34:
+ sprintf(pointer, "MCS3-l");
+ return;
+ case 19:
+ case 35:
+ sprintf(pointer, "MCS4-l");
+ return;
+ case 20:
+ case 36:
+ sprintf(pointer, "MCS5-l");
+ return;
+ case 21:
+ case 37:
+ sprintf(pointer, "MCS6-l");
+ return;
+ case 22:
+ case 38:
+ sprintf(pointer, "MCS7-l");
+ return;
+ case 23:
+ sprintf(pointer, "MCS0-s");
+ return;
+ case 24:
+ sprintf(pointer, "MCS1-s");
+ return;
+ case 25:
+ sprintf(pointer, "MCS2-s");
+ return;
+ case 26:
+ sprintf(pointer, "MCS3-s");
+ return;
+ case 27:
+ sprintf(pointer, "MCS4-s");
+ return;
+ case 28:
+ sprintf(pointer, "MCS5-s");
+ return;
+ case 29:
+ sprintf(pointer, "MCS6-s");
+ return;
+ case 30:
+ sprintf(pointer, "MCS7-s");
+ return;
+ default:
+ sprintf(pointer, "Unknow");
+ return;
+ };
+}
+
+static void ssv6xxx_get_rate(void *priv, struct ieee80211_sta *sta,
+ void *priv_sta,
+ struct ieee80211_tx_rate_control *txrc)
+{
+ struct ssv_softc *sc = priv;
+ struct ssv_rate_ctrl *ssv_rc = sc->rc;
+ struct ssv_sta_rc_info *rc_sta = priv_sta;
+ struct sk_buff *skb = txrc->skb;
+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+ struct ieee80211_tx_rate *rates = tx_info->control.rates;
+ struct rc_pid_sta_info *spinfo = &rc_sta->spinfo;
+ struct ssv_rc_rate *rc_rate = NULL;
+ struct ssv_sta_priv_data *ssv_sta_priv;
+ int rateidx = 99;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0)
+ if (rate_control_send_low(sta, priv_sta, txrc)) {
+ int i = 0;
+ int total_rates =
+ (sizeof(ssv_11bgn_rate_table) /
+ sizeof(ssv_11bgn_rate_table[0]));
+#if 1
+ if ((txrc->rate_idx_mask & (1 << rates[0].idx)) == 0) {
+ u32 rate_idx = rates[0].idx + 1;
+ u32 rate_idx_mask = txrc->rate_idx_mask >> rate_idx;
+ while (rate_idx_mask && (rate_idx_mask & 1) == 0) {
+ rate_idx_mask >>= 1;
+ rate_idx++;
+ }
+ if (rate_idx_mask)
+ rates[0].idx = rate_idx;
+ else {
+ WARN_ON(rate_idx_mask == 0);
+ }
+ }
+#endif
+ for (i = 0; i < total_rates; i++) {
+ if (rates[0].idx ==
+ ssv_11bgn_rate_table[i].dot11_rate_idx) {
+ break;
+ }
+ }
+ if (i < total_rates)
+ rc_rate = &ssv_rc->rc_table[i];
+ else {
+ WARN_ON("Failed to find matching low rate.");
+ }
+ }
+#endif
+ if (rc_rate == NULL) {
+ if (conf_is_ht(&sc->hw->conf) &&
+ (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING))
+ tx_info->flags |= IEEE80211_TX_CTL_LDPC;
+ if (conf_is_ht(&sc->hw->conf) &&
+ (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_TX_STBC))
+ tx_info->flags |= (1 << IEEE80211_TX_CTL_STBC_SHIFT);
+ if (sc->sc_flags & SC_OP_FIXED_RATE) {
+ rateidx = sc->max_rate_idx;
+ } else {
+ if (rc_sta->rc_valid == false) {
+ rateidx = 0;
+ } else {
+ if ((rc_sta->rc_wsid >=
+ SSV_RC_MAX_HARDWARE_SUPPORT)
+ || (rc_sta->rc_wsid < 0)) {
+ ssv_sta_priv =
+ (struct ssv_sta_priv_data *)
+ sta->drv_priv;
+ {
+ if ((rc_sta->ht_rc_type >=
+ RC_TYPE_HT_SGI_20)
+ &&
+ (ssv_sta_priv->rx_data_rate
+ <
+ SSV62XX_RATE_MCS_INDEX)) {
+ rateidx =
+ rc_sta->
+ pinfo.rinfo
+ [spinfo->txrate_idx].rc_index;
+ } else {
+ rateidx =
+ ssv_sta_priv->rx_data_rate;
+ }
+ }
+ } else {
+ if (rc_sta->is_ht) {
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+ rateidx =
+ rc_sta->ht.
+ groups.rates[MCS_GROUP_RATES
+ - 1].rc_index;
+#else
+ rateidx =
+ rc_sta->pinfo.
+ rinfo
+ [spinfo->txrate_idx].rc_index;
+#endif
+ } else {
+ {
+ BUG_ON
+ (spinfo->txrate_idx
+ >=
+ rc_sta->rc_num_rate);
+ rateidx =
+ rc_sta->
+ pinfo.rinfo
+ [spinfo->txrate_idx].rc_index;
+ }
+ if (rateidx < 4) {
+ if (rateidx) {
+ if ((sc->sc_flags & SC_OP_SHORT_PREAMBLE)
+ ||
+ (txrc->short_preamble))
+ {
+ rateidx
+ +=
+ 3;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ rc_rate = &ssv_rc->rc_table[rateidx];
+ if (spinfo->real_hw_index != rc_rate->hw_rate_idx) {
+ char string[24];
+ rateControlGetRate(rc_rate->hw_rate_idx, string);
+ }
+ spinfo->real_hw_index = rc_rate->hw_rate_idx;
+ rates[0].count = 4;
+ rates[0].idx = rc_rate->dot11_rate_idx;
+ tx_info->control.rts_cts_rate_idx =
+ ssv_rc->rc_table[rc_rate->ctrl_rate_idx].dot11_rate_idx;
+ if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+ rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
+ if (rc_rate->rc_flags & RC_FLAG_HT) {
+ rates[0].flags |= IEEE80211_TX_RC_MCS;
+ if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+ rates[0].flags |= IEEE80211_TX_RC_SHORT_GI;
+ if (rc_rate->rc_flags & RC_FLAG_HT_GF)
+ rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD;
+ }
+ }
+ rates[1].count = 0;
+ rates[1].idx = -1;
+ rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx;
+ rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx];
+ rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx;
+}
+
+int pide_frame_duration(size_t len, int rate, int short_preamble, int flags)
+{
+ int dur = 0;
+ if (flags == WLAN_RC_PHY_CCK) {
+ dur = 10;
+ dur += short_preamble ? (72 + 24) : (144 + 48);
+ dur += DIV_ROUND_UP(8 * (len + 4) * 10, rate);
+ } else {
+ dur = 16;
+ dur += 16;
+ dur += 4;
+ dur += 4 * DIV_ROUND_UP((16 + 8 * (len + 4) + 6) * 10,
+ 4 * rate);
+ }
+ return dur;
+}
+
+static void ssv62xx_rc_caps(struct ssv_sta_rc_info *rc_sta)
+{
+ struct rc_pid_sta_info *spinfo;
+ struct rc_pid_info *pinfo;
+ struct rc_pid_rateinfo *rinfo;
+ int i;
+ spinfo = &rc_sta->spinfo;
+ pinfo = &rc_sta->pinfo;
+ memset(spinfo, 0, sizeof(struct rc_pid_sta_info));
+ memset(pinfo, 0, sizeof(struct rc_pid_info));
+ rinfo = rc_sta->pinfo.rinfo;
+ for (i = 0; i < rc_sta->rc_num_rate; i++) {
+ rinfo[i].rc_index = ssv6xxx_rc_rate_set[rc_sta->rc_type][i + 1];
+ rinfo[i].diff = i * RC_PID_NORM_OFFSET;
+ rinfo[i].index = (u16) i;
+ rinfo[i].perfect_tx_time =
+ TDIFS + (TSLOT * 15 >> 1) + pide_frame_duration(1530,
+ ssv_11bgn_rate_table
+ [rinfo
+ [i].rc_index].rate_kbps
+ / 100, 1,
+ ssv_11bgn_rate_table
+ [rinfo
+ [i].rc_index].phy_type)
+ + pide_frame_duration(10,
+ ssv_11bgn_rate_table[rinfo[i].
+ rc_index].rate_kbps
+ / 100, 1,
+ ssv_11bgn_rate_table[rinfo[i].
+ rc_index].phy_type);
+ pr_debug("[RC]Init perfect_tx_time[%d][%d]\n", i,
+ rinfo[i].perfect_tx_time);
+ rinfo[i].throughput = 0;
+ }
+ if (rc_sta->is_ht) {
+ if (ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0] == 12)
+ spinfo->txrate_idx = 4;
+ else
+ spinfo->txrate_idx = 0;
+ } else {
+ spinfo->txrate_idx = ssv6xxx_rate_lowest_index(rc_sta);
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+ spinfo->txrate_idx = ssv6xxx_rate_highest_index(rc_sta);
+#endif
+ }
+ spinfo->real_hw_index = 0;
+ spinfo->probe_cnt = MAXPROBES;
+ spinfo->tmp_rate_idx = spinfo->txrate_idx;
+ spinfo->oldrate = spinfo->txrate_idx;
+ spinfo->last_sample = jiffies;
+ spinfo->last_report = jiffies;
+}
+
+static void ssv6xxx_rate_update_rc_type(void *priv,
+ struct ieee80211_supported_band *sband,
+ struct ieee80211_sta *sta,
+ void *priv_sta)
+{
+ struct ssv_softc *sc = priv;
+ struct ssv_hw *sh = sc->sh;
+ struct ssv_sta_rc_info *rc_sta = priv_sta;
+ int i;
+ u32 ht_supp_rates = 0;
+ BUG_ON(rc_sta->rc_valid == false);
+ dev_dbg(sc->dev, "[I] %s(): \n", __FUNCTION__);
+ rc_sta->ht_supp_rates = 0;
+ rc_sta->rc_supp_rates = 0;
+ rc_sta->is_ht = 0;
+#ifndef CONFIG_CH14_SUPPORT_GN_MODE
+ if (sc->cur_channel->hw_value == 14) {
+ dev_dbg(sc->dev, "[RC init ]Channel 14 support\n");
+ if ((sta->deflink.supp_rates[sband->band] & (~0xfL)) == 0x0) {
+ dev_dbg(sc->dev, "[RC init ]B only mode\n");
+ rc_sta->rc_type = RC_TYPE_B_ONLY;
+ } else {
+ dev_dbg(sc->dev, "[RC init ]GB mode\n");
+ rc_sta->rc_type = RC_TYPE_LEGACY_GB;
+ }
+ } else
+#endif
+ if (sta->deflink.ht_cap.ht_supported == true) {
+ dev_dbg(sc->dev, "[RC init ]HT support wsid\n");
+ for (i = 0; i < SSV_HT_RATE_MAX; i++) {
+ if (sta->deflink.ht_cap.mcs.rx_mask[i /
+ MCS_GROUP_RATES] & (1 << (i
+ %
+ MCS_GROUP_RATES)))
+ ht_supp_rates |= BIT(i);
+ }
+ rc_sta->ht_supp_rates = ht_supp_rates;
+ if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_GRN_FLD) {
+ rc_sta->rc_type = RC_TYPE_HT_GF;
+ rc_sta->ht_rc_type = RC_TYPE_HT_GF;
+ } else if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) {
+ rc_sta->rc_type = RC_TYPE_SGI_20;
+ rc_sta->ht_rc_type = RC_TYPE_HT_SGI_20;
+ } else {
+ rc_sta->rc_type = RC_TYPE_LGI_20;
+ rc_sta->ht_rc_type = RC_TYPE_HT_LGI_20;
+ }
+ } else {
+ if ((sta->deflink.supp_rates[sband->band] & (~0xfL)) == 0x0) {
+ rc_sta->rc_type = RC_TYPE_B_ONLY;
+ dev_dbg(sc->dev, "[RC init ]B only mode\n");
+ } else {
+ rc_sta->rc_type = RC_TYPE_LEGACY_GB;
+ dev_dbg(sc->dev, "[RC init ]legacy G mode\n");
+ }
+ }
+#ifdef CONFIG_SSV_DPD
+ if (rc_sta->rc_type == RC_TYPE_B_ONLY) {
+ SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3D3E84FE);
+ SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x1457D79);
+ SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x0);
+ } else {
+ SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3CBE84FE);
+ SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x4507F9);
+ SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x3);
+ }
+#endif
+ if ((rc_sta->rc_type != RC_TYPE_B_ONLY)
+ && (rc_sta->rc_type != RC_TYPE_LEGACY_GB)) {
+ if ((sta->deflink.ht_cap.ht_supported)
+ && (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX)) {
+ rc_sta->is_ht = 1;
+ ssv62xx_ht_rc_caps(ssv6xxx_rc_rate_set, rc_sta);
+ }
+ }
+ {
+ rc_sta->rc_num_rate =
+ (u8) ssv6xxx_rc_rate_set[rc_sta->rc_type][0];
+ if ((rc_sta->rc_type == RC_TYPE_HT_GF)
+ || (rc_sta->rc_type == RC_TYPE_LGI_20)
+ || (rc_sta->rc_type == RC_TYPE_SGI_20)) {
+ if (rc_sta->rc_num_rate == 12) {
+ rc_sta->rc_supp_rates =
+ sta->deflink.supp_rates[sband->band] & 0xfL;
+ rc_sta->rc_supp_rates |= (ht_supp_rates << 4);
+ } else
+ rc_sta->rc_supp_rates = ht_supp_rates;
+ } else if (rc_sta->rc_type == RC_TYPE_LEGACY_GB)
+ rc_sta->rc_supp_rates = sta->deflink.supp_rates[sband->band];
+ else if (rc_sta->rc_type == RC_TYPE_B_ONLY)
+ rc_sta->rc_supp_rates =
+ sta->deflink.supp_rates[sband->band] & 0xfL;
+ ssv62xx_rc_caps(rc_sta);
+ }
+}
+
+static void ssv6xxx_rate_update(void *priv,
+ struct ieee80211_supported_band *sband,
+ struct cfg80211_chan_def *chandef,
+ struct ieee80211_sta *sta, void *priv_sta,
+ u32 changed)
+{
+ pr_debug("%s: changed=%d\n", __FUNCTION__, changed);
+ return;
+}
+
+static void ssv6xxx_rate_init(void *priv,
+ struct ieee80211_supported_band *sband,
+ struct cfg80211_chan_def *chandef,
+ struct ieee80211_sta *sta, void *priv_sta)
+{
+ ssv6xxx_rate_update_rc_type(priv, sband, sta, priv_sta);
+}
+
+static void *ssv6xxx_rate_alloc_sta(void *priv, struct ieee80211_sta *sta,
+ gfp_t gfp)
+{
+ struct ssv_sta_priv_data *sta_priv =
+ (struct ssv_sta_priv_data *)sta->drv_priv;
+#ifndef RC_STA_DIRECT_MAP
+ struct ssv_softc *sc = priv;
+ struct ssv_rate_ctrl *ssv_rc = sc->rc;
+ int s;
+ sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ for (s = 0; s < SSV_RC_MAX_STA; s++) {
+ if (ssv_rc->sta_rc_info[s].rc_valid == false) {
+ dev_dbg(sc->dev, "%s(): use index %d\n", __FUNCTION__, s);
+ memset(&ssv_rc->sta_rc_info[s], 0,
+ sizeof(struct ssv_sta_rc_info));
+ ssv_rc->sta_rc_info[s].rc_valid = true;
+ ssv_rc->sta_rc_info[s].rc_wsid = -1;
+ sta_priv->rc_idx = s;
+ return &ssv_rc->sta_rc_info[s];
+ }
+ }
+ return NULL;
+#else
+ sta_priv->rc_idx = (-1);
+ return sta_priv;
+#endif
+}
+
+static void ssv6xxx_rate_free_sta(void *priv, struct ieee80211_sta *sta,
+ void *priv_sta)
+{
+ struct ssv_sta_rc_info *rc_sta = priv_sta;
+ rc_sta->rc_valid = false;
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
+static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw)
+#else
+static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw,
+ struct dentry *debugfsdir)
+#endif
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ssv_rate_ctrl *ssv_rc;
+ sc->rc = kzalloc(sizeof(struct ssv_rate_ctrl), GFP_KERNEL);
+ if (!sc->rc) {
+ pr_err("%s(): Unable to allocate RC structure !\n",
+ __FUNCTION__);
+ return NULL;
+ }
+ memset(sc->rc, 0, sizeof(struct ssv_rate_ctrl));
+ ssv_rc = (struct ssv_rate_ctrl *)sc->rc;
+ ssv_rc->rc_table = ssv_11bgn_rate_table;
+ skb_queue_head_init(&sc->rc_report_queue);
+ INIT_WORK(&sc->rc_sample_work, ssv6xxx_sample_work);
+ sc->rc_sample_workqueue = create_workqueue("ssv6xxx_rc_sample");
+ sc->rc_sample_sechedule = 0;
+ return hw->priv;
+}
+
+static void ssv6xxx_rate_free(void *priv)
+{
+ struct ssv_softc *sc = priv;
+ if (sc->rc) {
+ kfree(sc->rc);
+ sc->rc = NULL;
+ }
+ sc->rc_sample_sechedule = 0;
+ cancel_work_sync(&sc->rc_sample_work);
+ flush_workqueue(sc->rc_sample_workqueue);
+ destroy_workqueue(sc->rc_sample_workqueue);
+}
+
+static struct rate_control_ops ssv_rate_ops = {
+ .name = "ssv6xxx_rate_control",
+ .tx_status = ssv6xxx_tx_status,
+ .get_rate = ssv6xxx_get_rate,
+ .rate_init = ssv6xxx_rate_init,
+ .rate_update = ssv6xxx_rate_update,
+ .alloc = ssv6xxx_rate_alloc,
+ .free = ssv6xxx_rate_free,
+ .alloc_sta = ssv6xxx_rate_alloc_sta,
+ .free_sta = ssv6xxx_rate_free_sta,
+};
+
+void ssv6xxx_rc_mac8011_rate_idx(struct ssv_softc *sc,
+ int hw_rate_idx,
+ struct ieee80211_rx_status *rxs)
+{
+ struct ssv_rate_ctrl *ssv_rc = sc->rc;
+ struct ssv_rc_rate *rc_rate;
+ BUG_ON(hw_rate_idx >= RATE_TABLE_SIZE && hw_rate_idx < 0);
+ rc_rate = &ssv_rc->rc_table[hw_rate_idx];
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)
+ if (rc_rate->rc_flags & RC_FLAG_HT) {
+ rxs->flag |= RC_FLAG_HT;
+ if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+ rxs->flag |= RX_ENC_FLAG_SHORT_GI;
+ } else {
+ if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+ rxs->flag |= RX_ENC_FLAG_SHORTPRE;
+ }
+#else
+ if (rc_rate->rc_flags & RC_FLAG_HT) {
+ rxs->flag |= RC_FLAG_HT;
+ if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+ rxs->flag |= RX_FLAG_SHORT_GI;
+ } else {
+ if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+ rxs->flag |= RX_FLAG_SHORTPRE;
+ }
+#endif
+ rxs->rate_idx = rc_rate->dot11_rate_idx;
+}
+
+void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,
+ struct ieee80211_tx_info *info,
+ struct ssv_rate_info *sr)
+{
+ struct ieee80211_tx_rate *tx_rate;
+ struct ssv_rate_ctrl *ssv_rc = sc->rc;
+ tx_rate = &info->control.rates[0];
+ sr->d_flags =
+ (ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].phy_type ==
+ WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G : 0;
+ sr->d_flags |=
+ (ssv_rc->
+ rc_table[tx_rate[SSV_DRATE_IDX].
+ count].rc_flags & RC_FLAG_SHORT_PREAMBLE) ?
+ IEEE80211_RATE_SHORT_PREAMBLE : 0;
+ sr->c_flags =
+ (ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].phy_type ==
+ WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G : 0;
+ sr->c_flags |=
+ (ssv_rc->
+ rc_table[tx_rate[SSV_CRATE_IDX].
+ count].rc_flags & RC_FLAG_SHORT_PREAMBLE) ?
+ IEEE80211_RATE_SHORT_PREAMBLE : 0;
+ sr->drate_kbps =
+ ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].rate_kbps;
+ sr->drate_hw_idx = tx_rate[SSV_DRATE_IDX].count;
+ sr->crate_kbps =
+ ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].rate_kbps;
+ sr->crate_hw_idx = tx_rate[SSV_CRATE_IDX].count;
+}
+
+u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc,
+ u32 do_rts_cts)
+{
+ int ret = 0;
+ struct ssv_rate_ctrl *ssv_rc = sc->rc;
+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+ struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+ struct ieee80211_sta *sta = skb_info->sta;
+ struct ieee80211_tx_rate *rates = &tx_info->control.rates[0];
+ struct ssv_rc_rate *rc_rate = NULL;
+ u8 rateidx = 0;
+ struct ssv_sta_rc_info *rc_sta = NULL;
+ struct rc_pid_sta_info *spinfo;
+ struct ssv_sta_priv_data *sta_priv = NULL;
+ unsigned long period = 0;
+ if (sc->sc_flags & SC_OP_FIXED_RATE)
+ return ret;
+ if (sta == NULL)
+ return ret;
+ sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ if (sta_priv == NULL) {
+#ifdef RATE_CONTROL_DEBUG
+ dev_dbg(rc->dev, "%s sta_priv == NULL \n\r", __FUNCTION__);
+#endif
+ return ret;
+ }
+ if ((sta_priv->rc_idx < 0) || (sta_priv->rc_idx >= SSV_RC_MAX_STA)) {
+#ifdef RATE_CONTROL_DEBUG
+ dev_dbg(sc->dev, "%s rc_idx %x illegal \n\r", __FUNCTION__,
+ sta_priv->rc_idx);
+#endif
+ return ret;
+ }
+ rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx];
+ if (rc_sta->rc_valid == false) {
+#ifdef RATE_CONTROL_DEBUG
+ dev_dbg(sc->dev, "%s rc_valid false \n\r", __FUNCTION__);
+#endif
+ return ret;
+ }
+ spinfo = &rc_sta->spinfo;
+ period = msecs_to_jiffies(RC_PID_REPORT_INTERVAL);
+ if (time_after(jiffies, spinfo->last_report + period)) {
+ ret |= RC_FIRMWARE_REPORT_FLAG;
+ spinfo->last_report = jiffies;
+ }
+ {
+ if (spinfo->monitoring) {
+ if (spinfo->probe_report_flag == 0) {
+ ret |= RC_FIRMWARE_REPORT_FLAG;
+ spinfo->last_report = jiffies;
+ spinfo->probe_report_flag = 1;
+ rateidx = spinfo->real_hw_index;
+ } else if (spinfo->probe_cnt > 0
+ && spinfo->probe_report_flag) {
+ rateidx =
+ rc_sta->pinfo.rinfo[spinfo->
+ tmp_rate_idx].rc_index;
+ spinfo->probe_cnt--;
+ if (spinfo->probe_cnt == 0) {
+ ret |= RC_FIRMWARE_REPORT_FLAG;
+ spinfo->last_report = jiffies;
+ }
+ } else
+ rateidx = spinfo->real_hw_index;
+ } else
+ rateidx = spinfo->real_hw_index;
+ }
+ if (rateidx >= RATE_TABLE_SIZE) {
+ dev_err(sc->dev, "rateidx over range\n");
+ return 0;
+ }
+ rc_rate = &ssv_rc->rc_table[rateidx];
+#ifdef RATE_CONTROL_STUPID_DEBUG
+ if (spinfo->monitoring && (spinfo->probe_cnt)) {
+ char string[24];
+ rateControlGetRate(rc_rate->hw_rate_idx, string);
+ dev_dbg(sc->dev, "[RC]Probe rate[%s]\n", string);
+ }
+#endif
+ if (rc_rate == NULL)
+ return ret;
+ if (rc_rate->hw_rate_idx != rates[SSV_DRATE_IDX].count) {
+ rates[0].flags = 0;
+ if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+ rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
+ if (rc_rate->rc_flags & RC_FLAG_HT) {
+ rates[0].flags |= IEEE80211_TX_RC_MCS;
+ if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+ rates[0].flags |= IEEE80211_TX_RC_SHORT_GI;
+ if (rc_rate->rc_flags & RC_FLAG_HT_GF)
+ rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD;
+ }
+ rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx;
+ if (do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
+ rates[SSV_CRATE_IDX].count = 0;
+ } else {
+ rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx];
+ rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx;
+ }
+ ret |= 0x1;
+ }
+ return ret;
+}
+
+void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx)
+{
+ struct ssv_rate_ctrl *ssv_rc = sc->rc;
+ struct ssv_sta_rc_info *rc_sta;
+ u32 rc_hw_reg[] = { ADR_MTX_MIB_WSID0, ADR_MTX_MIB_WSID1 };
+ BUG_ON(rc_idx >= SSV_RC_MAX_STA);
+ rc_sta = &ssv_rc->sta_rc_info[rc_idx];
+ if (hwidx >= 0 && hwidx < SSV_NUM_HW_STA) {
+ rc_sta->rc_wsid = hwidx;
+ dev_dbg(sc->dev, "rc_wsid[%d] rc_idx[%d]\n", rc_sta[rc_idx].rc_wsid,
+ rc_idx);
+ SMAC_REG_WRITE(sc->sh, rc_hw_reg[hwidx], 0x40000000);
+ } else {
+ rc_sta->rc_wsid = -1;
+ }
+}
+
+#define UPDATE_PHY_INFO_ACK_RATE(_phy_info,_ack_rate_idx) ( _phy_info = (_phy_info&0xfffffc0f)|(_ack_rate_idx<<4))
+int ssv6xxx_rc_update_bmode_ctrl_rate(struct ssv_softc *sc, int rate_tbl_idx,
+ int ctrl_rate_idx)
+{
+ u32 temp32;
+ struct ssv_hw *sh = sc->sh;
+ u32 addr;
+ addr = sh->hw_pinfo + rate_tbl_idx * 4;
+ ssv_11bgn_rate_table[rate_tbl_idx].ctrl_rate_idx = ctrl_rate_idx;
+ SMAC_REG_READ(sh, addr, &temp32);
+ UPDATE_PHY_INFO_ACK_RATE(temp32, ctrl_rate_idx);
+ SMAC_REG_WRITE(sh, addr, temp32);
+ SMAC_REG_CONFIRM(sh, addr, temp32);
+ return 0;
+}
+
+void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates)
+{
+ int i;
+ int rate_idx, pre_rate_idx = 0;
+ for (i = 0; i < 4; i++) {
+ if (((basic_rates >> i) & 0x01)) {
+ rate_idx = i;
+ pre_rate_idx = i;
+ } else
+ rate_idx = pre_rate_idx;
+ ssv6xxx_rc_update_bmode_ctrl_rate(sc, i, rate_idx);
+ if (i)
+ ssv6xxx_rc_update_bmode_ctrl_rate(sc, i + 3, rate_idx);
+ }
+}
+
+int ssv6xxx_rate_control_register(void)
+{
+ return ieee80211_rate_control_register(&ssv_rate_ops);
+}
+
+void ssv6xxx_rate_control_unregister(void)
+{
+ ieee80211_rate_control_unregister(&ssv_rate_ops);
+}
+
+void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb,
+ u32 rate_index)
+{
+ struct ssv_softc *sc = hw->priv;
+ struct ieee80211_sta *sta;
+ struct ssv_sta_priv_data *ssv_sta_priv;
+ sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
+ if (sta == NULL) {
+ return;
+ }
+ ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+ ssv_sta_priv->rx_data_rate = rate_index;
+}
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc.h b/drivers/net/wireless/ssv6051/smac/ssv_rc.h
new file mode 100644
index 000000000000..911c182897fa
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_rc.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_RC_H_
+#define _SSV_RC_H_
+#include "ssv_rc_common.h"
+#define RC_PID_REPORT_INTERVAL 40
+#define RC_PID_INTERVAL 125
+#define RC_PID_DO_ARITH_RIGHT_SHIFT(x,y) \
+ ((x) < 0 ? -((-(x)) >> (y)) : (x) >> (y))
+#define RC_PID_NORM_OFFSET 3
+#define RC_PID_SMOOTHING_SHIFT 1
+#define RC_PID_SMOOTHING (1 << RC_PID_SMOOTHING_SHIFT)
+#define RC_PID_COEFF_P 15
+#define RC_PID_COEFF_I 15
+#define RC_PID_COEFF_D 5
+#define MAXPROBES 3
+#define SSV_DRATE_IDX (2)
+#define SSV_CRATE_IDX (3)
+
+struct ssv_softc;
+struct ssv_rc_rate *ssv6xxx_rc_get_rate(int rc_index);
+void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,
+ struct ieee80211_tx_info *info,
+ struct ssv_rate_info *sr);
+u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc,
+ u32 do_rts_cts);
+void ssv6xxx_rc_mac8011_rate_idx(struct ssv_softc *sc, int hw_rate_idx,
+ struct ieee80211_rx_status *rxs);
+void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx);
+void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates);
+int ssv6xxx_rate_control_register(void);
+void ssv6xxx_rate_control_unregister(void);
+void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb,
+ u32 rate_index);
+int pide_frame_duration(size_t len, int rate, int short_preamble, int flags);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h b/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
new file mode 100644
index 000000000000..13f3fdd8072b
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_RC_COM_H_
+#define _SSV_RC_COM_H_
+#define SSV_RC_MAX_STA 8
+#define MCS_GROUP_RATES 8
+#define SSV_HT_RATE_MAX 8
+#define TDIFS 34
+#define TSLOT 9
+#define SSV_RC_MAX_HARDWARE_SUPPORT 2
+#define RC_FIRMWARE_REPORT_FLAG 0x80
+#define RC_FLAG_INVALID 0x00000001
+#define RC_FLAG_LEGACY 0x00000002
+#define RC_FLAG_HT 0x00000004
+#define RC_FLAG_HT_SGI 0x00000008
+#define RC_FLAG_HT_GF 0x00000010
+#define RC_FLAG_SHORT_PREAMBLE 0x00000020
+enum ssv6xxx_rc_phy_type {
+ WLAN_RC_PHY_CCK,
+ WLAN_RC_PHY_OFDM,
+ WLAN_RC_PHY_HT_20_SS_LGI,
+ WLAN_RC_PHY_HT_20_SS_SGI,
+ WLAN_RC_PHY_HT_20_SS_GF,
+};
+#define RATE_TABLE_SIZE 39
+#define RC_STA_VALID 0x00000001
+#define RC_STA_CAP_HT 0x00000002
+#define RC_STA_CAP_GF 0x00000004
+#define RC_STA_CAP_SGI_20 0x00000008
+#define RC_STA_CAP_SHORT_PREAMBLE 0x00000010
+#define SSV62XX_G_RATE_INDEX 7
+#define SSV62XX_RATE_MCS_INDEX 15
+#define SSV62XX_RATE_MCS_LGI_INDEX 15
+#define SSV62XX_RATE_MCS_SGI_INDEX 23
+#define SSV62XX_RATE_MCS_GREENFIELD_INDEX 31
+enum ssv_rc_rate_type {
+ RC_TYPE_B_ONLY = 0,
+ RC_TYPE_LEGACY_GB,
+ RC_TYPE_SGI_20,
+ RC_TYPE_LGI_20,
+ RC_TYPE_HT_SGI_20,
+ RC_TYPE_HT_LGI_20,
+ RC_TYPE_HT_GF,
+ RC_TYPE_MAX,
+};
+struct ssv_rate_info {
+ int crate_kbps;
+ int crate_hw_idx;
+ int drate_kbps;
+ int drate_hw_idx;
+ u32 d_flags;
+ u32 c_flags;
+};
+struct ssv_rc_rate {
+ u32 rc_flags;
+ u16 phy_type;
+ u32 rate_kbps;
+ u8 dot11_rate_idx;
+ u8 ctrl_rate_idx;
+ u8 hw_rate_idx;
+ u8 arith_shift;
+ u8 target_pf;
+};
+struct rc_pid_sta_info {
+ unsigned long last_sample;
+ unsigned long last_report;
+ u16 tx_num_failed;
+ u16 tx_num_xmit;
+ u8 probe_report_flag;
+ u8 probe_wating_times;
+ u8 real_hw_index;
+ int txrate_idx;
+ u8 last_pf;
+ s32 err_avg_sc;
+ int last_dlr;
+ u8 feedback_probes;
+ u8 monitoring;
+ u8 oldrate;
+ u8 tmp_rate_idx;
+ u8 probe_cnt;
+};
+struct rc_pid_rateinfo {
+ u16 rc_index;
+ u16 index;
+ s32 diff;
+ u16 perfect_tx_time;
+ u32 throughput;
+ unsigned long this_attempt;
+ unsigned long this_success;
+ unsigned long this_fail;
+ u64 attempt;
+ u64 success;
+ u64 fail;
+};
+struct rc_pid_info {
+ unsigned int target;
+ int oldrate;
+ struct rc_pid_rateinfo rinfo[12];
+};
+struct mcs_group {
+ unsigned int duration[MCS_GROUP_RATES];
+};
+struct minstrel_rate_stats {
+ u16 rc_index;
+ unsigned int attempts, last_attempts;
+ unsigned int success, last_success;
+ u64 att_hist, succ_hist;
+ unsigned int cur_tp;
+ unsigned int cur_prob, probability;
+ unsigned int retry_count;
+ unsigned int retry_count_rtscts;
+ u8 sample_skipped;
+};
+struct minstrel_mcs_group_data {
+ u8 index;
+ u8 column;
+ unsigned int max_tp_rate;
+ unsigned int max_tp_rate2;
+ unsigned int max_prob_rate;
+ struct minstrel_rate_stats rates[MCS_GROUP_RATES];
+};
+struct ssv62xx_ht {
+ unsigned int ampdu_len;
+ unsigned int ampdu_packets;
+ unsigned int avg_ampdu_len;
+ unsigned int max_tp_rate;
+ unsigned int max_tp_rate2;
+ unsigned int max_prob_rate;
+ int first_try_count;
+ int second_try_count;
+ int other_try_count;
+ unsigned long stats_update;
+ unsigned int overhead;
+ unsigned int overhead_rtscts;
+ unsigned int total_packets;
+ unsigned int sample_packets;
+ u8 sample_wait;
+ u8 sample_tries;
+ u8 sample_count;
+ u8 sample_slow;
+ struct minstrel_mcs_group_data groups;
+};
+struct ssv_sta_rc_info {
+ u8 rc_valid;
+ u8 rc_type;
+ u8 rc_num_rate;
+ s8 rc_wsid;
+ u8 ht_rc_type;
+ u8 is_ht;
+ u32 rc_supp_rates;
+ u32 ht_supp_rates;
+ struct rc_pid_info pinfo;
+ struct rc_pid_sta_info spinfo;
+ struct ssv62xx_ht ht;
+};
+struct ssv_rate_ctrl {
+ struct ssv_rc_rate *rc_table;
+ struct ssv_sta_rc_info sta_rc_info[SSV_RC_MAX_STA];
+};
+#define HT_RC_UPDATE_INTERVAL 1000
+#endif
diff --git a/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c b/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
new file mode 100644
index 000000000000..10a9a77081db
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <asm/io.h>
+#include <linux/printk.h>
+#include <linux/err.h>
+
+static int g_wifidev_registered = 0;
+extern int ssvdevice_init(void);
+extern void ssvdevice_exit(void);
+extern int ssv6xxx_get_dev_status(void);
+
+static __init int ssv_init_module(void)
+{
+ int ret = 0;
+ int time = 5;
+
+ msleep(120);
+
+ g_wifidev_registered = 1;
+ ret = ssvdevice_init();
+
+ while(time-- > 0){
+ msleep(500);
+ if(ssv6xxx_get_dev_status() == 1)
+ break;
+ pr_info("%s : Retry to carddetect\n",__func__);
+ }
+
+ return ret;
+
+}
+static __exit void ssv_exit_module(void)
+{
+
+ if (g_wifidev_registered)
+ {
+ ssvdevice_exit();
+ msleep(50);
+ g_wifidev_registered = 0;
+ }
+
+ return;
+
+}
+
+module_init(ssv_init_module);
+module_exit(ssv_exit_module);
+
+MODULE_AUTHOR("iComm Semiconductor Co., Ltd");
+MODULE_FIRMWARE("ssv*-sw.bin");
+MODULE_FIRMWARE("ssv*-wifi.cfg");
+MODULE_DESCRIPTION("Shared library for SSV wireless LAN cards.");
+MODULE_LICENSE("Dual BSD/GPL");
+
diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
new file mode 100644
index 000000000000..503df1ea6dc3
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
@@ -0,0 +1,1765 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/export.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include <ssv6200_reg.h>
+#include <ssv6200.h>
+#include <hci/hctrl.h>
+#include <smac/dev.h>
+#include "ssv_cmd.h"
+#include <ssv_version.h>
+#include <ssv6200_configuration.h>
+#define SSV_CMD_PRINTF()
+struct ssv6xxx_dev_table {
+ u32 address;
+ u32 val;
+};
+struct ssv6xxx_debug {
+ struct device *dev;
+ struct platform_device *pdev;
+ struct ssv6xxx_hwif_ops *ifops;
+};
+static struct ssv6xxx_debug *ssv6xxx_debug_ifops;
+static char sg_cmd_buffer[CLI_BUFFER_SIZE + 1];
+static char *sg_argv[CLI_ARG_SIZE];
+static u32 sg_argc;
+extern char *ssv6xxx_result_buf;
+#if defined (CONFIG_ARM64) || defined (__x86_64__)
+u64 ssv6xxx_ifdebug_info[3] = { 0, 0, 0 };
+#else
+u32 ssv6xxx_ifdebug_info[3] = { 0, 0, 0 };
+#endif
+EXPORT_SYMBOL(ssv6xxx_ifdebug_info);
+struct sk_buff *ssvdevice_skb_alloc(s32 len)
+{
+ struct sk_buff *skb;
+ skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL);
+ if (skb != NULL) {
+ skb_put(skb, 0x20);
+ skb_pull(skb, 0x20);
+ }
+ return skb;
+}
+
+void ssvdevice_skb_free(struct sk_buff *skb)
+{
+ dev_kfree_skb_any(skb);
+}
+
+static int ssv_cmd_help(int argc, char *argv[])
+{
+ extern struct ssv_cmd_table cmd_table[];
+ struct ssv_cmd_table *sc_tbl;
+ char tmpbf[161];
+ int total_cmd = 0;
+ {
+ sprintf(ssv6xxx_result_buf, "Usage:\n");
+ for (sc_tbl = &cmd_table[3]; sc_tbl->cmd; sc_tbl++) {
+ sprintf(tmpbf, "%-20s\t\t%s\n", sc_tbl->cmd,
+ sc_tbl->usage);
+ strcat(ssv6xxx_result_buf, tmpbf);
+ total_cmd++;
+ }
+ sprintf(tmpbf,
+ "Total CMDs: %d\n\nType cli help [CMD] for more detail command.\n\n",
+ total_cmd);
+ strcat(ssv6xxx_result_buf, tmpbf);
+ }
+ return 0;
+}
+
+static int ssv_cmd_reg(int argc, char *argv[])
+{
+ u32 addr, value, count;
+ char tmpbf[64], *endp;
+ int s;
+ if (argc == 4 && strcmp(argv[1], "w") == 0) {
+ addr = simple_strtoul(argv[2], &endp, 16);
+ value = simple_strtoul(argv[3], &endp, 16);
+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, addr, value)) ;
+ sprintf(ssv6xxx_result_buf, " => write [0x%08x]: 0x%08x\n",
+ addr, value);
+ return 0;
+ } else if ((argc == 4 || argc == 3) && strcmp(argv[1], "r") == 0) {
+ count = (argc == 3) ? 1 : simple_strtoul(argv[3], &endp, 10);
+ addr = simple_strtoul(argv[2], &endp, 16);
+ sprintf(ssv6xxx_result_buf, "ADDRESS: 0x%08x\n", addr);
+ for (s = 0; s < count; s++, addr += 4) {
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+ sprintf(tmpbf, "%08x ", value);
+ strcat(ssv6xxx_result_buf, tmpbf);
+ if (((s + 1) & 0x07) == 0)
+ strcat(ssv6xxx_result_buf, "\n");
+ }
+ strcat(ssv6xxx_result_buf, "\n");
+ return 0;
+ } else {
+ sprintf(tmpbf, "reg [r|w] [address] [value|word-count]\n\n");
+ strcat(ssv6xxx_result_buf, tmpbf);
+ return 0;
+ }
+ return -1;
+}
+
+struct ssv6xxx_cfg ssv_cfg;
+EXPORT_SYMBOL(ssv_cfg);
+static int __string2u32(u8 * u8str, void *val, u32 arg)
+{
+ char *endp;
+ int base = 10;
+ if (u8str[0] == '0' && ((u8str[1] == 'x') || (u8str[1] == 'X')))
+ base = 16;
+ *(u32 *) val = simple_strtoul(u8str, &endp, base);
+ return 0;
+}
+
+static int __string2flag32(u8 * flag_str, void *flag, u32 arg)
+{
+ u32 *val = (u32 *) flag;
+ if (arg >= (sizeof(u32) << 3))
+ return -1;
+ if (strcmp(flag_str, "on") == 0) {
+ *val |= (1 << arg);
+ return 0;
+ }
+ if (strcmp(flag_str, "off") == 0) {
+ *val &= ~(1 << arg);
+ return 0;
+ }
+ return -1;
+}
+
+static int __string2mac(u8 * mac_str, void *val, u32 arg)
+{
+ int s, macaddr[6];
+ u8 *mac = (u8 *) val;
+ s = sscanf(mac_str, "%02x:%02x:%02x:%02x:%02x:%02x",
+ &macaddr[0], &macaddr[1], &macaddr[2],
+ &macaddr[3], &macaddr[4], &macaddr[5]);
+ if (s != 6)
+ return -1;
+ mac[0] = (u8) macaddr[0], mac[1] = (u8) macaddr[1];
+ mac[2] = (u8) macaddr[2], mac[3] = (u8) macaddr[3];
+ mac[4] = (u8) macaddr[4], mac[5] = (u8) macaddr[5];
+ return 0;
+}
+
+static int __string2str(u8 * path, void *val, u32 arg)
+{
+ u8 *temp = (u8 *) val;
+ sprintf(temp, "%s", path);
+ return 0;
+}
+
+static int __string2configuration(u8 * mac_str, void *val, u32 arg)
+{
+ unsigned int address, value;
+ int i;
+ i = sscanf(mac_str, "%08x:%08x", &address, &value);
+ if (i != 2)
+ return -1;
+ for (i = 0; i < EXTERNEL_CONFIG_SUPPORT; i++) {
+ if (ssv_cfg.configuration[i][0] == 0x0) {
+ ssv_cfg.configuration[i][0] = address;
+ ssv_cfg.configuration[i][1] = value;
+ return 0;
+ }
+ }
+ return 0;
+}
+
+struct ssv6xxx_cfg_cmd_table cfg_cmds[] = {
+ {"hw_mac", (void *)&ssv_cfg.maddr[0][0], 0, __string2mac},
+ {"hw_mac_2", (void *)&ssv_cfg.maddr[1][0], 0, __string2mac},
+ {"def_chan", (void *)&ssv_cfg.def_chan, 0, __string2u32},
+ {"hw_cap_ht", (void *)&ssv_cfg.hw_caps, 0, __string2flag32},
+ {"hw_cap_gf", (void *)&ssv_cfg.hw_caps, 1, __string2flag32},
+ {"hw_cap_2ghz", (void *)&ssv_cfg.hw_caps, 2, __string2flag32},
+ {"hw_cap_5ghz", (void *)&ssv_cfg.hw_caps, 3, __string2flag32},
+ {"hw_cap_security", (void *)&ssv_cfg.hw_caps, 4, __string2flag32},
+ {"hw_cap_sgi_20", (void *)&ssv_cfg.hw_caps, 5, __string2flag32},
+ {"hw_cap_sgi_40", (void *)&ssv_cfg.hw_caps, 6, __string2flag32},
+ {"hw_cap_ap", (void *)&ssv_cfg.hw_caps, 7, __string2flag32},
+ {"hw_cap_p2p", (void *)&ssv_cfg.hw_caps, 8, __string2flag32},
+ {"hw_cap_ampdu_rx", (void *)&ssv_cfg.hw_caps, 9, __string2flag32},
+ {"hw_cap_ampdu_tx", (void *)&ssv_cfg.hw_caps, 10, __string2flag32},
+ {"hw_cap_tdls", (void *)&ssv_cfg.hw_caps, 11, __string2flag32},
+ {"use_wpa2_only", (void *)&ssv_cfg.use_wpa2_only, 0, __string2u32},
+ {"wifi_tx_gain_level_gn", (void *)&ssv_cfg.wifi_tx_gain_level_gn, 0,
+ __string2u32},
+ {"wifi_tx_gain_level_b", (void *)&ssv_cfg.wifi_tx_gain_level_b, 0,
+ __string2u32},
+ {"rssi_ctl", (void *)&ssv_cfg.rssi_ctl, 0, __string2u32},
+ {"xtal_clock", (void *)&ssv_cfg.crystal_type, 0, __string2u32},
+ {"volt_regulator", (void *)&ssv_cfg.volt_regulator, 0, __string2u32},
+ {"force_chip_identity", (void *)&ssv_cfg.force_chip_identity, 0,
+ __string2u32},
+ {"firmware_path", (void *)&ssv_cfg.firmware_path[0], 0, __string2str},
+ {"flash_bin_path", (void *)&ssv_cfg.flash_bin_path[0], 0, __string2str},
+ {"mac_address_path", (void *)&ssv_cfg.mac_address_path[0], 0,
+ __string2str},
+ {"mac_output_path", (void *)&ssv_cfg.mac_output_path[0], 0,
+ __string2str},
+ {"ignore_efuse_mac", (void *)&ssv_cfg.ignore_efuse_mac, 0,
+ __string2u32},
+ {"mac_address_mode", (void *)&ssv_cfg.mac_address_mode, 0,
+ __string2u32},
+ {"sr_bhvr", (void *)&ssv_cfg.sr_bhvr, 0, __string2u32},
+ {"register", NULL, 0, __string2configuration},
+ {NULL, NULL, 0, NULL},
+};
+
+EXPORT_SYMBOL(cfg_cmds);
+static int ssv_cmd_cfg(int argc, char *argv[])
+{
+ char temp_buf[64];
+ int s;
+ if (argc == 2 && strcmp(argv[1], "reset") == 0) {
+ memset(&ssv_cfg, 0, sizeof(ssv_cfg));
+ return 0;
+ } else if (argc == 2 && strcmp(argv[1], "show") == 0) {
+ strcpy(ssv6xxx_result_buf, ">> ssv6xxx config:\n");
+ sprintf(temp_buf, " hw_caps = 0x%08x\n", ssv_cfg.hw_caps);
+ strcat(ssv6xxx_result_buf, temp_buf);
+ sprintf(temp_buf, " def_chan = %d\n", ssv_cfg.def_chan);
+ strcat(ssv6xxx_result_buf, temp_buf);
+ sprintf(temp_buf, " wifi_tx_gain_level_gn = %d\n",
+ ssv_cfg.wifi_tx_gain_level_gn);
+ strcat(ssv6xxx_result_buf, temp_buf);
+ sprintf(temp_buf, " wifi_tx_gain_level_b = %d\n",
+ ssv_cfg.wifi_tx_gain_level_b);
+ strcat(ssv6xxx_result_buf, temp_buf);
+ sprintf(temp_buf, " rssi_ctl = %d\n", ssv_cfg.rssi_ctl);
+ strcat(ssv6xxx_result_buf, temp_buf);
+ sprintf(temp_buf, " sr_bhvr = %d\n", ssv_cfg.sr_bhvr);
+ strcat(ssv6xxx_result_buf, temp_buf);
+ sprintf(temp_buf, " sta-mac = %02x:%02x:%02x:%02x:%02x:%02x",
+ ssv_cfg.maddr[0][0], ssv_cfg.maddr[0][1],
+ ssv_cfg.maddr[0][2], ssv_cfg.maddr[0][3],
+ ssv_cfg.maddr[0][4], ssv_cfg.maddr[0][5]);
+ strcat(ssv6xxx_result_buf, temp_buf);
+ strcat(ssv6xxx_result_buf, "\n");
+ return 0;
+ }
+ if (argc != 4)
+ return -1;
+ for (s = 0; cfg_cmds[s].cfg_cmd != NULL; s++) {
+ if (strcmp(cfg_cmds[s].cfg_cmd, argv[1]) == 0) {
+ cfg_cmds[s].translate_func(argv[3],
+ cfg_cmds[s].var,
+ cfg_cmds[s].arg);
+ strcpy(ssv6xxx_result_buf, "");
+ return 0;
+ }
+ }
+ return -1;
+}
+
+void *ssv_dbg_phy_table = NULL;
+EXPORT_SYMBOL(ssv_dbg_phy_table);
+u32 ssv_dbg_phy_len = 0;
+EXPORT_SYMBOL(ssv_dbg_phy_len);
+void *ssv_dbg_rf_table = NULL;
+EXPORT_SYMBOL(ssv_dbg_rf_table);
+u32 ssv_dbg_rf_len = 0;
+EXPORT_SYMBOL(ssv_dbg_rf_len);
+struct ssv_softc *ssv_dbg_sc = NULL;
+EXPORT_SYMBOL(ssv_dbg_sc);
+struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci = NULL;
+EXPORT_SYMBOL(ssv_dbg_ctrl_hci);
+struct Dump_Sta_Info {
+ char *dump_buf;
+ int sta_idx;
+};
+static void _dump_sta_info(struct ssv_softc *sc,
+ struct ssv_vif_info *vif_info,
+ struct ssv_sta_info *sta_info, void *param)
+{
+ char tmpbf[128];
+ struct Dump_Sta_Info *dump_sta_info = (struct Dump_Sta_Info *)param;
+ struct ssv_sta_priv_data *priv_sta =
+ (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+ if ((sta_info->s_flags & STA_FLAG_VALID) == 0)
+ sprintf(tmpbf,
+ " Station %d: %d is not valid\n",
+ dump_sta_info->sta_idx, priv_sta->sta_idx);
+ else
+ sprintf(tmpbf,
+ " Station %d: %d\n"
+ " Address: %02X:%02X:%02X:%02X:%02X:%02X\n"
+ " WISD: %d\n"
+ " AID: %d\n"
+ " Sleep: %d\n",
+ dump_sta_info->sta_idx, priv_sta->sta_idx,
+ sta_info->sta->addr[0], sta_info->sta->addr[1],
+ sta_info->sta->addr[2], sta_info->sta->addr[3],
+ sta_info->sta->addr[4], sta_info->sta->addr[5],
+ sta_info->hw_wsid, sta_info->aid, sta_info->sleeping);
+ dump_sta_info->sta_idx++;
+ strcat(dump_sta_info->dump_buf, tmpbf);
+}
+
+void ssv6xxx_dump_sta_info(struct ssv_softc *sc, char *target_buf)
+{
+ int j;
+ char tmpbf[128];
+ struct Dump_Sta_Info dump_sta_info = { target_buf, 0 };
+ sprintf(tmpbf, " >>>> bcast queue len[%d]\n", sc->bcast_txq.cur_qsize);
+ strcat(target_buf, tmpbf);
+ for (j = 0; j < SSV6200_MAX_VIF; j++) {
+ struct ieee80211_vif *vif = sc->vif_info[j].vif;
+ struct ssv_vif_priv_data *priv_vif;
+ struct ssv_sta_priv_data *sta_priv_iter;
+ if (vif == NULL) {
+ sprintf(tmpbf, " VIF: %d is not used.\n", j);
+ strcat(target_buf, tmpbf);
+ continue;
+ }
+ sprintf(tmpbf,
+ " VIF: %d - [%02X:%02X:%02X:%02X:%02X:%02X] type[%d] p2p[%d]\n",
+ j, vif->addr[0], vif->addr[1], vif->addr[2],
+ vif->addr[3], vif->addr[4], vif->addr[5], vif->type,
+ vif->p2p);
+ strcat(target_buf, tmpbf);
+ priv_vif = (struct ssv_vif_priv_data *)(vif->drv_priv);
+ list_for_each_entry(sta_priv_iter, &priv_vif->sta_list, list) {
+ if ((sta_priv_iter->sta_info->
+ s_flags & STA_FLAG_VALID) == 0) {
+ sprintf(tmpbf, " VIF: %d is not valid.\n",
+ j);
+ strcat(target_buf, tmpbf);
+ continue;
+ }
+ _dump_sta_info(sc, &sc->vif_info[priv_vif->vif_idx],
+ sta_priv_iter->sta_info, &dump_sta_info);
+ }
+ }
+}
+
+static int ssv_cmd_sta(int argc, char *argv[])
+{
+ if (argc >= 2 && strcmp(argv[1], "show") == 0)
+ ssv6xxx_dump_sta_info(ssv_dbg_sc, ssv6xxx_result_buf);
+ else
+ strcat(ssv6xxx_result_buf, "sta show\n\n");
+ return 0;
+}
+
+static int ssv_cmd_dump(int argc, char *argv[])
+{
+ u32 addr, regval;
+ char tmpbf[64];
+ int s;
+ if (!ssv6xxx_result_buf) {
+ pr_warn("ssv6xxx_result_buf = NULL!!\n");
+ return -1;
+ }
+ if (argc != 2) {
+ sprintf(tmpbf,
+ "dump [wsid|decision|phy-info|phy-reg|rf-reg]\n");
+ strcat(ssv6xxx_result_buf, tmpbf);
+ return 0;
+ }
+ if (strcmp(argv[1], "wsid") == 0) {
+ const u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
+ const u32 reg_wsid_tid0[] =
+ { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ };
+ const u32 reg_wsid_tid7[] =
+ { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ };
+ const u8 *op_mode_str[] = { "STA", "AP", "AD-HOC", "WDS" };
+ const u8 *ht_mode_str[] =
+ { "Non-HT", "HT-MF", "HT-GF", "RSVD" };
+ for (s = 0; s < SSV_NUM_HW_STA; s++) {
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, reg_wsid[s], &regval)) ;
+ sprintf(tmpbf,
+ "==>WSID[%d]\n\tvalid[%d] qos[%d] op_mode[%s] ht_mode[%s]\n",
+ s, regval & 0x1, (regval >> 1) & 0x1,
+ op_mode_str[((regval >> 2) & 3)],
+ ht_mode_str[((regval >> 4) & 3)]);
+ strcat(ssv6xxx_result_buf, tmpbf);
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, reg_wsid[s] + 4, &regval)) ;
+ sprintf(tmpbf, "\tMAC[%02x:%02x:%02x:%02x:",
+ (regval & 0xff), ((regval >> 8) & 0xff),
+ ((regval >> 16) & 0xff),
+ ((regval >> 24) & 0xff));
+ strcat(ssv6xxx_result_buf, tmpbf);
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, reg_wsid[s] + 8, &regval)) ;
+ sprintf(tmpbf, "%02x:%02x]\n", (regval & 0xff),
+ ((regval >> 8) & 0xff));
+ strcat(ssv6xxx_result_buf, tmpbf);
+ for (addr = reg_wsid_tid0[s]; addr <= reg_wsid_tid7[s];
+ addr += 4) {
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, addr, &regval)) ;
+ sprintf(tmpbf, "\trx_seq%d[%d]\n",
+ ((addr - reg_wsid_tid0[s]) >> 2),
+ ((regval) & 0xffff));
+ strcat(ssv6xxx_result_buf, tmpbf);
+ }
+ }
+ return 0;
+ }
+ if (strcmp(argv[1], "decision") == 0) {
+ strcpy(ssv6xxx_result_buf, ">> Decision Table:\n");
+ for (s = 0, addr = ADR_MRX_FLT_TB0; s < 16; s++, addr += 4) {
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &regval)) ;
+ sprintf(tmpbf, " [%d]: ADDR[0x%08x] = 0x%08x\n",
+ s, addr, regval);
+ strcat(ssv6xxx_result_buf, tmpbf);
+ }
+ strcat(ssv6xxx_result_buf, "\n\n>> Decision Mask:\n");
+ for (s = 0, addr = ADR_MRX_FLT_EN0; s < 9; s++, addr += 4) {
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &regval)) ;
+ sprintf(tmpbf, " [%d]: ADDR[0x%08x] = 0x%08x\n",
+ s, addr, regval);
+ strcat(ssv6xxx_result_buf, tmpbf);
+ }
+ strcat(ssv6xxx_result_buf, "\n\n");
+ return 0;
+ }
+ if (strcmp(argv[1], "phy-info") == 0) {
+ return 0;
+ }
+ if (strcmp(argv[1], "phy-reg") == 0) {
+ struct ssv6xxx_dev_table *raw;
+ raw = (struct ssv6xxx_dev_table *)ssv_dbg_phy_table;
+ strcpy(ssv6xxx_result_buf, ">> PHY Register Table:\n");
+ for (s = 0; s < ssv_dbg_phy_len; s++, raw++) {
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, raw->address, &regval)) ;
+ sprintf(tmpbf, " ADDR[0x%08x] = 0x%08x\n",
+ raw->address, regval);
+ strcat(ssv6xxx_result_buf, tmpbf);
+ }
+ strcat(ssv6xxx_result_buf, "\n\n");
+ return 0;
+ }
+ if (strcmp(argv[1], "rf-reg") == 0) {
+ struct ssv6xxx_dev_table *raw;
+ raw = (struct ssv6xxx_dev_table *)ssv_dbg_rf_table;
+ strcpy(ssv6xxx_result_buf, ">> RF Register Table:\n");
+ for (s = 0; s < ssv_dbg_rf_len; s++, raw++) {
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, raw->address, &regval)) ;
+ sprintf(tmpbf, " ADDR[0x%08x] = 0x%08x\n",
+ raw->address, regval);
+ strcat(ssv6xxx_result_buf, tmpbf);
+ }
+ strcat(ssv6xxx_result_buf, "\n\n");
+ return 0;
+ }
+ return -1;
+}
+
+static int ssv_cmd_irq(int argc, char *argv[])
+{
+ char *endp;
+ u32 irq_sts;
+ if (argc >= 3 && strcmp(argv[1], "set") == 0) {
+ if (strcmp(argv[2], "mask") == 0 && argc == 4) {
+ irq_sts = simple_strtoul(argv[3], &endp, 16);
+ if (!ssv6xxx_debug_ifops->ifops->irq_setmask) {
+ sprintf(ssv6xxx_result_buf,
+ "The interface doesn't provide irq_setmask operation.\n");
+ return 0;
+ }
+ ssv6xxx_debug_ifops->ifops->
+ irq_setmask(ssv6xxx_debug_ifops->dev, irq_sts);
+ sprintf(ssv6xxx_result_buf,
+ "set sdio irq mask to 0x%08x\n", irq_sts);
+ return 0;
+ }
+ if (strcmp(argv[2], "enable") == 0) {
+ if (!ssv6xxx_debug_ifops->ifops->irq_enable) {
+ sprintf(ssv6xxx_result_buf,
+ "The interface doesn't provide irq_enable operation.\n");
+ return 0;
+ }
+ ssv6xxx_debug_ifops->ifops->
+ irq_enable(ssv6xxx_debug_ifops->dev);
+ strcpy(ssv6xxx_result_buf, "enable sdio irq.\n");
+ return 0;
+ }
+ if (strcmp(argv[2], "disable") == 0) {
+ if (!ssv6xxx_debug_ifops->ifops->irq_disable) {
+ sprintf(ssv6xxx_result_buf,
+ "The interface doesn't provide irq_disable operation.\n");
+ return 0;
+ }
+ ssv6xxx_debug_ifops->ifops->
+ irq_disable(ssv6xxx_debug_ifops->dev, false);
+ strcpy(ssv6xxx_result_buf, "disable sdio irq.\n");
+ return 0;
+ }
+ return -1;
+ } else if (argc == 3 && strcmp(argv[1], "get") == 0) {
+ if (strcmp(argv[2], "mask") == 0) {
+ if (!ssv6xxx_debug_ifops->ifops->irq_getmask) {
+ sprintf(ssv6xxx_result_buf,
+ "The interface doesn't provide irq_getmask operation.\n");
+ return 0;
+ }
+ ssv6xxx_debug_ifops->ifops->
+ irq_getmask(ssv6xxx_debug_ifops->dev, &irq_sts);
+ sprintf(ssv6xxx_result_buf,
+ "sdio irq mask: 0x%08x, int_mask=0x%08x\n",
+ irq_sts, ssv_dbg_ctrl_hci->int_mask);
+ return 0;
+ }
+ if (strcmp(argv[2], "status") == 0) {
+ if (!ssv6xxx_debug_ifops->ifops->irq_getstatus) {
+ sprintf(ssv6xxx_result_buf,
+ "The interface doesn't provide irq_getstatus operation.\n");
+ return 0;
+ }
+ ssv6xxx_debug_ifops->ifops->
+ irq_getstatus(ssv6xxx_debug_ifops->dev, &irq_sts);
+ sprintf(ssv6xxx_result_buf, "sdio irq status: 0x%08x\n",
+ irq_sts);
+ return 0;
+ }
+ return -1;
+ } else {
+ sprintf(ssv6xxx_result_buf,
+ "irq [set|get] [mask|enable|disable|status]\n");
+ }
+ return 0;
+}
+
+static int ssv_cmd_mac(int argc, char *argv[])
+{
+ char temp_str[128], *endp;
+ u32 s;
+ int i;
+ if (argc == 3 && !strcmp(argv[1], "wsid") && !strcmp(argv[2], "show")) {
+ for (s = 0; s < SSV_NUM_HW_STA; s++) {
+ }
+ return 0;
+ } else if (argc == 3 && !strcmp(argv[1], "rx")) {
+ if (!strcmp(argv[2], "enable")) {
+ ssv_dbg_sc->dbg_rx_frame = 1;
+ } else {
+ ssv_dbg_sc->dbg_rx_frame = 0;
+ }
+ sprintf(temp_str, " dbg_rx_frame %d\n",
+ ssv_dbg_sc->dbg_rx_frame);
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ } else if (argc == 3 && !strcmp(argv[1], "tx")) {
+ if (!strcmp(argv[2], "enable")) {
+ ssv_dbg_sc->dbg_tx_frame = 1;
+ } else {
+ ssv_dbg_sc->dbg_tx_frame = 0;
+ }
+ sprintf(temp_str, " dbg_tx_frame %d\n",
+ ssv_dbg_sc->dbg_tx_frame);
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ } else if (argc == 3 && !strcmp(argv[1], "rxq")
+ && !strcmp(argv[2], "show")) {
+ sprintf(temp_str, ">> MAC RXQ: (%s)\n cur_qsize=%d\n",
+ ((ssv_dbg_sc->
+ sc_flags & SC_OP_OFFCHAN) ? "off channel" :
+ "on channel"), ssv_dbg_sc->rx.rxq_count);
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ } else if (argc == 4 && !strcmp(argv[1], "set")
+ && !strcmp(argv[2], "rate")) {
+ if (strcmp(argv[3], "auto") == 0) {
+ ssv_dbg_sc->sc_flags &= ~SC_OP_FIXED_RATE;
+ return 0;
+ }
+ i = simple_strtoul(argv[3], &endp, 10);
+ if (i < 0 || i > 38) {
+ strcpy(ssv6xxx_result_buf, " Invalid rat index !!\n");
+ return -1;
+ }
+ ssv_dbg_sc->max_rate_idx = i;
+ ssv_dbg_sc->sc_flags |= SC_OP_FIXED_RATE;
+ sprintf(temp_str, " Set rate to index %d\n", i);
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ } else if (argc == 3 && !strcmp(argv[1], "get")
+ && !strcmp(argv[2], "rate")) {
+ if (ssv_dbg_sc->sc_flags & SC_OP_FIXED_RATE)
+ sprintf(temp_str, " Current Rate Index: %d\n",
+ ssv_dbg_sc->max_rate_idx);
+ else
+ sprintf(temp_str, " Current Rate Index: auto\n");
+ strcpy(ssv6xxx_result_buf, temp_str);
+ return 0;
+ } else {
+ sprintf(temp_str, "mac [security|wsid|rxq] [show]\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "mac [set|get] [rate] [auto|idx]\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "mac [rx|tx] [eable|disable]\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ return 0;
+}
+
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+void print_irq_count(void)
+{
+ char temp_str[512];
+ sprintf(temp_str, "irq debug (%s)\n",
+ ssv_dbg_ctrl_hci->irq_enable ? "enable" : "disable");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "total irq (%d)\n", ssv_dbg_ctrl_hci->irq_count);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "invalid irq (%d)\n",
+ ssv_dbg_ctrl_hci->invalid_irq_count);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "rx irq (%d)\n", ssv_dbg_ctrl_hci->rx_irq_count);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "tx irq (%d)\n", ssv_dbg_ctrl_hci->tx_irq_count);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "real tx count irq (%d)\n",
+ ssv_dbg_ctrl_hci->real_tx_irq_count);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "tx packet count (%d)\n",
+ ssv_dbg_ctrl_hci->irq_tx_pkt_count);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "rx packet (%d)\n",
+ ssv_dbg_ctrl_hci->irq_rx_pkt_count);
+ strcat(ssv6xxx_result_buf, temp_str);
+}
+#endif
+void print_isr_info(void)
+{
+ char temp_str[512];
+ sprintf(temp_str, ">>>> HCI Calculate ISR TIME(%s) unit:us\n",
+ ((ssv_dbg_ctrl_hci->isr_summary_eable) ? "enable" : "disable"));
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "isr_routine_time(%d)\n",
+ jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_routine_time));
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "isr_tx_time(%d)\n",
+ jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_tx_time));
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "isr_rx_time(%d)\n",
+ jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_rx_time));
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "isr_idle_time(%d)\n",
+ jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_idle_time));
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "isr_rx_idle_time(%d)\n",
+ jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_rx_idle_time));
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "isr_miss_cnt(%d)\n", ssv_dbg_ctrl_hci->isr_miss_cnt);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "prev_isr_jiffes(%lu)\n",
+ ssv_dbg_ctrl_hci->prev_isr_jiffes);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "prev_rx_isr_jiffes(%lu)\n",
+ ssv_dbg_ctrl_hci->prev_rx_isr_jiffes);
+ strcat(ssv6xxx_result_buf, temp_str);
+}
+
+static int ssv_cmd_hci(int argc, char *argv[])
+{
+ struct ssv_hw_txq *txq;
+ char temp_str[512];
+ int s, ac = 0;
+ if (argc == 3 && !strcmp(argv[1], "txq") && !strcmp(argv[2], "show")) {
+ for (s = 0; s < WMM_NUM_AC; s++) {
+ if (ssv_dbg_sc != NULL)
+ ac = ssv_dbg_sc->tx.ac_txqid[s];
+ txq = &ssv_dbg_ctrl_hci->hw_txq[s];
+ sprintf(temp_str, ">> txq[%d]", txq->txq_no);
+ if (ssv_dbg_sc != NULL)
+ sprintf(temp_str, "(%s): ",
+ ((ssv_dbg_sc->
+ sc_flags & SC_OP_OFFCHAN) ?
+ "off channel" : "on channel"));
+ sprintf(temp_str, "cur_qsize=%d\n",
+ skb_queue_len(&txq->qhead));
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str,
+ " max_qsize=%d, pause=%d, resume_thres=%d",
+ txq->max_qsize, txq->paused, txq->resum_thres);
+ if (ssv_dbg_sc != NULL)
+ sprintf(temp_str, " flow_control[%d]\n",
+ !!(ssv_dbg_sc->tx.
+ flow_ctrl_status & (1 << ac)));
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, " Total %d frame sent\n",
+ txq->tx_pkt);
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ sprintf(temp_str,
+ ">> HCI Debug Counters:\n read_rs0_info_fail=%d, read_rs1_info_fail=%d\n",
+ ssv_dbg_ctrl_hci->read_rs0_info_fail,
+ ssv_dbg_ctrl_hci->read_rs1_info_fail);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str,
+ " rx_work_running=%d, isr_running=%d, xmit_running=%d\n",
+ ssv_dbg_ctrl_hci->rx_work_running,
+ ssv_dbg_ctrl_hci->isr_running,
+ ssv_dbg_ctrl_hci->xmit_running);
+ strcat(ssv6xxx_result_buf, temp_str);
+ if (ssv_dbg_sc != NULL)
+ sprintf(temp_str, " flow_ctrl_status=%08x\n",
+ ssv_dbg_sc->tx.flow_ctrl_status);
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ } else if (argc == 3 && !strcmp(argv[1], "rxq")
+ && !strcmp(argv[2], "show")) {
+ sprintf(temp_str, ">> HCI RX Queue (%s): cur_qsize=%d\n",
+ ((ssv_dbg_sc->
+ sc_flags & SC_OP_OFFCHAN) ? "off channel" :
+ "on channel"), ssv_dbg_ctrl_hci->rx_pkt);
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ } else if (argc == 3 && !strcmp(argv[1], "isr_time")
+ && !strcmp(argv[2], "start")) {
+ ssv_dbg_ctrl_hci->isr_summary_eable = 1;
+ ssv_dbg_ctrl_hci->isr_routine_time = 0;
+ ssv_dbg_ctrl_hci->isr_tx_time = 0;
+ ssv_dbg_ctrl_hci->isr_rx_time = 0;
+ ssv_dbg_ctrl_hci->isr_idle_time = 0;
+ ssv_dbg_ctrl_hci->isr_rx_idle_time = 0;
+ ssv_dbg_ctrl_hci->isr_miss_cnt = 0;
+ ssv_dbg_ctrl_hci->prev_isr_jiffes = 0;
+ ssv_dbg_ctrl_hci->prev_rx_isr_jiffes = 0;
+ print_isr_info();
+ return 0;
+ } else if (argc == 3 && !strcmp(argv[1], "isr_time")
+ && !strcmp(argv[2], "stop")) {
+ ssv_dbg_ctrl_hci->isr_summary_eable = 0;
+ print_isr_info();
+ return 0;
+ } else if (argc == 3 && !strcmp(argv[1], "isr_time")
+ && !strcmp(argv[2], "show")) {
+ print_isr_info();
+ return 0;
+ }
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+ else if (argc == 3 && !strcmp(argv[1], "isr_debug")
+ && !strcmp(argv[2], "reset")) {
+ ssv_dbg_ctrl_hci->irq_enable = 0;
+ ssv_dbg_ctrl_hci->irq_count = 0;
+ ssv_dbg_ctrl_hci->invalid_irq_count = 0;
+ ssv_dbg_ctrl_hci->tx_irq_count = 0;
+ ssv_dbg_ctrl_hci->real_tx_irq_count = 0;
+ ssv_dbg_ctrl_hci->rx_irq_count = 0;
+ ssv_dbg_ctrl_hci->isr_rx_idle_time = 0;
+ ssv_dbg_ctrl_hci->irq_rx_pkt_count = 0;
+ ssv_dbg_ctrl_hci->irq_tx_pkt_count = 0;
+ strcat(ssv6xxx_result_buf, "irq debug reset count\n");
+ return 0;
+ } else if (argc == 3 && !strcmp(argv[1], "isr_debug")
+ && !strcmp(argv[2], "show")) {
+ print_irq_count();
+ return 0;
+ } else if (argc == 3 && !strcmp(argv[1], "isr_debug")
+ && !strcmp(argv[2], "stop")) {
+ ssv_dbg_ctrl_hci->irq_enable = 0;
+ strcat(ssv6xxx_result_buf, "irq debug stop\n");
+ return 0;
+ } else if (argc == 3 && !strcmp(argv[1], "isr_debug")
+ && !strcmp(argv[2], "start")) {
+ ssv_dbg_ctrl_hci->irq_enable = 1;
+ strcat(ssv6xxx_result_buf, "irq debug start\n");
+ return 0;
+ }
+#endif
+ else {
+ strcat(ssv6xxx_result_buf,
+ "hci [txq|rxq] [show]\nhci [isr_time] [start|stop|show]\n\n");
+ return 0;
+ }
+ return -1;
+}
+
+static int ssv_cmd_hwq(int argc, char *argv[])
+{
+#undef GET_FFO0_CNT
+#undef GET_FFO1_CNT
+#undef GET_FFO2_CNT
+#undef GET_FFO3_CNT
+#undef GET_FFO4_CNT
+#undef GET_FFO5_CNT
+#undef GET_FFO6_CNT
+#undef GET_FFO7_CNT
+#undef GET_FFO8_CNT
+#undef GET_FFO9_CNT
+#undef GET_FFO10_CNT
+#undef GET_FFO11_CNT
+#undef GET_FFO12_CNT
+#undef GET_FFO13_CNT
+#undef GET_FFO14_CNT
+#undef GET_FFO15_CNT
+#undef GET_FF0_CNT
+#undef GET_FF1_CNT
+#undef GET_FF3_CNT
+#undef GET_FF5_CNT
+#undef GET_FF6_CNT
+#undef GET_FF7_CNT
+#undef GET_FF8_CNT
+#undef GET_FF9_CNT
+#undef GET_FF10_CNT
+#undef GET_FF11_CNT
+#undef GET_FF12_CNT
+#undef GET_FF13_CNT
+#undef GET_FF14_CNT
+#undef GET_FF15_CNT
+#undef GET_FF4_CNT
+#undef GET_FF2_CNT
+#undef GET_TX_ID_ALC_LEN
+#undef GET_RX_ID_ALC_LEN
+#undef GET_AVA_TAG
+#define GET_FFO0_CNT ((value & 0x0000001f ) >> 0)
+#define GET_FFO1_CNT ((value & 0x000003e0 ) >> 5)
+#define GET_FFO2_CNT ((value & 0x00000c00 ) >> 10)
+#define GET_FFO3_CNT ((value & 0x000f8000 ) >> 15)
+#define GET_FFO4_CNT ((value & 0x00300000 ) >> 20)
+#define GET_FFO5_CNT ((value & 0x0e000000 ) >> 25)
+#define GET_FFO6_CNT ((value1 & 0x0000000f ) >> 0)
+#define GET_FFO7_CNT ((value1 & 0x000003e0 ) >> 5)
+#define GET_FFO8_CNT ((value1 & 0x00007c00 ) >> 10)
+#define GET_FFO9_CNT ((value1 & 0x000f8000 ) >> 15)
+#define GET_FFO10_CNT ((value1 & 0x00f00000 ) >> 20)
+#define GET_FFO11_CNT ((value1 & 0x3e000000 ) >> 25)
+#define GET_FFO12_CNT ((value2 & 0x00000007 ) >> 0)
+#define GET_FFO13_CNT ((value2 & 0x00000060 ) >> 5)
+#define GET_FFO14_CNT ((value2 & 0x00000c00 ) >> 10)
+#define GET_FFO15_CNT ((value2 & 0x001f8000 ) >> 15)
+#define GET_FF0_CNT ((value & 0x0000001f ) >> 0)
+#define GET_FF1_CNT ((value & 0x000001e0 ) >> 5)
+#define GET_FF3_CNT ((value & 0x00003800 ) >> 11)
+#define GET_FF5_CNT ((value & 0x000e0000 ) >> 17)
+#define GET_FF6_CNT ((value & 0x00700000 ) >> 20)
+#define GET_FF7_CNT ((value & 0x03800000 ) >> 23)
+#define GET_FF8_CNT ((value & 0x1c000000 ) >> 26)
+#define GET_FF9_CNT ((value & 0xe0000000 ) >> 29)
+#define GET_FF10_CNT ((value1 & 0x00000007 ) >> 0)
+#define GET_FF11_CNT ((value1 & 0x00000038 ) >> 3)
+#define GET_FF12_CNT ((value1 & 0x000001c0 ) >> 6)
+#define GET_FF13_CNT ((value1 & 0x00000600 ) >> 9)
+#define GET_FF14_CNT ((value1 & 0x00001800 ) >> 11)
+#define GET_FF15_CNT ((value1 & 0x00006000 ) >> 13)
+#define GET_FF4_CNT ((value1 & 0x000f8000 ) >> 15)
+#define GET_FF2_CNT ((value1 & 0x00700000 ) >> 20)
+#define GET_TX_ID_ALC_LEN ((value & 0x0003fe00 ) >> 9)
+#define GET_RX_ID_ALC_LEN ((value & 0x07fc0000 ) >> 18)
+#define GET_AVA_TAG ((value1 & 0x01ff0000 ) >> 16)
+ u32 addr, value, value1, value2;
+ char temp_str[512];
+ addr = ADR_RD_FFOUT_CNT1;
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+ addr = ADR_RD_FFOUT_CNT2;
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
+ addr = ADR_RD_FFOUT_CNT3;
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value2)) ;
+ sprintf(temp_str,
+ "\n[TAG] MCU - HCI - SEC - RX - MIC - TX0 - TX1 - TX2 - TX3 - TX4 - SEC - MIC - TSH\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str,
+ "OUTPUT %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
+ GET_FFO0_CNT, GET_FFO1_CNT, GET_FFO3_CNT, GET_FFO4_CNT,
+ GET_FFO5_CNT, GET_FFO6_CNT, GET_FFO7_CNT, GET_FFO8_CNT,
+ GET_FFO9_CNT, GET_FFO10_CNT, GET_FFO11_CNT, GET_FFO12_CNT,
+ GET_FFO15_CNT);
+ strcat(ssv6xxx_result_buf, temp_str);
+ addr = ADR_RD_IN_FFCNT1;
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+ addr = ADR_RD_IN_FFCNT2;
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
+ sprintf(temp_str,
+ "INPUT %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
+ GET_FF0_CNT, GET_FF1_CNT, GET_FF3_CNT, GET_FF4_CNT, GET_FF5_CNT,
+ GET_FF6_CNT, GET_FF7_CNT, GET_FF8_CNT, GET_FF9_CNT,
+ GET_FF10_CNT, GET_FF11_CNT, GET_FF12_CNT, GET_FF15_CNT);
+ strcat(ssv6xxx_result_buf, temp_str);
+ addr = ADR_ID_LEN_THREADSHOLD2;
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+ addr = ADR_TAG_STATUS;
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
+ sprintf(temp_str, "TX[%d]RX[%d]AVA[%d]\n", GET_TX_ID_ALC_LEN,
+ GET_RX_ID_ALC_LEN, GET_AVA_TAG);
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+}
+
+#ifdef CONFIG_P2P_NOA
+static struct ssv6xxx_p2p_noa_param cmd_noa_param = {
+ 50,
+ 100,
+ 0x12345678,
+ 1,
+ 255,
+ {0x4c, 0xe6, 0x76, 0xa2, 0x4e, 0x7c}
+};
+
+void noa_dump(char *temp_str)
+{
+ sprintf(temp_str,
+ "NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]\n",
+ cmd_noa_param.enable, cmd_noa_param.interval,
+ cmd_noa_param.duration, cmd_noa_param.start_time,
+ cmd_noa_param.count, cmd_noa_param.addr[0],
+ cmd_noa_param.addr[1], cmd_noa_param.addr[2],
+ cmd_noa_param.addr[3], cmd_noa_param.addr[4],
+ cmd_noa_param.addr[5]);
+ strcat(ssv6xxx_result_buf, temp_str);
+}
+
+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
+ struct ssv6xxx_p2p_noa_param *p2p_noa_param)
+{
+ struct sk_buff *skb;
+ struct cfg_host_cmd *host_cmd;
+ int retry_cnt = 5;
+ skb =
+ ssvdevice_skb_alloc(HOST_CMD_HDR_LEN +
+ sizeof(struct ssv6xxx_p2p_noa_param));
+ skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param);
+ skb->len = skb->data_len;
+ host_cmd = (struct cfg_host_cmd *)skb->data;
+ host_cmd->c_type = HOST_CMD;
+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_SET_NOA;
+ host_cmd->len = skb->data_len;
+ memcpy(host_cmd->dat32, p2p_noa_param,
+ sizeof(struct ssv6xxx_p2p_noa_param));
+ while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
+ pr_debug("NOA cmd retry=%d\n", retry_cnt);
+ retry_cnt--;
+ }
+ ssvdevice_skb_free(skb);
+}
+
+static int ssv_cmd_noa(int argc, char *argv[])
+{
+ char temp_str[512];
+ char *endp;
+ if (argc == 2 && !strcmp(argv[1], "show")) {
+ ;
+ } else if (argc == 3 && !strcmp(argv[1], "duration")) {
+ cmd_noa_param.duration = simple_strtoul(argv[2], &endp, 0);
+ } else if (argc == 3 && !strcmp(argv[1], "interval")) {
+ cmd_noa_param.interval = simple_strtoul(argv[2], &endp, 0);
+ } else if (argc == 3 && !strcmp(argv[1], "start")) {
+ cmd_noa_param.start_time = simple_strtoul(argv[2], &endp, 0);
+ } else if (argc == 3 && !strcmp(argv[1], "enable")) {
+ cmd_noa_param.enable = simple_strtoul(argv[2], &endp, 0);
+ } else if (argc == 3 && !strcmp(argv[1], "count")) {
+ cmd_noa_param.count = simple_strtoul(argv[2], &endp, 0);
+ } else if (argc == 8 && !strcmp(argv[1], "addr")) {
+ cmd_noa_param.addr[0] = simple_strtoul(argv[2], &endp, 16);
+ cmd_noa_param.addr[1] = simple_strtoul(argv[3], &endp, 16);
+ cmd_noa_param.addr[2] = simple_strtoul(argv[4], &endp, 16);
+ cmd_noa_param.addr[3] = simple_strtoul(argv[5], &endp, 16);
+ cmd_noa_param.addr[4] = simple_strtoul(argv[6], &endp, 16);
+ cmd_noa_param.addr[5] = simple_strtoul(argv[7], &endp, 16);
+ } else if (argc == 2 && !strcmp(argv[1], "send")) {
+ ssv6xxx_send_noa_cmd(ssv_dbg_sc, &cmd_noa_param);
+ } else {
+ sprintf(temp_str, "## wrong command\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ }
+ noa_dump(temp_str);
+ return 0;
+}
+#endif
+static int ssv_cmd_mib(int argc, char *argv[])
+{
+ u32 addr, value;
+ char temp_str[512];
+ int i;
+ if (argc == 2 && !strcmp(argv[1], "reset")) {
+ addr = MIB_REG_BASE;
+ value = 0x0;
+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, MIB_REG_BASE, value)) ;
+ value = 0xffffffff;
+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, MIB_REG_BASE, value)) ;
+ value = 0x0;
+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0023F8, value)) ;
+ value = 0x100000;
+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0023F8, value)) ;
+ value = 0x0;
+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0043F8, value)) ;
+ value = 0x100000;
+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0043F8, value)) ;
+ value = 0x0;
+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE000088, value)) ;
+ value = 0x80000000;
+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE000088, value)) ;
+ sprintf(temp_str, " => MIB reseted\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ } else if (argc == 2 && !strcmp(argv[1], "list")) {
+ addr = MIB_REG_BASE;
+ for (i = 0; i < 120; i++, addr += 4) {
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+ sprintf(temp_str, "%08x ", value);
+ strcat(ssv6xxx_result_buf, temp_str);
+ if (((i + 1) & 0x07) == 0)
+ strcat(ssv6xxx_result_buf, "\n");
+ }
+ strcat(ssv6xxx_result_buf, "\n");
+ } else if (argc == 2 && strcmp(argv[1], "rx") == 0) {
+ sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\t\t%-10s\n",
+ "MRX_FCS_SUCC", "MRX_FCS_ERR", "MRX_ALC_FAIL",
+ "MRX_MISS");
+ strcat(ssv6xxx_result_buf, temp_str);
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, ADR_MRX_FCS_SUCC, &value)) {
+ sprintf(temp_str, "[%08x]\t\t", value);
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_FCS_ERR, &value)) {
+ sprintf(temp_str, "[%08x]\t\t", value);
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, ADR_MRX_ALC_FAIL, &value)) {
+ sprintf(temp_str, "[%08x]\t\t", value);
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_MISS, &value)) {
+ sprintf(temp_str, "[%08x]\n", value);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\t%-10s\n",
+ "MRX_MB_MISS", "MRX_NIDLE_MISS",
+ "DBG_LEN_ALC_FAIL", "DBG_LEN_CRC_FAIL");
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_MB_MISS, &value)) {
+ sprintf(temp_str, "[%08x]\t\t", value);
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, ADR_MRX_NIDLE_MISS, &value)) {
+ sprintf(temp_str, "[%08x]\t\t", value);
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, ADR_DBG_LEN_ALC_FAIL, &value)) {
+ sprintf(temp_str, "[%08x]\t\t", value);
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, ADR_DBG_LEN_CRC_FAIL, &value)) {
+ sprintf(temp_str, "[%08x]\n\n", value);
+ strcat(ssv6xxx_result_buf, temp_str);
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, ADR_DBG_AMPDU_PASS, &value)) {
+ sprintf(temp_str, "[%08x]\t\t", value);
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, ADR_DBG_AMPDU_FAIL, &value)) {
+ sprintf(temp_str, "[%08x]\t\t", value);
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, ADR_ID_ALC_FAIL1, &value)) {
+ sprintf(temp_str, "[%08x]\t\t", value);
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, ADR_ID_ALC_FAIL2, &value)) {
+ sprintf(temp_str, "[%08x]\n\n", value);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "PHY B mode:\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\n",
+ "CRC error", "CCA", "counter");
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0023E8, &value)) {
+ sprintf(temp_str, "[%08x]\t\t", value & 0xffff);
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0023EC, &value)) {
+ sprintf(temp_str, "[%08x]\t\t", (value >> 16) & 0xffff);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "[%08x]\t\t\n\n", value & 0xffff);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "PHY G/N mode:\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\n",
+ "CRC error", "CCA", "counter");
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0043E8, &value)) {
+ sprintf(temp_str, "[%08x]\t\t", value & 0xffff);
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0043EC, &value)) {
+ sprintf(temp_str, "[%08x]\t\t", (value >> 16) & 0xffff);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "[%08x]\t\t\n\n", value & 0xffff);
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ } else {
+ sprintf(temp_str, "mib [reset|list|rx]\n\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ return 0;
+}
+
+static int ssv_cmd_sdio(int argc, char *argv[])
+{
+ u32 addr, value;
+ char temp_str[512], *endp;
+ int ret = 0;
+ if (argc == 4 && !strcmp(argv[1], "reg") && !strcmp(argv[2], "r")) {
+ addr = simple_strtoul(argv[3], &endp, 16);
+ if (!ssv6xxx_debug_ifops->ifops->cmd52_read) {
+ sprintf(temp_str,
+ "The interface doesn't provide cmd52 read\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ }
+ ret =
+ ssv6xxx_debug_ifops->ifops->cmd52_read(ssv6xxx_debug_ifops->
+ dev, addr, &value);
+ if (ret >= 0) {
+ sprintf(temp_str, " ==> %x\n", value);
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ }
+ } else if (argc == 5 && !strcmp(argv[1], "reg")
+ && !strcmp(argv[2], "w")) {
+ addr = simple_strtoul(argv[3], &endp, 16);
+ value = simple_strtoul(argv[4], &endp, 16);
+ if (!ssv6xxx_debug_ifops->ifops->cmd52_write) {
+ sprintf(temp_str,
+ "The interface doesn't provide cmd52 write\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ }
+ ret =
+ ssv6xxx_debug_ifops->ifops->
+ cmd52_write(ssv6xxx_debug_ifops->dev, addr, value);
+ if (ret >= 0) {
+ sprintf(temp_str, " ==> write odne.\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ }
+ }
+ sprintf(temp_str, "sdio cmd52 fail: %d\n", ret);
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+}
+
+static struct ssv6xxx_iqk_cfg cmd_iqk_cfg = {
+ SSV6XXX_IQK_CFG_XTAL_26M,
+ SSV6XXX_IQK_CFG_PA_DEF,
+ 0,
+ 0,
+ 26,
+ 3,
+ 0x75,
+ 0x75,
+ 0x80,
+ 0x80,
+ SSV6XXX_IQK_CMD_INIT_CALI,
+ {SSV6XXX_IQK_TEMPERATURE
+ + SSV6XXX_IQK_RXDC
+ + SSV6XXX_IQK_RXRC
+ + SSV6XXX_IQK_TXDC + SSV6XXX_IQK_TXIQ + SSV6XXX_IQK_RXIQ},
+};
+
+static int ssv_cmd_iqk(int argc, char *argv[])
+{
+ char temp_str[512], *endp;
+ struct sk_buff *skb;
+ struct cfg_host_cmd *host_cmd;
+ u32 rxcnt_total, rxcnt_error;
+ sprintf(temp_str, "# got iqk command\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ if ((argc == 3) && (strcmp(argv[1], "cfg-pa") == 0)) {
+ cmd_iqk_cfg.cfg_pa = simple_strtoul(argv[2], &endp, 0);
+ sprintf(temp_str, "## set cfg_pa as %d\n", cmd_iqk_cfg.cfg_pa);
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ } else if ((argc == 3) && (strcmp(argv[1], "cfg-tssi-trgt") == 0)) {
+ cmd_iqk_cfg.cfg_tssi_trgt = simple_strtoul(argv[2], &endp, 0);
+ sprintf(temp_str, "## set cfg_tssi_trgt as %d\n",
+ cmd_iqk_cfg.cfg_tssi_trgt);
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ } else if ((argc == 3) && (strcmp(argv[1], "init-cali") == 0)) {
+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_INIT_CALI;
+ cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+ sprintf(temp_str, "## do init-cali\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ } else if ((argc == 3) && (strcmp(argv[1], "rtbl-load") == 0)) {
+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD;
+ cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+ sprintf(temp_str, "## do rtbl-load\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ } else if ((argc == 3) && (strcmp(argv[1], "rtbl-load-def") == 0)) {
+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD_DEF;
+ cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+ sprintf(temp_str, "## do rtbl-load\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ } else if ((argc == 3) && (strcmp(argv[1], "rtbl-reset") == 0)) {
+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_RESET;
+ cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+ sprintf(temp_str, "## do rtbl-reset\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ } else if ((argc == 3) && (strcmp(argv[1], "rtbl-set") == 0)) {
+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_SET;
+ cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+ sprintf(temp_str, "## do rtbl-set\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ } else if ((argc == 3) && (strcmp(argv[1], "rtbl-export") == 0)) {
+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_EXPORT;
+ cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+ sprintf(temp_str, "## do rtbl-export\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ } else if ((argc == 3) && (strcmp(argv[1], "tk-evm") == 0)) {
+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_EVM;
+ cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
+ sprintf(temp_str, "## do tk-evm\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ } else if ((argc == 3) && (strcmp(argv[1], "tk-tone") == 0)) {
+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_TONE;
+ cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
+ sprintf(temp_str, "## do tk-tone\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ } else if ((argc == 3) && (strcmp(argv[1], "channel") == 0)) {
+ cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_CHCH;
+ cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
+ sprintf(temp_str, "## do change channel\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ } else if ((argc == 2) && (strcmp(argv[1], "tk-rxcnt-report") == 0)) {
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, 0xCE0043E8, &rxcnt_error)) ;
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, 0xCE0043EC, &rxcnt_total)) ;
+ sprintf(temp_str, "## GN Rx error rate = (%06d/%06d)\n",
+ rxcnt_error, rxcnt_total);
+ strcat(ssv6xxx_result_buf, temp_str);
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, 0xCE0023E8, &rxcnt_error)) ;
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, 0xCE0023EC, &rxcnt_total)) ;
+ sprintf(temp_str, "## B Rx error rate = (%06d/%06d)\n",
+ rxcnt_error, rxcnt_total);
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ } else {
+ sprintf(temp_str, "## invalid iqk command\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "## cmd: cfg-pa/cfg-tssi-trgt\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str,
+ "## cmd: init-cali/rtbl-load/rtbl-load-def/rtbl-reset/rtbl-set/rtbl-export/tk-evm/tk-tone/tk-channel\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "## fx_sel: 0x0008: RXDC\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, " 0x0010: RXRC\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, " 0x0020: TXDC\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, " 0x0040: TXIQ\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, " 0x0080: RXIQ\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, " 0x0100: TSSI\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, " 0x0200: PAPD\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+ }
+ skb =
+ ssvdevice_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN +
+ PHY_SETTING_SIZE + RF_SETTING_SIZE);
+ if (skb == NULL) {
+ pr_err("ssv command ssvdevice_skb_alloc failure\n");
+ return 0;
+ }
+ if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) ||
+ (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) {
+ pr_err("Please check RF or PHY table size\n");
+ BUG_ON(1);
+ return 0;
+ }
+ skb->data_len =
+ HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE;
+ skb->len = skb->data_len;
+ host_cmd = (struct cfg_host_cmd *)skb->data;
+ host_cmd->c_type = HOST_CMD;
+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_INIT_CALI;
+ host_cmd->len = skb->data_len;
+ cmd_iqk_cfg.phy_tbl_size = PHY_SETTING_SIZE;
+ cmd_iqk_cfg.rf_tbl_size = RF_SETTING_SIZE;
+ memcpy(host_cmd->dat32, &cmd_iqk_cfg, IQK_CFG_LEN);
+ memcpy(host_cmd->dat8 + IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE);
+ memcpy(host_cmd->dat8 + IQK_CFG_LEN + PHY_SETTING_SIZE, asic_rf_setting,
+ RF_SETTING_SIZE);
+ if (ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb) == 0) {
+ sprintf(temp_str, "## hci send cmd success\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ } else {
+ sprintf(temp_str, "## hci send cmd fail\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ }
+ ssvdevice_skb_free(skb);
+ return 0;
+}
+
+#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
+ (((a) & 0xff00ff00) >> 8))
+#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
+static int ssv_cmd_version(int argc, char *argv[])
+{
+ char temp_str[256];
+ u32 regval;
+ u64 chip_tag = 0;
+ char chip_id[24] = "";
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_IC_TIME_TAG_1, &regval)) ;
+ chip_tag = ((u64) regval << 32);
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_IC_TIME_TAG_0, &regval)) ;
+ chip_tag |= (regval);
+ sprintf(temp_str, "CHIP TAG: %llx \n", chip_tag);
+ strcat(ssv6xxx_result_buf, temp_str);
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_3, &regval)) ;
+ *((u32 *) & chip_id[0]) = (u32) LONGSWAP(regval);
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_2, &regval)) ;
+ *((u32 *) & chip_id[4]) = (u32) LONGSWAP(regval);
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_1, &regval)) ;
+ *((u32 *) & chip_id[8]) = (u32) LONGSWAP(regval);
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_0, &regval)) ;
+ *((u32 *) & chip_id[12]) = (u32) LONGSWAP(regval);
+ sprintf(temp_str, "CHIP ID: %s \n", chip_id);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "# current Software mac version: %d\n",
+ ssv_root_version);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "SVN ROOT URL %s \n", SSV_ROOT_URl);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "COMPILER HOST %s \n", COMPILERHOST);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "COMPILER DATE %s \n", COMPILERDATE);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "COMPILER OS %s \n", COMPILEROS);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "COMPILER OS ARCH %s \n", COMPILEROSARCH);
+ strcat(ssv6xxx_result_buf, temp_str);
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, FW_VERSION_REG, &regval)) ;
+ sprintf(temp_str, "Firmware image version: %d\n", regval);
+ strcat(ssv6xxx_result_buf, temp_str);
+ sprintf(temp_str, "\n[Compiler Option!!]\n");
+ strcat(ssv6xxx_result_buf, temp_str);
+ return 0;
+}
+
+static int ssv_cmd_tool(int argc, char *argv[])
+{
+ u32 addr, value, count;
+ char tmpbf[12], *endp;
+ int s;
+ if (argc == 4 && strcmp(argv[1], "w") == 0) {
+ addr = simple_strtoul(argv[2], &endp, 16);
+ value = simple_strtoul(argv[3], &endp, 16);
+ if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, addr, value)) ;
+ sprintf(ssv6xxx_result_buf, "ok");
+ return 0;
+ }
+ if ((argc == 4 || argc == 3) && strcmp(argv[1], "r") == 0) {
+ count = (argc == 3) ? 1 : simple_strtoul(argv[3], &endp, 10);
+ addr = simple_strtoul(argv[2], &endp, 16);
+ for (s = 0; s < count; s++, addr += 4) {
+ if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+ sprintf(tmpbf, "%08x\n", value);
+ strcat(ssv6xxx_result_buf, tmpbf);
+ }
+ return 0;
+ }
+ return -1;
+}
+
+struct _ssv6xxx_txtput {
+ struct task_struct *txtput_tsk;
+ struct sk_buff *skb;
+ u32 size_per_frame;
+ u32 loop_times;
+ u32 occupied_tx_pages;
+};
+struct _ssv6xxx_txtput *ssv6xxx_txtput;
+struct _ssv6xxx_txtput ssv_txtput = { NULL, NULL, 0, 0, 0 };
+
+static int txtput_thread_m2(void *data)
+{
+#define Q_DELAY_MS 20
+ struct sk_buff *skb = NULL;
+ struct ssv6200_tx_desc *tx_desc;
+ int qlen = 0, max_qlen, q_delay_urange[2];
+ max_qlen =
+ (200 * 1000 / 8 * Q_DELAY_MS) / ssv6xxx_txtput->size_per_frame;
+ q_delay_urange[0] = Q_DELAY_MS * 1000;
+ q_delay_urange[1] = q_delay_urange[0] + 1000;
+ pr_debug("max_qlen: %d\n", max_qlen);
+ while (!kthread_should_stop() && ssv6xxx_txtput->loop_times > 0) {
+ ssv6xxx_txtput->loop_times--;
+ skb = ssvdevice_skb_alloc(ssv6xxx_txtput->size_per_frame);
+ if (skb == NULL) {
+ pr_debug("ssv command txtput_generate_m2 "
+ "ssvdevice_skb_alloc fail!!!\n");
+ goto end;
+ }
+ skb->data_len = ssv6xxx_txtput->size_per_frame;
+ skb->len = ssv6xxx_txtput->size_per_frame;
+ tx_desc = (struct ssv6200_tx_desc *)skb->data;
+ memset((void *)tx_desc, 0xff, SSV6XXX_TX_DESC_LEN);
+ tx_desc->len = skb->len;
+ tx_desc->c_type = M2_TXREQ;
+ tx_desc->fCmd = (M_ENG_CPU << 4) | M_ENG_HWHCI;
+ tx_desc->reason = ID_TRAP_SW_TXTPUT;
+ qlen = ssv_dbg_ctrl_hci->shi->hci_ops->hci_tx(skb, 0, 0);
+ if (qlen >= max_qlen) {
+ usleep_range(q_delay_urange[0], q_delay_urange[1]);
+ }
+ }
+ end:
+ ssv6xxx_txtput->txtput_tsk = NULL;
+ return 0;
+}
+
+static int txtput_thread(void *data)
+{
+ struct sk_buff *skb = ssv6xxx_txtput->skb;
+ struct ssv6xxx_hci_txq_info2 txq_info2;
+ u32 ret = 0, free_tx_page;
+ int send_cnt;
+ unsigned long start_time, end_time, throughput, time_elapse;
+ throughput =
+ ssv6xxx_txtput->loop_times * ssv6xxx_txtput->size_per_frame * 8;
+ start_time = jiffies;
+ while (!kthread_should_stop() && ssv6xxx_txtput->loop_times > 0) {
+ ret =
+ SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_TX_ID_ALL_INFO2,
+ (u32 *) & txq_info2);
+ if (ret < 0) {
+ pr_debug("%s, read ADR_TX_ID_ALL_INFO2 failed\n",
+ __func__);
+ goto end;
+ }
+ free_tx_page =
+ SSV6200_PAGE_TX_THRESHOLD - txq_info2.tx_use_page;
+ send_cnt = free_tx_page / ssv6xxx_txtput->occupied_tx_pages;
+ while (send_cnt > 0 && ssv6xxx_txtput->loop_times > 0) {
+ send_cnt--;
+ ssv6xxx_txtput->loop_times--;
+ ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb);
+ }
+ }
+ end_time = jiffies;
+ ssvdevice_skb_free(skb);
+ time_elapse = ((end_time - start_time) * 1000) / HZ;
+ if (time_elapse > 0) {
+ throughput = throughput / time_elapse;
+ pr_debug("duration %ldms, avg. throughput %d Kbps\n", time_elapse,
+ (int)throughput);
+ }
+ end:
+ ssv6xxx_txtput->txtput_tsk = NULL;
+ return 0;
+}
+
+int txtput_generate_m2(u32 size_per_frame, u32 loop_times)
+{
+ ssv6xxx_txtput->size_per_frame = size_per_frame;
+ ssv6xxx_txtput->loop_times = loop_times;
+ ssv6xxx_txtput->txtput_tsk =
+ kthread_run(txtput_thread_m2, NULL, "txtput_thread_m2");
+ return 0;
+}
+
+int txtput_generate_host_cmd(u32 size_per_frame, u32 loop_times)
+{
+#define PAGESIZE 256
+ struct cfg_host_cmd *host_cmd;
+ struct sk_buff *skb;
+ skb = ssvdevice_skb_alloc(size_per_frame);
+ if (skb == NULL) {
+ pr_debug
+ ("ssv command txtput_generate_host_cmd ssvdevice_skb_alloc fail!!!\n");
+ return 0;
+ }
+ skb->data_len = size_per_frame;
+ skb->len = skb->data_len;
+ host_cmd = (struct cfg_host_cmd *)skb->data;
+ host_cmd->c_type = TEST_CMD;
+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_TX_TPUT;
+ host_cmd->len = skb->data_len;
+ memcpy(host_cmd->dat32, skb->data, size_per_frame);
+ ssv6xxx_txtput->occupied_tx_pages =
+ (size_per_frame / PAGESIZE) + ((size_per_frame % PAGESIZE) != 0);
+ ssv6xxx_txtput->size_per_frame = size_per_frame;
+ ssv6xxx_txtput->loop_times = loop_times;
+ ssv6xxx_txtput->skb = skb;
+ ssv6xxx_txtput->txtput_tsk =
+ kthread_run(txtput_thread, NULL, "txtput_thread");
+ return 0;
+}
+
+int txtput_tsk_cleanup(void)
+{
+ int ret = 0;
+ if (ssv6xxx_txtput->txtput_tsk) {
+ ret = kthread_stop(ssv6xxx_txtput->txtput_tsk);
+ ssv6xxx_txtput->txtput_tsk = NULL;
+ }
+ return ret;
+}
+
+int watchdog_controller(struct ssv_hw *sh, u8 flag)
+{
+ struct sk_buff *skb;
+ struct cfg_host_cmd *host_cmd;
+ int ret = 0;
+ pr_debug("watchdog_controller %d\n", flag);
+ skb = ssvdevice_skb_alloc(HOST_CMD_HDR_LEN);
+ if (skb == NULL) {
+ pr_err("init watchdog_controller failure\n");
+ return (-1);
+ }
+ skb->data_len = HOST_CMD_HDR_LEN;
+ skb->len = skb->data_len;
+ host_cmd = (struct cfg_host_cmd *)skb->data;
+ host_cmd->c_type = HOST_CMD;
+ host_cmd->h_cmd = (u8) flag;
+ host_cmd->len = skb->data_len;
+ sh->hci.hci_ops->hci_send_cmd(skb);
+ ssvdevice_skb_free(skb);
+ return ret;
+}
+
+static int ssv_cmd_txtput(int argc, char *argv[])
+{
+ char tmpbf[64], *endp;
+ u32 size_per_frame, loop_times, pkt_type;
+ ssv6xxx_txtput = &ssv_txtput;
+ if (argc == 2 && !strcmp(argv[1], "stop")) {
+ txtput_tsk_cleanup();
+ return 0;
+ }
+ if (argc != 4) {
+ sprintf(tmpbf, "* txtput stop\n");
+ strcat(ssv6xxx_result_buf, tmpbf);
+ sprintf(tmpbf, "* txtput [type] [size] [frames]\n");
+ strcat(ssv6xxx_result_buf, tmpbf);
+ sprintf(tmpbf, " type(packet type):\n");
+ strcat(ssv6xxx_result_buf, tmpbf);
+ sprintf(tmpbf, " 0 = host_cmd\n");
+ strcat(ssv6xxx_result_buf, tmpbf);
+ sprintf(tmpbf, " 1 = m2_type \n");
+ strcat(ssv6xxx_result_buf, tmpbf);
+ sprintf(tmpbf, " EX: txtput 1 14000 9999 \n");
+ strcat(ssv6xxx_result_buf, tmpbf);
+ return 0;
+ }
+ pkt_type = simple_strtoul(argv[1], &endp, 10);
+ size_per_frame = simple_strtoul(argv[2], &endp, 10);
+ loop_times = simple_strtoul(argv[3], &endp, 10);
+ sprintf(tmpbf, "type&size&frames:%d&%d&%d\n", pkt_type, size_per_frame,
+ loop_times);
+ strcat(ssv6xxx_result_buf, tmpbf);
+ if (ssv6xxx_txtput->txtput_tsk) {
+ sprintf(tmpbf, "txtput already in progress\n");
+ strcat(ssv6xxx_result_buf, tmpbf);
+ return 0;
+ }
+ watchdog_controller(((struct ssv_softc *)ssv_dbg_sc)->sh,
+ (u8) SSV6XXX_HOST_CMD_WATCHDOG_STOP);
+ ((struct ssv_softc *)ssv_dbg_sc)->watchdog_flag = WD_SLEEP;
+ if (pkt_type)
+ txtput_generate_m2(size_per_frame + SSV6XXX_TX_DESC_LEN,
+ loop_times);
+ else
+ txtput_generate_host_cmd(size_per_frame + HOST_CMD_HDR_LEN,
+ loop_times);
+ return 0;
+}
+
+static int ssv_cmd_rxtput(int argc, char *argv[])
+{
+ struct sk_buff *skb;
+ struct cfg_host_cmd *host_cmd;
+ struct sdio_rxtput_cfg cmd_rxtput_cfg;
+ char tmpbf[32], *endp;
+ if (argc != 3) {
+ sprintf(ssv6xxx_result_buf, "rxtput [size] [frames]\n");
+ return 0;
+ }
+ skb =
+ ssvdevice_skb_alloc(HOST_CMD_HDR_LEN +
+ sizeof(struct sdio_rxtput_cfg));
+ if (skb == NULL) {
+ pr_err("ssv command ssvdevice_skb_alloc fail\n");
+ return 0;
+ }
+ watchdog_controller(((struct ssv_softc *)ssv_dbg_sc)->sh,
+ (u8) SSV6XXX_HOST_CMD_WATCHDOG_STOP);
+ ((struct ssv_softc *)ssv_dbg_sc)->watchdog_flag = WD_SLEEP;
+ cmd_rxtput_cfg.size_per_frame = simple_strtoul(argv[1], &endp, 10);
+ cmd_rxtput_cfg.total_frames = simple_strtoul(argv[2], &endp, 10);
+ sprintf(tmpbf, "size&frames:%d&%d\n", cmd_rxtput_cfg.size_per_frame,
+ cmd_rxtput_cfg.total_frames);
+ strcat(ssv6xxx_result_buf, tmpbf);
+ skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct sdio_rxtput_cfg);
+ skb->len = skb->data_len;
+ host_cmd = (struct cfg_host_cmd *)skb->data;
+ host_cmd->c_type = HOST_CMD;
+ host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_RX_TPUT;
+ host_cmd->len = skb->data_len;
+ memcpy(host_cmd->dat32, &cmd_rxtput_cfg,
+ sizeof(struct sdio_rxtput_cfg));
+ if (ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb) == 0) {
+ strcat(ssv6xxx_result_buf,
+ "## hci cmd was sent successfully\n");
+ } else {
+ strcat(ssv6xxx_result_buf, "## hci cmd was sent failed\n");
+ }
+ ssvdevice_skb_free(skb);
+ return 0;
+}
+
+static int ssv_cmd_check(int argc, char *argv[])
+{
+ u32 size, i, j, x, y, id, value, address, id_value;
+ char *endp;
+ u32 id_base_address[4];
+ id_base_address[0] = 0xcd010008;
+ id_base_address[1] = 0xcd01000c;
+ id_base_address[2] = 0xcd010054;
+ id_base_address[3] = 0xcd010058;
+ if (argc != 2) {
+ sprintf(ssv6xxx_result_buf, "check [packet size]\n");
+ return 0;
+ }
+ size = simple_strtoul(argv[1], &endp, 10);
+ size = size >> 2;
+ for (x = 0; x < 4; x++) {
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops, id_base_address[x], &id_value)) ;
+ for (y = 0; y < 32 && id_value; y++, id_value >>= 1) {
+ if (id_value & 0x1) {
+ id = 32 * x + y;
+ address = 0x80000000 + (id << 16);
+ {
+ for (i = 0; i < size; i += 8) {
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops,
+ address, &value)) ;
+ address += 4;
+ for (j = 1; j < 8; j++) {
+ if (SSV_REG_READ1
+ (ssv6xxx_debug_ifops,
+ address, &value)) ;
+ address += 4;
+ }
+ }
+ }
+ }
+ }
+ }
+ return 0;
+}
+
+struct ssv_cmd_table cmd_table[] = {
+ {"help", ssv_cmd_help, "ssv6200 command usage."},
+ {"-h", ssv_cmd_help, "ssv6200 command usage."},
+ {"--help", ssv_cmd_help, "ssv6200 command usage."},
+ {"reg", ssv_cmd_reg, "ssv6200 register read/write."},
+ {"cfg", ssv_cmd_cfg, "ssv6200 configuration."},
+ {"sta", ssv_cmd_sta, "svv6200 station info."},
+ {"dump", ssv_cmd_dump, "dump ssv6200 tables."},
+ {"hwq", ssv_cmd_hwq, "hardware queue staus"},
+#ifdef CONFIG_P2P_NOA
+ {"noa", ssv_cmd_noa, "config noa param"},
+#endif
+ {"irq", ssv_cmd_irq, "get sdio irq status."},
+ {"mac", ssv_cmd_mac, "ieee80211 swmac."},
+ {"hci", ssv_cmd_hci, "HCI command."},
+ {"sdio", ssv_cmd_sdio, "SDIO command."},
+ {"iqk", ssv_cmd_iqk, "iqk command"},
+ {"version", ssv_cmd_version, "version information"},
+ {"mib", ssv_cmd_mib, "mib counter related"},
+ {"tool", ssv_cmd_tool, "ssv6200 tool register read/write."},
+ {"rxtput", ssv_cmd_rxtput, "test rx sdio throughput"},
+ {"txtput", ssv_cmd_txtput, "test tx sdio throughput"},
+ {"check", ssv_cmd_check, "dump all allocate packet buffer"},
+ {NULL, NULL, NULL},
+};
+
+int ssv_cmd_submit(char *cmd)
+{
+ struct ssv_cmd_table *sc_tbl;
+ char *pch, ch;
+ int ret;
+ ssv6xxx_debug_ifops = (void *)ssv6xxx_ifdebug_info;
+ strcpy(sg_cmd_buffer, cmd);
+ for (sg_argc = 0, ch = 0, pch = sg_cmd_buffer;
+ (*pch != 0x00) && (sg_argc < CLI_ARG_SIZE); pch++) {
+ if ((ch == 0) && (*pch != ' ')) {
+ ch = 1;
+ sg_argv[sg_argc] = pch;
+ }
+ if ((ch == 1) && (*pch == ' ')) {
+ *pch = 0x00;
+ ch = 0;
+ sg_argc++;
+ }
+ }
+ if (ch == 1) {
+ sg_argc++;
+ } else if (sg_argc > 0) {
+ *(pch - 1) = ' ';
+ }
+ if (sg_argc > 0) {
+ for (sc_tbl = cmd_table; sc_tbl->cmd; sc_tbl++) {
+ if (!strcmp(sg_argv[0], sc_tbl->cmd)) {
+ if ((sc_tbl->cmd_func_ptr != ssv_cmd_cfg) &&
+ (!ssv6xxx_debug_ifops->dev ||
+ !ssv6xxx_debug_ifops->ifops ||
+ !ssv6xxx_debug_ifops->pdev)) {
+ strcpy(ssv6xxx_result_buf,
+ "Member of ssv6xxx_ifdebug_info is NULL !\n");
+ return -1;
+ }
+ ssv6xxx_result_buf[0] = 0x00;
+ ret = sc_tbl->cmd_func_ptr(sg_argc, sg_argv);
+ if (ret < 0) {
+ strcpy(ssv6xxx_result_buf,
+ "Invalid command !\n");
+ }
+ return 0;
+ }
+ }
+ strcpy(ssv6xxx_result_buf, "Command not found !\n");
+ } else {
+ strcpy(ssv6xxx_result_buf, "./cli -h\n");
+ }
+ return 0;
+}
diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
new file mode 100644
index 000000000000..d96bfcc54954
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_CMD_H_
+#define _SSV_CMD_H_
+#define CLI_BUFFER_SIZE 256
+#define CLI_ARG_SIZE 10
+#define CLI_RESULT_BUF_SIZE (4096)
+#define DEBUG_DIR_ENTRY "ssv"
+#define DEBUG_DEVICETYPE_ENTRY "ssv_devicetype"
+#define DEBUG_CMD_ENTRY "ssv_cmd"
+#define MAX_CHARS_PER_LINE 256
+struct ssv_cmd_table {
+ const char *cmd;
+ int (*cmd_func_ptr)(int, char **);
+ const char *usage;
+};
+struct ssv6xxx_cfg_cmd_table {
+ u8 *cfg_cmd;
+ void *var;
+ u32 arg;
+ int (*translate_func)(u8 *, void *, u32);
+};
+#define SSV_REG_READ1(ops,reg,val) \
+ (ops)->ifops->readreg((ops)->dev, reg, val)
+#define SSV_REG_WRITE1(ops,reg,val) \
+ (ops)->ifops->writereg((ops)->dev, reg, val)
+#define SSV_REG_SET_BITS1(ops,reg,set,clr) \
+ { \
+ u32 reg_val; \
+ SSV_REG_READ(ops, reg, &reg_val); \
+ reg_val &= ~(clr); \
+ reg_val |= (set); \
+ SSV_REG_WRITE(ops, reg, reg_val); \
+ }
+int ssv_cmd_submit(char *cmd);
+#endif
diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c b/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
new file mode 100644
index 000000000000..eb848553798f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/slab.h>
+#include <asm/uaccess.h>
+#include <linux/errno.h>
+#include "ssv_cmd.h"
+#include "ssv_cfg.h"
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#include <linux/buffer_head.h>
+#include <linux/ctype.h>
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#endif
+
+char *ssv_initmac = NULL;
+EXPORT_SYMBOL(ssv_initmac);
+module_param(ssv_initmac, charp, 0644);
+MODULE_PARM_DESC(ssv_initmac, "Wi-Fi MAC address");
+
+u32 ssv_devicetype = 0;
+EXPORT_SYMBOL(ssv_devicetype);
+
+#ifdef CONFIG_DEBUG_FS
+static struct dentry *debugfs;
+#endif
+
+struct proc_dir_entry *procfs;
+static char *ssv6xxx_cmd_buf;
+char *ssv6xxx_result_buf;
+extern struct ssv6xxx_cfg_cmd_table cfg_cmds[];
+extern struct ssv6xxx_cfg ssv_cfg;
+char DEFAULT_CFG_PATH[] = "/lib/firmware/ssv6051-wifi.cfg";
+static int ssv6xxx_dbg_open(struct inode *inode, struct file *filp)
+{
+ filp->private_data = inode->i_private;
+ return 0;
+}
+
+static ssize_t ssv6xxx_dbg_read(struct file *filp, char __user * buffer,
+ size_t count, loff_t * ppos)
+{
+ int len;
+ if (*ppos != 0)
+ return 0;
+ len = strlen(ssv6xxx_result_buf) + 1;
+ if (len == 1)
+ return 0;
+ if (copy_to_user(buffer, ssv6xxx_result_buf, len))
+ return -EFAULT;
+ ssv6xxx_result_buf[0] = 0x00;
+ return len;
+}
+
+static ssize_t ssv6xxx_dbg_write(struct file *filp, const char __user * buffer,
+ size_t count, loff_t * ppos)
+{
+ if (*ppos != 0 || count > 255)
+ return 0;
+ if (copy_from_user(ssv6xxx_cmd_buf, buffer, count))
+ return -EFAULT;
+ ssv6xxx_cmd_buf[count - 1] = 0x00;
+ ssv_cmd_submit(ssv6xxx_cmd_buf);
+ return count;
+}
+
+size_t read_line(struct file * fp, char *buf, size_t size)
+{
+ size_t num_read = 0;
+ size_t total_read = 0;
+ char *buffer;
+ char ch;
+ size_t start_ignore = 0;
+ if (size <= 0 || buf == NULL) {
+ total_read = -EINVAL;
+ return -EINVAL;
+ }
+ buffer = buf;
+ for (;;) {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
+ num_read = kernel_read(fp, &ch, 1, &fp->f_pos);
+#else
+ mm_segment_t fs;
+ fs = get_fs();
+ set_fs(KERNEL_DS);
+ num_read = vfs_read(fp, &ch, 1, &fp->f_pos);
+ set_fs(fs);
+#endif
+ if (num_read < 0) {
+ if (num_read == EINTR)
+ continue;
+ else
+ return -1;
+ } else if (num_read == 0) {
+ if (total_read == 0)
+ return 0;
+ else
+ break;
+ } else {
+ if (ch == '#')
+ start_ignore = 1;
+ if (total_read < size - 1) {
+ total_read++;
+ if (start_ignore)
+ *buffer++ = '\0';
+ else
+ *buffer++ = ch;
+ }
+ if (ch == '\n')
+ break;
+ }
+ }
+ *buffer = '\0';
+ return total_read;
+}
+
+int ischar(char *c)
+{
+ int is_char = 1;
+ while (*c) {
+ if (isalpha(*c) || isdigit(*c) || *c == '_' || *c == ':'
+ || *c == '/' || *c == '.' || *c == '-')
+ c++;
+ else {
+ is_char = 0;
+ break;
+ }
+ }
+ return is_char;
+}
+
+void sta_cfg_set(void)
+{
+ struct file *fp = (struct file *)NULL;
+ char buf[MAX_CHARS_PER_LINE], cfg_cmd[32], cfg_value[32];
+ size_t s, read_len = 0, is_cmd_support = 0;
+
+ memset(&ssv_cfg, 0, sizeof(ssv_cfg));
+ memset(buf, 0, sizeof(buf));
+ fp = filp_open(DEFAULT_CFG_PATH, O_RDONLY, 0);
+ if (IS_ERR(fp) || fp == NULL) {
+ WARN_ON(1);
+ return;
+ }
+ if (fp->f_path.dentry == NULL) {
+ WARN_ON(1);
+ return;
+ }
+ do {
+ memset(cfg_cmd, '\0', sizeof(cfg_cmd));
+ memset(cfg_value, '\0', sizeof(cfg_value));
+ read_len = read_line(fp, buf, MAX_CHARS_PER_LINE);
+ sscanf(buf, "%s = %s", cfg_cmd, cfg_value);
+ if (!ischar(cfg_cmd) || !ischar(cfg_value)) {
+ pr_warn("Invalid configuration parameter: %s\n", buf);
+ continue;
+ }
+ is_cmd_support = 0;
+ for (s = 0; cfg_cmds[s].cfg_cmd != NULL; s++) {
+ if (strcmp(cfg_cmds[s].cfg_cmd, cfg_cmd) == 0) {
+ cfg_cmds[s].translate_func(cfg_value,
+ cfg_cmds[s].var,
+ cfg_cmds[s].arg);
+ is_cmd_support = 1;
+ break;
+ }
+ }
+ if (!is_cmd_support && strlen(cfg_cmd) > 0) {
+ pr_warn("Unsupported configuration command: %s", cfg_cmd);
+ }
+ } while (read_len > 0);
+ filp_close(fp, NULL);
+}
+
+static const struct file_operations ssv6xxx_dbg_fops = {
+ .owner = THIS_MODULE,
+ .open = ssv6xxx_dbg_open,
+ .read = ssv6xxx_dbg_read,
+ .write = ssv6xxx_dbg_write,
+};
+
+extern int ssv6xxx_hci_init(void);
+extern void ssv6xxx_hci_exit(void);
+extern int ssv6xxx_init(void);
+extern void ssv6xxx_exit(void);
+extern int ssv6xxx_sdio_init(void);
+extern void ssv6xxx_sdio_exit(void);
+
+int ssvdevice_init(void)
+{
+ ssv6xxx_cmd_buf =
+ (char *)kzalloc(CLI_BUFFER_SIZE + CLI_RESULT_BUF_SIZE, GFP_KERNEL);
+ if (!ssv6xxx_cmd_buf)
+ return -ENOMEM;
+ ssv6xxx_result_buf = ssv6xxx_cmd_buf + CLI_BUFFER_SIZE;
+ ssv6xxx_cmd_buf[0] = 0x00;
+ ssv6xxx_result_buf[0] = 0x00;
+#ifdef CONFIG_DEBUG_FS
+ debugfs = debugfs_create_dir(DEBUG_DIR_ENTRY, NULL);
+ if (!debugfs)
+ return -ENOMEM;
+ debugfs_create_u32(DEBUG_DEVICETYPE_ENTRY, S_IRUGO | S_IWUSR, debugfs,
+ &ssv_devicetype);
+ debugfs_create_file(DEBUG_CMD_ENTRY, S_IRUGO | S_IWUSR, debugfs, NULL,
+ &ssv6xxx_dbg_fops);
+#endif
+ sta_cfg_set();
+ {
+ int ret;
+ ret = ssv6xxx_hci_init();
+ if (!ret) {
+ ret = ssv6xxx_init();
+ }
+ if (!ret) {
+ ret = ssv6xxx_sdio_init();
+ }
+ return ret;
+ }
+
+ return 0;
+}
+
+void ssvdevice_exit(void)
+{
+
+ ssv6xxx_exit();
+ ssv6xxx_hci_exit();
+ ssv6xxx_sdio_exit();
+
+#ifdef CONFIG_DEBUG_FS
+ debugfs_remove_recursive(debugfs);
+#endif
+ kfree(ssv6xxx_cmd_buf);
+}
+
+EXPORT_SYMBOL(ssvdevice_init);
+EXPORT_SYMBOL(ssvdevice_exit);
--
2.34.1
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