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build/patch/kernel/archive/rockchip64-4.4/zz-add-rk3328-firefly-core-dtsi.patch

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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
Date: Sat, 20 Jun 2020 22:39:57 +0200
Subject: [ARCHEOLOGY] Initial ROCK Pi E support (as WIP) (#2042)
> X-Git-Archeology: > recovered message: > * WIP: Adding RockpiE config
> X-Git-Archeology: > recovered message: > Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: > recovered message: > * Mainline u-boot for ROCK Pi E
> X-Git-Archeology: > recovered message: > * Initial ROCK Pi E device tree in kernel
> X-Git-Archeology: > recovered message: > * Fixed supplies for ROCK Pi E device tree
> X-Git-Archeology: > recovered message: > * Adjusted u-boot load address for rockchip64 boards with 256MB eg. ROCK Pi E
> X-Git-Archeology: > recovered message: > * Blacklisted lima on ROCK Pi E
> X-Git-Archeology: > recovered message: > * Fixed ROCK Pi E patch after merge from master
> X-Git-Archeology: > recovered message: > * Removed mode settings from rk805 regulators
> X-Git-Archeology: > recovered message: > * Fixed issues with offloading for gigabit interface of RockPi E
> X-Git-Archeology: > recovered message: > * Adjusted ROCK Pi E board config
> X-Git-Archeology: > recovered message: > * Added dev branch for ROCK Pi E
> X-Git-Archeology: > recovered message: > * Add build targets
> X-Git-Archeology: > recovered message: > Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
> X-Git-Archeology: > recovered message: > * Exchange legacy to current in ROCK Pi E build targets
> X-Git-Archeology: > recovered message: > Co-authored-by: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: - Revision e1ecb098330dc372740371dc2386f911833a0529: https://github.com/armbian/build/commit/e1ecb098330dc372740371dc2386f911833a0529
> X-Git-Archeology: Date: Sat, 20 Jun 2020 22:39:57 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Initial ROCK Pi E support (as WIP) (#2042)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 72257bd0648c28fca32962126bb885a4a2c188cc: https://github.com/armbian/build/commit/72257bd0648c28fca32962126bb885a4a2c188cc
> X-Git-Archeology: Date: Tue, 23 Jun 2020 16:37:54 +0200
> X-Git-Archeology: From: Piotr Szczepanik <piter75@gmail.com>
> X-Git-Archeology: Subject: Make USB3 support of ROCK Pi E on par with other rk3328 boards (#2050)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 36405e3397b68600bdd2c34d5a7bcfa0a09b1226: https://github.com/armbian/build/commit/36405e3397b68600bdd2c34d5a7bcfa0a09b1226
> X-Git-Archeology: Date: Sat, 29 Aug 2020 00:16:28 +0200
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Add Rockpi 4C (#2129)
> X-Git-Archeology:
> X-Git-Archeology: - Revision a1e96e68d864ddc2fef169f3f503a9493311313b: https://github.com/armbian/build/commit/a1e96e68d864ddc2fef169f3f503a9493311313b
> X-Git-Archeology: Date: Mon, 04 Jan 2021 11:51:43 +0100
> X-Git-Archeology: From: Oleg <balbes-150@yandex.ru>
> X-Git-Archeology: Subject: add station legacy (#2521)
> X-Git-Archeology:
> X-Git-Archeology: - Revision 438563b6656ccdd5d1176974ecf064d0a80736c5: https://github.com/armbian/build/commit/438563b6656ccdd5d1176974ecf064d0a80736c5
> X-Git-Archeology: Date: Fri, 22 Jan 2021 20:34:45 +0100
> X-Git-Archeology: From: JMCC <jmcc1@gmx.com>
> X-Git-Archeology: Subject: Station M1 Legacy: Enable 1.51Ghz OPP
> X-Git-Archeology:
> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100
> X-Git-Archeology: From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704)
> X-Git-Archeology:
---
arch/arm64/boot/dts/rockchip/rk3328-firefly-core.dtsi | 453 ++++++++++
1 file changed, 453 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-firefly-core.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-firefly-core.dtsi
new file mode 100644
index 000000000000..db60b8597d51
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-firefly-core.dtsi
@@ -0,0 +1,453 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+#include "rk3328-linux.dtsi"
+#include <dt-bindings/input/input.h>
+#include "rk3328-box-plus-dram-timing.dtsi"
+
+/ {
+ compatible = "firefly,rk3328-firefly-core", "rockchip,rk3328";
+
+ chosen {
+ bootargs = "rockchip_jtag earlyprintk=uart8250-32bit,0xff130000 swiotlb=1 kpti=0 console=ttyFIQ0 ro root=PARTLABEL=rootfs rootfstype=ext4 rootwait overlayroot=device:dev=PARTLABEL=userdata,fstype=ext4,mkfs=1 systemd.gpt_auto=0 cgroup_enable=memory swapaccount=1";
+ stdout-path = "serial2:1500000n8";
+ };
+
+ fiq-debugger {
+ compatible = "rockchip,fiq-debugger";
+ rockchip,serial-id = <2>;
+ rockchip,signal-irq = <159>;
+ rockchip,wake-irq = <0>;
+ /* If enable uart uses irq instead of fiq */
+ rockchip,irq-mode-enable = <0>;
+ rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vccio_sd: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ //pinctrl-names = "default";
+ //pinctrl-0 = <&sd_pwr_1800_sel>;
+ regulator-name = "vccio_sd";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ status="okay";
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ status = "okay";
+ center-supply = <&vdd_logic>;
+};
+
+&dmc_opp_table {
+ status = "okay";
+};
+
+&cpu0_opp_table {
+
+ rockchip,leakage-voltage-sel = <
+ 1 8 0
+ 9 254 1
+ >;
+ nvmem-cells = <&cpu_leakage>;
+ nvmem-cell-names = "cpu_leakage";
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <975000>;
+ opp-microvolt-L0 = <975000>;
+ opp-microvolt-L1 = <950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <975000>;
+ opp-microvolt-L0 = <975000>;
+ opp-microvolt-L1 = <950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1025000>;
+ opp-microvolt-L0 = <1025000>;
+ opp-microvolt-L1 = <1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1125000>;
+ opp-microvolt-L0 = <1125000>;
+ opp-microvolt-L1 = <1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1250000>;
+ opp-microvolt-L0 = <1250000>;
+ opp-microvolt-L1 = <1225000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1325000>;
+ opp-microvolt-L0 = <1325000>;
+ opp-microvolt-L1 = <1300000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1392000000 {
+ opp-hz = /bits/ 64 <1392000000>;
+ opp-microvolt = <1350000>;
+ opp-microvolt-L0 = <1350000>;
+ opp-microvolt-L1 = <1325000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1512000000 {
+ status = "okay";
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <1425000>;
+ opp-microvolt-L0 = <1425000>;
+ opp-microvolt-L1 = <1425000>;
+ clock-latency-ns = <40000>;
+ };
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ supports-emmc;
+ disable-wp;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc_18emmc>;
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+ mali-supply = <&vdd_logic>;
+};
+
+&gpu_opp_table {
+
+ rockchip,leakage-voltage-sel = <
+ 1 8 0
+ 9 254 1
+ >;
+ nvmem-cells = <&logic_leakage>;
+ nvmem-cell-names = "gpu_leakage";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1050000>;
+ opp-microvolt-L0 = <1050000>;
+ opp-microvolt-L1 = <1025000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1050000>;
+ opp-microvolt-L0 = <1050000>;
+ opp-microvolt-L1 = <1025000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1050000>;
+ opp-microvolt-L0 = <1050000>;
+ opp-microvolt-L1 = <1025000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1125000>;
+ opp-microvolt-L0 = <1125000>;
+ opp-microvolt-L1 = <1100000>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ status = "okay";
+ reg = <0x18>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+
+ rtc {
+ status = "okay";
+ };
+
+ pwrkey {
+ status = "disabled";
+ };
+
+ gpio {
+ status = "okay";
+ };
+
+ regulators {
+ compatible = "rk805-regulator";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_logic: RK805_DCDC1@0 {
+ regulator-compatible = "RK805_DCDC1";
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-initial-mode = <0x1>;
+ regulator-ramp-delay = <12500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-mode = <0x2>;
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: RK805_DCDC2@1 {
+ regulator-compatible = "RK805_DCDC2";
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-initial-mode = <0x1>;
+ regulator-ramp-delay = <12500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-mode = <0x2>;
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: RK805_DCDC3@2 {
+ regulator-compatible = "RK805_DCDC3";
+ regulator-name = "vcc_ddr";
+ regulator-initial-mode = <0x1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-mode = <0x2>;
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: RK805_DCDC4@3 {
+ regulator-compatible = "RK805_DCDC4";
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <0x1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-mode = <0x2>;
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd_18: RK805_LDO1@4 {
+ regulator-compatible = "RK805_LDO1";
+ regulator-name = "vdd_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_18emmc: RK805_LDO2@5 {
+ regulator-compatible = "RK805_LDO2";
+ regulator-name = "vcc_18emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_11: RK805_LDO3@6 {
+ regulator-compatible = "RK805_LDO3";
+ regulator-name = "vdd_11";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1100000>;
+ };
+ };
+ };
+ };
+};
+
+&h265e {
+ status = "okay";
+};
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc_18emmc>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vdd_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins =
+ <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio1_d0 */
+ };
+ };
+
+};
+
+&rkvdec {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ clock-freq-min-max = <400000 80000000>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ supports-sd;
+ status = "okay";
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vccio_sd>;
+};
+
+&tsadc {
+ status = "okay";
+};
+
--
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