136 lines
3.3 KiB
Diff
136 lines
3.3 KiB
Diff
From 0d27d4148080e8e9cbeb98a71630f9f375b76cb1 Mon Sep 17 00:00:00 2001
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From: Kali Prasad <kprasadvnsi@protonmail.com>
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Date: Sun, 19 Sep 2021 13:38:20 +0530
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Subject: [PATCH 39/50] arm64: dts: allwinner: h616: Add thermal sensor and
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thermal zones
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There are four sensors, CPU, GPU, VE, and DDR.
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Signed-off-by: Kali Prasad <kprasadvnsi@protonmail.com>
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---
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.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 74 +++++++++++++++++++
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1 file changed, 74 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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index a4a5f25d8..e4f5a085f 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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@@ -8,6 +8,7 @@
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#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
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#include <dt-bindings/reset/sun50i-h616-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
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+#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&gic>;
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@@ -24,6 +25,8 @@ cpu0: cpu@0 {
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reg = <0>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ #cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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@@ -32,6 +35,8 @@ cpu1: cpu@1 {
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reg = <1>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ #cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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@@ -40,6 +45,8 @@ cpu2: cpu@2 {
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reg = <2>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ #cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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@@ -48,6 +55,8 @@ cpu3: cpu@3 {
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reg = <3>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ #cooling-cells = <2>;
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};
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};
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@@ -822,5 +831,70 @@ r_rsb: rsb@7083000 {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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+
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+ ths: thermal-sensor@5070400 {
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+ compatible = "allwinner,sun50i-h616-ths";
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+ reg = <0x05070400 0x400>;
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+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_THS>;
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+ clock-names = "bus";
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+ resets = <&ccu RST_BUS_THS>;
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+ nvmem-cells = <&ths_calibration>;
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+ nvmem-cell-names = "calibration";
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+ #thermal-sensor-cells = <1>;
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+ };
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+ };
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+ thermal-zones {
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+ cpu-thermal {
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+ polling-delay-passive = <500>;
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+ polling-delay = <1000>;
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+ thermal-sensors = <&ths 2>;
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+ sustainable-power = <1000>;
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+ k_po = <20>;
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+ k_pu = <40>;
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+ k_i = <0>;
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+
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+ trips {
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+ cpu_threshold: trip-point@0 {
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+ temperature = <60000>;
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+ type = "passive";
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+ hysteresis = <0>;
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+ };
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+ cpu_target: trip-point@1 {
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+ temperature = <70000>;
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+ type = "passive";
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+ hysteresis = <0>;
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+ };
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+ };
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+
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+ cooling-maps {
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+ map0 {
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+ trip = <&cpu_target>;
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+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+ };
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+
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+ gpu-thermal {
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+ polling-delay-passive = <500>;
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+ polling-delay = <1000>;
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+ thermal-sensors = <&ths 0>;
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+ sustainable-power = <1100>;
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+ };
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+
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+ ve-thermal {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&ths 1>;
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+ };
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+
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+ ddr-thermal {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&ths 3>;
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+ };
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};
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};
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--
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2.34.1
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