75 lines
2.0 KiB
Diff
75 lines
2.0 KiB
Diff
From 4d97b78aec8d19fc765e1715d910515a7bca2b3d Mon Sep 17 00:00:00 2001
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From: Chris Morgan <macromorgan@hotmail.com>
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Date: Thu, 12 Aug 2021 21:45:43 +0800
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Subject: [PATCH 049/478] arm64: dts: rockchip: Add SFC to PX30
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Add a devicetree entry for the Rockchip SFC for the PX30 SOC.
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Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
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Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
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Link: https://lore.kernel.org/r/20210812134546.31340-4-jon.lin@rock-chips.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/px30.dtsi | 38 ++++++++++++++++++++++++++
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1 file changed, 38 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
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index 185bcc5c16ac..64f643145688 100644
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--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
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@@ -987,6 +987,18 @@ emmc: mmc@ff390000 {
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status = "disabled";
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};
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+ sfc: spi@ff3a0000 {
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+ compatible = "rockchip,sfc";
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+ reg = <0x0 0xff3a0000 0x0 0x4000>;
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+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
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+ clock-names = "clk_sfc", "hclk_sfc";
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+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
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+ pinctrl-names = "default";
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+ power-domains = <&power PX30_PD_MMC_NAND>;
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+ status = "disabled";
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+ };
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+
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nfc: nand-controller@ff3b0000 {
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compatible = "rockchip,px30-nfc";
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reg = <0x0 0xff3b0000 0x0 0x4000>;
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@@ -2008,6 +2020,32 @@ flash_bus8: flash-bus8 {
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};
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};
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+ sfc {
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+ sfc_bus4: sfc-bus4 {
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+ rockchip,pins =
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+ <1 RK_PA0 3 &pcfg_pull_none>,
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+ <1 RK_PA1 3 &pcfg_pull_none>,
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+ <1 RK_PA2 3 &pcfg_pull_none>,
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+ <1 RK_PA3 3 &pcfg_pull_none>;
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+ };
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+
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+ sfc_bus2: sfc-bus2 {
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+ rockchip,pins =
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+ <1 RK_PA0 3 &pcfg_pull_none>,
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+ <1 RK_PA1 3 &pcfg_pull_none>;
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+ };
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+
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+ sfc_cs0: sfc-cs0 {
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+ rockchip,pins =
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+ <1 RK_PA4 3 &pcfg_pull_none>;
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+ };
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+
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+ sfc_clk: sfc-clk {
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+ rockchip,pins =
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+ <1 RK_PB1 3 &pcfg_pull_none>;
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+ };
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+ };
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+
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lcdc {
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lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
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rockchip,pins =
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--
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2.35.3
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