120 lines
3.8 KiB
Diff
120 lines
3.8 KiB
Diff
From f6cb9e907edd5b5f7b85d6e475eb0263fd5b247a Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Thu, 22 Jul 2021 12:38:52 -0400
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Subject: [PATCH 090/478] arm64: dts: rockchip: add rk356x combophy nodes
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Add the combophy nodes to the rk356x device tree.
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These support sata, xmii, pcie, and usb modes.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 16 ++++++++
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 52 ++++++++++++++++++++++++
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2 files changed, 68 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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index 2fd313a295f8..305d49c587f2 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -71,6 +71,22 @@ gmac0_mtl_tx_setup: tx-queues-config {
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queue0 {};
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};
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};
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+
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+ combphy0_us: phy@fe820000 {
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+ compatible = "rockchip,rk3568-naneng-combphy";
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+ reg = <0x0 0xfe820000 0x0 0x100>;
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+ #phy-cells = <1>;
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+ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
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+ assigned-clock-rates = <100000000>;
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+ clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,
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+ <&cru PCLK_PIPE>;
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+ clock-names = "refclk", "apbclk", "pipe_clk";
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+ resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
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+ reset-names = "combphy-apb", "combphy";
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+ rockchip,pipe-grf = <&pipegrf>;
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+ rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
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+ status = "disabled";
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+ };
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};
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&cpu0_opp_table {
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diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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index 1767461d7b6d..340827747f5e 100644
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -258,11 +258,31 @@ pmu_io_domains: io-domains {
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};
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};
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+ pipegrf: syscon@fdc50000 {
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+ compatible = "rockchip,rk3568-pipegrf", "syscon";
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+ reg = <0x0 0xfdc50000 0x0 0x1000>;
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+ };
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+
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grf: syscon@fdc60000 {
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compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
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reg = <0x0 0xfdc60000 0x0 0x10000>;
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};
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+ pipe_phy_grf0: syscon@fdc70000 {
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+ compatible = "rockchip,pipe-phy-grf", "syscon";
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+ reg = <0x0 0xfdc70000 0x0 0x1000>;
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+ };
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+
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+ pipe_phy_grf1: syscon@fdc80000 {
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+ compatible = "rockchip,pipe-phy-grf", "syscon";
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+ reg = <0x0 0xfdc80000 0x0 0x1000>;
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+ };
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+
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+ pipe_phy_grf2: syscon@fdc90000 {
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+ compatible = "rockchip,pipe-phy-grf", "syscon";
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+ reg = <0x0 0xfdc90000 0x0 0x1000>;
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+ };
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+
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usb2phy0_grf: syscon@fdca0000 {
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compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
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reg = <0x0 0xfdca0000 0x0 0x8000>;
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@@ -1131,6 +1151,38 @@ pwm15: pwm@fe700030 {
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status = "disabled";
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};
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+ combphy1_usq: phy@fe830000 {
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+ compatible = "rockchip,rk3568-naneng-combphy";
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+ reg = <0x0 0xfe830000 0x0 0x100>;
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+ #phy-cells = <1>;
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+ assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
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+ assigned-clock-rates = <100000000>;
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+ clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>,
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+ <&cru PCLK_PIPE>;
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+ clock-names = "refclk", "apbclk", "pipe_clk";
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+ resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>;
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+ reset-names = "combphy-apb", "combphy";
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+ rockchip,pipe-grf = <&pipegrf>;
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+ rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
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+ status = "disabled";
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+ };
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+
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+ combphy2_psq: phy@fe840000 {
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+ compatible = "rockchip,rk3568-naneng-combphy";
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+ reg = <0x0 0xfe840000 0x0 0x100>;
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+ #phy-cells = <1>;
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+ assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
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+ assigned-clock-rates = <100000000>;
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+ clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>,
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+ <&cru PCLK_PIPE>;
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+ clock-names = "refclk", "apbclk", "pipe_clk";
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+ resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>;
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+ reset-names = "combphy-apb", "combphy";
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+ rockchip,pipe-grf = <&pipegrf>;
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+ rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
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+ status = "disabled";
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+ };
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+
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usb2phy0: usb2-phy@fe8a0000 {
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compatible = "rockchip,rk3568-usb2phy";
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reg = <0x0 0xfe8a0000 0x0 0x10000>;
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--
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2.35.3
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