165 lines
4.2 KiB
Diff
165 lines
4.2 KiB
Diff
From e05e45e853e2c278aec5165e37deaa1132aad196 Mon Sep 17 00:00:00 2001
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From: Levin Du <djw@t-chip.com.cn>
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Date: Fri, 9 Jul 2021 16:01:26 +0800
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Subject: [PATCH 008/478] arm64: dts: rockchip: add support for Firefly
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ROC-RK3328-PC
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ROC-RK3328-PC is the board inside the portable Firefly Station M1
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Geek PC. As a redesign after the ROC-RK3328-CC, it uses TypeC as
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power input and OTG port, embedded with eMMC 5.1 storage and a
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SDIO WiFi/BT chip (RTL8723DS).
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- Rockchip RK3328 SoC
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- 2/4GB LPDDR3 RAM
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- 16/32/64/128GB eMMC 5.1
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- TF card slot
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- USB 3.0 Port x 1, USB 2.0 Port x 1, TypeC Port x 1 (Power/OTG)
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- HDMI
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- Gigabit Ethernet
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- WiFi: RTL8723DS
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- Audio: RK3328
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- Key: Power, Reset, Recovery
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- LED: POWER, USER
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- IR
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Signed-off-by: Levin Du <djw@t-chip.com.cn>
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Link: https://lore.kernel.org/r/20210709080126.17045-3-djw@t-chip.com.cn
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/Makefile | 1 +
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.../arm64/boot/dts/rockchip/rk3328-roc-pc.dts | 110 ++++++++++++++++++
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2 files changed, 111 insertions(+)
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
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diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
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index 7fdb41de01ec..46652b6d7c4d 100644
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--- a/arch/arm64/boot/dts/rockchip/Makefile
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+++ b/arch/arm64/boot/dts/rockchip/Makefile
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@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
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new file mode 100644
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index 000000000000..e3e3984d01d4
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
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@@ -0,0 +1,110 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+// Copyright (c) 2021 T-Chip Intelligent Technology Co., Ltd
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/input/input.h>
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+
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+#include "rk3328-roc-cc.dts"
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+
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+/ {
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+ model = "Firefly ROC-RK3328-PC";
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+ compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328";
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+
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+ adc-keys {
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+ compatible = "adc-keys";
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+ io-channels = <&saradc 0>;
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+ io-channel-names = "buttons";
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+ keyup-threshold-microvolt = <1750000>;
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+
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+ /* This button is unpopulated out of the factory. */
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+ button-recovery {
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+ label = "Recovery";
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+ linux,code = <KEY_VENDOR>;
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+ press-threshold-microvolt = <10000>;
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+ };
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+ };
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+
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+ ir-receiver {
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+ compatible = "gpio-ir-receiver";
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+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
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+ linux,rc-map-name = "rc-khadas";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&ir_int>;
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+ };
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+
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+ sdio_pwrseq: sdio-pwrseq {
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+ compatible = "mmc-pwrseq-simple";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&wifi_en>, <&wifi_host_wake>;
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+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
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+ };
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+};
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+
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+&codec {
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+ mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
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+};
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+
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+&gpu {
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+ mali-supply = <&vdd_logic>;
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+};
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+
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+&pinctrl {
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+ ir {
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+ ir_int: ir-int {
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+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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+ sdmmcio {
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+ sdio_per_pin: sdio-per-pin {
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+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
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+ };
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+ };
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+
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+ wifi {
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+ wifi_en: wifi-en {
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+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+
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+ wifi_host_wake: wifi-host-wake {
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+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>;
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+ };
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+
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+ bt_rst: bt-rst {
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+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+
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+ bt_en: bt-en {
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+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+};
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+
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+&pmic_int_l {
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+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
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+};
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+
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+&rk805 {
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+ interrupt-parent = <&gpio0>;
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+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
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+};
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+
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+&saradc {
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+ vref-supply = <&vcc_18>;
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+ status = "okay";
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+};
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+
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+&usb20_host_drv {
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+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
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+};
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+
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+&vcc_host1_5v {
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+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
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+};
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+
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+&vcc_sdio {
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+ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&sdio_per_pin>;
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+};
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--
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2.35.3
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