92 lines
2.5 KiB
Diff
92 lines
2.5 KiB
Diff
From fc57d78344e1eb03c41f7b51b8d1f82f8db79121 Mon Sep 17 00:00:00 2001
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From: Michael Riesch <michael.riesch@wolfvision.net>
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Date: Thu, 29 Jul 2021 11:39:13 +0200
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Subject: [PATCH 036/478] arm64: dts: rockchip: rk3568-evb1-v10: add ethernet
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support
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Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
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Link: https://lore.kernel.org/r/20210729093913.8917-3-michael.riesch@wolfvision.net
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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.../boot/dts/rockchip/rk3568-evb1-v10.dts | 57 +++++++++++++++++++
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1 file changed, 57 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
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index 69786557093d..65e536c78d2e 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
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@@ -13,6 +13,11 @@ / {
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model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
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compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
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+ aliases {
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+ ethernet0 = &gmac0;
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+ ethernet1 = &gmac1;
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+ };
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+
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chosen: chosen {
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stdout-path = "serial2:1500000n8";
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};
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@@ -67,6 +72,58 @@ regulator-state-mem {
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};
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};
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+&gmac0 {
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+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
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+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
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+ assigned-clock-rates = <0>, <125000000>;
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+ clock_in_out = "output";
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+ phy-handle = <&rgmii_phy0>;
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+ phy-mode = "rgmii-id";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&gmac0_miim
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+ &gmac0_tx_bus2
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+ &gmac0_rx_bus2
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+ &gmac0_rgmii_clk
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+ &gmac0_rgmii_bus>;
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+ status = "okay";
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+};
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+
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+&gmac1 {
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+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
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+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
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+ assigned-clock-rates = <0>, <125000000>;
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+ clock_in_out = "output";
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+ phy-handle = <&rgmii_phy1>;
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+ phy-mode = "rgmii-id";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&gmac1m1_miim
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+ &gmac1m1_tx_bus2
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+ &gmac1m1_rx_bus2
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+ &gmac1m1_rgmii_clk
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+ &gmac1m1_rgmii_bus>;
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+ status = "okay";
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+};
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+
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+&mdio0 {
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+ rgmii_phy0: ethernet-phy@0 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <0x0>;
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+ reset-assert-us = <20000>;
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+ reset-deassert-us = <100000>;
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+ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
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+ };
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+};
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+
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+&mdio1 {
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+ rgmii_phy1: ethernet-phy@0 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <0x0>;
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+ reset-assert-us = <20000>;
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+ reset-deassert-us = <100000>;
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+ reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
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+ };
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+};
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+
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&sdhci {
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bus-width = <8>;
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max-frequency = <200000000>;
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--
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2.35.3
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