build/patch/kernel/archive/sunxi-5.15/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch

50 lines
1.7 KiB
Diff

From 4d53fb5f18ef04523972df9698069c0bcb47cda6 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Wed, 7 Oct 2020 02:11:35 +0200
Subject: [PATCH 316/478] clk: sunxi-ng: sun50i-a64: Switch parent of MIPI-DSI
to periph0(1x)
This makes video0(1x) clock less constrained, and improves compatibility
with external monitors on Pinephone when using both internal display
and HDMI output at once.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 03e8051e3452..a61d261135ed 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -950,6 +950,8 @@ static struct ccu_rate_reset_nb sun50i_a64_pll_video0_reset_tcon0_nb = {
.common = &pll_video0_clk.common,
};
+#define CCU_MIPI_DSI_CLK 0x168
+
static int sun50i_a64_ccu_probe(struct platform_device *pdev)
{
struct resource *res;
@@ -968,9 +970,16 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val);
- if (ret)
+ if (ret) {
writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
+ /* Set MIPI-DSI clock parent to periph0(1x), so that video0(1x) is free to change. */
+ val = readl(reg + CCU_MIPI_DSI_CLK);
+ val &= 0x30f;
+ val |= (2 << 8) | ((4 - 1) << 0); /* M-1 */
+ writel(val, reg + CCU_MIPI_DSI_CLK);
+ }
+
/* Force the parent of TCON0 to PLL-MIPI */
val = readl(reg + SUN50I_A64_TCON0_REG);
val &= ~GENMASK(26, 24);
--
2.35.3