645 lines
79 KiB
PHP
645 lines
79 KiB
PHP
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//===- TableGen'erated file -------------------------------------*- C++ -*-===//
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//
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// Target Instruction Descriptors
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//
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// Automatically generated file, do not edit!
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//
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//===----------------------------------------------------------------------===//
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namespace llvm {
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static const TargetRegisterClass* Barriers1[] = { &PPC::CARRYRCRegClass, NULL };
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static const unsigned ImplicitList1[] = { PPC::CARRY, 0 };
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static const unsigned ImplicitList2[] = { PPC::R1, 0 };
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static const unsigned ImplicitList3[] = { PPC::CR0, 0 };
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static const unsigned ImplicitList4[] = { PPC::CTR, 0 };
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static const unsigned ImplicitList5[] = { PPC::CTR8, PPC::RM, 0 };
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static const TargetRegisterClass* Barriers2[] = { &PPC::CARRYRCRegClass, &PPC::CTRRC8RegClass, NULL };
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static const unsigned ImplicitList6[] = { PPC::X0, PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CARRY, 0 };
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static const unsigned ImplicitList7[] = { PPC::CTR, PPC::RM, 0 };
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static const TargetRegisterClass* Barriers3[] = { &PPC::CARRYRCRegClass, &PPC::CTRRCRegClass, NULL };
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static const unsigned ImplicitList8[] = { PPC::R0, PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CARRY, 0 };
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static const unsigned ImplicitList9[] = { PPC::R0, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CARRY, 0 };
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static const unsigned ImplicitList10[] = { PPC::RM, 0 };
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static const unsigned ImplicitList11[] = { PPC::LR, PPC::RM, 0 };
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static const unsigned ImplicitList12[] = { PPC::X1, 0 };
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static const unsigned ImplicitList13[] = { PPC::CTR8, 0 };
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static const unsigned ImplicitList14[] = { PPC::LR, 0 };
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static const unsigned ImplicitList15[] = { PPC::LR8, 0 };
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static const TargetRegisterClass* Barriers4[] = { &PPC::CTRRCRegClass, NULL };
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static const TargetRegisterClass* Barriers5[] = { &PPC::CTRRC8RegClass, NULL };
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static const unsigned ImplicitList16[] = { PPC::CR6, 0 };
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static const TargetOperandInfo OperandInfo2[] = { { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo3[] = { { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo4[] = { { -1, 0, 0 }, { -1, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { -1, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo5[] = { { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo6[] = { { -1, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo7[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo8[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo9[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo10[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo11[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo12[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo13[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo14[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo15[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo16[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo17[] = { { -1, 0|(1<<TOI::Predicate), 0 }, { PPC::CRRCRegClassID, 0|(1<<TOI::Predicate), 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo18[] = { { -1, 0|(1<<TOI::Predicate), 0 }, { PPC::CRRCRegClassID, 0|(1<<TOI::Predicate), 0 }, };
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static const TargetOperandInfo OperandInfo19[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo20[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo21[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo22[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo23[] = { { PPC::CRBITRCRegClassID, 0, 0 }, { PPC::CRBITRCRegClassID, 0, 0 }, { PPC::CRBITRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo24[] = { { PPC::CRBITRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo25[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
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static const TargetOperandInfo OperandInfo26[] = { { -1, 0, 0 }, { -1, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo27[] = { { -1, 0, 0 }, { -1, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo28[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { -1, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
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static const TargetOperandInfo OperandInfo29[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { -1, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
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static const TargetOperandInfo OperandInfo30[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo31[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo32[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo33[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo34[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo35[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo36[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo37[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo38[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo39[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo40[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo41[] = { { PPC::GPRCRegClassID, 0, 0 }, { -1, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
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static const TargetOperandInfo OperandInfo42[] = { { PPC::G8RCRegClassID, 0, 0 }, { -1, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
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static const TargetOperandInfo OperandInfo43[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
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static const TargetOperandInfo OperandInfo44[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
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static const TargetOperandInfo OperandInfo45[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
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static const TargetOperandInfo OperandInfo46[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
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static const TargetOperandInfo OperandInfo47[] = { { PPC::G8RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo48[] = { { PPC::G8RCRegClassID, 0, 0 }, { -1, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo49[] = { { PPC::F8RCRegClassID, 0, 0 }, { -1, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
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static const TargetOperandInfo OperandInfo50[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
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static const TargetOperandInfo OperandInfo51[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
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static const TargetOperandInfo OperandInfo52[] = { { PPC::F4RCRegClassID, 0, 0 }, { -1, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
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static const TargetOperandInfo OperandInfo53[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { -1, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
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static const TargetOperandInfo OperandInfo54[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
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static const TargetOperandInfo OperandInfo55[] = { { PPC::GPRCRegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo56[] = { { PPC::G8RCRegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo57[] = { { PPC::VRRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
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static const TargetOperandInfo OperandInfo58[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo59[] = { { PPC::GPRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo60[] = { { PPC::F8RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo61[] = { { PPC::VRRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo62[] = { { -1, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo63[] = { { PPC::F8RCRegClassID, 0, 0 }, { -1, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
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static const TargetOperandInfo OperandInfo64[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo65[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo66[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo67[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo68[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { PPC::G8RCRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo69[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { PPC::GPRCRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo70[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo71[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { -1, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo72[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo73[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo74[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo75[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo76[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo77[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo78[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::GPRCRegClassID, 0, 0 }, { -1, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, };
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static const TargetOperandInfo OperandInfo79[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::G8RCRegClassID, 0, 0 }, { -1, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, };
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static const TargetOperandInfo OperandInfo80[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::F8RCRegClassID, 0, 0 }, { -1, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, };
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static const TargetOperandInfo OperandInfo81[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::F4RCRegClassID, 0, 0 }, { -1, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, };
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static const TargetOperandInfo OperandInfo82[] = { { PPC::CTRRCRegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo83[] = { { PPC::CTRRC8RegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo84[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo85[] = { { PPC::VRRCRegClassID, 0, 0 }, { -1, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo86[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, };
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static const TargetOperandInfo OperandInfo87[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, };
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||
|
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static const TargetOperandInfo OperandInfo88[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { -1, 0, 0 }, };
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static const TargetOperandInfo OperandInfo89[] = { { PPC::VRRCRegClassID, 0, 0 }, { -1, 0, 0 }, };
|
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|
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|
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static const TargetInstrDesc PPCInsts[] = {
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{ 0, 0, 0, 52, "PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, 0 }, // Inst #0 = PHI
|
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|
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{ 1, 0, 0, 52, "INLINEASM", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, 0 }, // Inst #1 = INLINEASM
|
||
|
|
{ 2, 1, 0, 52, "PROLOG_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo2 }, // Inst #2 = PROLOG_LABEL
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||
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{ 3, 1, 0, 52, "EH_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo2 }, // Inst #3 = EH_LABEL
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||
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|
{ 4, 1, 0, 52, "GC_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo2 }, // Inst #4 = GC_LABEL
|
||
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{ 5, 0, 0, 52, "KILL", 0|(1<<TID::Variadic), 0x0ULL, NULL, NULL, NULL, 0 }, // Inst #5 = KILL
|
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{ 6, 3, 1, 52, "EXTRACT_SUBREG", 0, 0x0ULL, NULL, NULL, NULL, OperandInfo3 }, // Inst #6 = EXTRACT_SUBREG
|
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{ 7, 4, 1, 52, "INSERT_SUBREG", 0, 0x0ULL, NULL, NULL, NULL, OperandInfo4 }, // Inst #7 = INSERT_SUBREG
|
||
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|
{ 8, 1, 1, 52, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0x0ULL, NULL, NULL, NULL, OperandInfo2 }, // Inst #8 = IMPLICIT_DEF
|
||
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{ 9, 4, 1, 52, "SUBREG_TO_REG", 0, 0x0ULL, NULL, NULL, NULL, OperandInfo5 }, // Inst #9 = SUBREG_TO_REG
|
||
|
|
{ 10, 3, 1, 52, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0x0ULL, NULL, NULL, NULL, OperandInfo3 }, // Inst #10 = COPY_TO_REGCLASS
|
||
|
|
{ 11, 0, 0, 52, "DBG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0x0ULL, NULL, NULL, NULL, 0 }, // Inst #11 = DBG_VALUE
|
||
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{ 12, 1, 1, 52, "REG_SEQUENCE", 0|(1<<TID::Variadic)|(1<<TID::CheapAsAMove), 0x0ULL, NULL, NULL, NULL, OperandInfo2 }, // Inst #12 = REG_SEQUENCE
|
||
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{ 13, 2, 1, 52, "COPY", 0|(1<<TID::CheapAsAMove), 0x0ULL, NULL, NULL, NULL, OperandInfo6 }, // Inst #13 = COPY
|
||
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|
{ 14, 3, 1, 14, "ADD4", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #14 = ADD4
|
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{ 15, 3, 1, 14, "ADD8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #15 = ADD8
|
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{ 16, 3, 1, 14, "ADDC", 0, 0xcULL, NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #16 = ADDC
|
||
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{ 17, 3, 1, 14, "ADDC8", 0, 0xcULL, NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #17 = ADDC8
|
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{ 18, 3, 1, 14, "ADDE", 0, 0x8ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #18 = ADDE
|
||
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{ 19, 3, 1, 14, "ADDE8", 0, 0x8ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #19 = ADDE8
|
||
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{ 20, 3, 1, 14, "ADDI", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo9 }, // Inst #20 = ADDI
|
||
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{ 21, 3, 1, 14, "ADDI8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo10 }, // Inst #21 = ADDI8
|
||
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{ 22, 3, 1, 14, "ADDIC", 0, 0xcULL, NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #22 = ADDIC
|
||
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{ 23, 3, 1, 14, "ADDIC8", 0, 0x8ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #23 = ADDIC8
|
||
|
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{ 24, 3, 1, 14, "ADDICo", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #24 = ADDICo
|
||
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|
{ 25, 3, 1, 14, "ADDIS", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo9 }, // Inst #25 = ADDIS
|
||
|
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{ 26, 3, 1, 14, "ADDIS8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo10 }, // Inst #26 = ADDIS8
|
||
|
|
{ 27, 2, 1, 14, "ADDME", 0, 0x8ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #27 = ADDME
|
||
|
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{ 28, 2, 1, 14, "ADDME8", 0, 0x8ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #28 = ADDME8
|
||
|
|
{ 29, 2, 1, 14, "ADDZE", 0, 0x8ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #29 = ADDZE
|
||
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{ 30, 2, 1, 14, "ADDZE8", 0, 0x8ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #30 = ADDZE8
|
||
|
|
{ 31, 1, 0, 52, "ADJCALLSTACKDOWN", 0, 0x0ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo2 }, // Inst #31 = ADJCALLSTACKDOWN
|
||
|
|
{ 32, 2, 0, 52, "ADJCALLSTACKUP", 0, 0x0ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo6 }, // Inst #32 = ADJCALLSTACKUP
|
||
|
|
{ 33, 3, 1, 14, "AND", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #33 = AND
|
||
|
|
{ 34, 3, 1, 14, "AND8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #34 = AND8
|
||
|
|
{ 35, 3, 1, 14, "ANDC", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #35 = ANDC
|
||
|
|
{ 36, 3, 1, 14, "ANDC8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #36 = ANDC8
|
||
|
|
{ 37, 3, 1, 14, "ANDISo", 0, 0x8ULL, NULL, ImplicitList3, NULL, OperandInfo9 }, // Inst #37 = ANDISo
|
||
|
|
{ 38, 3, 1, 14, "ANDISo8", 0, 0x8ULL, NULL, ImplicitList3, NULL, OperandInfo10 }, // Inst #38 = ANDISo8
|
||
|
|
{ 39, 3, 1, 14, "ANDIo", 0, 0x8ULL, NULL, ImplicitList3, NULL, OperandInfo9 }, // Inst #39 = ANDIo
|
||
|
|
{ 40, 3, 1, 14, "ANDIo8", 0, 0x8ULL, NULL, ImplicitList3, NULL, OperandInfo10 }, // Inst #40 = ANDIo8
|
||
|
|
{ 41, 5, 1, 52, "ATOMIC_CMP_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #41 = ATOMIC_CMP_SWAP_I16
|
||
|
|
{ 42, 5, 1, 52, "ATOMIC_CMP_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #42 = ATOMIC_CMP_SWAP_I32
|
||
|
|
{ 43, 5, 1, 52, "ATOMIC_CMP_SWAP_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo14 }, // Inst #43 = ATOMIC_CMP_SWAP_I64
|
||
|
|
{ 44, 5, 1, 52, "ATOMIC_CMP_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #44 = ATOMIC_CMP_SWAP_I8
|
||
|
|
{ 45, 4, 1, 52, "ATOMIC_LOAD_ADD_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #45 = ATOMIC_LOAD_ADD_I16
|
||
|
|
{ 46, 4, 1, 52, "ATOMIC_LOAD_ADD_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #46 = ATOMIC_LOAD_ADD_I32
|
||
|
|
{ 47, 4, 1, 52, "ATOMIC_LOAD_ADD_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo16 }, // Inst #47 = ATOMIC_LOAD_ADD_I64
|
||
|
|
{ 48, 4, 1, 52, "ATOMIC_LOAD_ADD_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #48 = ATOMIC_LOAD_ADD_I8
|
||
|
|
{ 49, 4, 1, 52, "ATOMIC_LOAD_AND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #49 = ATOMIC_LOAD_AND_I16
|
||
|
|
{ 50, 4, 1, 52, "ATOMIC_LOAD_AND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #50 = ATOMIC_LOAD_AND_I32
|
||
|
|
{ 51, 4, 1, 52, "ATOMIC_LOAD_AND_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo16 }, // Inst #51 = ATOMIC_LOAD_AND_I64
|
||
|
|
{ 52, 4, 1, 52, "ATOMIC_LOAD_AND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #52 = ATOMIC_LOAD_AND_I8
|
||
|
|
{ 53, 4, 1, 52, "ATOMIC_LOAD_NAND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #53 = ATOMIC_LOAD_NAND_I16
|
||
|
|
{ 54, 4, 1, 52, "ATOMIC_LOAD_NAND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #54 = ATOMIC_LOAD_NAND_I32
|
||
|
|
{ 55, 4, 1, 52, "ATOMIC_LOAD_NAND_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo16 }, // Inst #55 = ATOMIC_LOAD_NAND_I64
|
||
|
|
{ 56, 4, 1, 52, "ATOMIC_LOAD_NAND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #56 = ATOMIC_LOAD_NAND_I8
|
||
|
|
{ 57, 4, 1, 52, "ATOMIC_LOAD_OR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #57 = ATOMIC_LOAD_OR_I16
|
||
|
|
{ 58, 4, 1, 52, "ATOMIC_LOAD_OR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #58 = ATOMIC_LOAD_OR_I32
|
||
|
|
{ 59, 4, 1, 52, "ATOMIC_LOAD_OR_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo16 }, // Inst #59 = ATOMIC_LOAD_OR_I64
|
||
|
|
{ 60, 4, 1, 52, "ATOMIC_LOAD_OR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #60 = ATOMIC_LOAD_OR_I8
|
||
|
|
{ 61, 4, 1, 52, "ATOMIC_LOAD_SUB_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #61 = ATOMIC_LOAD_SUB_I16
|
||
|
|
{ 62, 4, 1, 52, "ATOMIC_LOAD_SUB_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #62 = ATOMIC_LOAD_SUB_I32
|
||
|
|
{ 63, 4, 1, 52, "ATOMIC_LOAD_SUB_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo16 }, // Inst #63 = ATOMIC_LOAD_SUB_I64
|
||
|
|
{ 64, 4, 1, 52, "ATOMIC_LOAD_SUB_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #64 = ATOMIC_LOAD_SUB_I8
|
||
|
|
{ 65, 4, 1, 52, "ATOMIC_LOAD_XOR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #65 = ATOMIC_LOAD_XOR_I16
|
||
|
|
{ 66, 4, 1, 52, "ATOMIC_LOAD_XOR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #66 = ATOMIC_LOAD_XOR_I32
|
||
|
|
{ 67, 4, 1, 52, "ATOMIC_LOAD_XOR_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo16 }, // Inst #67 = ATOMIC_LOAD_XOR_I64
|
||
|
|
{ 68, 4, 1, 52, "ATOMIC_LOAD_XOR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #68 = ATOMIC_LOAD_XOR_I8
|
||
|
|
{ 69, 4, 1, 52, "ATOMIC_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #69 = ATOMIC_SWAP_I16
|
||
|
|
{ 70, 4, 1, 52, "ATOMIC_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #70 = ATOMIC_SWAP_I32
|
||
|
|
{ 71, 4, 1, 52, "ATOMIC_SWAP_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo16 }, // Inst #71 = ATOMIC_SWAP_I64
|
||
|
|
{ 72, 4, 1, 52, "ATOMIC_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0x0ULL, ImplicitList3, NULL, NULL, OperandInfo15 }, // Inst #72 = ATOMIC_SWAP_I8
|
||
|
|
{ 73, 1, 0, 0, "B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0x38ULL, NULL, NULL, NULL, OperandInfo2 }, // Inst #73 = B
|
||
|
|
{ 74, 3, 0, 0, "BCC", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x38ULL, NULL, NULL, NULL, OperandInfo17 }, // Inst #74 = BCC
|
||
|
|
{ 75, 0, 0, 0, "BCTR", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x38ULL, ImplicitList4, NULL, NULL, 0 }, // Inst #75 = BCTR
|
||
|
|
{ 76, 0, 0, 0, "BCTRL8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0x38ULL, ImplicitList5, ImplicitList6, Barriers2, 0 }, // Inst #76 = BCTRL8_Darwin
|
||
|
|
{ 77, 0, 0, 0, "BCTRL8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic), 0x38ULL, ImplicitList5, ImplicitList6, Barriers2, 0 }, // Inst #77 = BCTRL8_ELF
|
||
|
|
{ 78, 0, 0, 0, "BCTRL_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0x38ULL, ImplicitList7, ImplicitList8, Barriers3, 0 }, // Inst #78 = BCTRL_Darwin
|
||
|
|
{ 79, 0, 0, 0, "BCTRL_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic), 0x38ULL, ImplicitList7, ImplicitList9, Barriers3, 0 }, // Inst #79 = BCTRL_SVR4
|
||
|
|
{ 80, 1, 0, 0, "BL8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, ImplicitList6, Barriers2, OperandInfo2 }, // Inst #80 = BL8_Darwin
|
||
|
|
{ 81, 1, 0, 0, "BL8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, ImplicitList6, Barriers2, OperandInfo2 }, // Inst #81 = BL8_ELF
|
||
|
|
{ 82, 1, 0, 0, "BLA8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0x38ULL, ImplicitList10, ImplicitList6, Barriers2, OperandInfo2 }, // Inst #82 = BLA8_Darwin
|
||
|
|
{ 83, 1, 0, 0, "BLA8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic), 0x38ULL, ImplicitList10, ImplicitList6, Barriers2, OperandInfo2 }, // Inst #83 = BLA8_ELF
|
||
|
|
{ 84, 1, 0, 0, "BLA_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0x38ULL, ImplicitList10, ImplicitList8, Barriers3, OperandInfo2 }, // Inst #84 = BLA_Darwin
|
||
|
|
{ 85, 1, 0, 0, "BLA_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic), 0x38ULL, ImplicitList10, ImplicitList9, Barriers3, OperandInfo2 }, // Inst #85 = BLA_SVR4
|
||
|
|
{ 86, 2, 0, 0, "BLR", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic), 0x38ULL, ImplicitList11, NULL, NULL, OperandInfo18 }, // Inst #86 = BLR
|
||
|
|
{ 87, 1, 0, 0, "BL_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, ImplicitList8, Barriers3, OperandInfo2 }, // Inst #87 = BL_Darwin
|
||
|
|
{ 88, 1, 0, 0, "BL_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, ImplicitList9, Barriers3, OperandInfo2 }, // Inst #88 = BL_SVR4
|
||
|
|
{ 89, 3, 1, 11, "CMPD", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo19 }, // Inst #89 = CMPD
|
||
|
|
{ 90, 3, 1, 11, "CMPDI", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo20 }, // Inst #90 = CMPDI
|
||
|
|
{ 91, 3, 1, 11, "CMPLD", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo19 }, // Inst #91 = CMPLD
|
||
|
|
{ 92, 3, 1, 11, "CMPLDI", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo20 }, // Inst #92 = CMPLDI
|
||
|
|
{ 93, 3, 1, 11, "CMPLW", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo21 }, // Inst #93 = CMPLW
|
||
|
|
{ 94, 3, 1, 11, "CMPLWI", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo22 }, // Inst #94 = CMPLWI
|
||
|
|
{ 95, 3, 1, 11, "CMPW", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo21 }, // Inst #95 = CMPW
|
||
|
|
{ 96, 3, 1, 11, "CMPWI", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo22 }, // Inst #96 = CMPWI
|
||
|
|
{ 97, 2, 1, 14, "CNTLZD", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo12 }, // Inst #97 = CNTLZD
|
||
|
|
{ 98, 2, 1, 14, "CNTLZW", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo11 }, // Inst #98 = CNTLZW
|
||
|
|
{ 99, 3, 1, 1, "CREQV", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo23 }, // Inst #99 = CREQV
|
||
|
|
{ 100, 3, 1, 1, "CROR", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo23 }, // Inst #100 = CROR
|
||
|
|
{ 101, 1, 1, 1, "CRSET", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo24 }, // Inst #101 = CRSET
|
||
|
|
{ 102, 2, 0, 30, "DCBA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x2ULL, NULL, NULL, NULL, OperandInfo25 }, // Inst #102 = DCBA
|
||
|
|
{ 103, 2, 0, 30, "DCBF", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x2ULL, NULL, NULL, NULL, OperandInfo25 }, // Inst #103 = DCBF
|
||
|
|
{ 104, 2, 0, 30, "DCBI", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x2ULL, NULL, NULL, NULL, OperandInfo25 }, // Inst #104 = DCBI
|
||
|
|
{ 105, 2, 0, 30, "DCBST", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x2ULL, NULL, NULL, NULL, OperandInfo25 }, // Inst #105 = DCBST
|
||
|
|
{ 106, 2, 0, 30, "DCBT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x2ULL, NULL, NULL, NULL, OperandInfo25 }, // Inst #106 = DCBT
|
||
|
|
{ 107, 2, 0, 30, "DCBTST", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x2ULL, NULL, NULL, NULL, OperandInfo25 }, // Inst #107 = DCBTST
|
||
|
|
{ 108, 2, 0, 30, "DCBZ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x2ULL, NULL, NULL, NULL, OperandInfo25 }, // Inst #108 = DCBZ
|
||
|
|
{ 109, 2, 0, 30, "DCBZL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x2ULL, NULL, NULL, NULL, OperandInfo25 }, // Inst #109 = DCBZL
|
||
|
|
{ 110, 3, 1, 12, "DIVD", 0, 0xdULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #110 = DIVD
|
||
|
|
{ 111, 3, 1, 12, "DIVDU", 0, 0xdULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #111 = DIVDU
|
||
|
|
{ 112, 3, 1, 13, "DIVW", 0, 0xdULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #112 = DIVW
|
||
|
|
{ 113, 3, 1, 13, "DIVWU", 0, 0xdULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #113 = DIVWU
|
||
|
|
{ 114, 4, 0, 33, "DSS", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo5 }, // Inst #114 = DSS
|
||
|
|
{ 115, 4, 0, 33, "DSSALL", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo5 }, // Inst #115 = DSSALL
|
||
|
|
{ 116, 4, 0, 33, "DST", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo26 }, // Inst #116 = DST
|
||
|
|
{ 117, 4, 0, 33, "DST64", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo27 }, // Inst #117 = DST64
|
||
|
|
{ 118, 4, 0, 33, "DSTST", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo26 }, // Inst #118 = DSTST
|
||
|
|
{ 119, 4, 0, 33, "DSTST64", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo27 }, // Inst #119 = DSTST64
|
||
|
|
{ 120, 4, 0, 33, "DSTSTT", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo26 }, // Inst #120 = DSTSTT
|
||
|
|
{ 121, 4, 0, 33, "DSTSTT64", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo27 }, // Inst #121 = DSTSTT64
|
||
|
|
{ 122, 4, 0, 33, "DSTT", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo26 }, // Inst #122 = DSTT
|
||
|
|
{ 123, 4, 0, 33, "DSTT64", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo27 }, // Inst #123 = DSTT64
|
||
|
|
{ 124, 4, 1, 52, "DYNALLOC", 0, 0x0ULL, ImplicitList2, ImplicitList2, NULL, OperandInfo28 }, // Inst #124 = DYNALLOC
|
||
|
|
{ 125, 4, 1, 52, "DYNALLOC8", 0, 0x0ULL, ImplicitList12, ImplicitList12, NULL, OperandInfo29 }, // Inst #125 = DYNALLOC8
|
||
|
|
{ 126, 3, 1, 14, "EQV", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #126 = EQV
|
||
|
|
{ 127, 3, 1, 14, "EQV8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #127 = EQV8
|
||
|
|
{ 128, 2, 1, 14, "EXTSB", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo11 }, // Inst #128 = EXTSB
|
||
|
|
{ 129, 2, 1, 14, "EXTSB8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo12 }, // Inst #129 = EXTSB8
|
||
|
|
{ 130, 2, 1, 14, "EXTSH", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo11 }, // Inst #130 = EXTSH
|
||
|
|
{ 131, 2, 1, 14, "EXTSH8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo12 }, // Inst #131 = EXTSH8
|
||
|
|
{ 132, 2, 1, 14, "EXTSW", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo12 }, // Inst #132 = EXTSW
|
||
|
|
{ 133, 2, 1, 14, "EXTSW_32", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo11 }, // Inst #133 = EXTSW_32
|
||
|
|
{ 134, 2, 1, 14, "EXTSW_32_64", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo30 }, // Inst #134 = EXTSW_32_64
|
||
|
|
{ 135, 2, 1, 8, "FABSD", 0, 0x18ULL, NULL, NULL, NULL, OperandInfo31 }, // Inst #135 = FABSD
|
||
|
|
{ 136, 2, 1, 8, "FABSS", 0, 0x18ULL, NULL, NULL, NULL, OperandInfo32 }, // Inst #136 = FABSS
|
||
|
|
{ 137, 3, 1, 8, "FADD", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #137 = FADD
|
||
|
|
{ 138, 3, 1, 8, "FADDS", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo34 }, // Inst #138 = FADDS
|
||
|
|
{ 139, 3, 1, 8, "FADDrtz", 0, 0x1aULL, ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #139 = FADDrtz
|
||
|
|
{ 140, 2, 1, 8, "FCFID", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo31 }, // Inst #140 = FCFID
|
||
|
|
{ 141, 3, 1, 4, "FCMPUD", 0|(1<<TID::UnmodeledSideEffects), 0x18ULL, NULL, NULL, NULL, OperandInfo35 }, // Inst #141 = FCMPUD
|
||
|
|
{ 142, 3, 1, 4, "FCMPUS", 0|(1<<TID::UnmodeledSideEffects), 0x18ULL, NULL, NULL, NULL, OperandInfo36 }, // Inst #142 = FCMPUS
|
||
|
|
{ 143, 2, 1, 8, "FCTIDZ", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo31 }, // Inst #143 = FCTIDZ
|
||
|
|
{ 144, 2, 1, 8, "FCTIWZ", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo31 }, // Inst #144 = FCTIWZ
|
||
|
|
{ 145, 3, 1, 5, "FDIV", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #145 = FDIV
|
||
|
|
{ 146, 3, 1, 6, "FDIVS", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo34 }, // Inst #146 = FDIVS
|
||
|
|
{ 147, 4, 1, 7, "FMADD", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #147 = FMADD
|
||
|
|
{ 148, 4, 1, 8, "FMADDS", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo38 }, // Inst #148 = FMADDS
|
||
|
|
{ 149, 2, 1, 8, "FMR", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo32 }, // Inst #149 = FMR
|
||
|
|
{ 150, 4, 1, 7, "FMSUB", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #150 = FMSUB
|
||
|
|
{ 151, 4, 1, 8, "FMSUBS", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo38 }, // Inst #151 = FMSUBS
|
||
|
|
{ 152, 3, 1, 7, "FMUL", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #152 = FMUL
|
||
|
|
{ 153, 3, 1, 8, "FMULS", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo34 }, // Inst #153 = FMULS
|
||
|
|
{ 154, 2, 1, 8, "FNABSD", 0, 0x18ULL, NULL, NULL, NULL, OperandInfo31 }, // Inst #154 = FNABSD
|
||
|
|
{ 155, 2, 1, 8, "FNABSS", 0, 0x18ULL, NULL, NULL, NULL, OperandInfo32 }, // Inst #155 = FNABSS
|
||
|
|
{ 156, 2, 1, 8, "FNEGD", 0, 0x18ULL, NULL, NULL, NULL, OperandInfo31 }, // Inst #156 = FNEGD
|
||
|
|
{ 157, 2, 1, 8, "FNEGS", 0, 0x18ULL, NULL, NULL, NULL, OperandInfo32 }, // Inst #157 = FNEGS
|
||
|
|
{ 158, 4, 1, 7, "FNMADD", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #158 = FNMADD
|
||
|
|
{ 159, 4, 1, 8, "FNMADDS", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo38 }, // Inst #159 = FNMADDS
|
||
|
|
{ 160, 4, 1, 7, "FNMSUB", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #160 = FNMSUB
|
||
|
|
{ 161, 4, 1, 8, "FNMSUBS", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo38 }, // Inst #161 = FNMSUBS
|
||
|
|
{ 162, 2, 1, 8, "FRSP", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo39 }, // Inst #162 = FRSP
|
||
|
|
{ 163, 4, 1, 8, "FSELD", 0, 0x18ULL, NULL, NULL, NULL, OperandInfo37 }, // Inst #163 = FSELD
|
||
|
|
{ 164, 4, 1, 8, "FSELS", 0, 0x18ULL, NULL, NULL, NULL, OperandInfo40 }, // Inst #164 = FSELS
|
||
|
|
{ 165, 2, 1, 10, "FSQRT", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo31 }, // Inst #165 = FSQRT
|
||
|
|
{ 166, 2, 1, 10, "FSQRTS", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #166 = FSQRTS
|
||
|
|
{ 167, 3, 1, 8, "FSUB", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #167 = FSUB
|
||
|
|
{ 168, 3, 1, 8, "FSUBS", 0, 0x18ULL, ImplicitList10, NULL, NULL, OperandInfo34 }, // Inst #168 = FSUBS
|
||
|
|
{ 169, 3, 1, 14, "LA", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo9 }, // Inst #169 = LA
|
||
|
|
{ 170, 3, 1, 33, "LBZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo41 }, // Inst #170 = LBZ
|
||
|
|
{ 171, 3, 1, 33, "LBZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo42 }, // Inst #171 = LBZ8
|
||
|
|
{ 172, 4, 2, 33, "LBZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo43 }, // Inst #172 = LBZU
|
||
|
|
{ 173, 4, 2, 33, "LBZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo44 }, // Inst #173 = LBZU8
|
||
|
|
{ 174, 3, 1, 33, "LBZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo45 }, // Inst #174 = LBZX
|
||
|
|
{ 175, 3, 1, 33, "LBZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo46 }, // Inst #175 = LBZX8
|
||
|
|
{ 176, 3, 1, 35, "LD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo42 }, // Inst #176 = LD
|
||
|
|
{ 177, 3, 1, 36, "LDARX", 0|(1<<TID::MayLoad), 0x0ULL, NULL, NULL, NULL, OperandInfo46 }, // Inst #177 = LDARX
|
||
|
|
{ 178, 4, 2, 35, "LDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo44 }, // Inst #178 = LDU
|
||
|
|
{ 179, 3, 1, 35, "LDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo46 }, // Inst #179 = LDX
|
||
|
|
{ 180, 1, 0, 35, "LDinto_toc", 0|(1<<TID::FoldableAsLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo47 }, // Inst #180 = LDinto_toc
|
||
|
|
{ 181, 3, 1, 35, "LDtoc", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo48 }, // Inst #181 = LDtoc
|
||
|
|
{ 182, 0, 0, 35, "LDtoc_restore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, 0 }, // Inst #182 = LDtoc_restore
|
||
|
|
{ 183, 3, 1, 37, "LFD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo49 }, // Inst #183 = LFD
|
||
|
|
{ 184, 4, 2, 37, "LFDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo50 }, // Inst #184 = LFDU
|
||
|
|
{ 185, 3, 1, 38, "LFDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo51 }, // Inst #185 = LFDX
|
||
|
|
{ 186, 3, 1, 38, "LFS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo52 }, // Inst #186 = LFS
|
||
|
|
{ 187, 4, 2, 38, "LFSU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo53 }, // Inst #187 = LFSU
|
||
|
|
{ 188, 3, 1, 38, "LFSX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo54 }, // Inst #188 = LFSX
|
||
|
|
{ 189, 3, 1, 39, "LHA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x14ULL, NULL, NULL, NULL, OperandInfo41 }, // Inst #189 = LHA
|
||
|
|
{ 190, 3, 1, 39, "LHA8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x14ULL, NULL, NULL, NULL, OperandInfo42 }, // Inst #190 = LHA8
|
||
|
|
{ 191, 4, 2, 33, "LHAU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo43 }, // Inst #191 = LHAU
|
||
|
|
{ 192, 4, 2, 33, "LHAU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo44 }, // Inst #192 = LHAU8
|
||
|
|
{ 193, 3, 1, 39, "LHAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x14ULL, NULL, NULL, NULL, OperandInfo45 }, // Inst #193 = LHAX
|
||
|
|
{ 194, 3, 1, 39, "LHAX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x14ULL, NULL, NULL, NULL, OperandInfo46 }, // Inst #194 = LHAX8
|
||
|
|
{ 195, 3, 1, 33, "LHBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo45 }, // Inst #195 = LHBRX
|
||
|
|
{ 196, 3, 1, 33, "LHZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo41 }, // Inst #196 = LHZ
|
||
|
|
{ 197, 3, 1, 33, "LHZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo42 }, // Inst #197 = LHZ8
|
||
|
|
{ 198, 4, 2, 33, "LHZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo43 }, // Inst #198 = LHZU
|
||
|
|
{ 199, 4, 2, 33, "LHZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo44 }, // Inst #199 = LHZU8
|
||
|
|
{ 200, 3, 1, 33, "LHZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo45 }, // Inst #200 = LHZX
|
||
|
|
{ 201, 3, 1, 33, "LHZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo46 }, // Inst #201 = LHZX8
|
||
|
|
{ 202, 2, 1, 14, "LI", 0|(1<<TID::Rematerializable), 0x8ULL, NULL, NULL, NULL, OperandInfo55 }, // Inst #202 = LI
|
||
|
|
{ 203, 2, 1, 14, "LI8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo56 }, // Inst #203 = LI8
|
||
|
|
{ 204, 2, 1, 14, "LIS", 0|(1<<TID::Rematerializable), 0x8ULL, NULL, NULL, NULL, OperandInfo55 }, // Inst #204 = LIS
|
||
|
|
{ 205, 2, 1, 14, "LIS8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo56 }, // Inst #205 = LIS8
|
||
|
|
{ 206, 3, 1, 33, "LVEBX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo57 }, // Inst #206 = LVEBX
|
||
|
|
{ 207, 3, 1, 33, "LVEHX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo57 }, // Inst #207 = LVEHX
|
||
|
|
{ 208, 3, 1, 33, "LVEWX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo57 }, // Inst #208 = LVEWX
|
||
|
|
{ 209, 3, 1, 33, "LVSL", 0, 0x10ULL, NULL, NULL, NULL, OperandInfo57 }, // Inst #209 = LVSL
|
||
|
|
{ 210, 3, 1, 33, "LVSR", 0, 0x10ULL, NULL, NULL, NULL, OperandInfo57 }, // Inst #210 = LVSR
|
||
|
|
{ 211, 3, 1, 33, "LVX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo57 }, // Inst #211 = LVX
|
||
|
|
{ 212, 3, 1, 33, "LVXL", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo57 }, // Inst #212 = LVXL
|
||
|
|
{ 213, 3, 1, 42, "LWA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x14ULL, NULL, NULL, NULL, OperandInfo42 }, // Inst #213 = LWA
|
||
|
|
{ 214, 3, 1, 43, "LWARX", 0|(1<<TID::MayLoad), 0x0ULL, NULL, NULL, NULL, OperandInfo45 }, // Inst #214 = LWARX
|
||
|
|
{ 215, 3, 1, 39, "LWAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x14ULL, NULL, NULL, NULL, OperandInfo46 }, // Inst #215 = LWAX
|
||
|
|
{ 216, 3, 1, 33, "LWBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo45 }, // Inst #216 = LWBRX
|
||
|
|
{ 217, 3, 1, 33, "LWZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo41 }, // Inst #217 = LWZ
|
||
|
|
{ 218, 3, 1, 33, "LWZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo42 }, // Inst #218 = LWZ8
|
||
|
|
{ 219, 4, 2, 33, "LWZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo43 }, // Inst #219 = LWZU
|
||
|
|
{ 220, 4, 2, 33, "LWZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo44 }, // Inst #220 = LWZU8
|
||
|
|
{ 221, 3, 1, 33, "LWZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo45 }, // Inst #221 = LWZX
|
||
|
|
{ 222, 3, 1, 33, "LWZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0x10ULL, NULL, NULL, NULL, OperandInfo46 }, // Inst #222 = LWZX8
|
||
|
|
{ 223, 2, 1, 2, "MCRF", 0|(1<<TID::UnmodeledSideEffects), 0x21ULL, NULL, NULL, NULL, OperandInfo58 }, // Inst #223 = MCRF
|
||
|
|
{ 224, 2, 1, 54, "MFCRpseud", 0|(1<<TID::UnmodeledSideEffects), 0x20ULL, NULL, NULL, NULL, OperandInfo55 }, // Inst #224 = MFCRpseud
|
||
|
|
{ 225, 1, 1, 56, "MFCTR", 0|(1<<TID::UnmodeledSideEffects), 0x9ULL, ImplicitList4, NULL, NULL, OperandInfo59 }, // Inst #225 = MFCTR
|
||
|
|
{ 226, 1, 1, 56, "MFCTR8", 0|(1<<TID::UnmodeledSideEffects), 0x9ULL, ImplicitList13, NULL, NULL, OperandInfo47 }, // Inst #226 = MFCTR8
|
||
|
|
{ 227, 1, 1, 15, "MFFS", 0, 0x1aULL, ImplicitList10, NULL, NULL, OperandInfo60 }, // Inst #227 = MFFS
|
||
|
|
{ 228, 1, 1, 56, "MFLR", 0|(1<<TID::UnmodeledSideEffects), 0x9ULL, ImplicitList14, NULL, NULL, OperandInfo59 }, // Inst #228 = MFLR
|
||
|
|
{ 229, 1, 1, 56, "MFLR8", 0|(1<<TID::UnmodeledSideEffects), 0x9ULL, ImplicitList15, NULL, NULL, OperandInfo47 }, // Inst #229 = MFLR8
|
||
|
|
{ 230, 2, 1, 54, "MFOCRF", 0|(1<<TID::UnmodeledSideEffects), 0x21ULL, NULL, NULL, NULL, OperandInfo55 }, // Inst #230 = MFOCRF
|
||
|
|
{ 231, 1, 1, 14, "MFVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0x9ULL, NULL, NULL, NULL, OperandInfo59 }, // Inst #231 = MFVRSAVE
|
||
|
|
{ 232, 1, 1, 33, "MFVSCR", 0|(1<<TID::MayLoad), 0x0ULL, NULL, NULL, NULL, OperandInfo61 }, // Inst #232 = MFVSCR
|
||
|
|
{ 233, 2, 0, 3, "MTCRF", 0|(1<<TID::UnmodeledSideEffects), 0x20ULL, NULL, NULL, NULL, OperandInfo62 }, // Inst #233 = MTCRF
|
||
|
|
{ 234, 1, 0, 60, "MTCTR", 0, 0x9ULL, NULL, ImplicitList4, Barriers4, OperandInfo59 }, // Inst #234 = MTCTR
|
||
|
|
{ 235, 1, 0, 60, "MTCTR8", 0, 0x9ULL, NULL, ImplicitList13, Barriers5, OperandInfo47 }, // Inst #235 = MTCTR8
|
||
|
|
{ 236, 1, 0, 17, "MTFSB0", 0, 0x1aULL, ImplicitList10, ImplicitList10, NULL, OperandInfo2 }, // Inst #236 = MTFSB0
|
||
|
|
{ 237, 1, 0, 17, "MTFSB1", 0, 0x1aULL, ImplicitList10, ImplicitList10, NULL, OperandInfo2 }, // Inst #237 = MTFSB1
|
||
|
|
{ 238, 4, 1, 17, "MTFSF", 0, 0x1aULL, ImplicitList10, ImplicitList10, NULL, OperandInfo63 }, // Inst #238 = MTFSF
|
||
|
|
{ 239, 1, 0, 60, "MTLR", 0|(1<<TID::UnmodeledSideEffects), 0x9ULL, NULL, ImplicitList14, NULL, OperandInfo59 }, // Inst #239 = MTLR
|
||
|
|
{ 240, 1, 0, 60, "MTLR8", 0|(1<<TID::UnmodeledSideEffects), 0x9ULL, NULL, ImplicitList15, NULL, OperandInfo47 }, // Inst #240 = MTLR8
|
||
|
|
{ 241, 1, 0, 14, "MTVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0xaULL, NULL, NULL, NULL, OperandInfo59 }, // Inst #241 = MTVRSAVE
|
||
|
|
{ 242, 1, 0, 33, "MTVSCR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo61 }, // Inst #242 = MTVSCR
|
||
|
|
{ 243, 3, 1, 20, "MULHD", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #243 = MULHD
|
||
|
|
{ 244, 3, 1, 21, "MULHDU", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #244 = MULHDU
|
||
|
|
{ 245, 3, 1, 20, "MULHW", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #245 = MULHW
|
||
|
|
{ 246, 3, 1, 21, "MULHWU", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #246 = MULHWU
|
||
|
|
{ 247, 3, 1, 19, "MULLD", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #247 = MULLD
|
||
|
|
{ 248, 3, 1, 22, "MULLI", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo9 }, // Inst #248 = MULLI
|
||
|
|
{ 249, 3, 1, 20, "MULLW", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #249 = MULLW
|
||
|
|
{ 250, 1, 0, 52, "MovePCtoLR", 0|(1<<TID::UnmodeledSideEffects), 0x38ULL, NULL, ImplicitList14, NULL, OperandInfo2 }, // Inst #250 = MovePCtoLR
|
||
|
|
{ 251, 1, 0, 52, "MovePCtoLR8", 0|(1<<TID::UnmodeledSideEffects), 0x38ULL, NULL, ImplicitList15, NULL, OperandInfo2 }, // Inst #251 = MovePCtoLR8
|
||
|
|
{ 252, 3, 1, 14, "NAND", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #252 = NAND
|
||
|
|
{ 253, 3, 1, 14, "NAND8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #253 = NAND8
|
||
|
|
{ 254, 2, 1, 14, "NEG", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo11 }, // Inst #254 = NEG
|
||
|
|
{ 255, 2, 1, 14, "NEG8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo12 }, // Inst #255 = NEG8
|
||
|
|
{ 256, 0, 0, 14, "NOP", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, 0 }, // Inst #256 = NOP
|
||
|
|
{ 257, 3, 1, 14, "NOR", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #257 = NOR
|
||
|
|
{ 258, 3, 1, 14, "NOR8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #258 = NOR8
|
||
|
|
{ 259, 3, 1, 14, "OR", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #259 = OR
|
||
|
|
{ 260, 3, 1, 14, "OR4To8", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo64 }, // Inst #260 = OR4To8
|
||
|
|
{ 261, 3, 1, 14, "OR8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #261 = OR8
|
||
|
|
{ 262, 3, 1, 14, "OR8To4", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo65 }, // Inst #262 = OR8To4
|
||
|
|
{ 263, 3, 1, 14, "ORC", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #263 = ORC
|
||
|
|
{ 264, 3, 1, 14, "ORC8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #264 = ORC8
|
||
|
|
{ 265, 3, 1, 14, "ORI", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo9 }, // Inst #265 = ORI
|
||
|
|
{ 266, 3, 1, 14, "ORI8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo10 }, // Inst #266 = ORI8
|
||
|
|
{ 267, 3, 1, 14, "ORIS", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo9 }, // Inst #267 = ORIS
|
||
|
|
{ 268, 3, 1, 14, "ORIS8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo10 }, // Inst #268 = ORIS8
|
||
|
|
{ 269, 4, 1, 25, "RLDCL", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo66 }, // Inst #269 = RLDCL
|
||
|
|
{ 270, 4, 1, 25, "RLDICL", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo67 }, // Inst #270 = RLDICL
|
||
|
|
{ 271, 4, 1, 25, "RLDICR", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo67 }, // Inst #271 = RLDICR
|
||
|
|
{ 272, 5, 1, 25, "RLDIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo68 }, // Inst #272 = RLDIMI
|
||
|
|
{ 273, 6, 1, 24, "RLWIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0xcULL, NULL, NULL, NULL, OperandInfo69 }, // Inst #273 = RLWIMI
|
||
|
|
{ 274, 5, 1, 14, "RLWINM", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo70 }, // Inst #274 = RLWINM
|
||
|
|
{ 275, 5, 1, 14, "RLWINMo", 0|(1<<TID::UnmodeledSideEffects), 0xcULL, NULL, ImplicitList3, NULL, OperandInfo70 }, // Inst #275 = RLWINMo
|
||
|
|
{ 276, 5, 1, 14, "RLWNM", 0|(1<<TID::UnmodeledSideEffects), 0x8ULL, NULL, NULL, NULL, OperandInfo71 }, // Inst #276 = RLWNM
|
||
|
|
{ 277, 5, 1, 52, "SELECT_CC_F4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0x2ULL, NULL, NULL, NULL, OperandInfo72 }, // Inst #277 = SELECT_CC_F4
|
||
|
|
{ 278, 5, 1, 52, "SELECT_CC_F8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0x2ULL, NULL, NULL, NULL, OperandInfo73 }, // Inst #278 = SELECT_CC_F8
|
||
|
|
{ 279, 5, 1, 52, "SELECT_CC_I4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0x2ULL, NULL, NULL, NULL, OperandInfo74 }, // Inst #279 = SELECT_CC_I4
|
||
|
|
{ 280, 5, 1, 52, "SELECT_CC_I8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0x2ULL, NULL, NULL, NULL, OperandInfo75 }, // Inst #280 = SELECT_CC_I8
|
||
|
|
{ 281, 5, 1, 52, "SELECT_CC_VRRC", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0x2ULL, NULL, NULL, NULL, OperandInfo76 }, // Inst #281 = SELECT_CC_VRRC
|
||
|
|
{ 282, 3, 1, 25, "SLD", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo77 }, // Inst #282 = SLD
|
||
|
|
{ 283, 3, 1, 14, "SLW", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #283 = SLW
|
||
|
|
{ 284, 3, 0, 52, "SPILL_CR", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo41 }, // Inst #284 = SPILL_CR
|
||
|
|
{ 285, 3, 1, 25, "SRAD", 0, 0x8ULL, NULL, ImplicitList1, Barriers1, OperandInfo77 }, // Inst #285 = SRAD
|
||
|
|
{ 286, 3, 1, 25, "SRADI", 0, 0x8ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #286 = SRADI
|
||
|
|
{ 287, 3, 1, 26, "SRAW", 0, 0x8ULL, NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #287 = SRAW
|
||
|
|
{ 288, 3, 1, 26, "SRAWI", 0, 0x8ULL, NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #288 = SRAWI
|
||
|
|
{ 289, 3, 1, 25, "SRD", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo77 }, // Inst #289 = SRD
|
||
|
|
{ 290, 3, 1, 14, "SRW", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #290 = SRW
|
||
|
|
{ 291, 3, 0, 33, "STB", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo41 }, // Inst #291 = STB
|
||
|
|
{ 292, 3, 0, 33, "STB8", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo42 }, // Inst #292 = STB8
|
||
|
|
{ 293, 4, 1, 33, "STBU", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo78 }, // Inst #293 = STBU
|
||
|
|
{ 294, 4, 1, 33, "STBU8", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo79 }, // Inst #294 = STBU8
|
||
|
|
{ 295, 3, 0, 33, "STBX", 0|(1<<TID::MayStore), 0x14ULL, NULL, NULL, NULL, OperandInfo45 }, // Inst #295 = STBX
|
||
|
|
{ 296, 3, 0, 33, "STBX8", 0|(1<<TID::MayStore), 0x14ULL, NULL, NULL, NULL, OperandInfo46 }, // Inst #296 = STBX8
|
||
|
|
{ 297, 3, 0, 46, "STD", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo42 }, // Inst #297 = STD
|
||
|
|
{ 298, 3, 0, 47, "STDCX", 0|(1<<TID::MayStore), 0x0ULL, NULL, ImplicitList3, NULL, OperandInfo46 }, // Inst #298 = STDCX
|
||
|
|
{ 299, 4, 1, 46, "STDU", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo79 }, // Inst #299 = STDU
|
||
|
|
{ 300, 3, 0, 46, "STDUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo46 }, // Inst #300 = STDUX
|
||
|
|
{ 301, 3, 0, 46, "STDX", 0|(1<<TID::MayStore), 0x14ULL, NULL, NULL, NULL, OperandInfo46 }, // Inst #301 = STDX
|
||
|
|
{ 302, 3, 0, 46, "STDX_32", 0|(1<<TID::MayStore), 0x14ULL, NULL, NULL, NULL, OperandInfo45 }, // Inst #302 = STDX_32
|
||
|
|
{ 303, 3, 0, 46, "STD_32", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo41 }, // Inst #303 = STD_32
|
||
|
|
{ 304, 3, 0, 51, "STFD", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo49 }, // Inst #304 = STFD
|
||
|
|
{ 305, 4, 1, 33, "STFDU", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo80 }, // Inst #305 = STFDU
|
||
|
|
{ 306, 3, 0, 51, "STFDX", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo51 }, // Inst #306 = STFDX
|
||
|
|
{ 307, 3, 0, 51, "STFIWX", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo51 }, // Inst #307 = STFIWX
|
||
|
|
{ 308, 3, 0, 51, "STFS", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo52 }, // Inst #308 = STFS
|
||
|
|
{ 309, 4, 1, 33, "STFSU", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo81 }, // Inst #309 = STFSU
|
||
|
|
{ 310, 3, 0, 51, "STFSX", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo54 }, // Inst #310 = STFSX
|
||
|
|
{ 311, 3, 0, 33, "STH", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo41 }, // Inst #311 = STH
|
||
|
|
{ 312, 3, 0, 33, "STH8", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo42 }, // Inst #312 = STH8
|
||
|
|
{ 313, 3, 0, 33, "STHBRX", 0|(1<<TID::MayStore), 0x14ULL, NULL, NULL, NULL, OperandInfo45 }, // Inst #313 = STHBRX
|
||
|
|
{ 314, 4, 1, 33, "STHU", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo78 }, // Inst #314 = STHU
|
||
|
|
{ 315, 4, 1, 33, "STHU8", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo79 }, // Inst #315 = STHU8
|
||
|
|
{ 316, 3, 0, 33, "STHX", 0|(1<<TID::MayStore), 0x14ULL, NULL, NULL, NULL, OperandInfo45 }, // Inst #316 = STHX
|
||
|
|
{ 317, 3, 0, 33, "STHX8", 0|(1<<TID::MayStore), 0x14ULL, NULL, NULL, NULL, OperandInfo46 }, // Inst #317 = STHX8
|
||
|
|
{ 318, 3, 0, 33, "STVEBX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo57 }, // Inst #318 = STVEBX
|
||
|
|
{ 319, 3, 0, 33, "STVEHX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo57 }, // Inst #319 = STVEHX
|
||
|
|
{ 320, 3, 0, 33, "STVEWX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo57 }, // Inst #320 = STVEWX
|
||
|
|
{ 321, 3, 0, 33, "STVX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo57 }, // Inst #321 = STVX
|
||
|
|
{ 322, 3, 0, 33, "STVXL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo57 }, // Inst #322 = STVXL
|
||
|
|
{ 323, 3, 0, 33, "STW", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo41 }, // Inst #323 = STW
|
||
|
|
{ 324, 3, 0, 33, "STW8", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo42 }, // Inst #324 = STW8
|
||
|
|
{ 325, 3, 0, 33, "STWBRX", 0|(1<<TID::MayStore), 0x14ULL, NULL, NULL, NULL, OperandInfo45 }, // Inst #325 = STWBRX
|
||
|
|
{ 326, 3, 0, 49, "STWCX", 0|(1<<TID::MayStore), 0x0ULL, NULL, ImplicitList3, NULL, OperandInfo45 }, // Inst #326 = STWCX
|
||
|
|
{ 327, 4, 1, 33, "STWU", 0|(1<<TID::MayStore), 0x10ULL, NULL, NULL, NULL, OperandInfo78 }, // Inst #327 = STWU
|
||
|
|
{ 328, 3, 0, 33, "STWUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x10ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #328 = STWUX
|
||
|
|
{ 329, 3, 0, 33, "STWX", 0|(1<<TID::MayStore), 0x14ULL, NULL, NULL, NULL, OperandInfo45 }, // Inst #329 = STWX
|
||
|
|
{ 330, 3, 0, 33, "STWX8", 0|(1<<TID::MayStore), 0x14ULL, NULL, NULL, NULL, OperandInfo46 }, // Inst #330 = STWX8
|
||
|
|
{ 331, 3, 1, 14, "SUBF", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #331 = SUBF
|
||
|
|
{ 332, 3, 1, 14, "SUBF8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #332 = SUBF8
|
||
|
|
{ 333, 3, 1, 14, "SUBFC", 0, 0xcULL, NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #333 = SUBFC
|
||
|
|
{ 334, 3, 1, 14, "SUBFC8", 0, 0xcULL, NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #334 = SUBFC8
|
||
|
|
{ 335, 3, 1, 14, "SUBFE", 0, 0x8ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #335 = SUBFE
|
||
|
|
{ 336, 3, 1, 14, "SUBFE8", 0, 0x8ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #336 = SUBFE8
|
||
|
|
{ 337, 3, 1, 14, "SUBFIC", 0, 0x8ULL, NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #337 = SUBFIC
|
||
|
|
{ 338, 3, 1, 14, "SUBFIC8", 0, 0x8ULL, NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #338 = SUBFIC8
|
||
|
|
{ 339, 2, 1, 14, "SUBFME", 0, 0x8ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #339 = SUBFME
|
||
|
|
{ 340, 2, 1, 14, "SUBFME8", 0, 0x8ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #340 = SUBFME8
|
||
|
|
{ 341, 2, 1, 14, "SUBFZE", 0, 0x8ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #341 = SUBFZE
|
||
|
|
{ 342, 2, 1, 14, "SUBFZE8", 0, 0x8ULL, ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #342 = SUBFZE8
|
||
|
|
{ 343, 0, 0, 50, "SYNC", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, 0 }, // Inst #343 = SYNC
|
||
|
|
{ 344, 1, 0, 0, "TAILB", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, NULL, NULL, OperandInfo2 }, // Inst #344 = TAILB
|
||
|
|
{ 345, 1, 0, 0, "TAILB8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, NULL, NULL, OperandInfo2 }, // Inst #345 = TAILB8
|
||
|
|
{ 346, 1, 0, 0, "TAILBA", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, NULL, NULL, OperandInfo2 }, // Inst #346 = TAILBA
|
||
|
|
{ 347, 1, 0, 0, "TAILBA8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, NULL, NULL, OperandInfo2 }, // Inst #347 = TAILBA8
|
||
|
|
{ 348, 0, 0, 0, "TAILBCTR", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, NULL, NULL, 0 }, // Inst #348 = TAILBCTR
|
||
|
|
{ 349, 0, 0, 0, "TAILBCTR8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, NULL, NULL, 0 }, // Inst #349 = TAILBCTR8
|
||
|
|
{ 350, 2, 0, 52, "TCRETURNai", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0x0ULL, ImplicitList10, NULL, NULL, OperandInfo6 }, // Inst #350 = TCRETURNai
|
||
|
|
{ 351, 2, 0, 52, "TCRETURNai8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0x0ULL, ImplicitList10, NULL, NULL, OperandInfo6 }, // Inst #351 = TCRETURNai8
|
||
|
|
{ 352, 2, 0, 52, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, NULL, NULL, OperandInfo6 }, // Inst #352 = TCRETURNdi
|
||
|
|
{ 353, 2, 0, 52, "TCRETURNdi8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, NULL, NULL, OperandInfo6 }, // Inst #353 = TCRETURNdi8
|
||
|
|
{ 354, 2, 0, 52, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, NULL, NULL, OperandInfo82 }, // Inst #354 = TCRETURNri
|
||
|
|
{ 355, 2, 0, 52, "TCRETURNri8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, NULL, NULL, OperandInfo83 }, // Inst #355 = TCRETURNri8
|
||
|
|
{ 356, 0, 0, 33, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, 0 }, // Inst #356 = TRAP
|
||
|
|
{ 357, 2, 1, 52, "UPDATE_VRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, NULL, OperandInfo11 }, // Inst #357 = UPDATE_VRSAVE
|
||
|
|
{ 358, 3, 1, 67, "VADDCUW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #358 = VADDCUW
|
||
|
|
{ 359, 3, 1, 67, "VADDFP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #359 = VADDFP
|
||
|
|
{ 360, 3, 1, 67, "VADDSBS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #360 = VADDSBS
|
||
|
|
{ 361, 3, 1, 67, "VADDSHS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #361 = VADDSHS
|
||
|
|
{ 362, 3, 1, 67, "VADDSWS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #362 = VADDSWS
|
||
|
|
{ 363, 3, 1, 70, "VADDUBM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #363 = VADDUBM
|
||
|
|
{ 364, 3, 1, 67, "VADDUBS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #364 = VADDUBS
|
||
|
|
{ 365, 3, 1, 70, "VADDUHM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #365 = VADDUHM
|
||
|
|
{ 366, 3, 1, 67, "VADDUHS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #366 = VADDUHS
|
||
|
|
{ 367, 3, 1, 70, "VADDUWM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #367 = VADDUWM
|
||
|
|
{ 368, 3, 1, 67, "VADDUWS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #368 = VADDUWS
|
||
|
|
{ 369, 3, 1, 67, "VAND", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #369 = VAND
|
||
|
|
{ 370, 3, 1, 67, "VANDC", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #370 = VANDC
|
||
|
|
{ 371, 3, 1, 67, "VAVGSB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #371 = VAVGSB
|
||
|
|
{ 372, 3, 1, 67, "VAVGSH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #372 = VAVGSH
|
||
|
|
{ 373, 3, 1, 67, "VAVGSW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #373 = VAVGSW
|
||
|
|
{ 374, 3, 1, 67, "VAVGUB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #374 = VAVGUB
|
||
|
|
{ 375, 3, 1, 67, "VAVGUH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #375 = VAVGUH
|
||
|
|
{ 376, 3, 1, 67, "VAVGUW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #376 = VAVGUW
|
||
|
|
{ 377, 3, 1, 67, "VCFSX", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo85 }, // Inst #377 = VCFSX
|
||
|
|
{ 378, 3, 1, 67, "VCFUX", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo85 }, // Inst #378 = VCFUX
|
||
|
|
{ 379, 3, 1, 68, "VCMPBFP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #379 = VCMPBFP
|
||
|
|
{ 380, 3, 1, 68, "VCMPBFPo", 0, 0x28ULL, NULL, ImplicitList16, NULL, OperandInfo84 }, // Inst #380 = VCMPBFPo
|
||
|
|
{ 381, 3, 1, 68, "VCMPEQFP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #381 = VCMPEQFP
|
||
|
|
{ 382, 3, 1, 68, "VCMPEQFPo", 0, 0x28ULL, NULL, ImplicitList16, NULL, OperandInfo84 }, // Inst #382 = VCMPEQFPo
|
||
|
|
{ 383, 3, 1, 68, "VCMPEQUB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #383 = VCMPEQUB
|
||
|
|
{ 384, 3, 1, 68, "VCMPEQUBo", 0, 0x28ULL, NULL, ImplicitList16, NULL, OperandInfo84 }, // Inst #384 = VCMPEQUBo
|
||
|
|
{ 385, 3, 1, 68, "VCMPEQUH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #385 = VCMPEQUH
|
||
|
|
{ 386, 3, 1, 68, "VCMPEQUHo", 0, 0x28ULL, NULL, ImplicitList16, NULL, OperandInfo84 }, // Inst #386 = VCMPEQUHo
|
||
|
|
{ 387, 3, 1, 68, "VCMPEQUW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #387 = VCMPEQUW
|
||
|
|
{ 388, 3, 1, 68, "VCMPEQUWo", 0, 0x28ULL, NULL, ImplicitList16, NULL, OperandInfo84 }, // Inst #388 = VCMPEQUWo
|
||
|
|
{ 389, 3, 1, 68, "VCMPGEFP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #389 = VCMPGEFP
|
||
|
|
{ 390, 3, 1, 68, "VCMPGEFPo", 0, 0x28ULL, NULL, ImplicitList16, NULL, OperandInfo84 }, // Inst #390 = VCMPGEFPo
|
||
|
|
{ 391, 3, 1, 68, "VCMPGTFP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #391 = VCMPGTFP
|
||
|
|
{ 392, 3, 1, 68, "VCMPGTFPo", 0, 0x28ULL, NULL, ImplicitList16, NULL, OperandInfo84 }, // Inst #392 = VCMPGTFPo
|
||
|
|
{ 393, 3, 1, 68, "VCMPGTSB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #393 = VCMPGTSB
|
||
|
|
{ 394, 3, 1, 68, "VCMPGTSBo", 0, 0x28ULL, NULL, ImplicitList16, NULL, OperandInfo84 }, // Inst #394 = VCMPGTSBo
|
||
|
|
{ 395, 3, 1, 68, "VCMPGTSH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #395 = VCMPGTSH
|
||
|
|
{ 396, 3, 1, 68, "VCMPGTSHo", 0, 0x28ULL, NULL, ImplicitList16, NULL, OperandInfo84 }, // Inst #396 = VCMPGTSHo
|
||
|
|
{ 397, 3, 1, 68, "VCMPGTSW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #397 = VCMPGTSW
|
||
|
|
{ 398, 3, 1, 68, "VCMPGTSWo", 0, 0x28ULL, NULL, ImplicitList16, NULL, OperandInfo84 }, // Inst #398 = VCMPGTSWo
|
||
|
|
{ 399, 3, 1, 68, "VCMPGTUB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #399 = VCMPGTUB
|
||
|
|
{ 400, 3, 1, 68, "VCMPGTUBo", 0, 0x28ULL, NULL, ImplicitList16, NULL, OperandInfo84 }, // Inst #400 = VCMPGTUBo
|
||
|
|
{ 401, 3, 1, 68, "VCMPGTUH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #401 = VCMPGTUH
|
||
|
|
{ 402, 3, 1, 68, "VCMPGTUHo", 0, 0x28ULL, NULL, ImplicitList16, NULL, OperandInfo84 }, // Inst #402 = VCMPGTUHo
|
||
|
|
{ 403, 3, 1, 68, "VCMPGTUW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #403 = VCMPGTUW
|
||
|
|
{ 404, 3, 1, 68, "VCMPGTUWo", 0, 0x28ULL, NULL, ImplicitList16, NULL, OperandInfo84 }, // Inst #404 = VCMPGTUWo
|
||
|
|
{ 405, 3, 1, 67, "VCTSXS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo85 }, // Inst #405 = VCTSXS
|
||
|
|
{ 406, 3, 1, 67, "VCTUXS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo85 }, // Inst #406 = VCTUXS
|
||
|
|
{ 407, 2, 1, 67, "VEXPTEFP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo86 }, // Inst #407 = VEXPTEFP
|
||
|
|
{ 408, 2, 1, 67, "VLOGEFP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo86 }, // Inst #408 = VLOGEFP
|
||
|
|
{ 409, 4, 1, 67, "VMADDFP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo87 }, // Inst #409 = VMADDFP
|
||
|
|
{ 410, 3, 1, 67, "VMAXFP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #410 = VMAXFP
|
||
|
|
{ 411, 3, 1, 67, "VMAXSB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #411 = VMAXSB
|
||
|
|
{ 412, 3, 1, 67, "VMAXSH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #412 = VMAXSH
|
||
|
|
{ 413, 3, 1, 67, "VMAXSW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #413 = VMAXSW
|
||
|
|
{ 414, 3, 1, 67, "VMAXUB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #414 = VMAXUB
|
||
|
|
{ 415, 3, 1, 67, "VMAXUH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #415 = VMAXUH
|
||
|
|
{ 416, 3, 1, 67, "VMAXUW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #416 = VMAXUW
|
||
|
|
{ 417, 4, 1, 67, "VMHADDSHS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo87 }, // Inst #417 = VMHADDSHS
|
||
|
|
{ 418, 4, 1, 67, "VMHRADDSHS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo87 }, // Inst #418 = VMHRADDSHS
|
||
|
|
{ 419, 3, 1, 67, "VMINFP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #419 = VMINFP
|
||
|
|
{ 420, 3, 1, 67, "VMINSB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #420 = VMINSB
|
||
|
|
{ 421, 3, 1, 67, "VMINSH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #421 = VMINSH
|
||
|
|
{ 422, 3, 1, 67, "VMINSW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #422 = VMINSW
|
||
|
|
{ 423, 3, 1, 67, "VMINUB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #423 = VMINUB
|
||
|
|
{ 424, 3, 1, 67, "VMINUH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #424 = VMINUH
|
||
|
|
{ 425, 3, 1, 67, "VMINUW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #425 = VMINUW
|
||
|
|
{ 426, 4, 1, 67, "VMLADDUHM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo87 }, // Inst #426 = VMLADDUHM
|
||
|
|
{ 427, 3, 1, 67, "VMRGHB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #427 = VMRGHB
|
||
|
|
{ 428, 3, 1, 67, "VMRGHH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #428 = VMRGHH
|
||
|
|
{ 429, 3, 1, 67, "VMRGHW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #429 = VMRGHW
|
||
|
|
{ 430, 3, 1, 67, "VMRGLB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #430 = VMRGLB
|
||
|
|
{ 431, 3, 1, 67, "VMRGLH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #431 = VMRGLH
|
||
|
|
{ 432, 3, 1, 67, "VMRGLW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #432 = VMRGLW
|
||
|
|
{ 433, 4, 1, 67, "VMSUMMBM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo87 }, // Inst #433 = VMSUMMBM
|
||
|
|
{ 434, 4, 1, 67, "VMSUMSHM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo87 }, // Inst #434 = VMSUMSHM
|
||
|
|
{ 435, 4, 1, 67, "VMSUMSHS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo87 }, // Inst #435 = VMSUMSHS
|
||
|
|
{ 436, 4, 1, 67, "VMSUMUBM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo87 }, // Inst #436 = VMSUMUBM
|
||
|
|
{ 437, 4, 1, 67, "VMSUMUHM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo87 }, // Inst #437 = VMSUMUHM
|
||
|
|
{ 438, 4, 1, 67, "VMSUMUHS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo87 }, // Inst #438 = VMSUMUHS
|
||
|
|
{ 439, 3, 1, 67, "VMULESB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #439 = VMULESB
|
||
|
|
{ 440, 3, 1, 67, "VMULESH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #440 = VMULESH
|
||
|
|
{ 441, 3, 1, 67, "VMULEUB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #441 = VMULEUB
|
||
|
|
{ 442, 3, 1, 67, "VMULEUH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #442 = VMULEUH
|
||
|
|
{ 443, 3, 1, 67, "VMULOSB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #443 = VMULOSB
|
||
|
|
{ 444, 3, 1, 67, "VMULOSH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #444 = VMULOSH
|
||
|
|
{ 445, 3, 1, 67, "VMULOUB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #445 = VMULOUB
|
||
|
|
{ 446, 3, 1, 67, "VMULOUH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #446 = VMULOUH
|
||
|
|
{ 447, 4, 1, 67, "VNMSUBFP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo87 }, // Inst #447 = VNMSUBFP
|
||
|
|
{ 448, 3, 1, 67, "VNOR", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #448 = VNOR
|
||
|
|
{ 449, 3, 1, 67, "VOR", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #449 = VOR
|
||
|
|
{ 450, 4, 1, 67, "VPERM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo87 }, // Inst #450 = VPERM
|
||
|
|
{ 451, 3, 1, 67, "VPKPX", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #451 = VPKPX
|
||
|
|
{ 452, 3, 1, 67, "VPKSHSS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #452 = VPKSHSS
|
||
|
|
{ 453, 3, 1, 67, "VPKSHUS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #453 = VPKSHUS
|
||
|
|
{ 454, 3, 1, 67, "VPKSWSS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #454 = VPKSWSS
|
||
|
|
{ 455, 3, 1, 67, "VPKSWUS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #455 = VPKSWUS
|
||
|
|
{ 456, 3, 1, 67, "VPKUHUM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #456 = VPKUHUM
|
||
|
|
{ 457, 3, 1, 67, "VPKUHUS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #457 = VPKUHUS
|
||
|
|
{ 458, 3, 1, 67, "VPKUWUM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #458 = VPKUWUM
|
||
|
|
{ 459, 3, 1, 67, "VPKUWUS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #459 = VPKUWUS
|
||
|
|
{ 460, 2, 1, 67, "VREFP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo86 }, // Inst #460 = VREFP
|
||
|
|
{ 461, 2, 1, 67, "VRFIM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo86 }, // Inst #461 = VRFIM
|
||
|
|
{ 462, 2, 1, 67, "VRFIN", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo86 }, // Inst #462 = VRFIN
|
||
|
|
{ 463, 2, 1, 67, "VRFIP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo86 }, // Inst #463 = VRFIP
|
||
|
|
{ 464, 2, 1, 67, "VRFIZ", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo86 }, // Inst #464 = VRFIZ
|
||
|
|
{ 465, 3, 1, 67, "VRLB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #465 = VRLB
|
||
|
|
{ 466, 3, 1, 67, "VRLH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #466 = VRLH
|
||
|
|
{ 467, 3, 1, 67, "VRLW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #467 = VRLW
|
||
|
|
{ 468, 2, 1, 67, "VRSQRTEFP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo86 }, // Inst #468 = VRSQRTEFP
|
||
|
|
{ 469, 4, 1, 67, "VSEL", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo87 }, // Inst #469 = VSEL
|
||
|
|
{ 470, 3, 1, 67, "VSL", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #470 = VSL
|
||
|
|
{ 471, 3, 1, 67, "VSLB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #471 = VSLB
|
||
|
|
{ 472, 4, 1, 67, "VSLDOI", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo88 }, // Inst #472 = VSLDOI
|
||
|
|
{ 473, 3, 1, 67, "VSLH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #473 = VSLH
|
||
|
|
{ 474, 3, 1, 67, "VSLO", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #474 = VSLO
|
||
|
|
{ 475, 3, 1, 67, "VSLW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #475 = VSLW
|
||
|
|
{ 476, 3, 1, 71, "VSPLTB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo85 }, // Inst #476 = VSPLTB
|
||
|
|
{ 477, 3, 1, 71, "VSPLTH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo85 }, // Inst #477 = VSPLTH
|
||
|
|
{ 478, 2, 1, 71, "VSPLTISB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo89 }, // Inst #478 = VSPLTISB
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{ 479, 2, 1, 71, "VSPLTISH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo89 }, // Inst #479 = VSPLTISH
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{ 480, 2, 1, 71, "VSPLTISW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo89 }, // Inst #480 = VSPLTISW
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{ 481, 3, 1, 71, "VSPLTW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo85 }, // Inst #481 = VSPLTW
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{ 482, 3, 1, 67, "VSR", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #482 = VSR
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{ 483, 3, 1, 67, "VSRAB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #483 = VSRAB
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{ 484, 3, 1, 67, "VSRAH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #484 = VSRAH
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{ 485, 3, 1, 67, "VSRAW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #485 = VSRAW
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{ 486, 3, 1, 67, "VSRB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #486 = VSRB
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{ 487, 3, 1, 67, "VSRH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #487 = VSRH
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{ 488, 3, 1, 67, "VSRO", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #488 = VSRO
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{ 489, 3, 1, 67, "VSRW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #489 = VSRW
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{ 490, 3, 1, 67, "VSUBCUW", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #490 = VSUBCUW
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||
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{ 491, 3, 1, 70, "VSUBFP", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #491 = VSUBFP
|
||
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{ 492, 3, 1, 67, "VSUBSBS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #492 = VSUBSBS
|
||
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{ 493, 3, 1, 67, "VSUBSHS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #493 = VSUBSHS
|
||
|
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{ 494, 3, 1, 67, "VSUBSWS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #494 = VSUBSWS
|
||
|
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{ 495, 3, 1, 70, "VSUBUBM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #495 = VSUBUBM
|
||
|
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{ 496, 3, 1, 67, "VSUBUBS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #496 = VSUBUBS
|
||
|
|
{ 497, 3, 1, 70, "VSUBUHM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #497 = VSUBUHM
|
||
|
|
{ 498, 3, 1, 67, "VSUBUHS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #498 = VSUBUHS
|
||
|
|
{ 499, 3, 1, 70, "VSUBUWM", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #499 = VSUBUWM
|
||
|
|
{ 500, 3, 1, 67, "VSUBUWS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #500 = VSUBUWS
|
||
|
|
{ 501, 3, 1, 67, "VSUM2SWS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #501 = VSUM2SWS
|
||
|
|
{ 502, 3, 1, 67, "VSUM4SBS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #502 = VSUM4SBS
|
||
|
|
{ 503, 3, 1, 67, "VSUM4SHS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #503 = VSUM4SHS
|
||
|
|
{ 504, 3, 1, 67, "VSUM4UBS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #504 = VSUM4UBS
|
||
|
|
{ 505, 3, 1, 67, "VSUMSWS", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #505 = VSUMSWS
|
||
|
|
{ 506, 2, 1, 67, "VUPKHPX", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo86 }, // Inst #506 = VUPKHPX
|
||
|
|
{ 507, 2, 1, 67, "VUPKHSB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo86 }, // Inst #507 = VUPKHSB
|
||
|
|
{ 508, 2, 1, 67, "VUPKHSH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo86 }, // Inst #508 = VUPKHSH
|
||
|
|
{ 509, 2, 1, 67, "VUPKLPX", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo86 }, // Inst #509 = VUPKLPX
|
||
|
|
{ 510, 2, 1, 67, "VUPKLSB", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo86 }, // Inst #510 = VUPKLSB
|
||
|
|
{ 511, 2, 1, 67, "VUPKLSH", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo86 }, // Inst #511 = VUPKLSH
|
||
|
|
{ 512, 3, 1, 67, "VXOR", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo84 }, // Inst #512 = VXOR
|
||
|
|
{ 513, 1, 1, 67, "V_SET0", 0, 0x28ULL, NULL, NULL, NULL, OperandInfo61 }, // Inst #513 = V_SET0
|
||
|
|
{ 514, 3, 1, 14, "XOR", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo7 }, // Inst #514 = XOR
|
||
|
|
{ 515, 3, 1, 14, "XOR8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo8 }, // Inst #515 = XOR8
|
||
|
|
{ 516, 3, 1, 14, "XORI", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo9 }, // Inst #516 = XORI
|
||
|
|
{ 517, 3, 1, 14, "XORI8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo10 }, // Inst #517 = XORI8
|
||
|
|
{ 518, 3, 1, 14, "XORIS", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo9 }, // Inst #518 = XORIS
|
||
|
|
{ 519, 3, 1, 14, "XORIS8", 0, 0x8ULL, NULL, NULL, NULL, OperandInfo10 }, // Inst #519 = XORIS8
|
||
|
|
};
|
||
|
|
} // End llvm namespace
|