aixiao/wiringPi_Blueberry
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修改源码格式

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This commit is contained in:
aixiao 2023-11-30 12:50:07 +08:00
parent d6e6b3b2d2
commit e95a874564
2 changed files with 1839 additions and 1911 deletions
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3726
wiringPi/OrangePi.c
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24
wiringPi/OrangePi.h
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@ -37,7 +37,7 @@
#define GPIO_BASE_MAP (0x01C20800) #define GPIO_BASE_MAP (0x01C20800)
#define MEM_INFO (1024) #define MEM_INFO (1024)
#define GPIOL_BASE (0x01F02c00) #define GPIOL_BASE (0x01F02c00)
#define GPIOL_BASE_MAP (0x01F02000) #define GPIOL_BASE_MAP (0x01F02000)
#define MAP_SIZE_L (4096 * 2) #define MAP_SIZE_L (4096 * 2)
#define GPIO_PWM_OP (0x01C21000) #define GPIO_PWM_OP (0x01C21000)
#endif #endif
@ -49,7 +49,7 @@
#define GPIO_BASE_MAP (0x01C20800) #define GPIO_BASE_MAP (0x01C20800)
#define MEM_INFO (1024) #define MEM_INFO (1024)
#define GPIOL_BASE (0x01F02c00) #define GPIOL_BASE (0x01F02c00)
#define GPIOL_BASE_MAP (0x01F02000) #define GPIOL_BASE_MAP (0x01F02000)
#define MAP_SIZE_L (4096 * 2) #define MAP_SIZE_L (4096 * 2)
#define GPIO_PWM_OP (0x01C21000) #define GPIO_PWM_OP (0x01C21000)
#endif #endif
@ -61,7 +61,7 @@
#define GPIO_BASE_MAP (0x01C20800) #define GPIO_BASE_MAP (0x01C20800)
#define MEM_INFO (1024) #define MEM_INFO (1024)
#define GPIOL_BASE (0x01F02c00) #define GPIOL_BASE (0x01F02c00)
#define GPIOL_BASE_MAP (0x01F02000) #define GPIOL_BASE_MAP (0x01F02000)
#define MAP_SIZE_L (4096 * 2) #define MAP_SIZE_L (4096 * 2)
#define GPIO_PWM_OP (0x01C21000) #define GPIO_PWM_OP (0x01C21000)
#endif #endif
@ -73,7 +73,7 @@
#define GPIO_BASE_MAP (0x0300B000) #define GPIO_BASE_MAP (0x0300B000)
#define MEM_INFO (1024) #define MEM_INFO (1024)
#define GPIOL_BASE (0x07022000) #define GPIOL_BASE (0x07022000)
#define GPIOL_BASE_MAP (0x07022000) #define GPIOL_BASE_MAP (0x07022000)
#define MAP_SIZE_L (4096 * 1) #define MAP_SIZE_L (4096 * 1)
#define GPIO_PWM_OP (0x0300A000) #define GPIO_PWM_OP (0x0300A000)
#endif #endif
@ -85,7 +85,7 @@
#define GPIO_BASE_MAP (0x0300B000) #define GPIO_BASE_MAP (0x0300B000)
#define MEM_INFO (1024) #define MEM_INFO (1024)
#define GPIOL_BASE (0x07022000) #define GPIOL_BASE (0x07022000)
#define GPIOL_BASE_MAP (0x07022000) #define GPIOL_BASE_MAP (0x07022000)
#define MAP_SIZE_L (4096 * 1) #define MAP_SIZE_L (4096 * 1)
#define GPIO_PWM_OP (0x0300A000) #define GPIO_PWM_OP (0x0300A000)
#endif #endif
@ -105,7 +105,7 @@
#define RK3399_GRF_GPIO2_3_4_P_OFFSET 0x00040U #define RK3399_GRF_GPIO2_3_4_P_OFFSET 0x00040U
#define RK3399_PMUGRF_GPIO0_1_P_OFFSET 0x00040U #define RK3399_PMUGRF_GPIO0_1_P_OFFSET 0x00040U
#define PMUGRF_BASE 0xff320000 #define PMUGRF_BASE 0xff320000
#define PMUGRF_GPIO1A_IOMUX 0x00010 #define PMUGRF_GPIO1A_IOMUX 0x00010
#define PMUGRF_GPIO1B_IOMUX 0x00014 #define PMUGRF_GPIO1B_IOMUX 0x00014
#define PMUGRF_GPIO1C_IOMUX 0x00018 #define PMUGRF_GPIO1C_IOMUX 0x00018
@ -122,10 +122,9 @@
#define GRF_GPIO4C_IOMUX_OFFSET 0x28 #define GRF_GPIO4C_IOMUX_OFFSET 0x28
#define GRF_GPIO4D_IOMUX_OFFSET 0x2c #define GRF_GPIO4D_IOMUX_OFFSET 0x2c
#define CRU_BASE 0xff760000 #define CRU_BASE 0xff760000
#define PMUCRU_BASE 0xff750000 #define PMUCRU_BASE 0xff750000
#define CRU_CLKGATE_CON31_OFFSET 0x037c //bit 3 4 5 #define CRU_CLKGATE_CON31_OFFSET 0x037c //bit 3 4 5
#define PMUCRU_CLKGATE_CON1_OFFSET 0x0104 #define PMUCRU_CLKGATE_CON1_OFFSET 0x0104
#define MEM_INFO (2048) #define MEM_INFO (2048)
@ -142,7 +141,6 @@ extern volatile unsigned int *gpio4_base;
#endif /* CONFIG_ORANGEPI_RK3399 */ #endif /* CONFIG_ORANGEPI_RK3399 */
//csy 2019.1.8 //csy 2019.1.8
/*********** OrangePi R1PLUS *************/ /*********** OrangePi R1PLUS *************/
#if CONFIG_ORANGEPI_R1PLUS #if CONFIG_ORANGEPI_R1PLUS
@ -170,7 +168,7 @@ extern volatile unsigned int *gpio4_base;
#define GRF_GPIO3D_IOMUX_OFFSET 0x4c #define GRF_GPIO3D_IOMUX_OFFSET 0x4c
#define CRU_BASE 0xff440000 #define CRU_BASE 0xff440000
#define CRU_CLKGATE_CON16_OFFSET 0x0240 //bit 7 8 9 10 9877 #define CRU_CLKGATE_CON16_OFFSET 0x0240 //bit 7 8 9 10 9877
#define MEM_INFO (2048) #define MEM_INFO (2048)
#define MAP_SIZE_L (4*1024) #define MAP_SIZE_L (4*1024)
@ -180,12 +178,9 @@ extern volatile unsigned int *gpio3_base;
extern volatile unsigned int *cru_base; extern volatile unsigned int *cru_base;
extern volatile unsigned int *grf_base; extern volatile unsigned int *grf_base;
#endif /* CONFIG_ORANGEPI_R1PLUS */ #endif /* CONFIG_ORANGEPI_R1PLUS */
//FG 2020.11.26 //FG 2020.11.26
/****************** Global data *********************/ /****************** Global data *********************/
/* Current version */ /* Current version */
#define PI_MAKER_ORANGEPI 4 #define PI_MAKER_ORANGEPI 4
@ -197,7 +192,6 @@ extern volatile unsigned int *grf_base;
#define ORANGEPI_MEM_INFO MEM_INFO #define ORANGEPI_MEM_INFO MEM_INFO
#define GPIO_PWM GPIO_PWM_OP #define GPIO_PWM GPIO_PWM_OP
//sunxi_pwm //sunxi_pwm
#define SUNXI_PWM_BASE (0x01c21400) #define SUNXI_PWM_BASE (0x01c21400)
#define SUNXI_PWM_CTRL_REG (SUNXI_PWM_BASE) #define SUNXI_PWM_CTRL_REG (SUNXI_PWM_BASE)
@ -261,7 +255,6 @@ extern int sunxi_pwm_get_act(void);
extern void sunxi_pwm_set_period(int period_cys); extern void sunxi_pwm_set_period(int period_cys);
extern void sunxi_pwm_set_act(int act_cys); extern void sunxi_pwm_set_act(int act_cys);
#ifdef CONFIG_ORANGEPI #ifdef CONFIG_ORANGEPI
extern const char *piModelNames[6]; extern const char *piModelNames[6];
#endif #endif
@ -281,6 +274,5 @@ extern int ORANGEPI_PIN_MASK[5][32];
#elif CONFIG_ORANGEPI_R1PLUS #elif CONFIG_ORANGEPI_R1PLUS
extern int ORANGEPI_PIN_MASK[5][32]; extern int ORANGEPI_PIN_MASK[5][32];
#endif #endif
#endif #endif