46 lines
1.6 KiB
Diff
46 lines
1.6 KiB
Diff
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From 6606ce73fb42a987b1cc45edbeb7c5e78246fb51 Mon Sep 17 00:00:00 2001
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From: Aditya Prayoga <aditya@kobol.io>
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Date: Wed, 10 Jun 2020 17:21:06 +0700
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Subject: [PATCH] backport pcie fix power stable and config access
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Signed-off-by: Aditya Prayoga <aditya@kobol.io>
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---
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drivers/pci/host/pcie-rockchip.c | 14 ++++++++++++--
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1 file changed, 12 insertions(+), 2 deletions(-)
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diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
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index 1823323f8..f57571863 100644
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--- a/drivers/pci/host/pcie-rockchip.c
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+++ b/drivers/pci/host/pcie-rockchip.c
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@@ -394,8 +394,11 @@ static void rockchip_pcie_cfg_configuration_accesses(
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{
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u32 ob_desc_0;
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- /* Configuration Accesses for region 0 */
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- rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
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+ /*
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+ * Configuration Accesses for region 0.
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+ * Bit 19 is for enabling IO base and limit registers.
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+ */
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+ rockchip_pcie_write(rockchip, BIT(19), PCIE_RC_BAR_CONF);
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rockchip_pcie_write(rockchip,
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(RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
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@@ -701,6 +704,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
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/* Enable Gen1 training */
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rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
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PCIE_CLIENT_CONFIG);
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+ /*
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+ * According to PCI Express Card Electromechanical Specification
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+ * Revision 3.0, Table 2-4, power stable and reference clk stable
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+ * before PERST# inactive should be at least 100ms and 100us
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+ * respectively. Otherwise we do see some failures for link training.
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+ */
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+ msleep(100);
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gpiod_set_value(rockchip->ep_gpio, 1);
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--
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Created with Armbian build tools https://github.com/armbian/build
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