build/patch/kernel/archive/rk3399-4.4/pci-host-rockchip-0001-backport-fix-power-stable-and-config-access.patch

46 lines
1.6 KiB
Diff

From 6606ce73fb42a987b1cc45edbeb7c5e78246fb51 Mon Sep 17 00:00:00 2001
From: Aditya Prayoga <aditya@kobol.io>
Date: Wed, 10 Jun 2020 17:21:06 +0700
Subject: [PATCH] backport pcie fix power stable and config access
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
---
drivers/pci/host/pcie-rockchip.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 1823323f8..f57571863 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -394,8 +394,11 @@ static void rockchip_pcie_cfg_configuration_accesses(
{
u32 ob_desc_0;
- /* Configuration Accesses for region 0 */
- rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
+ /*
+ * Configuration Accesses for region 0.
+ * Bit 19 is for enabling IO base and limit registers.
+ */
+ rockchip_pcie_write(rockchip, BIT(19), PCIE_RC_BAR_CONF);
rockchip_pcie_write(rockchip,
(RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
@@ -701,6 +704,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
/* Enable Gen1 training */
rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
PCIE_CLIENT_CONFIG);
+ /*
+ * According to PCI Express Card Electromechanical Specification
+ * Revision 3.0, Table 2-4, power stable and reference clk stable
+ * before PERST# inactive should be at least 100ms and 100us
+ * respectively. Otherwise we do see some failures for link training.
+ */
+ msleep(100);
gpiod_set_value(rockchip->ep_gpio, 1);
--
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