51 lines
1.6 KiB
Diff
51 lines
1.6 KiB
Diff
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From 198cad9a30ea2a5a252ceb97736f3475d7a6b08d Mon Sep 17 00:00:00 2001
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From: ashthespy <ashthespy@gmail.com>
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Date: Mon, 3 Feb 2020 17:19:33 +0100
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Subject: [PATCH 20/23] arm64: dts: rockchip: Add acodec node for rk3308
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Change-Id: I76f4a877711d33620bdef295e9047bdba26d4da4
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Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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---
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arch/arm64/boot/dts/rockchip/rk3308.dtsi | 18 +++++++++++++++++-
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1 file changed, 17 insertions(+), 1 deletion(-)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
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index c711c248ce29..3863f8cc2517 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
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@@ -510,7 +510,7 @@ rk_timer_rtc: rk-timer-rtc@ff1a0020 {
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clock-names = "pclk", "timer";
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status = "disabled";
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};
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-
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+
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saradc: saradc@ff1e0000 {
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compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
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reg = <0x0 0xff1e0000 0x0 0x100>;
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@@ -837,6 +837,22 @@ cru: clock-controller@ff500000 {
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assigned-clock-rates = <32768>;
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};
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+ acodec: acodec@ff560000 {
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+ compatible = "rockchip,rk3308-codec";
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+ reg = <0x0 0xff560000 0x0 0x10000>;
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+ rockchip,grf = <&grf>;
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+ rockchip,detect-grf = <&detect_grf>;
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+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru PCLK_ACODEC>,
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+ <&cru SCLK_I2S2_8CH_TX_OUT>,
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+ <&cru SCLK_I2S2_8CH_RX_OUT>;
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+ clock-names = "acodec", "mclk_tx", "mclk_rx";
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+ resets = <&cru SRST_ACODEC_P>;
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+ reset-names = "acodec-reset";
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+ status = "disabled";
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+};
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+
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gic: interrupt-controller@ff580000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xff581000 0x0 0x1000>,
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--
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2.25.1
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