54 lines
1.9 KiB
Diff
54 lines
1.9 KiB
Diff
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From edc93fd70ee759fd989664fcb85996cb48a006e6 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Mon, 14 Aug 2023 07:28:09 +0200
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Subject: [PATCH 210/464] clk: sunxi-ng: a64: keep tcon0 clock rate when
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pll-video0's rate changes
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Notify TCON0 clock (and in consequence PLL-MIPI by CLK_SET_RATE_PARENT)
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to reset when PLL-Video0 changes (because of HDMI PHY clk which is a
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child of PLL-Video0 and has CLK_SET_RATE_PARENT set). In this way we can
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get clock tree to satisfy both pipelines.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
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---
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drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 15 +++++++++++++++
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1 file changed, 15 insertions(+)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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index ef567775fc95..93beedb0428e 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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@@ -943,6 +943,17 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = {
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.bypass_index = 1, /* index of 24 MHz oscillator */
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};
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+/*
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+ * Since PLL-Video0 is an ancestor of both tcon0 and HDMI PYH, tcon0 clock will
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+ * conflict with HDMI PHY clock which is on another display pipeline.
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+ *
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+ * Therefore, a notifier is required to restore the rate of TCON0 when the rate
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+ * of PLL-Video0 changed.
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+ */
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+static struct ccu_rate_reset_nb sun50i_a64_pll_video0_reset_tcon0_nb = {
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+ .common = &pll_video0_clk.common,
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+};
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+
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static int sun50i_a64_ccu_probe(struct platform_device *pdev)
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{
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void __iomem *reg;
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@@ -978,6 +989,10 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
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ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
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&sun50i_a64_cpu_nb);
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+ /* Reset the rate of TCON0 clock when PLL-VIDEO0 is changed */
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+ sun50i_a64_pll_video0_reset_tcon0_nb.target_clk = tcon0_clk.common.hw.clk;
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+ ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_reset_tcon0_nb);
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+
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return 0;
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}
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--
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2.34.1
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