39 lines
1.3 KiB
Diff
39 lines
1.3 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Wed, 6 Apr 2022 01:04:45 +0200
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Subject: dt-bindings: riscv: sifive-ccache: Support StarFive JH71x0 SoCs
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This cache controller is also used on the StarFive JH7100 and JH7110
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SoCs.
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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---
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Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml | 4 ++++
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1 file changed, 4 insertions(+)
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diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
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index bf3f07421f7e..41eb60da04a4 100644
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--- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
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+++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
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@@ -25,6 +25,8 @@ select:
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- sifive,ccache0
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- sifive,fu540-c000-ccache
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- sifive,fu740-c000-ccache
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+ - starfive,jh7100-ccache
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+ - starfive,jh7110-ccache
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required:
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- compatible
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@@ -37,6 +39,8 @@ properties:
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- sifive,ccache0
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- sifive,fu540-c000-ccache
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- sifive,fu740-c000-ccache
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+ - starfive,jh7100-ccache
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+ - starfive,jh7110-ccache
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- const: cache
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- items:
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- const: microchip,mpfs-ccache
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--
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Armbian
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