96 lines
3.2 KiB
Diff
96 lines
3.2 KiB
Diff
From 864881b284ad9276b91dd95a2b60b8b7fb4e4847 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Thu, 16 Sep 2021 13:48:34 -0400
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Subject: [PATCH 435/478] phy: rockchip: sync combophy driver with latest
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submission
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This syncs the combophy driver to the latest submission from rockchip.
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It renames the clocks and includes a fix for their submission.
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This will need changes to the devicetree for the clock renames.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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.../rockchip/phy-rockchip-naneng-combphy.c | 38 ++++++++++++++++---
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1 file changed, 32 insertions(+), 6 deletions(-)
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diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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index d28fe5728e7a..e399d79a62bb 100644
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--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -411,7 +411,7 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
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/* Configure PHY reference clock frequency */
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for (i = 0; i < priv->num_clks; i++) {
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- if (!strncmp(priv->clks[i].id, "refclk", 6)) {
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+ if (!strncmp(priv->clks[i].id, "ref", 6)) {
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refclk = priv->clks[i].clk;
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break;
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}
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@@ -448,6 +448,27 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
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val |= 0x01;
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writel(val, priv->mmio + (0x0e << 2));
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+ /* Set PLL KVCO fine tuning signals */
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+ val = readl(priv->mmio + (0x20 << 2));
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+ val &= ~(0x7 << 2);
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+ val |= 0x2 << 2;
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+ writel(val, priv->mmio + (0x20 << 2));
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+
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+ /* Set PLL LPF R1 to su_trim[10:7]=1001 */
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+ writel(0x4, priv->mmio + (0xb << 2));
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+
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+ /* Set PLL input clock divider 1/2 */
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+ val = readl(priv->mmio + (0x5 << 2));
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+ val &= ~(0x3 << 6);
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+ val |= 0x1 << 6;
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+ writel(val, priv->mmio + (0x5 << 2));
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+
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+ /* Set PLL loop divider */
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+ writel(0x32, priv->mmio + (0x11 << 2));
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+
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+ /* Set PLL KVCO to min and set PLL charge pump current to max */
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+ writel(0xf0, priv->mmio + (0xa << 2));
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+
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param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
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param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
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param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
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@@ -484,7 +505,7 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
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switch (rate) {
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case 24000000:
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- if (priv->mode == PHY_TYPE_USB3) {
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+ if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) {
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/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
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val = readl(priv->mmio + (0x0e << 2));
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val &= ~GENMASK(7, 6);
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@@ -519,7 +540,12 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
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writel(0x32, priv->mmio + (0x11 << 2));
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writel(0xf0, priv->mmio + (0xa << 2));
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-
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+ } else if (priv->mode == PHY_TYPE_SATA) {
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+ /* downward spread spectrum +500ppm */
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+ val = readl(priv->mmio + (0x1f << 2));
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+ val &= ~GENMASK(7, 4);
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+ val |= 0x50;
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+ writel(val, priv->mmio + (0x1f << 2));
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}
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break;
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default:
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@@ -586,9 +612,9 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
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};
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static const struct clk_bulk_data rk3568_clks[] = {
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- { .id = "refclk" },
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- { .id = "apbclk" },
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- { .id = "pipe_clk" },
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+ { .id = "ref" },
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+ { .id = "apb" },
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+ { .id = "pipe" },
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};
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static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
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--
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2.35.3
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