100 lines
2.6 KiB
Groff
100 lines
2.6 KiB
Groff
From 56131b6002a59ef06ca96a6d38131e4f4dc281b9 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Sat, 2 Dec 2017 15:13:12 +0800
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Subject: [PATCH 08/35] arm64: allwinner: h6: add device tree nodes for MMC
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controllers
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The Allwinner H6 SoC have 3 MMC controllers.
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Add device tree nodes for them.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 56 ++++++++++++++++++++++++++++
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1 file changed, 56 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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index d4697bb..19c7ee8 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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@@ -125,12 +125,76 @@
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interrupt-controller;
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#interrupt-cells = <3>;
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+ mmc0_pins: mmc0-pins {
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+ pins = "PF0", "PF1", "PF2", "PF3",
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+ "PF4", "PF5";
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+ function = "mmc0";
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+ drive-strength = <30>;
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+ bias-pull-up;
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+ };
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+
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+ mmc1_pins: mmc1-pins {
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+ pins = "PG0", "PG1", "PG2", "PG3",
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+ "PG4", "PG5";
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+ function = "mmc1";
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+ drive-strength = <30>;
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+ bias-pull-up;
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+ };
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+
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+ mmc2_pins: mmc2-pins {
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+ pins = "PC1", "PC4", "PC5", "PC6",
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+ "PC7", "PC8", "PC9", "PC10",
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+ "PC11", "PC12", "PC13", "PC14";
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+ function = "mmc2";
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+ drive-strength = <30>;
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+ bias-pull-up;
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+ };
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+
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uart0_ph_pins: uart0-ph {
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pins = "PH0", "PH1";
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function = "uart0";
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};
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};
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+ mmc0: mmc@4020000 {
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+ compatible = "allwinner,sun50i-h6-mmc";
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+ reg = <0x04020000 0x1000>;
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+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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+ clock-names = "ahb", "mmc";
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+ resets = <&ccu RST_BUS_MMC0>;
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+ reset-names = "ahb";
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+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mmc1: mmc@4021000 {
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+ compatible = "allwinner,sun50i-h6-mmc";
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+ reg = <0x04021000 0x1000>;
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+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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+ clock-names = "ahb", "mmc";
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+ resets = <&ccu RST_BUS_MMC1>;
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+ reset-names = "ahb";
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+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ mmc2: mmc@4022000 {
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+ compatible = "allwinner,sun50i-h6-emmc";
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+ reg = <0x04022000 0x1000>;
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+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
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+ clock-names = "ahb", "mmc";
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+ resets = <&ccu RST_BUS_MMC2>;
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+ reset-names = "ahb";
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+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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uart0: serial@5000000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000000 0x400>;
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--
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2.7.4
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