build/patch/kernel/archive/sunxi-6.2/patches.megous/arm64-dts-rk3399-pinephone-pro-Use-unused-GPLL-for-VOPs-DCLK.patch

40 lines
1.5 KiB
Diff

From f9b39cf4e873807063127892be4c1436c81dd44d Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megi@xff.cz>
Date: Mon, 24 Oct 2022 03:20:27 +0200
Subject: [PATCH 290/391] arm64: dts: rk3399-pinephone-pro: Use unused GPLL for
VOPs DCLK
GPLL allows us to get 74.25MHz just by dividing 594 by 8. Use GPLL by default
for VOPs.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
---
arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
index 221082568..26c98a89a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
@@ -1555,7 +1555,7 @@ &vopb {
status = "okay";
assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>, <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
- assigned-clock-parents = <&cru PLL_CPLL>, <&cru DCLK_VOP0_FRAC>;
+ assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>;
};
&vopb_mmu {
@@ -1566,7 +1566,7 @@ &vopl {
status = "okay";
assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>, <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
- assigned-clock-parents = <&cru PLL_CPLL>, <&cru DCLK_VOP1_FRAC>;
+ assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>;
};
&vopl_mmu {
--
2.35.3